AT89C2051X2-8PL [ATMEL]
Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDIP20, 0.300 INCH, PLASTIC, MS-001AD, DIP-20;
| 型号： | AT89C2051X2-8PL |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDIP20, 0.300 INCH, PLASTIC, MS-001AD, DIP-20 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总19页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS®-51 Products
• 2K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
8-bit
Microcontroller
with 2K Bytes
Flash
• On-chip Analog Comparator
• Low-power Idle and Power-down Modes
• 6 Clocks per Machine Cycle Operation
Description
The AT89C2051x2 is a low-voltage, high-performance CMOS 8-bit microcontroller
with 2K bytes of Flash programmable memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on
a monolithic chip, the Atmel AT89C2051x2 is a powerful microcomputer which pro-
vides a highly-flexible and cost-effective solution to many embedded control
applications.
AT89C2051x2
The AT89C2051x2 provides the following standard features: 2K bytes of Flash, 128
bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator
and clock circuitry. In addition, the AT89C2051x2 is designed with static logic for oper-
ation down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port and interrupt system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator disabling all other chip functions until the next
hardware reset.
Furthermore, the AT89C2051x2 executes one machine cycle in 6 clock cycles, provid-
ing twice the speed of the AT89C2051 device. The user gains the flexibility to divide
input frequency crystals by 2 (using less expensive components), while keeping the
same CPU power. Alternatively, the user can save on power consumption while keep-
ing the same CPU power (oscillator power saving).
Pin Configuration
PDIP/SOIC
RST/VPP
(RXD) P3.0
(TXD) P3.1
XTAL2
1
2
3
4
5
6
7
8
9
20 VCC
19 P1.7
18 P1.6
17 P1.5
XTAL1
16 P1.4
15 P1.3
14 P1.2
(INT0) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
13 P1.1 (AIN1)
12 P1.0 (AIN0)
11 P3.7
GND 10
Rev. 3285B–MICRO–10/03
Block Diagram
2
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Pin Description
VCC
Supply voltage.
Ground.
GND
Port 1
Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull-ups.
P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog com-
parator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7
are used as inputs and are externally pulled low, they will source current (IIL) because of
the internal pull-ups.
Port 1 also receives code data during Flash programming and verification.
Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups.
P3.6 is hard-wired as an input to the output of the on-chip comparator and is not acces-
sible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s
are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL)
because of the pull-ups.
Port 3 also serves the functions of various special features of the AT89C2051x2 as
listed below:
Port Pin
P3.0
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
P3.1
P3.2
P3.3
P3.4
P3.5
Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin
high for two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 6 oscillator or clock cycles.
XTAL1
XTAL2
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
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3285B–MICRO–10/03
Oscillator
Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which
can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external clock signal, since the input
to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and
maximum voltage high and low time specifications must be observed.
Figure 1. Oscillator Connections
Note:
C1, C2 = 30 pF 10 pF for Crystals
= 40 pF 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
X2 Mode Description The clock for the entire circuit and peripherals is normally divided by 2 before being
used by the CPU core and peripherals. This allows any cyclic ratio (duty cycle) to be
accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on
XTAL1 must have a cyclic ratio (duty cycle) between 40% to 60%. Figure 3 shows the
clock generation block diagram.
Figure 3. Clock Generation Block Diagram
X2 Mode
(XTAL1)/2
÷
2
XTAL1
FXTAL
State Machine: 6 Clock Cycles
CPU Control
FOSC
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AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Special
Function
Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown
in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data,
and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Table 1. AT89C2051x2 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
B
00000000
ACC
00000000
PSW
00000000
IP
XXX00000
P3
11111111
IE
0XX00000
SCON
SBUF
00000000
XXXXXXXX
90H
P1
97H
11111111
88H
TCON
TMOD
TL0
TL1
TH0
TH1
8FH
00000000
00000000
00000000
00000000
00000000
00000000
80H
SP
DPL
DPH
PCON
87H
00000111
00000000
00000000
0XXX0000
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3285B–MICRO–10/03
Restrictions on
Certain Instructions
The AT89C2051x2 is an economical and cost-effective member of Atmel’s growing fam-
ily of microcontrollers. It contains 2K bytes of Flash program memory. It is fully
compatible with the MCS-51 architecture, and can be programmed using the MCS-51
instruction set. However, there are a few considerations one must keep in mind when
utilizing certain instructions to program this device.
All the instructions related to jumping or branching should be restricted such that the
destination address falls within the physical program memory space of the device, which
is 2K for the AT89C2051x2. This should be the responsibility of the software program-
mer. For example, LJMP 7E0H would be a valid instruction for the AT89C2051x2 (with
2K of memory), whereas LJMP 900H would not.
Branching Instructions
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR
These unconditional branching instructions will execute correctly as long as the pro-
grammer keeps in mind that the destination branching address must fall within the
physical boundaries of the program memory size (locations 00H to 7FFH for the
AT89C2051x2). Violating the physical space limits may cause unknown program
behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ
With these conditional branching instructions, the same rule above applies. Again, vio-
lating the memory boundaries may cause erratic execution.
For applications involving interrupts, the normal interrupt service routine address loca-
tions of the 80C51 family architecture have been preserved.
MOVX-related Instructions,
Data Memory
The AT89C2051x2 contains 128 bytes of internal data memory. Thus, in the
AT89C2051x2, the stack depth is limited to 128 bytes, the amount of available RAM.
External DATA memory access is not supported in this device, nor is external PRO-
GRAM memory execution. Therefore, no MOVX [...] instructions should be included in
the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in vio-
lation of the restrictions mentioned above. It is the responsibility of the controller user to
know the physical features and limitations of the device being used and adjust the
instructions used correspondingly.
Program Memory
Lock Bits
On the chip are two lock bits which can be left unprogrammed (U) or can be pro-
grammed (P) to obtain the additional features listed in the table below:
Lock Bit Protection Modes(1)
Program Lock Bits
LB1
U
LB2
U
Protection Type
1
2
3
No program lock features.
P
U
Further programming of the Flash is disabled.
Same as mode 2, also verify is disabled.
P
P
Note:
1. The Lock Bits can only be erased with the Chip Erase operation.
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AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special
functions registers remain unchanged during this mode. The idle mode can be termi-
nated by any enabled interrupt or by a hardware reset.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
It should be noted that when idle is terminated by a hardware reset, the device normally
resumes program execution, from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM
in this event, but access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that writes to a port pin or to external
memory.
Power-down Mode
In the power-down mode the oscillator is stopped, and the instruction that invokes
power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the power-down mode is terminated. The only exit
from power-down is a hardware reset. Reset redefines the SFRs but does not change
the on-chip RAM. The reset should not be activated before VCC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if
external pull-ups are used.
Programming
the Flash
The AT89C2051x2 is shipped with the 2K bytes of on-chip Flash code memory array in
the erased state (i.e., contents = FFH) and ready to be programmed. The code memory
array is programmed one byte at a time. Once the array is programmed, to re-program
any non-blank byte, the entire memory array needs to be erased electrically.
Internal Address Counter: The AT89C2051x2 contains an internal memory address
counter which is always reset to 000H on the rising edge of RST and is advanced by
applying a positive going pulse to pin XTAL1.
Programming Algorithm: To program the AT89C2051x2, the following sequence is
recommended.
1. Power-up sequence:
Apply power between VCC and GND pins
Set RST and XTAL1 to GND
2. Set pin RST to “H”
Set pin P3.2 to “H”
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P3.3, P3.4, P3.5, P3.7 to select one of the programming operations
shown in the Flash Programming Modes table.
To Program and Verify the Array:
1. Apply data for Code byte at location 000H to P1.0 to P1.7.
2. Raise RST to 12V to enable programming.
3. Pulse P3.2 once to program a byte in the program memory array or the lock bits.
The byte-write cycle is self-timed and typically takes 1.2 ms.
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3285B–MICRO–10/03
4. To verify the programmed data, lower RST from 12V to logic “H” level and set
pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port
P1 pins.
5. To program a byte at the next address location, pulse XTAL1 pin once to advance
the internal address counter. Apply new data to the port P1 pins.
6. Repeat steps 6 through 8, changing data and advancing the address counter for
the entire 2-Kbyte array or until the end of the object file is reached.
7. Power-off sequence:
set XTAL1 to “L”
set RST to “L”
Turn VCC power off
Data Polling: The AT89C2051x2 features Data Polling to indicate the end of a write
cycle. During a write cycle, an attempted read of the last byte written will result in the
complement of the written data on P1.7. Once the write cycle has been completed, true
data is valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The Progress of byte programming can also be monitored by the
RDY/BSY output signal. Pin P3.1 is pulled low after P3.2 goes High during programming
to indicate BUSY. P3.1 is pulled High again when programming is done to indicate
READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed code data can be
read back via the data lines for verification:
1. Reset the internal address counter to 000H by bringing RST from “L” to “H”.
2. Apply the appropriate control signals for Read Code data and read the output
data at the port P1 pins.
3. Pulse pin XTAL1 once to advance the internal address counter.
4. Read the next code data byte at the port P1 pins.
5. Repeat steps 3 and 4 until the entire array is read.
The lock bits cannot be verified directly. Verification of the lock bits is achieved by
observing that their features are enabled.
Chip Erase: The entire program memory array (2K bytes) and the two Lock Bits are
erased electrically by using the proper combination of control signals and by holding
P3.2 low for 10 ms. The code array is written with all “1”s in the Chip Erase operation
and must be executed before any non-blank memory byte can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as
a normal verification of locations 000H, 001H, and 002H, except that P3.5 and P3.7
must be pulled to a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(001H) = 22H indicates AT89C2051x2
Programming
Interface
Every code byte in the Flash array can be written and the entire array can be erased by
using the appropriate combination of control signals. The write operation cycle is self-
timed and once initiated, will automatically time itself to completion.
Most worldwide major programming vendors offer support for the Atmel microcontroller
series. Please contact your local programming vendor for the appropriate software
revision.
8
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Flash Programming Modes
Mode
RST/VPP
P3.2/PROG
P3.3
P3.4
P3.5
P3.7
Write Code Data(1)(3)
12V
L
H
H
H
Read Code Data(1)
H
H
L
L
H
H
H
H
Write Lock
Bit - 1
Bit - 2
12V
H
H
12V
12V
H
H
H
L
H
L
L
L
L
L
L
L
L
Chip Erase
(2)
Read Signature Byte
H
Notes: 1. The internal memory address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at
XTAL1 pin.
2. Chip Erase requires a 10 ms PROG pulse.
3. P3.1 is pulled Low during programming to indicate RDY/BSY.
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3285B–MICRO–10/03
Figure 4. Programming the Flash Memory
4.5V - 5.5V
AT89C2051x2
VCC
RDY/BSY
PGM
DATA
P3.2
PROG
P1
P3.3
P3.4
P3.5
P3.7
SEE FLASH
PROGRAMMING
MODES TABLE
VIH/VPP
RST
XTAL1
GND
TO INCREMENT
ADDRESS COUNTER
Figure 5. Verifying the Flash Memory
4.5V - 5.5V
AT89C2051x2
VCC
P1
PGM
DATA
VIH
P3.2
P3.3
P3.4
P3.5
P3.7
SEE FLASH
PROGRAMMING
MODES TABLE
VIH
XTAL1
GND
RST
10
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol
VPP
Parameter
Min
Max
12.5
250
Units
V
Programming Enable Voltage
Programming Enable Current
Data Setup to PROG Low
Data Hold after PROG
P3.4 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold after PROG
11.5
IPP
µA
µs
µs
µs
µs
µs
µs
µs
µs
ns
ms
µs
ns
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tELQV
tEHQZ
tGHBL
tWC
1.0
1.0
1.0
10
10
1
PROG Width
110
1.0
1.0
50
ENABLE Low to Data Valid
Data Float after ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
RDY/BSY\ to Increment Clock Delay
Increment Clock High
0
2.0
tBHIH
tIHIL
Note:
1.0
200
1. Only used in 12-volt programming mode.
Flash Programming and Verification Waveforms
11
3285B–MICRO–10/03
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature ................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 25.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
0.2 VCC - 0.1
VCC + 0.5
VCC + 0.5
0.5
Units
Input Low-voltage
Input High-voltage
Input High-voltage
V
V
V
V
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
Output Low-voltage(1)
(Ports 1, 3)
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 2.7V
VOH
Output High-voltage
(Ports 1, 3)
IOH = -80 µA, VCC = 5V 10%
2.4
V
V
I
I
OH = -30 µA
OH = -12 µA
0.75 VCC
0.9 VCC
V
IIL
ITL
ILI
Logical 0 Input Current
(Ports 1, 3)
VIN = 0.45V
-50
-750
10
µA
Logical 1 to 0 Transition Current
(Ports 1, 3)
VIN = 2V, VCC = 5V 10%
0 < VIN < VCC
µA
µA
Input Leakage Current
(Port P1.0, P1.1)
VOS
VCM
Comparator Input Offset Voltage
VCC = 5V
20
mV
V
Comparator Input Common
Mode Voltage
0
VCC
RRST
CIO
Reset Pull-down Resistor
Pin Capacitance
50
300
10
KΩ
pF
Test Freq. = 1 MHz, TA = 25°C
ICC
Power Supply Current
Active Mode, 12 MHz, VCC = 6V/3V
15/5.5
5/1
mA
mA
Idle Mode, 12 MHz, VCC = 6V/3V
P1.0 & P1.1 = 0V or VCC
Power-down Mode(2)
VCC = 6V, P1.0 & P1.1 = 0V or VCC
100
20
µA
µA
VCC = 3V, P1.0 & P1.1 = 0V or VCC
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 20 mA
Maximum total IOL for all output pins: 80 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
12
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
External Clock Drive Waveforms
External Clock Drive
VCC = 2.7V to 6.0V
VCC = 4.0V to 6.0V
Symbol
1/tCLCL
tCLCL
Parameter
Min
Max
Min
Max
Units
MHz
ns
Oscillator Frequency
Clock Period
High Time
0
12.5
45
8
0
16
62.5
22.5
22.5
tCHCX
tCLCX
ns
Low Time
45
ns
tCLCH
Rise Time
10
10
60
10
10
60
ns
tCHCL
Fall Time
ns
t
CHCX/tCLCX
Cyclic Ratio (duty cycle)
40
40
%
13
()
Serial Port Timing: Shift Register Mode Test Conditions
VCC = 5.0V 20%; Load Capacitance = 80 pF
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
1.0
700
50
Max
Min
12tCLCL
10tCLCL-133
2tCLCL-117
0
Max
Units
µs
Serial Port Clock Cycle Time
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold after Clock Rising Edge
Input Data Hold after Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
0
ns
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH
min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when 100 mV change from the loaded VOH/VOL level occurs.
14
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
AT89C2051x2
TYPICAL ICC - ACTIVE (85˚C)
20
15
10
5
Vcc=6.0V
I
C
C
Vcc=5.0V
Vcc=3.0V
m
A
0
0
3
6
9
12
FREQUENCY (MHz)
AT89C2051x2
TYPICAL ICC - IDLE (85˚C)
3
2
1
0
Vcc=6.0V
I
C
C
Vcc=5.0V
m
A
Vcc=3.0V
0
1.5
3
4.5
6
FREQUENCY (MHz)
AT89C2051x2
TYPICAL ICC vs.VOLTAGE - POWER DOWN (85˚C)
20
15
10
5
I
C
C
µ
A
0
3.0V
4.0V
5.0V
6.0V
Vcc VOLTAGE
Notes: 1. XTAL1 tied to GND for ICC (power-down).
2. P.1.0 and P1.1 = VCC or GND.
3. Lock bits programmed.
15
3285B–MICRO–10/03
Ordering Information
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
8
2.7V to 6.0V
AT89C2051x2-8PC
AT89C2051x2-8SC
20P3
20S2
Commercial
(0°C to 70°C)
AT89C2051x2-8PI
AT89C2051x2-8SI
20P3
20S2
Industrial
(-40°C to 85°C)
16
4.0V to 6.0V
AT89C2051x2-16PC
AT89C2051x2-16SC
20P3
20S2
Commercial
(0°C to 70°C)
AT89C2051x2-16PI
AT89C2051x2-16SI
20P3
20S2
Industrial
(-40°C to 85°C)
Package Type
20P3
20S2
20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP)
20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)
16
AT89C2051x2
3285B–MICRO–10/03
AT89C2051x2
Package Information
20P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
25.984
7.620
6.096
0.356
1.270
2.921
0.203
–
25.493 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.551
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
09/28/01
DRAWING NO. REV.
20P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
17
3285B–MICRO–10/03
20S2 – SOIC
C
1
H
E
N
A1
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
MIN
MAX
NOM
NOTE
SYMBOL
e
b
A
A1
b
0.0926
0.0040
0.0130
0.0091
0.4961
0.2914
0.3940
0.0160
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
0.4190
0.050
A
4
C
D
E
H
L
D
1
2
Side View
3
e
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
1/9/02
(0.024") per side.
TITLE
DRAWING NO.
REV.
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
2325 Orchard Parkway
San Jose, CA 95131
A
20S2
R
18
AT89C2051x2
3285B–MICRO–10/03
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Printed on recycled paper.
3285B–MICRO–10/03
xM
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