AT89C51AC3_04 [ATMEL]
Microcontrollers; 微控制器
| 型号： | AT89C51AC3_04 |
| 厂家： | 
ATMEL |
| 描述： | Microcontrollers |
| 文件： | 总26页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Protocol
– UART Used as Physical Layer
– Based on the Intel Hex-type Records
– Autobaud
• In-System Programming
– Read/Write Flash and EEPROM Memories
– Read Device ID
– Full-chip Erase
– Read/Write Configuration Bytes
– Security Setting From ISP Command
– Remote Application Start Command
• In-Application Programming/Self Programming
– Read/Write Flash and EEPROM Memories
– Read Device ID
80C51
Microcontrollers
– Block Erase
– Read/Write Configuration Bytes
– Bootloader Start
AT89C51AC3
UART
Bootloader
Description
This document describes the UART bootloader functionalities as well as the serial
protocol to efficiently perform operations on the on chip Flash (EEPROM) memories.
Additional information on the AT89C51AC3 product can be found in the AT89C51AC3
datasheet and the AT89C51AC3 errata sheet available on the Atmel web site.
The bootloader software package (source code and binary) currently used for produc-
tion is available from the Atmel web site.
Bootloader Revision
Purpose of Modifications
Date
Revision 1.0.1
First release
01/08/2003
Rev. 4386A–8051–10/04
Functional Description
The AT89C51AC3 Bootloader facilitates In-System Programming and In-Application
Programming.
In-System Programming In-System Programming allows the user to program or reprogram a microcontroller on-
chip Flash memory without removing it from the system and without the need of a pre-
programmed application.
Capability
The UART bootloader can manage a communication with a host through the serial net-
work. It can also access and perform requested operations on the on-chip Flash
Memory.
In-Application
Programming or Self-
Programming Capability
In-Application Programming (IAP) allows the reprogramming of a microcontroller on-
chip Flash memory without removing it from the system and while the embedded appli-
cation is running.
The UART bootloader contains some Application Programming Interface routines
named API routines allowing IAP by using the user’s firmware.
Block Diagram
This section describes the different parts of the bootloader. The figure below shows the
on-chip bootloader and IAP processes.
Figure 1. Bootloader Process Description
On chip
User
External host via the
UART Protocol
Communication
Application
IAP
ISP Communication
User Call
Management
Management
Flash Memory
Management
Flash
Memory
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ISP Communication
Management
The purpose of this process is to manage the communication and its protocol between
the on-chip bootloader and an external device (host). The on-chip bootloader imple-
ments a Serial protocol (see Section “Protocol”). This process translates serial
communication frames (UART) into Flash memory accesses (read, write, erase...).
User Call Management
Several Application Program Interface (API) calls are available to the application pro-
gram to selectively erase and program Flash pages. All calls are made through a
common interface (API calls) included in the bootloader. The purpose of this process is
to translate the application request into internal Flash Memory operations.
Flash Memory Management
This process manages low level accesses to the Flash memory (performs read and
write accesses).
Bootloader Configuration
Configuration and
Manufacturer Information
The table below lists Configuration and Manufacturer byte information used by the boot-
loader. This information can be accessed through a set of API or ISP commands.
Mnemonic
BSB
Description
Default value
FFh
Boot Status Byte
Software Boot Vector
Software Security Byte
Extra Byte
SBV
FCh
SSB
FFh
EB
FFh
Manufacturer
Id1: Family code
Id2: Product Name
Id3: Product Revision
58h
D7h
FFh
FEh
Mapping and Default Value of The 4 MSB of the Hardware Byte can be read/written by software (this area is called
Hardware Security Byte
Fuse bits). The 4 LSB can only be read by software and written by hardware in parallel
mode (with parallel programmer devices).
Bit Position
Mnemonic
X2B
Default Value
Description
7
U
To start in x1 mode
To map the boot area in code area between F800h-
FFFFh
6
BLJB
P
5
4
3
2
1
0
reserved
reserved
reserved
LB2
U
U
U
P
U
U
LB1
To lock the chip (see datasheet)
LB0
Note:
U: Unprogram = 1
P: Program = 0
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Security
The bootloader has Software Security Byte (SSB) to protect itself from user access or
ISP access.
The Software Security Byte (SSB) protects from ISP accesses. The command "Program
Software Security Bit" can only write a higher priority level. There are three levels of
security:
•
level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or level 2.
•
level 1: WRITE_SECURITY (FEh)
In this level it is impossible to write in the Flash memory, BSB and SBV.
The Bootloader returns an error message.
From level 1, one can write only level 2.
•
level 2: RD_WR_SECURITY (FCh)
Level 2 forbids all read and write accesses to/from the Flash memory.
The Bootloader returns an error message.
Only a full chip erase command can reset the software security bits.
Level 0
Any access allowed
Any access allowed
Level 1
Read only access allowed
Read only access allowed
Read only access allowed
Write level2 allowed
Read only access allowed
Read only access allowed
Not allowed
Level 2
All access not allowed
All access not allowed
All access not allowed
Read only access allowed
Read only access allowed
Read only access allowed
Not allowed
Flash/EEPROM
Fuse bit
BSB & SBV & EB Any access allowed
SSB Any access allowed
Manufacturer info Read only access allowed
Bootloader info
Erase block
Read only access allowed
Allowed
Full chip erase
Blank Check
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Software Boot Vector
The Software Boot Vector (SBV) forces the execution of a user bootloader starting at
address [SBV]00h in the application area (FM0).
The way to start this user bootloader is described in the section “Boot Process”.
UART Bootloader
User Bootloader
FM1
[SBV]00h
Application
FM0
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FLIP Software Program
FLIP is a PC software program running under Windows 9x / NT / 2K / XP and LINUX
that supports all Atmel C51 Flash microcontrollers.
This free software program is available on the Atmel web site.
In-System
Programming
The ISP allows the user to program or reprogram a microcontroller’s on-chip Flash
memory through the serial line without removing it from the system and without the need
of a pre-programmed application.
This section describes how to start the UART bootloader and the higher level protocol
over the serial line.
Boot Process
The bootloader can be activated in two ways:
•
•
Hardware conditions
Regular boot process
Hardware Condition
The Hardware conditions (EA = 1, PSEN = 0) during the RESET# falling edge force the
on-chip bootloader execution. In this way the bootloader can be carried out whatever the
user Flash memory content.
As PSEN is an output port in normal operating mode (running user application or boot-
loader code) after reset, it is recommended to release PSEN after falling edge of reset
signal. The hardware conditions are sampled at reset signal falling edge, thus they can
be released at any time when reset input is low.
To ensure correct microcontroller startup. The PSEN pin should not be tied to ground
during power-on.
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Regular Boot Process
bit ENBOOT in AUXR1 Register is
initialized with BLJB inverted
RESET
ENBOOT = 1
PC = F800h
FCON = 00h
Yes
Hardware
Condition
No
ENBOOT = 0
PC = 0000h
Yes
BLJB = 1
No
ENBOOT = 1
PC = F800h
FCON = 0Fh
Yes
FCON = 00h
No
No
SBV < F8h
Yes
Start Application
Start User Bootloader
Start Bootloader
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Physical Layer
The UART used to transmit information has the following configuration:
•
•
•
•
•
Character: 8-bit data
Parity: none
Stop: 2 bits
Flow control: none
Baud rate: autobaud is performed by the bootloader to compute the baud rate
chosen by the host.
Frame Description
The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summarized below.
Table 1. Intel Hex Type Frame
Record Mark ‘:’ Record length
Load Offset
Record Type
Data or Info
Checksum
1 byte
1 byte
2 bytes
1 bytes
n byte
1 byte
•
•
Record Mark:
–
Record Mark is the start of frame. This field must contain ’:’.
Record length:
–
Record length specifies the number of Bytes of information or data which
follows the Record Type field of the record.
•
Load Offset:
–
Load Offset specifies the 16-bit starting load offset of the data Bytes,
therefore this field is used only for
–
Data Program Record.
•
•
Record Type:
Record Type specifies the command type. This field is used to interpret the
remaining information within the frame.
Data/Info:
Data/Info is a variable length field. It consists of zero or more Bytes encoded
–
–
as pairs of hexadecimal digits. The meaning of data depends on the Record
Type.
•
Checksum:
The two’s complement of the 8-bit Bytes that result from converting each pair
–
of ASCII hexadecimal digits to one Byte of binary, and including the Record
Length field to and including the last Byte of the Data/Info field. Therefore,
the sum of all the ASCII pairs in a record after converting to binary, from the
Record Length field to and including the Checksum field, is zero.
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Protocol
Overview
An initialization step must be performed after each Reset. After microcontroller reset,
the bootloader waits for an autobaud sequence (see Section “Autobaud
Performances”).
When the communication is initialized the protocol depends on the record type issued
by the host.
Communication Initialization
The host initiates the communication by sending a ’U’ character to help the bootloader
to compute the baud rate (autobaud).
Figure 2. Initialization
Bootloader
Host
Init Communication
"U"
"U"
Performs Autobaud
If (not received "U")
Else
Sends Back ‘U’ Character
Communication Opened
Autobaud Performances
The bootloader supports a wide range of baud rates. It is also adaptable to a wide range
of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in
a received character. This information is then used to program the baud rate in terms of
timer counts based on the oscillator frequency. Table 2 shows the autobaud capabilities.
Table 2. Autobaud Performances
Frequency
(MHz)
Baudrate
(kHz)
1.8432
2
2.4576
OK
OK
OK
OK
OK
-
3
3.6864
OK
OK
OK
OK
OK
OK
-
4
OK
OK
OK
-
5
6
7.3728
OK
2400
OK
OK
OK
OK
-
OK
OK
OK
OK
OK
OK
OK
OK
-
OK
OK
OK
OK
OK
-
4800
-
-
-
-
-
-
OK
9600
OK
19200
38400
57600
115200
OK
-
OK
-
OK
-
-
-
-
OK
-
-
-
-
-
OK
Frequency
(MHz)
Baudrate
(kHz)
8
10
11.0592
OK
12
14.746
OK
16
20
24
26.6
OK
OK
OK
2400
4800
9600
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
OK
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Frequency
(MHz)
Baudrate
(kHz)
8
10
11.0592
OK
12
OK
OK
-
14.746
OK
16
OK
OK
OK
-
20
OK
OK
OK
-
24
OK
OK
OK
-
26.6
OK
OK
OK
-
19200
38400
57600
115200
OK
OK
-
-
-
-
-
-
OK
OK
OK
OK
OK
-
OK
Command Data Stream Protocol
All commands are sent using the same flow. Each frame sent by the host is echoed by
the bootloader.
Figure 3. Command Flow
Host
Bootloader
":"
":"
If (not received ":")
Sends first character of the
Frame
Else
Sends echo and start
reception
Sends frame (made of 2 ASCII
characters per Byte)
Echo analysis
Gets frame, and sends back echo
for each received Byte
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Programming the Flash or
EEPROM data
The flow described below shows how to program data in the Flash memory or in the
EEPROM data memory.
The bootloader programs on a page of 128 bytes basis when it is possible.
The host must take care that:
•
The data to program transmitted within a frame are in the same page.
Requests from Host
Record
Length
Record
Type
Load
Offset
Command Name
Data[0]
...
Data[127]
start
address
Program Flash
00h
07h
nb of Data
nb of Data
x
...
x
Program EEPROM
Data
start
address
x
...
x
Answers from Bootloader
The bootloader answers with:
•
•
•
‘.’ & ‘CR’ & ’LF’ when the data are programmed
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘P’ & ‘CR’ & ‘LF’ if the Security is set
Flow Description
Bootloader
Host
Write Command
’X’ & CR & LF
Send Write Command
Wait Write Command
OR
Checksum error
Wait Checksum Error
COMMAND ABORTED
Send Checksum error
NO_SECURITY
OR
’P’ & CR & LF
’.’ & CR & LF
Wait Security Error
Send Security error
COMMAND ABORTED
Wait Programming
Wait COMMAND_OK
COMMAND FINISHED
Send COMMAND_OK
Example
Programming Data (write 55h at address 0010h in the Flash)
HOST
: 01 0010 00 55 9A
BOOTLOADER
: 01 0010 00 55 9A . CR LF
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Read the Flash or EEPROM
Data
The flow described below allows the user to read data in the Flash memory or in the
EEPROM data memory. A blank check command is possible with this flow.
The device splits into blocks of 16 bytes the data to transfer to the Host if the number of
data to display is greater than 16 data bytes.
Requests from Host
Record
Record
Type
Load
Offset
Command Name
Length Data[0] Data[1] Data[2] Data[3] Data[4]
Read Flash
00h
01h
Blank check on
Flash
04h
x
05h
start address
end Address
Read EEPROM
Data
02h
Note:
The field “Load offset” is not used.
Answers from Bootloader
The bootloader answers to a read Flash or EEPROM Data memory command:
•
‘Address = data ‘ & ‘CR’ & ’LF’
up to 16 data by line.
•
•
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘L’ & ‘CR’ & ‘LF’ if the Security is set
The bootloader answers to blank check command:
•
•
•
•
‘.’ & ‘CR’ & ’LF’ when the blank check is ok
‘First Address wrong’ ‘CR’ & ‘LF’ when the blank check is fail
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘P’ & ‘CR’ & ‘LF’ if the Security is set
Flow Description: Blank Check
Command
Bootloader
Host
Blank Check Command
Send Blank Check Command
Wait Blank Check Command
OR
Checksum error
Flash blank
’X’ & CR & LF
Wait Checksum Error
Send Checksum error
Send COMMAND_OK
COMMAND ABORTED
’.’ & CR & LF
Wait COMMAND_OK
COMMAND FINISHED
OR
address & CR & LF
Send first Address
not erased
Wait Address not
erased
COMMAND FINISHED
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Example
Blank Check ok
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ko at address xxxx
HOST
: 05 0000 04 0000 7FFF 01 78
BOOTLOADER
: 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check with checksum error
HOST
: 05 0000 04 0000 7FFF 01 70
BOOTLOADER
: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Flow Description: Read
Command
Bootloader
Host
Display Command
Send Display Command
Wait Display Command
OR
Checksum error
’X’ & CR & LF
’L’ & CR & LF
Wait Checksum Error
Send Checksum Error
COMMAND ABORTED
RD_WR_SECURITY
OR
Wait Security Error
Send Security Error
COMMAND ABORTED
Read Data
All data read
Complete Frame
"Address = "
"Reading value"
CR & LF
Wait Display Data
Send Display Data
All data read
All data read
COMMAND FINISHED
COMMAND FINISHED
Note:
The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.
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Example
Display data from address 0000h to 0020h
HOST
: 05 0000 04 0000 0020 00 D7
: 05 0000 04 0000 0020 00 D7
0000=-----data------ CR LF
0010=-----data------ CR LF
0020=data CR LF
BOOTLOADER
BOOTLOADER
BOOTLOADER
BOOTLOADER
(16 data)
(16 data)
( 1 data)
Program Configuration
Information
The flow described below allows the user to program Configuration Information regard-
ing the bootloader functionality.
The Boot Process Configuration:
BSB
SBV
Fuse bits (BLJB and X2 bits) (see Section “Mapping and Default Value of Hardware
Security Byte”)
SSB
EB
Requests from Host
Record
Length
Record
Type
Load
Offset
Command Name
Erase SBV & BSB
Program SSB level1
Program SSB level2
Program BSB
Data[0]
Data[1]
00h
Data[2]
02h
04h
-
-
-
00h
02h
05h
06h
0Ah
01h
00h
03h
x
Program SBV
03h
03h
01h
value
Program EB
06h
Program bit BLJB
Program bit X2
04h
bit value
08h
Note:
1. The field “Load Offset” is not used
2. To program the BLJB and X2 bit the “bit value” is 00h or 01h.
Answers from Bootloader
The bootloader answers with:
•
•
•
‘.’ & ‘CR’ & ’LF’ when the value is programmed
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘P’ & ‘CR’ & ‘LF’ if the Security is set
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4386A–8051–10/04
Flow Description
Bootloader
Host
Write Command
’X’ & CR & LF
Send Write Command
Wait Write Command
OR
Checksum error
Wait Checksum Error
Send Checksum error
COMMAND ABORTED
NO_SECURITY
OR
’P’ & CR & LF
’.’ & CR & LF
Wait Security Error
Send Security error
COMMAND ABORTED
Wait Programming
Wait COMMAND_OK
COMMAND FINISHED
Send COMMAND_OK
Example
Programming Atmel function (write SSB to level 2)
HOST
: 02 0000 03 05 01 F5
BOOTLOADER
: 02 0000 03 05 01 F5. CR LF
Writing Frame (write BSB to 55h)
HOST
: 03 0000 03 06 00 55 9F
BOOTLOADER
: 03 0000 03 06 00 55 9F . CR LF
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Read Configuration
Information or Manufacturer
Information
The flow described below allows the user to read the configuration or manufacturer
information.
Requests from Host
Record
Length
Record
Type
Load
Offset
Command Name
Read Manufacturer Code
Read Family Code
Read Product Name
Read Product Revision
Read SSB
Data[0]
Data[1]
00h
01h
02h
03h
00h
01h
02h
06h
00h
00h
01h
00h
00h
Read BSB
05h
x
02h
07h
Read SBV
Read EB
Read HSB (Fuse bit)
Read Device ID1
Read Device ID2
Read Bootloader version
0Bh
0Eh
0Fh
Note:
The field “Load Offset” is not used
Answers from Bootloader
The bootloader answers with:
•
•
•
‘value’ & ‘.’ & ‘CR’ & ’LF’ when the value is programmed
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘P’ & ‘CR’ & ‘LF’ if the Security is set
Flow Description
Bootloader
Host
Read Command
’X’ & CR & LF
Send Read Command
Wait Read Command
OR
Checksum error
Wait Checksum Error
COMMAND ABORTED
Send Checksum error
RD_WR_SECURITY
OR
’L’ & CR & LF
Wait Security Error
Send Security error
COMMAND ABORTED
Read Value
’value’ & ’.’ & CR & LF
Wait Value of Data
Send Data Read
COMMAND FINISHED
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Example
Read function (read SBV)
HOST
: 02 0000 05 07 02 F0
: 02 0000 05 07 02 F0 Value . CR LF
BOOTLOADER
Atmel Read function (read Bootloader version)
HOST
: 02 0000 01 02 00 FB
BOOTLOADER
: 02 0000 01 02 00 FB Value . CR LF
Erase the Flash
The flow described below allows the user to erase the Flash memory.
Two modes of Flash erasing are possible:
•
•
Full Chip erase
Block erase
The Full Chip erase command erases the whole Flash (64 Kbytes) and sets some Con-
figuration Bytes at their default values:
•
•
•
BSB = FFh
SBV = FCh
SSB = FFh (NO_SECURITY)
The full chip erase is always executed whatever the Software Security Byte value is.
The Block erase command erases only a part of the Flash.
Three Blocks are defined in the AT89C51AC3:
•
•
•
•
•
block0 (From 0000h to 1FFFh)
block1 (From 2000h to 3FFFh)
block2 (From 4000h to 7FFFh)
block3 (From 8000h to BFFFh)
block4 (From C000h to FFFFh)
Requests from Host
Record
Length
Record
Type
Load
Offset
Command Name
Erase block0 (0k to 8k)
Erase block1 (8k to 16k)
Erase block2 (16k to 32k)
Erase block3 (32k to 48k)
Erase block4 (48k to 64k)
Full chip erase
Data[0]
01h
Data[1]
00h
20h
40h
80h
C0h
-
02h
01h
03h
x
07h
Answers from Bootloader
As the Program Configuration Information flows, the erase block command has three
possible answers:
•
•
•
‘.’ & ‘CR’ & ’LF’ when the data are programmed
‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
‘P’ & ‘CR’ & ‘LF’ if the Security is set
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Flow Description
Bootloader
Host
Erase Command
’X’ & CR & LF
Send Erase Command
Wait Erase Command
OR
Checksum error
Wait Checksum Error
Send Checksum error
COMMAND ABORTED
NO_SECURITY
OR
’P’ & CR & LF
’.’ & CR & LF
Wait Security Error
Send Security error
COMMAND ABORTED
Wait Erasing
Wait COMMAND_OK
COMMAND FINISHED
Send COMMAND_OK
Example
Full Chip Erase
HOST
: 01 0000 03 07 F5
: 01 0000 03 07 F5 . CR LF
BOOTLOADER
Erase Block1(8k to 16k)
HOST
: 02 0000 03 01 20 DA
: 02 0000 03 01 20 DA . CR LF
BOOTLOADER
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Start the Application
The flow described below allows to start the application directly from the bootloader
upon a specific command reception.
Two options are possible:
•
Start the application with a reset pulse generation (using watchdog).
When the device receives this command the watchdog is enabled and the
bootloader enters a waiting loop until the watchdog resets the device.
Take care that if an external reset chip is used the reset pulse in output may be
wrong and in this case the reset sequence is not correctly executed.
•
Start the application without reset
A jump at the address 0000h is used to start the application without reset.
Requests from Host
Record
type
Load
Offset
Record
Length
Command Name
Data[0]
Data[1]
Data[2]
Data[3]
Start application with a reset
pulse generation
02h
04h
00h
-
-
03h
x
03h
Start application with a jump
at “address”
01h
Address
Answer from Bootloader
Example
No answer is returned by the device.
Start Application with reset pulse
HOST
: 02 0000 03 03 00 F8
: 02 0000 03 03 00 F8
BOOTLOADER
Start Application without reset at address 0000h
HOST
: 04 0000 03 03 01 00 00 F5
: 04 0000 03 03 01 00 00 F5
BOOTLOADER
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In-Application
Programming/Self-
Programming
The IAP allows to reprogram a microcontroller on-chip Flash memory without removing
it from the system and while the embedded application is running.
The user application can call some Application Programming Interface (API) routines
allowing IAP. These API are executed by the bootloader.
To call the corresponding API, the user must use a set of Flash_api routines which can
be linked with the application.
Example of Flash_api routines are available on the Atmel web site on the software
package:
C Flash Drivers for the AT89C51AC3
The Flash_api routines on the package work only with the UART bootloader.
The Flash_api routines are listed in Appendix-2.
API Call
Process
The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.
All calls are made through a common interface “USER_CALL” at the address FFF0h.
The jump at the USER_CALL must be done by LCALL instruction to be able to come-
back in the application.
Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.
The interrupts are not disabled by the bootloader.
Constraints
Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled
when returning.
Interrupts must also be disabled before accessing EEPROM Data then re-enabled after.
The user must take care of hardware watchdog before launching a Flash operation.
For more information regarding the Flash writing time see the AT89C51AC3 datasheet.
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API Commands
Several types of APIs are available:
•
•
•
•
•
Read/Program Flash and EEPROM Data memory
Read Configuration and Manufacturer Information
Program Configuration Information
Erase Flash
Start bootloader
Read/Program Flash and
EEPROM Data Memory
All routines to access EEPROM Data are managed directly from the application without
using bootloader resources.
To read the Flash memory the bootloader is not involved.
For more details on these routines see the AT89C51AC3 datasheet sections “Pro-
gram/Code Memory” and “EEPROM Data Memory”
Two routines are available to program the Flash:
–
–
__api_wr_code_byte
__api_wr_code_page
•
•
The application program load the column latches of the Flash then call the
__api_wr_code_byte or __api_wr_code_page see datasheet in section
“Program/Code Memory”.
Parameter settings
API_name
R1
DPTR0
DPTR1
Acc
Address in
Flash
memory to
write
__api_wr_code_byte
02h
-
Value to write
Address of
the first Byte
to program in
the Flash
Address in
XRAM of the
first data to
program
Number of Byte
to program
__api_wr_code_page
09h
memory
•
instruction: LCALL FFF0h.
Note:
No special resources are used by the bootloader during this operation
Read Configuration and
Manufacturer Information
•
Parameter settings
API_name
__api_rd_HSB
__api_rd_BSB
__api_rd_SBV
__api_rd_SSB
__api_rd_EB
R1
DPTR0
0000h
0001h
0002h
0000h
0006h
DPTR1
Acc
0Bh
07h
07h
07h
07h
x
x
x
x
x
return HSB
return BSB
return SBV
return SSB
return EB
return
manufacturer id
__api_rd_manufacturer
__api_rd_device_id1
00h
00h
0000h
0001h
x
x
return id1
20
4386A–8051–10/04
API_name
R1
DPTR0
0002h
0003h
0000h
DPTR1
Acc
__api_rd_device_id2
__api_rd_device_id3
__api_rd_bootloader_version
00h
00h
0Fh
x
x
x
return id2
return id3
return value
•
•
Instruction: LCALL FFF0h.
At the complete API execution by the bootloader, the value to read is in the
api_value variable.
Note:
No special resources are used by the bootloader during this operation
Program Configuration
Information
•
Parameter settings
API Name
__api_set_X2
R1
DPTR0
0008h
0008h
0004h
0004h
0000h
0001h
0006h
FFh
DPTR1
Acc
0Ah
0Ah
0Ah
0Ah
06h
06h
06h
05h
05h
05h
x
x
x
x
x
x
x
x
x
x
00h
__api_clr_X2
01h
__api_set_BLJB
__api_clr_BLJB
00h
01h
__api_wr_BSB
value to write
__api_wr_SBV
value to write
__api_wr_EB
value to write
__api_wr_SSB_LEVEL0
__api_wr_SSB_LEVEL1
__api_wr_SSB_LEVEL2
x
x
x
FEh
FCh
•
instruction: LCALL FFF0h.
Note:
1. See in the AT89C51AC3 datasheet the time that a write operation takes.
2. No special resources are used by the bootloader during these operations
21
4386A–8051–10/04
Erase Flash
The AT89C51AC3 flash memory is divided in several blocks:
Block 0: from address 0000h to 1FFFh
Block 1: from address 2000h to 3FFFh
Block 2: from address 4000h to 7FFFh
These three blocks contain 128 pages.
•
Parameter settings
API name
R1
DPTR0
0000h
2000h
4000h
8000h
C000h
DPTR1
Acc
__api_erase_block0
__api_erase_block1
__api_erase_block2
__api_erase_block3
__api_erase_block4
instruction: LCALL FFF0h.
x
x
x
x
x
x
x
x
x
x
01h
•
Note:
1. See the AT89C51AC3 datasheet for the time that a write operation takes and this
time must multiply by the number of pages.
2. No special resources are used by the bootloader during these operations
Start Bootloader
This routine allows to start at the beginning of the bootloader as after a reset. After call-
ing this routine the regular boot process is performed and the communication must be
opened before any action.
•
•
•
No special parameter setting
Set bit ENBOOT in AUXR1 register
instruction: LJUMP or LCALL at address F800h
22
4386A–8051–10/04
APPENDIX-A
Table 3. Summary of Frames from Host
Record
Length
Record
Type
Command
Offset
Data[0]
Data[1]
Data[2]
Data[3]
Data[4]
nb of data
(up to 80h)
start
address
Program Nb Data Byte in Flash.
00h
x
x
x
x
x
Erase block0 (0000h-1FFFh)
Erase block1 (2000h-3FFFh)
Erase block2 (4000h-7FFFh)
Erase block3 (8000h-BFFFh)
Erase block4 (C000h-FFFFh)
00h
20h
40h
80h
C0h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
02h
x
01h
Start application with a reset pulse
generation
02h
04h
x
x
00h
01h
-
-
-
-
03h
Start application with a jump at
“address”
address
03h
Erase SBV & BSB
Program SSB level 1
Program SSB level 2
Program BSB
x
x
x
x
x
x
x
x
x
04h
05h
00h
00h
01h
00h
01h
06h
-
-
-
-
-
-
-
-
-
-
-
-
02h
03h
-
-
-
-
value
value
value
-
-
Program SBV
06h
-
Program EB
-
Full Chip Erase
01h
03h
07h
0Ah
-
Program bit BLJB
Program bit X2
04h
08h
bit value
bit value
-
-
Read Flash
00h
Blank Check
04h
05h
x
Start Address
End Address
01h
Read EEPROM Data
Read Manufacturer Code
Read Family Code
Read Product Name
Read Product Revision
Read SSB
02h
00h
01h
02h
03h
00h
01h
02h
06h
00h
00h
01h
00h
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
00h
07h
Read BSB
05h
02h
x
Read SBV
Read EB
Read Hardware Byte
Read Device Boot ID1
Read Device Boot ID2
Read Bootloader Version
0Bh
0Eh
0Fh
x
nb of data
(up to 80h)
start
address
Program Nb Data byte in EEPROM
00h
x
x
x
x
23
4386A–8051–10/04
APPENDIX-B
Table 4. API Summary
Bootloader
Execution
Function Name
R1
DPTR0
DPTR1
Acc
__api_rd_code_byte
no
Address in
Flash memory
to write
__api_wr_code_byte
__api_wr_code_page
yes
02h
09h
-
Value to write
Address of the
first Byte to
program in the
Flash memory
Address in
XRAM of the
first data to
program
Number of Byte to
program
yes
__api_erase_block0
__api_erase_block1
__api_erase_block2
__api_erase_block3
__api_erase_block4
__api_rd_HSB
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
no
01h
01h
01h
01h
01h
0Bh
0Ah
0Ah
0Ah
0Ah
07h
06h
07h
06h
06h
07h
05h
05h
05h
07h
06h
00h
00h
00h
00h
0Fh
0000h
2000h
4000h
8000h
C000h
0000h
0008h
0008h
0004h
0004h
0001h
0000h
0002h
0001h
0001h
0000h
00FFh
00FEh
00FCh
0006h
0006h
0000h
0001h
0002h
0003h
0000h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
return value
00h
__api_set_X2
__api_clr_X2
01h
__api_set_BLJB
00h
__api_clr_BLJB
01h
__api_rd_BSB
return value
value
__api_wr_BSB
__api_rd_SBV
return value
value
__api_wr_SBV
__api_erase_SBV
__api_rd_SSB
FCh
return value
x
__api_wr_SSB_level0
__api_wr_SSB_level1
__api_wr_SSB_level2
__api_rd_EB
x
x
return value
value
__api_wr_EB
__api_rd_manufacturer
__api_rd_device_id1
__api_rd_device_id2
__api_rd_device_id3
__api_rd_bootloader_version
__api_eeprom_busy
return value
return value
return value
return value
return value
24
4386A–8051–10/04
Table 4. API Summary (Continued)
Bootloader
Execution
Function Name
__api_rd_eeprom_byte
__api_wr_eeprom_byte
__api_start_bootloader
R1
DPTR0
DPTR1
Acc
no
no
no
25
4386A–8051–10/04
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