AT89C51RC2-RLTUM_技术文档

Features

• 80C52 Compatible

– 8051 Pin and Instruction Compatible

– Four 8-bit I/O Ports

– Three 16-bit Timer/Counters

– 256 Bytes Scratch Pad RAM

– 9 Interrupt Sources with 4 Priority Levels

– Dual Data Pointer

• Variable Length MOVX for Slow RAM/Peripherals

• ISP (In-system Programming) Using Standard V_CCPower Supply

• Boot ROM Contains Low Level Flash Programming Routines and a Default Serial

Loader

8-bit

• High-speed Architecture

Microcontroller

with 16K/

32K Bytes Flash

– In Standard Mode:

40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– 16K/32K Bytes On-chip Flash Program/Data Memory

– Byte and Page (128 Bytes) Erase and Write

– 100K Write Cycles

AT89C51RB2

AT89C51RC2

• On-chip 1024 Bytes Expanded RAM (XRAM)

– Software Selectable Size (0, 256, 512, 768, 1024 Bytes)

– 256 Bytes Selected at Reset for TS87C51RB2/RC2 Compatibility

• Keyboard Interrupt Interface on Port P1

• SPI Interface (Master/Slave Mode)

• 8-bit Clock Prescaler

• Improved X2 Mode with Independent Selection for CPU and Each Peripheral

• Programmable Counter Array 5 Channels

– High-speed Output

– Compare/Capture

– Pulse Width Modulator

– Watchdog Timer Capabilities

• Asynchronous Port Reset

• Full Duplex Enhanced UART

• Dedicated Baud Rate Generator for UART

• Low EMI (Inhibit ALE)

• Hardware Watchdog Timer (One-time Enabled with Reset-out)

• Power Control Modes

– Idle Mode

– Power-down Mode

– Power-off Flag

• Power Supply:

– 2.7 to 3.6 (3V Version)

– 2.7 to 5.5V (5V Version)

• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)

• Packages: PDIL40, PLCC44, VQFP44

Description

The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro-

controllers. It contains a 16K or 32K Bytes Flash memory block for program and data.

The Flash memory can be programmed either in parallel mode or in serial mode with

the ISP capability or with software. The programming voltage is internally generated

from the standard VCC pin.

Rev. 4180E–8051–10/06

The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal

RAM, a 9-source 4-level interrupt controller and three timer/counters.

In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM of

1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a

more versatile serial channel that facilitates multiprocessor communication (EUART)

and a speed improvement mechanism (X2 mode).

The Pinout is the standard 40/44 pins of the C52.

The fully static design reduces system power consumption of the AT89C51RB2/RC2 by

allowing it to bring the clock frequency down to any value, even DC, without loss of data.

The AT89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8-bit

clock prescaler for further reduction in power consumption. In Idle mode, the CPU is fro-

zen while the peripherals and the interrupt system are still operating. In power-down

mode, the RAM is saved and all other functions are inoperative.

The added features of the AT89C51RB2/RC2 make it more powerful for applications

that need pulse width modulation, high speed I/O and counting capabilities such as

alarms, motor control, corded phones, and smart card readers.

Table 1. Memory Size

TOTAL RAM

Part Number

AT89C51RB2

AT89C51RC2

AT89C51IC2

Flash (Bytes)

XRAM (Bytes)

1024

(Bytes)

I/O

32

16K

32K

1280

1024

1280

1024

1280

2

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Block Diagram

Figure 1. Block Diagram

(2) (2)

(1)

(1) (1) (1)

XTAL1

XTAL2

Boot

ROM

2Kx8

EUART

+

BRG

Flash

32Kx8 or

16Kx8

RAM

256x8

XRAM

1Kx8

PCA

Timer2

ALE/PROG

PSEN

C51

CORE

IB-bus

CPU

EA

(2)

Parallel I/O Ports & Ext. Bus

Port 0Port 1

Timer 0

Timer 1

INT

Ctrl

Watch Key

Dog Board

RD

SPI

Port 2 Port 3

WR

(2) (2)

(1) (1) (1)

(1)

Notes: 1. Alternate function of Port 1.

2. Alternate function of Port 3.

3

4180E–8051–10/06

SFR Mapping

The Special Function Registers (SFRs) of the AT89C51RB2/RC2 fall into the following

categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP

I/O port registers: P0, P1, P2, P3

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,

RCAP2L, RCAP2H

•

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,

CCAPxL (x: 0 to 4)

•

Power and clock control registers: PCON

Hardware Watchdog Timer registers: WDTRST, WDTPRG

Interrupt system registers: IEN0, IPL0, IPH0, IEN1, IPL1, IPH1

Keyboard Interface registers: KBE, KBF, KBLS

SPI registers: SPCON, SPSTR, SPDAT

BRG (Baud Rate Generator) registers: BRL, BDRCON

Flash register: FCON

Clock Prescaler register: CKRL

Others: AUXR, AUXR1, CKCON0, CKCON1

4

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 2. C51 Core SFRs

Mnemonic

ACC

B

Add Name

7

6

5

4

3

2

1

0

E0h Accumulator

F0h B Register

PSW

SP

D0h Program Status Word

81h Stack Pointer

CY

AC

F0

RS1

RS0

OV

F1

P

DPL

82h Data Pointer Low Byte

83h Data Pointer High Byte

DPH

Table 3. System Management SFRs

Mnemonic

Add Name

7

6

5

-

4

3

2

1

0

PCON

87h Power Control

SMOD1

SMOD0

POF

GF1

XRS1

GF3

GF0

XRS0

0

PD

EXTRAM

-

IDL

AO

AUXR

8Eh Auxiliary Register 0

A2h Auxiliary Register 1

97h Clock Reload Register

8Fh Clock Control Register 0

AFh Clock Control Register 1

DPU

-

M0

XRS2

AUXR1

-

ENBOOT

CKRL5

PCAX2

-

CKRL4

SIX2

-

DPS

CKRL0

X2

CKRL

CKRL7

CKRL6

WDTX2

-

CKRL3

T2X2

-

CKRL2

T1X2

-

CKRL1

T0X2

-

CKCKON0

CKCKON1

-

SPIX2

Table 4. Interrupt SFRs

Mnemonic

Add Name

7

6

EC

-

5

4

3

2

1

0

IEN0

A8h Interrupt Enable Control 0

B1h Interrupt Enable Control 1

EA

ET2

ES

ET1

EX1

ET0

EX0

IEN1

-

PHS

PLS

-

ESPI

PX1H

PX1L

SPIH

SPIL

EI2C

PT0H

PT0L

IE2CH

IE2CL

KBD

PX0H

PX0L

KBDH

KBDL

IPH0

B7h Interrupt Priority Control High 0

B8h Interrupt Priority Control Low 0

B3h Interrupt Priority Control High 1

B2h Interrupt Priority Control Low 1

PPCH

PT2H

PT1H

IPL0

PPCL

PT2L

PT1L

IPH1

-

IPL1

-

Table 5. Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

P0

P1

P2

P3

80h 8-bit Port 0

90h 8-bit Port 1

A0h 8-bit Port 2

B0h 8-bit Port 3

5

4180E–8051–10/06

Table 6. Timer SFRs

Mnemonic

TCON

TMOD

TL0

Add Name

7

6

5

4

3

2

1

0

88h Timer/Counter 0 and 1 Control

89h Timer/Counter 0 and 1 Modes

8Ah Timer/Counter 0 Low Byte

8Ch Timer/Counter 0 High Byte

8Bh Timer/Counter 1 Low Byte

8Dh Timer/Counter 1 High Byte

A6h Watchdog Timer Reset

TF1

TR1

C/T1#

TF0

M11

TR0

M01

IE1

IT1

IE0

M10

IT0

M00

GATE1

GATE0

C/T0#

TH0

TL1

TH1

WDTRST

WDTPRG

T2CON

T2MOD

A7h Watchdog Timer Program

C8h Timer/Counter 2 control

C9h Timer/Counter 2 Mode

-

TF2

-

EXF2

-

RCLK

-

TCLK

-

WTO2

TR2

-

WTO1

C/T2#

T2OE

WTO0

CP/RL2#

DCEN

EXEN2

-

Timer/Counter 2 Reload/Capture

High Byte

RCAP2H

RCAP2L

CBh

Timer/Counter 2 Reload/Capture

Low Byte

CAh

TH2

TL2

CDh Timer/Counter 2 High Byte

CCh Timer/Counter 2 Low Byte

Table 7. PCA SFRs

Mnemo-

nic

Add Name

7

6

5

4

3

CCF3

-

2

1

0

CCON

CMOD

CL

D8h PCA Timer/Counter Control

D9h PCA Timer/Counter Mode

E9h PCA Timer/Counter Low Byte

F9h PCA Timer/Counter High Byte

CF

CR

-

CCF4

-

CCF2

CPS1

CCF1

CPS0

CCF0

ECF

CIDL

WDTE

CH

CCAPM0 DAh PCA Timer/Counter Mode 0

CCAPM1 DBh PCA Timer/Counter Mode 1

CCAPM2 DCh PCA Timer/Counter Mode 2

CCAPM3 DDh PCA Timer/Counter Mode 3

CCAPM4 DEh PCA Timer/Counter Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

TOG0

PWM0

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

MAT1

MAT2

MAT3

MAT4

TOG1

TOG2

TOG3

TOG4

PWM1

PWM2

PWM3

PWM4

-

CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0

CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0

CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0

CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0

CCAP4H FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0

CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0

CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0

CCAP2L ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0

CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0

CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0

6

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 8. Serial I/O Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

SCON

98h Serial Control

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SBUF

99h Serial Data Buffer

B9h Slave Address Mask

A9h Slave Address

9Bh Baud Rate Control

9Ah Baud Rate Reload

SADEN

SADDR

BDRCON

BRL

BRR

TBCK

RBCK

SPD

SRC

Table 9. SPI Controller SFRs

Mnemonic

SPCON

SPSTA

Add Name

7

6

5

4

3

2

1

0

C3h SPI Control

C4h SPI Status

C5h SPI Data

SPR2

SPIF

SPD7

SPEN

WCOL

SPD6

SSDIS

SSERR

SPD5

MSTR

MODF

SPD4

CPOL

-

CPHA

-

SPR1

-

SPR0

-

SPDAT

SPD3

SPD2

SPD1

SPD0

Table 10. Keyboard Interface SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

KBLS

9Ch Keyboard Level Selector

9Dh Keyboard Input Enable

9Eh Keyboard Flag Register

KBLS7

KBE7

KBF7

KBLS6

KBE6

KBF6

KBLS5

KBE5

KBF5

KBLS4

KBE4

KBF4

KBLS3

KBE3

KBF3

KBLS2

KBE2

KBF2

KBLS1

KBE1

KBF1

KBLS0

KBE0

KBF0

KBE

KBF

7

4180E–8051–10/06

Table 11 shows all SFRs with their address and their reset value.

Table 11. SFR Mapping

Bit

addressable

Non Bit addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

CH

CCAP0H

XXXX

CCAP1H

XXXX

CCAPL2H

XXXX

CCAPL3H

XXXX

CCAPL4H

XXXX

F8h

F0h

E8h

E0h

FFh

F7h

EFh

E7h

0000 0000

B

0000 0000

CL

CCAP0L

CCAP1L

CCAPL2L

CCAPL3L

CCAPL4L

0000 0000

XXXX XXXX

ACC

0000 0000

CCON

CMOD

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

D8h

D0h

C8h

C0h

DFh

D7h

CFh

C7h

00X0 0000

00XX X000

X000 0000

PSW

0000 0000

FCON⁽¹⁾

XXXX 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

SPCON

SPSTA

SPDAT

0001 0100

0000 0000

XXXX XXXX

IPL0

SADEN

B8h

B0h

A8h

A0h

98h

90h

88h

80h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

X000 000

0000 0000

P3

IEN1

IPL1

IPH1

IPH0

1111 1111

XXXXX 000

XXXXX000

XXXX X000

X000 0000

IEN0

SADDR

CKCON1

0000 0000

XXXX XXX0

P2

AUXR1

WDTRST

WDTPRG

1111 1111

XXXXX0X0

XXXX XXXX

XXXX X000

SCON

SBUF

BRL

BDRCON

KBLS

KBE

KBF

0000 0000

XXXX XXXX

0000 0000

XXX0 0000

0000 0000

P1

CKRL

1111 1111

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON0

AUXR

XX0X 0000

0000 0000

P0

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

1111 1111

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

1.

FCON access is reserved for the Flash API and ISP software.

Reserved

8

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Pin Configurations

Figure 2. Pin Configurations

P1.0/T2

40

39

38

1

2

VCC

P0.0/AD0

P0.1/AD1

P1.1/T2EX/SS

P1.2/ECI

P1.3CEX0

P1.4/CEX1

3

4

37 P0.2/AD2

6

5 4 3 2 1 44 43 42 41 40

P0.3/AD3

P0.4/AD4

36

35

34

33

32

31

30

5

6

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEx4/MOSI

RST

39

38

7

8

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7CEX4/MOSI

RST

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P0.5/AD5

P0.6/AD6

P0.7/AD7

7

8

37

9

10

36

35

34

33

9

P3.0/RxD

NIC*

11

12

13

EA

P3.0/RxD 10

PDIL40

ALE/PROG

PSEN

P3.1/TxD

11

12

13

PLCC44

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

29

28

ALE/PROG

PSEN

P3.2/INT0

P3.3/INT1

P3.4/T0

P2.7/A15

P2.6/A14

14

15

16

17

32

31

30

29

P3.4/T0 14

27

26

P2.7/A15

P2.6/A14

P2.5/A13

15

16

P3.5/T1

P2.4/A12

P2.3/A11

P3.5/T1

25

P3.6/WR

18 19 20 21 22 23 24 25 26 27 28

17

18

19

20

24

23

22

21

P3.7/RD

XTAL2

P2.2/A10

P2.1/A9

P2.0/A8

XTAL1

VSS

44 43 42 41 40 39

38 37 36 35 34

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEX4/MOSI

RST

33

32

1

2

31

30

29

28

27

3

4

P3.0/RxD

NIC*

5

6

7

8

VQFP44 1.4

NIC*

P3.1/TxD

ALE/PROG

PSEN

26

25

24

P3.2/INT0

P3.3/INT1

P3.4/T0

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

23

P3.5/T1

12 13 141516 17 18 19202122

*NIC: No Internal Connection

9

4180E–8051–10/06

Table 12. Pin Description for 40 - 44 Pin Packages

Pin Number

Mnemonic

DIL

LCC

VQFP44 1.4

Type

Name and Function

V_SS

20

22

16

I

Ground: 0V reference

Power Supply: This is the power supply voltage for normal, idle and power-down

operation

V_CC

40

44

38

I

P0.0 - P0.7

39 - 32

43 - 36

37 - 30

I/O

Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s

written to them float and can be used as high impedance inputs. Port 0 must be

polarized to V_CCor V_SSin order to prevent any parasitic current consumption. Port 0

is also the multiplexed low-order address and data bus during access to external

program and data memory. In this application, it uses strong internal pull-up when

emitting 1s. Port 0 also inputs the code Bytes during Flash programming. External

pull-ups are required during program verification during which P0 outputs the code

Bytes.

P1.0 - P1.7

1 - 8

2 - 9

40 - 44

1 - 3

I/O

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 1 pins that are externally pulled low will source current

because of the internal pull-ups. Port 1 also receives the low-order address Byte

during memory programming and verification.

Alternate functions for AT89C51RB2/RC2 Port 1 include:

1

2

3

40

41

I/O

I

P1.0: Input/Output

T2 (P1.0): Timer/Counter 2 external count input/Clockout

P1.1: Input/Output

T2EX: Timer/Counter 2 Reload/Capture/Direction Control

SS: SPI Slave Select

I

3

4

5

6

4

5

6

7

42

43

44

1

I/O

I

P1.2: Input/Output

ECI: External Clock for the PCA

I/O

P1.3: Input/Output

CEX0: Capture/Compare External I/O for PCA Module 0

P1.4: Input/Output

CEX1: Capture/Compare External I/O for PCA Module 1

P1.5: Input/Output

CEX2: Capture/Compare External I/O for PCA Module 2

MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave peripheral. When

SPI is in slave mode, MISO outputs data to the master controller.

7

8

9

2

3

I/O

P1.6: Input/Output

CEX3: Capture/Compare External I/O for PCA Module 3

SCK: SPI Serial Clock

SCK outputs clock to the slave peripheral

P1.7: Input/Output:

I/O

10

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 12. Pin Description for 40 - 44 Pin Packages (Continued)

Pin Number

Mnemonic

DIL

LCC

VQFP44 1.4

Type

I/O

Name and Function

CEX4: Capture/Compare External I/O for PCA Module 4

MOSI: SPI Master Output Slave Input line

P1.0 - P1.7

I/O

When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI

is in slave mode, MOSI receives data from the master controller.

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock

generator circuits.

XTAL1

19

21

15

I

XTAL2

18

20

14

O

Crystal 2: Output from the inverting oscillator amplifier

P2.0 - P2.7

21 - 28

24 - 31

18 - 25

I/O

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 2 pins that are externally pulled low will source current

because of the internal pull-ups. Port 2 emits the high - order address Byte during

fetches from external program memory and during accesses to external data

memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses

strong internal pull-ups emitting 1s. During accesses to external data memory that

use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some

Port 2 pins receive the high order address bits during EPROM programming and

verification:

P2.0 to P2.5 for 16 KB devices

P2.0 to P2.6 for 32KB devices

P3.0 - P3.7

10 - 17

11,

13 - 19

5,

7 - 13

I/O

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 3 pins that are externally pulled low will source current

because of the internal pull-ups. Port 3 also serves the special features of the

80C51 family, as listed below.

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

I

10

11

12

13

I

O

Reset: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to V_SSpermits a power-on reset using

only an external capacitor to V_CC. This pin is an output when the hardware

watchdog forces a system reset.

RST

9

10

33

4

I/O

ALE/PROG

30

27

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low Byte of

the address during an access to external memory. In normal operation, ALE is

emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can

be used for external timing or clocking. Note that one ALE pulse is skipped during

each access to external data memory. This pin is also the program pulse input

(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR. 0

bit. With this bit set, ALE will be inactive during internal fetches.

11

4180E–8051–10/06

Table 12. Pin Description for 40 - 44 Pin Packages (Continued)

Pin Number

Mnemonic

DIL

LCC

VQFP44 1.4

Type

Name and Function

PSEN

29

32

26

O

Program Strobe Enable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to

external data memory. PSEN is not activated during fetches from internal program

memory.

EA

31

35

29

I

External Access Enable: EA must be externally held low to enable the device to

fetch code from external program memory locations 0000H to FFFFH (RD). If

security level 1 is programmed, EA will be internally latched on Reset.

12

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Port Types

AT89C51RB2/RC2 I/O ports (P1, P2, P3) implement the quasi-bidirectional output that

is common on the 80C51 and most of its derivatives. This output type can be used as

both an input and output without the need to reconfigure the port. This is possible

because when the port outputs a logic high, it is weakly driven, allowing an external

device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink

a fairly large current. These features are somewhat similar to an open drain output

except that there are three pull-up transistors in the quasi-bidirectional output that serve

different purposes. One of these pull-ups, called the "weak" pull-up, is turned on when-

ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small

current that will pull the pin high if it is left floating. A second pull-up, called the "medium"

pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is

also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidi-

rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an

external device, the medium pull-up turns off, and only the weak pull-up remains on. In

order to pull the pin low under these conditions, the external device has to sink enough

current to overpower the medium pull-up and take the voltage on the port pin below its

input threshold.

The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up

low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from

a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two

CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all

ports when latch data is logical 0.

The quasi-bidirectional port configuration is shown in Figure 3.

Figure 3. Quasi-Bidirectional Output

P

2 CPU

Clock Delay

Strong

Weak

Medium

Port Latch

Data

N

DPU

AUXR.7

Input

Data

13

4180E–8051–10/06

Oscillator

To optimize the power consumption and execution time needed for a specific task, an

internal, prescaler feature has been implemented between the oscillator and the CPU

and peripherals.

Registers

Table 13. CKRL Register

CKRL – Clock Reload Register (97h)

7

6

5

4

3

2

1

0

CKRL7

CKRL6

CKRL5

CKRL4

CKRL3

CKRL2

CKRL1

CKRL0

Bit Number

Mnemonic

CKRL

Description

Clock Reload Register

7:0

Prescaler value

Reset Value = 1111 1111b

Not bit addressable

Table 14. PCON Register

PCON – Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit Number

Bit Mnemonic Description

Serial Port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

SMOD1

SMOD0

-

Serial Port Mode bit 0

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

6

5

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-off Flag

Cleared to recognize next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can

also be set by software.

4

POF

General-purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

General-purpose Flag

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle Mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b Not bit addressable

14

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Functional Block

Diagram

Figure 4. Functional Oscillator Block Diagram

Reload

Reset

CKRL

F_OSC

Xtal1

Osc

1

0

8-bit

Prescaler-Divider

Xtal2

:2

1

0

CLK

X2

Peripheral Clock

PERIPH

CKCON0

CLK

CPU clock

CPU

Idle

CKRL = 0xFF?

Prescaler Divider

•

A hardware RESET puts the prescaler divider in the following state:

CKRL = FFh: F_{CLK CPU}= F_{CLK PERIPH}= F_OSC/2 (Standard C51 feature)

•

Any value between FFh down to 00h can be written by software into CKRL register

in order to divide frequency of the selected oscillator:

•

CKRL = 00h: minimum frequency

F

_{CLK CPU}= F_{CLK PERIPH}= F_OSC/1020 (Standard Mode)

_{CLK CPU}= F_{CLK PERIPH}= F_OSC/510 (X2 Mode)

•

CKRL = FFh: maximum frequency

F_{CLK CPU}= F_{CLK PERIPH}= F_OSC/2 (Standard Mode)

F

_{CLK CPU}= F_{CLK PERIPH}= F_OSC(X2 Mode)

F_{CLK CPU}and F_{CLK PERIPH}

In X2 Mode, for CKRL<>0xFF:

F_OSC

F_CPU= F_CLKPERIPH= -----------------------------------------------

2 × (255 CKRL)

In X1 Mode, for CKRL<>0xFF then:

F_OSC

F_CPU= F_CLKPERIPH= -----------------------------------------------

4 × (255 CKRL)

15

4180E–8051–10/06

Enhanced Features

In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new fea-

tures, which are:

•

X2 option

Dual Data Pointer

Extended RAM

Programmable Counter Array (PCA)

Hardware Watchdog

SPI interface

4-level interrupt priority system

power-off flag

ONCE mode

ALE disabling

Some enhanced features are also located in the UART and the timer 2

X2 Feature

The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature

called ‘X2’ provides the following advantages:

•

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Save power consumption while keeping same CPU power (oscillator power saving).

Save power consumption by dividing dynamically the operating frequency by 2 in

operating and idle modes.

•

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripherals is first divided by 2 before being used by

the CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge

of the XTAL1÷2 to avoid glitches when switching from X2 to X1 mode. Figure 6 shows

the switching mode waveforms.

Figure 5. Clock Generation Diagram

CKRL

F_OSC

XTAL1:2

2

XTAL1

F_{CLK CPU}

F_{CLK PERIPH}

0

1

8 bit Prescaler

FXTAL

X2

CKCON0

16

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Figure 6. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 Bit

F_OSC

CPU Clock

x1 Mode

X2 Mode

X1 Mode

The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods

per instruction to 6 clock periods and vice versa. At reset, the speed is set according to

X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the

X2 bit activates the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register

(Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from

standard peripheral speed (12 clock periods per peripheral clock cycle) to fast periph-

eral speed (6 clock periods per peripheral clock cycle). These bits are active only in X2

mode.

17

4180E–8051–10/06

Table 15. CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

-

6

5

4

3

2

1

0

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

7

Reserved

Watchdog Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

6

WDX2

PCAX2

SIX2

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

5

4

Enhanced UART Clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer 2 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle.

3

2

1

T2X2

T1X2

T0X2

Set to select 12 clock periods per peripheral clock cycle.

Timer 1 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer0 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

CPU Clock

Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU

and all the peripherals. Set to select 6 clock periods per machine cycle (X2

mode) and to enable the individual peripherals’X2’ bits. Programmed by

hardware after Power-up regarding Hardware Security Byte (HSB), Default

setting, X2 is cleared.

0

X2

Reset Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)

Not bit addressable

18

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 16. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

SPIX2

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

-

Reserved

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

0

SPIX2

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = XXXX XXX0b

Not bit addressable

19

4180E–8051–10/06

Dual Data Pointer

Register (DPTR)

The additional data pointer can be used to speed up code execution and reduce code

size.

The dual DPTR structure is a way by which the chip will specify the address of an exter-

nal data memory location. There are two 16-bit DPTR registers that address the external

memory, and a single bit called DPS = AUXR1.0 (see Table 17) that allows the program

code to switch between them (see Figure 7).

Figure 7. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

20

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 17. AUXR1 register

AUXR1- Auxiliary Register 1(0A2h)

7

-

6

-

5

4

-

3

2

1

-

0

ENBOOT

GF3

0

DPS

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Boot Flash

Cleared to disable boot ROM.

5

4

ENBOOT

-

Set to map the boot ROM between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

2

GF3

0

This bit is a general-purpose user flag.⁽¹⁾

Always Cleared

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

DPS

Reset Value = XXXX XX0X0b

Not bit addressable

Note:

1. Bit 2 stuck at 0; this allows using INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a Byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the Byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

21

4180E–8051–10/06

INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the

AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit

to a particular state, but simply toggles it. In simple routines, such as the block move

example, only the fact that DPS is toggled in the proper sequence matters, not its actual

value. In other words, the block move routine works the same whether DPS is '0' or '1'

on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with

DPS in the opposite state.

22

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Expanded RAM

(XRAM)

The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM)

space for increased data parameter handling and high-level language usage.

AT89C51RB2/RC2 devices have expanded RAM in external data space; maximum size

and location are described in Table 18.

Table 18. Expanded RAM

Address

Part Number

XRAM Size

Start

End

AT89C51RB2/RC2

1024

00h

3FFh

The AT89C51RB2/RC2 has internal data memory that is mapped into four separate

segments.

The four segments are:

1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly

addressable.

2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable

only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly

addressable only.

4. The expanded RAM Bytes are indirectly accessed by MOVX instructions, and

with the EXTRAM bit cleared in the AUXR register (see Table 18).

The lower 128 Bytes can be accessed by either direct or indirect addressing. The Upper

128 Bytes can be accessed by indirect addressing only. The Upper 128 Bytes occupy

the same address space as the SFR. That means they have the same address, but are

physically separate from SFR space.

Figure 8. Internal and External Data Memory Address

0FFh or 3FFh

0FFh

0FFFFh

Upper

128 Bytes

Internal

Special

Function

External

Data

Memory

Register

RAM

Direct Accesses

Indirect Accesses

80h

7Fh

80h

XRAM

Lower

128 Bytes

Internal

RAM

Direct or Indirect

Accesses

00FFh up to 03FFh

0000

00

When an instruction accesses an internal location above address 7Fh, the CPU knows

whether the access is to the upper 128 Bytes of data RAM or to SFR space by the

addressing mode used in the instruction.

•

Instructions that use direct addressing access SFR space. For example:

MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).

23

4180E–8051–10/06

•

Instructions that use indirect addressing access the Upper 128 Bytes of data RAM.

For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte

at address 0A0h, rather than P2 (whose address is 0A0h).

The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared

and MOVX instructions. This part of memory that is physically located on-chip,

logically occupies the first Bytes of external data memory. The bits XRS0 and XRS1

are used to hide a part of the available XRAM as explained in Table 18. This can be

useful if external peripherals are mapped at addresses already used by the internal

XRAM.

•

With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An

access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For

example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,

accesses the XRAM at address 0A0H rather than external memory. An access to

external data memory locations higher than the accessible size of the XRAM will be

performed with the MOVX DPTR instructions in the same way as in the standard

80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and

read timing signals. Accesses to XRAM above 0FFH can only be done by the use of

DPTR.

•

With EXTRAM = 1, MOVX @RI and MOVX @DPTR will be similar to the standard

80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0

and any output port pins can be used to output higher order address bits. This is to

provide the external paging capability. MOVX @DPTR will generate a sixteen-bit

address. Port2 outputs the high-order eight address bits (the contents of DPH) while

Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ RI and

MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7

(RD).

The stack pointer (SP) may be located anywhere in the 256 Bytes RAM (lower and

upper RAM) internal data memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses

are extended from 6 to 30 clock periods. This is useful to access external slow

peripherals.

24

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Registers

Table 19. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

-

5

4

-

3

2

1

0

DPU

M0

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Disable Weak Pull-up

7

6

DPU

-

Cleared to activate the permanent weak pull up when latch data is logical 1

Set to disactive the weak pull-up (reduce power consumption)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse Length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock

periods (default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock

periods.

Reserved

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

XRS1

XRAM Size

XRS1 XRS0 XRAM size

0

1

0

1

0

1

256 Bytes (default)

512 Bytes

2

XRS0

768 Bytes

1024 Bytes

EXTRAM Bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

EXTRAM Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

1

0

(HSB), default setting, XRAM selected.

ALE Output Bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AO

Reset Value = XX0X 00’HSB. XRAM’0b (see Table 65)

Not bit addressable

25

4180E–8051–10/06

Timer 2

The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2MOD (Table 21)

registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 selects F_OSC/12 (timer

operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2

allows TL2 to increment by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These

modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).

see the Atmel 8-bit Microcontroller Hardware description for the description of Capture

and Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

•

Auto-reload mode with up or down counter

Programmable clock-output

Auto-reload Mode

The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-

matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (see the

Atmel C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an

Up/down timer/counter as shown in Figure 9. In this mode the T2EX pin controls the

direction of count.

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of

the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit

resolution.

26

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1)

F_{CLK PERIPH}

:6

1

T2

TR2

C/T2

T2CON

T2EX:

(DOWN COUNTING RELOAD VALUE)

if DCEN = 1, 1 = UP

FFh

(8-bit)

FFh

(8-bit)

if DCEN = 1, 0 = DOWN

if DCEN = 0, up counting

T2CON

EXF2

TOGGLE

TL2

(8-bit)

TH2

(8-bit)

TIMER 2

INTERRUPT

TF2

T2CON

RCAP2L RCAP2H

(8-bit)

8-bit)

(UP COUNTING RELOAD VALUE)

Programmable Clock-out In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen-

erator (see Figure 10). The input clock increments TL2 at frequency F_{CLK PERIPH}/2. The

Mode

timer repeatedly counts to overflow from a loaded value. At overflow, the contents of

RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2

overflows do not generate interrupts. The formula gives the clock-out frequency as a

function of the system oscillator frequency and the value in the RCAP2H and RCAP2L

registers:

F

CLKPERIPH

Clock OutFrequency

4 × (65536 RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(F_{CLK PERIPH}/2¹⁶) to 4 MHz (F_{CLK PERIPH}/4). The generated clock signal is brought out to

T2 pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

•

Set T2OE bit in T2MOD register.

Clear C/T2 bit in T2CON register.

Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

•

Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or a different one depending on the application.

•

To start the timer, set TR2 run control bit in T2CON register.

It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

27

4180E–8051–10/06

Figure 10. Clock-Out Mode C/T2 = 0

:6

FCLK PERIPH

TR2

T2CON

TL2

(8-bit)

TH2

(8-bit)

OVER-

FLOW

RCAP2H

RCAP2L

(8-bit) (8-bit)

Toggle

T2

Q

D

T2OE

T2MOD

TIMER 2

INTERRUPT

T2EX

EXF2

T2CON

EXEN2

T2CON

28

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Registers

Table 20. T2CON Register

T2CON – Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic Description

Timer 2 Overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2 = 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2

interrupt is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down

counter mode (DCEN = 1).

Receive Clock Bit

5

4

RCLK

TCLK

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock Bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable Bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run Control Bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

Timer/Counter 2 Select Bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0

for clock out mode.

C/T2#

Timer 2 Capture/Reload Bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload

on Timer 2 overflow.

Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin

if EXEN2 = 1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

Reset Value = 0000 0000b

Bit addressable

29

4180E–8051–10/06

Table 21. T2MOD Register

T2MOD – Timer 2 Mode Control Register (C9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable Bitt

1

0

T2OE

DCEN

Cleared to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable Bit

Cleared to disable Timer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

30

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Programmable

Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. The PCA consists of a dedicated timer/counter which serves as the time base for

an array of five compare/capture Modules. Its clock input can be programmed to count

any one of the following signals:

•

Peripheral clock frequency (F_{CLK PERIPH}) ÷ 6

Peripheral clock frequency (F_{CLK PERIPH}) ÷ 2

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture Modules can be programmed in any one of the following modes:

•

Rising and/or falling edge capture

Software timer

High-speed output

Pulse width modulator

Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog

Timer", page 42).

When the compare/capture Modules are programmed in the capture mode, software

timer, or high speed output mode, an interrupt can be generated when the Module exe-

cutes its function. All five Modules plus the PCA timer overflow share one interrupt

vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O.

These pins are listed below. If one or several bits in the port are not used for the PCA,

they can still be used for standard I/O.

PCA Component

16-bit Counter

External I/O Pin

P1.2/ECI

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

The PCA timer is a common time base for all five Modules (see Figure 11). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD register

(Table 22) and can be programmed to run at:

•

1/6 the peripheral clock frequency (F_{CLK PERIPH}

1/2 the peripheral clock frequency (F_{CLK PERIPH}

The Timer 0 overflow

)

The input on the ECI pin (P1.2)

31

4180E–8051–10/06

Figure 11. PCA Timer/Counter

To PCA

Modules

F_{CLK PERIPH}/6

F_{CLK PERIPH}/2

T0 OVF

overflow

It

CH

CL

16-bit up Counter

P1.2

CMOD

0xD9

CIDL

CF

CPS1 CPS0 ECF

WDTE

CR

Idle

CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

32

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4180E–8051–10/06

AT89C51RB2/RC2

Registers

Table 22. CMOD Register

CMOD – PCA Counter Mode Register (D9h)

7

6

5

-

4

-

3

-

2

1

0

CIDL

WDTE

CPS1

CPS0

ECF

Bit

Number

Mnemonic Description

Counter Idle Control

7

6

CIDL

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

Watchdog Timer Enable

WDTE

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

5

4

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

CPS1

PCA Count Pulse Select

CPS1 CPS0 Selected PCA input

0

1

0

1

0

1

Internal clock F_{CLK PERIPH}/6

Internal clock F_{LK PERIPH}/2

1

0

CPS0

ECF

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.

Set to enable CF bit in CCON to generate an interrupt.

Reset Value = 00XX X000b

Not bit addressable

The CMOD register includes three additional bits associated with the PCA.

•

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the watchdog function on Module 4.

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in

the CCON SFR) to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer (CF) and each Module (see Table 23).

•

Bit CR (CCON. 6) must be set by software to run the PCA. The PCA is shut off by

clearing this bit.

•

Bit CF: The CF bit (CCON. 7) is set when the PCA counter overflows and an

interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can

only be cleared by software.

•

Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1,

etc. ) and are set by hardware when either a match or a capture occurs. These flags

also can only be cleared by software.

33

4180E–8051–10/06

Table 23. CCON Register

CCON – PCA Counter Control Register (D8h)

7

6

5

-

4

3

2

1

0

CF

CR

CCF4

CCF3

CCF2

CCF1

CCF0

Bit

Number

Mnemonic Description

PCA Counter Overflow Flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in

CMOD is set. CF may be set by either hardware or software but can only be

cleared by software.

7

CF

PCA Counter Run Control Bit

6

5

4

CR

-

Must be cleared by software to turn the PCA counter off.

Set by software to turn the PCA counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA Module 4 Interrupt Flag

CCF4

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 3 Interrupt Flag

3

2

1

0

CCF3

CCF2

CCF1

CCF0

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 2 Interrupt Flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 1 Interrupt Flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 0 Interrupt Flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

Reset Value = 000X 0000b

Bit addressable

The watchdog timer function is implemented in Module 4 (see Figure 14).

The PCA interrupt system is shown in Figure 12.

34

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Figure 12. PCA Interrupt System

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

To Interrupt

Priority Decoder

Module 4

CMOD. 0

IEN0. 6

EC

IEN0. 7

EA

CCAPMn. 0

ECCFn

ECF

PCA Modules: each one of the five compare/capture Modules has six possible func-

tions. It can perform:

•

16-bit Capture, positive-edge triggered

16-bit Capture, negative-edge triggered

16-bit Capture, both positive and negative-edge triggered

16-bit Software Timer

16-bit High-speed Output

8-bit Pulse Width Modulator

In addition, Module 4 can be used as a Watchdog Timer.

Each Module in the PCA has a special function register associated with it. These regis-

ters are: CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (see Table 24). The

registers contain the bits that control the mode that each Module will operate in.

•

The ECCF bit (CCAPMn. 0 where n = 0, 1, 2, 3, or 4 depending on the Module)

enables the CCF flag in the CCON SFR to generate an interrupt when a match or

compare occurs in the associated Module.

•

PWM (CCAPMn. 1) enables the pulse width modulation mode.

The TOG bit (CCAPMn. 2) when set causes the CEX output associated with the

Module to toggle when there is a match between the PCA counter and the Module's

capture/compare register.

•

The match bit MAT (CCAPMn. 3) when set will cause the CCFn bit in the CCON

register to be set when there is a match between the PCA counter and the Module's

capture/compare register.

The next two bits CAPN (CCAPMn. 4) and CAPP (CCAPMn. 5) determine the edge

that a capture input will be active on. The CAPN bit enables the negative edge, and

the CAPP bit enables the positive edge. If both bits are set both edges will be

enabled and a capture will occur for either transition.

•

The last bit in the register ECOM (CCAPMn. 6) when set enables the comparator

function.

Table 24 shows the CCAPMn settings for the various PCA functions.

35

4180E–8051–10/06

Table 24. CCAPMn Registers (n = 0-4)

CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh)

CCAPM1 – PCA Module 1 Compare/Capture Control Register (0DBh)

CCAPM2 – PCA Module 2 Compare/Capture Control Register (0DCh)

CCAPM3 – PCA Module 3 Compare/Capture Control Register (0DDh)

CCAPM4 – PCA Module 4 Compare/Capture Control Register (0DEh)

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Comparator

ECOMn Cleared to disable the comparator function.

Set to enable the comparator function.

Capture Positive

5

4

CAPPn

CAPNn

Cleared to disable positive edge capture.

Set to enable positive edge capture.

Capture Negative

Cleared to disable negative edge capture.

Set to enable negative edge capture.

Match

When MATn = 1, a match of the PCA counter with this Module's

compare/capture register causes the CCFn bit in CCON to be set, flagging an

interrupt.

3

MATn

Toggle

2

1

TOGn

PWMn

When TOGn = 1, a match of the PCA counter with this Module's

compare/capture register causes theCEXn pin to toggle.

Pulse Width Modulation Mode

Cleared to disable the CEXn pin to be used as a pulse width modulated output.

Set to enable the CEXn pin to be used as a pulse width modulated output.

Enable CCF Interrupt

Cleared to disable compare/capture flag CCFn in the CCON register to generate

an interrupt.

0

CCF0

Set to enable compare/capture flag CCFn in the CCON register to generate an

interrupt.

Reset Value = X000 0000b

Not bit addressable

36

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Table 25. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn

MATn

TOGn

PWMm ECCFn Module Function

0

1

0

No Operation

16-bit capture by a positive-edge

trigger on CEXn

X

0

1

0

X

16-bit capture by a negative trigger

on CEXn

X

1

0

1

0

1

0

X

16-bit capture by a transition on

CEXn

16-bit Software Timer/Compare

mode.

1

0

1

0

1

0

1

0

X

0

16-bit High-speed Output

8-bit PWM

X

Watchdog Timer (Module 4 only)

There are two additional registers associated with each of the PCA Modules. They are

CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a

capture occurs or a compare should occur. When a Module is used in the PWM mode

these registers are used to control the duty cycle of the output (see Table 26 and

Table 27).

Table 26. CCAPnH Registers (n = 0-4)

CCAP0H – PCA Module 0 Compare/Capture Control Register High (0FAh)

CCAP1H – PCA Module 1 Compare/Capture Control Register High (0FBh)

CCAP2H – PCA Module 2 Compare/Capture Control Register High (0FCh)

CCAP3H – PCA Module 3 Compare/Capture Control Register High (0FDh)

CCAP4H – PCA Module 4 Compare/Capture Control Register High (0FEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnH Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

37

4180E–8051–10/06

Table 27. CCAPnL Registers (n = 0-4)

CCAP0L – PCA Module 0 Compare/Capture Control Register Low (0EAh)

CCAP1L – PCA Module 1 Compare/Capture Control Register Low (0EBh)

CCAP2L – PCA Module 2 Compare/Capture Control Register Low (0ECh)

CCAP3L – PCA Module 3 Compare/Capture Control Register Low (0EDh)

CCAP4L – PCA Module 4 Compare/Capture Control Register Low (0EEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnL Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

Table 28. CH Register

CH – PCA Counter Register High (0F9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Counter

CH Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

Table 29. CL Register

CL – PCA Counter Register Low (0E9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Counter

CL Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

38

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

PCA Capture Mode

To use one of the PCA Modules in the capture mode either one or both of the CCAPM

bits CAPN and CAPP for that Module must be set. The external CEX input for the Mod-

ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA

hardware loads the value of the PCA counter registers (CH and CL) into the Module's

capture registers (CCAPnL and CCAPnH). If the CCFn bit for the Module in the CCON

SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated

(see Figure 13).

Figure 13. PCA Capture Mode

CCON

CCF4 CCF3 CCF2 CCF1 CCF0

CF

CR

0xD8

PCA IT

PCA Counter/Timer

Cex. n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

39

4180E–8051–10/06

16-bit Software Timer/

Compare Mode

The PCA Modules can be used as software timers by setting both the ECOM and MAT

bits in the Modules CCAPMn register. The PCA timer will be compared to the Module's

capture registers and when a match occurs, an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the Module are both set (see Figure 14).

Figure 14. PCA Compare Mode and PCA Watchdog Timer

CCON

0xD8

CCF4

CF

CCF3 CCF2 CCF1 CCF0

CR

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16 bit Comparator

RESET⁽¹⁾

CH

CL

PCA Counter/Timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL

CPS1 CPS0 ECF

WDTE

Note:

1. Only for Module 4

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

40

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

High-speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the modules capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR

must be set (see Figure 15).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

Figure 15. PCA High-speed Output Mode

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

Enable

1

Match

16-bit Comparator

CEXn

CH

CL

PCA Counter/Timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non-zero value,

otherwise an unwanted match could occur.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

41

4180E–8051–10/06

Pulse Width Modulator

Mode

All of the PCA Modules can be used as PWM outputs. Figure 16 shows the PWM func-

tion. The frequency of the output depends on the source for the PCA timer. All of the

Modules will have the same frequency of output because they all share the PCA timer.

The duty cycle of each Module is independently variable using the module's capture

register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-

ule's CCAPLn SFR the output will be low, when it is equal to or greater than the output

will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in

CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in

the module's CCAPMn register must be set to enable the PWM mode.

Figure 16. PCA PWM Mode

CCAPnH

Overflow

CCAPnL

“0”

CEXn

Enable

8-bit Comparator

“1”

CL

PCA Counter/Timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the

system without increasing chip count. Watchdog timers are useful for systems that are

susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only

PCA Module that can be programmed as a watchdog. However, this Module can still be

used for other modes if the watchdog is not needed. Figure 14 shows a diagram of how

the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just

like the other compare modes, this 16-bit value is compared to the PCA timer value. If a

match is allowed to occur, an internal reset will be generated. This will not cause the

RST pin to be driven high.

In order to hold off the reset, the user has the following three options:

1. Periodically change the compare value so it will never match the PCA timer.

2. Periodically change the PCA timer value so it will never match the compare

values.

3. Disable the watchdog by clearing the WDTE bit before a match occurs and then

re-enable it.

The first two options are more reliable because the watchdog timer is never disabled as

in option #3. If the program counter ever goes astray, a match will eventually occur and

cause an internal reset. The second option is also not recommended if other PCA Mod-

ules are being used. Remember, the PCA timer is the time base for all modules;

42

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

changing the time base for other Modules would not be a good idea. Thus, in most appli-

cations the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

43

4180E–8051–10/06

Serial I/O Port

The serial I/O port in the AT89C51RB2/RC2 is compatible with the serial I/O port in the

80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

Automatic address recognition

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 17).

Figure 17. Framing Error Block Diagram

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

PCON (87h)

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See Table 33.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 18. and Figure 19.).

Figure 18. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

44

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Figure 19. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, the user may enable the automatic address recognition feature in mode 1.In

this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when

the received command frame address matches the device’s address and is terminated

by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN

register is a mask byte that contains don’t-care bits (defined by zeros) to form the

device’s given address. The don’t-care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

45

4180E–8051–10/06

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To commu-

nicate with slave A only, the master must send an address where bit 0 is clear (e. g.

1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both

set (e. g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e. g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e. g. :

SADDR0101 0110b

SADEN1111 1100b

Broadcast =SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR=1111 0011b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and

broadcast addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial

port will reply to any address, and so, that it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition.

46

AT89C51RB2/RC2

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AT89C51RB2/RC2

Registers

Table 30. SADEN Register

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 31. SADDR Register

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Baud Rate Selection for

UART for Mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via

the T2CON and BDRCON registers.

Figure 20. Baud Rate Selection

TIMER1

TIMER_BRG_RX

0

1

0

1

TIMER2

/ 16

Rx Clock

RCLK

RBCK

INT_BRG

TIMER1

TIMER2

TIMER_BRG_TX

0

1

0

1

/ 16

Tx Clock

TCLK

TBCK

INT_BRG

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4180E–8051–10/06

Table 32. Baud Rate Selection Table UART

TCLK

RCLK

TBCK

RBCK

Clock Source

UART Tx

Clock Source

UART Rx

(T2CON)

(BDRCON)

0

1

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

Timer 1

Timer 2

Timer 1

Timer 2

INT_BRG

Timer 1

Timer 2

INT_BRG

Timer 2

INT_BRG

Internal Baud Rate Generator When the internal Baud Rate Generator is used, the Baud Rates are determined by the

(BRG)

BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)

in BDRCON register and the value of the SMOD1 bit in PCON register.

Figure 21. Internal Baud Rate

F_{Clk Periph}

÷ 6

0

1

Overflow

BRG

(8 bits)

÷ 2

0

1

INT_BRG

SPD

BDRCON.1

BRR

BDRCON.4

SMOD1

PCON.7

BRL

(8 bits)

•

The baud rate for UART is token by formula:

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

Baud_Rate =

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

BRL = 256 -

48

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AT89C51RB2/RC2

Table 33. SCON Register

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

FE

SMOD0 must be set to enable access to the FE bit.

7

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SM1

SMOD0 must be cleared to enable access to the SM0 bit.

Serial port Mode bit 1

SM0 SM1

Mode

Baud Rate

0

1

0

1

0

1

Shift Register F_XTAL/12 (or F_XTAL/6 in mode X2)

6

5

8-bit UART

9-bit UART

Variable

_XTAL/64 or F_XTAL/32

Variable

F

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

SM2

Set to enable multiprocessor communication feature in mode 2 and 3, and

eventually mode 1.This bit should be cleared in mode 0.

Reception Enable bit

4

3

REN

TB8

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not

used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning

of the stop bit in the other modes.

1

0

TI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 18.

and Figure 19. in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

49

4180E–8051–10/06

Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1

Baud Rates

F_OSC= 16. 384 MHz

F_OSC= 24MHz

Error (%)

BRL

Error (%)

1.23

BRL

243

230

217

204

178

100

-

115200

57600

38400

28800

19200

9600

247

238

229

220

203

149

43

0.16

-

1.23

0.63

0.31

4800

1.23

Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0

Baud Rates

F

BRL

247

238

220

185

_OSC= 16. 384 MHz

F_OSC= 24MHz

Error (%)

BRL

243

230

202

152

Error (%)

0.16

4800

2400

1200

600

1.23

0.16

3.55

0.16

The baud rate generator can be used for mode 1 or 3 (refer to Figure 20.), but also for

mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)

UART Registers

Table 36. SADEN Register

SADEN - Slave Address Mask Register for UART (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Table 37. SADDR Register

SADDR - Slave Address Register for UART (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

50

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AT89C51RB2/RC2

Table 38. SBUF Register

SBUF - Serial Buffer Register for UART (99h)

7

6

5

4

3

2

1

0

Reset Value = XXXX XXXXb

Table 39. BRL Register

BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

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4180E–8051–10/06

Table 40. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic

Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2

interrupt is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down

counter mode (DCEN = 1)

Receive Clock bit for UART

5

4

RCLK

TCLK

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit for UART

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be

0 for clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

timer 2 overflow.

Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin

if EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

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AT89C51RB2/RC2

Table 41. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic

Description

Serial port Mode bit 1 for UART

7

6

5

SMOD1

SMOD0

-

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0 for UART

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

4

POF

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset

doesn’t affect the value of this bit.

53

4180E–8051–10/06

Table 42. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Mnemonic Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

4

3

2

1

BRR

TBCK

RBCK

SPD

Cleared to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

Cleared to select F_OSC/12 as the Baud Rate Generator (F_{CLK PERIPH}/6 in X2

mode).

0

SRC

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset Value = XXX0 0000b

Not bit addressablef

54

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Interrupt System

The AT89C51RB2/RC2 has a total of 9 interrupt vectors: two external interrupts (INT0

and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI inter-

rupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in

Figure 22.

Figure 22. Interrupt Control System

High Priority

IPH, IPL

Interrupt

3

INT0

IE0

0

3

0

TF0

Interrupt

3

INT1

IE1

Polling

0

3

Sequence, Decreasing From

High to Low Priority

TF1

0

3

PCA IT

0

3

0

RI

TI

3

TF2

EXF2

0

3

KBD IT

SPI IT

0

3

0

Individual Enable

Low Priority

Interrupt

Global Disable

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (Table 45 and Table 47). This register also

contains a global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority lev-

els by setting or clearing a bit in the Interrupt Priority register (Table 48) and in the

Interrupt Priority High register (Table 46 and Table 47) shows the bit values and priority

levels associated with each combination.

55

4180E–8051–10/06

Registers

A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

Table 43. Priority Level Bit Values

IPH. x

IPL. x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

If two interrupt requests of different priority levels are received simultaneously, the

request of higher-priority level is serviced. If interrupt requests of the same priority level

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

56

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4180E–8051–10/06

AT89C51RB2/RC2

Table 44. IENO Register

IEN0 - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic Description

Enable All Interrupt Bit

7

6

EA

EC

Cleared to disable all interrupts.

Set to enable all interrupts.

PCA Interrupt Enable Bit

Cleared to disable.

Set to enable.

Timer 2 Overflow Interrupt Enable Bit

Cleared to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

5

4

3

2

1

0

ET2

ES

Serial Port Enable Bit

Cleared to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 Overflow Interrupt Enable Bit

Cleared to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External Interrupt 1 Enable Bit

Cleared to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 Overflow Interrupt Enable Bit

Cleared to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External Interrupt 0 Enable Bit

Cleared to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

Bit addressable

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4180E–8051–10/06

Table 45. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7

-

6

5

4

3

2

1

0

PPCL

PT2L

PSL

PT1L

PX1L

PT0L

PX0L

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Interrupt Priority Bit

see PPCH for priority level.

PPCL

PT2L

PSL

Timer 2 Overflow Interrupt Priority Bit

see PT2H for priority level.

Serial Port Priority Bit

see PSH for priority level.

Timer 1 Overflow Interrupt Priority Bit

see PT1H for priority level.

PT1L

PX1L

PT0L

PX0L

External Interrupt 1 Priority Bit

see PX1H for priority level.

Timer 0 Overflow Interrupt Priority Bit

see PT0H for priority level.

External Interrupt 0 Priority Bit

see PX0H for priority level.

Reset Value = X000 0000b

Bit addressable

58

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AT89C51RB2/RC2

Table 46. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7

6

5

4

3

2

1

0

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Interrupt Priority High Bit

PPCHPPCL Priority Level

0

1

0

1

0

1

Lowest

6

PPCH

PT2H

PSH

Highest

Timer 2 Overflow Interrupt Priority High Bit

PT2HPT2L

0

1

Priority Level

Lowest

0

1

0

1

5

4

3

2

1

0

Highest

Serial Port Priority High Bit

PSH PSL

0

1

Priority Level

Lowest

0

1

0

1

Highest

Timer 1 Overflow Interrupt Priority High Bit

PT1HPT1L

0

1

Priority Level

Lowest

0

1

0

1

PT1H

PX1H

PT0H

PX0H

Highest

External Interrupt 1 Priority High Bit

PX1HPX1L

0

1

Priority Level

Lowest

0

1

0

1

Highest

Timer 0 Overflow Interrupt Priority High Bit

PT0HPT0L

0

1

Priority Level

Lowest

0

1

0

1

Highest

External Interrupt 0 Priority High Bit

PX0H PX0L Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = X000 0000b

Not bit addressable

59

4180E–8051–10/06

Table 47. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)

7

6

5

4

3

2

1

0

-

ESPI

-

KBD

Bit

Number

Mnemonic Description

7

6

5

4

3

-

Reserved

SPI Interrupt Enable Bit

Cleared to disable SPI interrupt.

2

1

0

ESPI

-

Set to enable SPI interrupt.

Reserved

Keyboard Interrupt Enable Bit

Cleared to disable keyboard interrupt.

Set to enable keyboard interrupt.

KBD

Reset Value = XXXX X000b

Bit addressable

60

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AT89C51RB2/RC2

Table 48. IPL1 Register

IPL1 - Interrupt Priority Register (B2h)

7

-

6

-

5

-

4

-

3

-

2

1

-

0

SPIL

KBDL

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority Bit

see SPIH for priority level.

SPIL

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Keyboard Interrupt Priority Bit

see KBDH for priority level.

KBDL

Reset Value = XXXX X000b

Bit addressable

61

4180E–8051–10/06

Table 49. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)

7

-

6

-

5

-

4

-

3

-

2

1

-

0

SPIH

KBDH

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority High Bit

SPIHSPIL

Priority Level

Lowest

0

1

0

1

0

1

2

1

0

SPIH

Highest

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Keyboard Interrupt Priority High Bit

KB DHKBDL Priority Level

0

1

0

1

0

1

Lowest

KBDH

Highest

Reset Value = XXXX X000b

Not bit addressable

62

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Interrupt Sources and

Vector Addresses

Table 50. Interrupt Sources and Vector Addresses

Vector

Interrupt

Request

Number

Polling Priority

Interrupt Source

Reset

Address

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

6

7

5

8

9

0000h

0003h

000Bh

0013h

001Bh

0023h

002Bh

0033h

003Bh

004Bh

INT0

IE0

Timer 0

INT1

TF0

IE1

Timer 1

UART

IF1

RI+TI

Timer 2

PCA

TF2+EXF2

CF + CCFn (n = 0-4)

KBDIT

Keyboard

SPI

SPIIT

63

4180E–8051–10/06

Keyboard Interface

The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a

8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on

both high or low level. These inputs are available as alternate function of P1 and allow to

exit from idle and power-down modes.

The keyboard interfaces with the C51 core through 3 special function registers: KBLS,

the Keyboard Level Selection register (Table 53), KBE, the Keyboard interrupt Enable

register (Table 52), and KBF, the Keyboard Flag register (Table 51).

Interrupt

The keyboard inputs are considered as 8 independent interrupt sources sharing the

same interrupt vector. An interrupt enable bit (KBD in IEN1) allows global enable or dis-

able of the keyboard interrupt (see Figure 23). As detailed in Figure 24 each keyboard

input has the capability to detect a programmable level according to KBLS. x bit value.

Level detection is then reported in interrupt flags KBF. x that can be masked by software

using KBE. x bits.

This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allow

usage of P1 inputs for other purpose.

Figure 23. Keyboard Interface Block Diagram

V_CC

0

P1:x

KBF. x

1

KBE. x

Internal Pull-up

KBLS. x

Figure 24. Keyboard Input Circuitry

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Input Circuitry

KBDIT

Keyboard Interface

Interrupt Request

KBD

IEN1

Power Reduction Mode

P1 inputs allow exit from idle and power down modes as detailed in Section “Power-

down Mode”, page 82.

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Registers

Table 51. KBF Register

KBF - Keyboard Flag Register (9Eh)

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Bit

Number

Mnemonic Description

Keyboard Line 7 Flag

Set by hardware when the Port line 7 detects a programmed level. It generates a

Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.

Must be cleared by software.

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Keyboard Line 6 Flag

Set by hardware when the Port line 6 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 5 Flag

Set by hardware when the Port line 5 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 4 Flag

Set by hardware when the Port line 4 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 3 Flag

Set by hardware when the Port line 3 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 2 Flag

Set by hardware when the Port line 2 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 1 Flag

Set by hardware when the Port line 1 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set.

Must be cleared by software.

Keyboard Line 0 Flag

Set by hardware when the Port line 0 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set.

Must be cleared by software.

Reset Value = 0000 0000b

This register is read only access, all flags are automatically cleared by reading the

register.

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Table 52. KBE Register

KBE - Keyboard Input Enable Register (9Dh)

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Bit

Number

Mnemonic Description

Keyboard Line 7 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 7 bit in KBF register to generate an interrupt request.

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Keyboard Line 6 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 6 bit in KBF register to generate an interrupt request.

Keyboard Line 5 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 5 bit in KBF register to generate an interrupt request.

Keyboard Line 4 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 4 bit in KBF register to generate an interrupt request.

Keyboard Line 3 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 3 bit in KBF register to generate an interrupt request.

Keyboard Line 2 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 2 bit in KBF register to generate an interrupt request.

Keyboard Line 1 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 1 bit in KBF register to generate an interrupt request.

Keyboard Line 0 Enable Bit

Cleared to enable standard I/O pin.

Set to enable KBF. 0 bit in KBF register to generate an interrupt request.

Reset Value = 0000 0000b

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Table 53. KBLS Register

KBLS - Keyboard Level Selector Register (9Ch)

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Bit

Number

Mnemonic Description

Keyboard Line 7 Level Selection Bit

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Cleared to enable a low level detection on Port line 7.

Set to enable a high level detection on Port line 7.

Keyboard Line 6 Level Selection Bit

Cleared to enable a low level detection on Port line 6.

Set to enable a high level detection on Port line 6.

Keyboard Line 5 Level Selection Bit

Cleared to enable a low level detection on Port line 5.

Set to enable a high level detection on Port line 5.

Keyboard Line 4 Level Selection Bit

Cleared to enable a low level detection on Port line 4.

Set to enable a high level detection on Port line 4.

Keyboard Line 3 Level Selection Bit

Cleared to enable a low level detection on Port line 3.

Set to enable a high level detection on Port line 3.

Keyboard Line 2 Level Selection Bit

Cleared to enable a low level detection on Port line 2.

Set to enable a high level detection on Port line 2.

Keyboard Line 1 Level Selection Bit

Cleared to enable a low level detection on Port line 1.

Set to enable a high level detection on Port line 1.

Keyboard Line 0 Level Selection Bit

Cleared to enable a low level detection on Port line 0.

Set to enable a high level detection on Port line 0.

Reset Value = 0000 0000b

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Serial Port Interface

(SPI)

The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial

communication between the MCU and peripheral devices, including other MCUs.

Features

Features of the SPI Module include the following:

•

Full-duplex, three-wire synchronous transfers

Master or Slave operation

Eight programmable Master clock rates

Serial clock with programmable polarity and phase

Master Mode fault error flag with MCU interrupt capability

Write collision flag protection

Signal Description

Figure 25 shows a typical SPI bus configuration using one Master controller and many

Slave peripherals. The bus is made of three wires connecting all the devices.

Figure 25. SPI Master/Slaves Interconnection

Slave 1

MISO

MOSI

SCK

SS

VDD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

The Master device selects the individual Slave devices by using four pins of a parallel

port to control the four SS pins of the Slave devices.

Master Output Slave Input

(MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device.

The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,

it is an output signal from the Master, and an input signal to a Slave. A Byte (8-bit word)

is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output

(MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device.

The MISO line is used to transfer data in series from the Slave to the Master. Therefore,

it is an output signal from the Slave, and an input signal to the Master. A Byte (8-bit

word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK)

Slave Select (SS)

This signal is used to synchronize the data movement both in and out of the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles

which allows to exchange one Byte on the serial lines.

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. It is obvious that only one Master (SS high level) can

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drive the network. The Master may select each Slave device by software through port

pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be

selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in

the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and

SCK (see Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

•

The device is configured as a Master and the SSDIS control bit in SPCON is set.

This kind of configuration can be found when only one Master is driving the network

and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in

the SPSTA will never be set⁽¹⁾.

The Device is configured as a Slave with CPHA and SSDIS control bits set⁽²⁾. This

kind of configuration can happen when the system comprises one Master and one

Slave only. Therefore, the device should always be selected and there is no reason

that the Master uses the SS pin to select the communicating Slave device.

Note:

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because

in this mode, the SS is used to start the transmission.

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is con-

trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is

selected from one of seven clock rates resulting from the division of the internal clock by

2, 4, 8, 16, 32, 64 or 128.

Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0.

Table 54. SPI Master Baud Rate Selection

SPR2

SPR1

SPR0

Clock Rate

_{CLK PERIPH}/2

_{CLK PERIPH}/4

_{CLK PERIPH}/8

Baud Rate Divisor (BD)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

F

2

4

F

8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

16

32

64

F

_{CLK PERIPH}/128

Don’t Use

128

No BRG

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Functional Description

Figure 26 shows a detailed structure of the SPI Module.

Figure 26. SPI Module Block Diagram

Internal Bus

SPDAT

Shift Register

FCLK PERIPH

7

6

5

4

3

2

1

0

/4

/8

/16

/32

/64

Clock

Divider

Receive Data Register

Control

Logic

MOSI

MISO

/128

Clock

Logic

M

S

SCK

SS

Clock

Select

SPR2

SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

Control

1-bit signal

SPI Interrupt Request

SPSTA

-

SPIF WCOL

MODF

Operating Modes

The Serial Peripheral Interface can be configured in one of the two modes: Master

mode or Slave mode. The configuration and initialization of the SPI Module is made

through one register:

•

The Serial Peripheral Control register (SPCON)

Once the SPI is configured, the data exchange is made using:

•

SPCON

The Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave

device responds by sending data to the Master device via the MISO line. This implies

full-duplex transmission with both data out and data in synchronized with the same clock

(Figure 27).

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Figure 27. Full-Duplex Master-Slave Interconnection

MISO

MOSI

MISO

MOSI

8-bit Shift register

SPI

SCK

SS

SCK

Clock Generator

SS

VDD

Master MCU

Slave MCU

VSS

Master Mode

The SPI operates in Master mode when the Master bit, MSTR ⁽¹⁾, in the SPCON register

is set. Only one Master SPI device can initiate transmissions. Software begins the trans-

mission from a Master SPI Module by writing to the Serial Peripheral Data Register

(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift

register. The Byte begins shifting out on MOSI pin under the control of the serial clock,

SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.

The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA

becomes set. At the same time that SPIF becomes set, the received Byte from the Slave

is transferred to the receive data register in SPDAT. Software clears SPIF by reading

the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the

SPDAT.

Slave Mode

The SPI operates in Slave mode when the Master bit, MSTR ⁽²⁾, in the SPCON register is

cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave

device must be set to ’0’. SS must remain low until the transmission is complete.

In a Slave SPI Module, data enters the shift register under the control of the SCK from

the Master SPI Module. After a Byte enters the shift register, it is immediately trans-

ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an

overflow condition, Slave software must then read the SPDAT before another Byte

enters the shift register ⁽³⁾. A Slave SPI must complete the write to the SPDAT (shift reg-

ister) at least one bus cycle before the Master SPI starts a transmission. If the write to

the data register is late, the SPI transmits the data already in the shift register from the

previous transmission. The maximum SCK frequency allowed in slave mode is F_{CLK PERIPH}

/4.

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity

using two bits in the SPCON: the Clock Polarity (CPOL ⁽⁴⁾) and the Clock Phase

(CPHA⁴). CPOL defines the default SCK line level in idle state. It has no significant

effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 28 and Figure 29).

The clock phase and polarity should be identical for the Master SPI device and the com-

municating Slave device.

1.

The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,

the Master SPI should be configured before the Slave SPI.

2.

3.

The SPI Module should be configured as a Slave before it is enabled (SPEN set).

The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock

speed.

4.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

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Figure 28. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MISO (from Slave)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MSB

SS (to Slave)

Capture Point

Figure 29. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

LSB

MISO (from Slave)

SS (to Slave)

Capture Point

Figure 30. CPHA/SS Timing

Byte 3

MISO/MOSI

Byte 1

Byte 2

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

As shown in Figure 28, the first SCK edge is the MSB capture strobe. Therefore, the

Slave must begin driving its data before the first SCK edge, and a falling edge on the SS

pin is used to start the transmission. The SS pin must be toggled high and then low

between each Byte transmitted (Figure 30).

Figure 29 shows an SPI transmission in which CPHA is ’1’. In this case, the Master

begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first

SCK edge as a start transmission signal. The SS pin can remain low between transmis-

sions (Figure 30). This format may be preffered in systems having only one Master and

only one Slave driving the MISO data line.

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Error Conditions

The following flags in the SPSTA signal SPI error conditions:

Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS)

pin is inconsistent with the actual mode of the device. MODF is set to warn that there

may be a multi-master conflict for system control. In this case, the SPI system is

affected in the following ways:

•

An SPI receiver/error CPU interrupt request is generated

The SPEN bit in SPCON is cleared. This disables the SPI

The MSTR bit in SPCON is cleared

When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set

when the SS signal becomes ’0’.

However, as stated before, for a system with one Master, if the SS pin of the Master

device is pulled low, there is no way that another Master attempts to drive the network.

In this case, to prevent the MODF flag from being set, software can set the SSDIS bit in

the SPCON register and therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set,

followed by a write to the SPCON register. SPEN Control bit may be restored to its orig-

inal set state after the MODF bit has been cleared.

Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is

done during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA

and an access to SPDAT.

Overrun Condition

An overrun condition occurs when the Master device tries to send several data Bytes

and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte

transmitted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was

last cleared. A read of the SPDAT returns this Byte. All others Bytes are lost.

This condition is not detected by the SPI peripheral.

SS Error Flag (SSERR)

A Synchronous Serial Slave Error occurs when SS goes high before the end of a

received data in slave mode. SSERR does not cause in interruption, this bit is cleared

by writing 0 to SPEN bit (reset of the SPI state machine).

Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 55. SPI Interrupts

Flag

Request

SPIF (SP data transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer

has been completed. SPIF bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is

inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error

CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.

Figure 31 gives a logical view of the above statements.

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Figure 31. SPI Interrupt Requests Generation

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SPI Receiver/error

CPU Interrupt Request

SSDIS

Registers

There are three registers in the Module that provide control, status and data storage functions. These registers

are describes in the following paragraphs.

Serial Peripheral Control

Register (SPCON)

•

The Serial Peripheral Control Register does the following:

Selects one of the Master clock rates

Configure the SPI Module as Master or Slave

Selects serial clock polarity and phase

Enables the SPI Module

Frees the SS pin for a general-purpose

Table 56 describes this register and explains the use of each bit

Table 56. SPCON Register

SPCON - Serial Peripheral Control Register (0C3H)

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit Number

Bit Mnemonic

Description

Serial Peripheral Rate 2

7

SPR2

SPEN

Bit with SPR1 and SPR0 define the clock rate.

Serial Peripheral Enable

6

5

Cleared to disable the SPI interface.

Set to enable the SPI interface.

SS Disable

Cleared to enable SS in both Master and Slave modes.

SSDIS

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated.

Serial Peripheral Master

4

3

MSTR

CPOL

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle low.

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle

state (see CPOL).

2

CPHA

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

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Bit Number

Bit Mnemonic

Description

SPR2 SPR1

SPR0 Serial Peripheral Rate

SPR1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

F_{CLK PERIPH}/2

_{CLK PERIPH}/4

1

F

F_{CLK PERIPH}/8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

F_{CLK PERIPH}/128

Invalid

0

SPR0

Reset Value = 0001 0100b

Not bit addressable

Serial Peripheral Status Register The Serial Peripheral Status Register contains flags to signal the following conditions:

(SPSTA)

•

Data transfer complete

Write collision

Inconsistent logic level on SS pin (mode fault error)

Table 57 describes the SPSTA register and explains the use of every bit in the register.

Table 57. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

7

6

5

4

3

-

2

-

1

-

0

-

SPIF

WCOL

SSERR

MODF

Bit

Number

Mnemonic Description

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.

7

SPIF

Set by hardware to indicate that the data transfer has been completed.

Write Collision Flag

Cleared by hardware to indicate that no collision has occurred or has been

approved by a clearing sequence.

6

5

4

WCOL

Set by hardware to indicate that a collision has been detected.

Synchronous Serial Slave Error Flag

SSERR Set by hardware when SS is deasserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or

has been approved by a clearing sequence.

MODF

Set by hardware to indicate that the SS pin is at inappropriate logic level.

Reserved

3

2

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

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Bit

Number

Mnemonic Description

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = 00X0 XXXXb

Not Bit addressable

Serial Peripheral DATa Register The Serial Peripheral Data Register (Table 58) is a read/write buffer for the receive data

(SPDAT)

register. A write to SPDAT places data directly into the shift register. No transmit buffer is

available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content

of the shift register.

Table 58. SPDAT Register

SPDAT - Serial Peripheral Data Register (0C5H)

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there

is no on-going exchange. However, special care should be taken when writing to them

while a transmission is on-going:

•

Do not change SPR2, SPR1 and SPR0

Do not change CPHA and CPOL

Do not change MSTR

Clearing SPEN would immediately disable the peripheral

Writing to the SPDAT will cause an overflow.

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Hardware Watchdog

Timer

The WDT is intended as a recovery method in situations where the CPU may be sub-

jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable

the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location

0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator

is running and there is no way to disable the WDT except through reset (either hardware

reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST-pin.

Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR

location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH

and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it

reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will

increment every machine cycle while the oscillator is running. This means the user must

reset the WDT at least every 16383 machine cycle. To reset the WDT the user must

write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter

cannot be read or written. When WDT overflows, it will generate an output RESET pulse

at the RST-pin. The RESET pulse duration is 96 x T_{CLK PERIPH}, where T_{CLK PERIPH}= 1/F_CLK

_PERIPH. To make the best use of the WDT, it should be serviced in those sections of code

that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out

capability, ranking from 16 ms to 2 s @ F_OSCA= 12 MHz. To manage this feature, see

WDTPRG register description, Table 59.

Table 59. WDTRST Register

WDTRST - Watchdog Reset Register (0A6h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in

sequence.

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Table 60. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)

7

-

6

-

5

-

4

-

3

-

2

1

0

S2

S1

S0

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

0

-

Reserved

-

The value read from this bit is undetermined. Do not try to set this bit.

-

S2

S1

S0

WDT Time-out Select Bit 2

WDT Time-out Select Bit 1

WDT Time-out Select Bit 0

S2

0

1

S1

0

1

0

1

S0Selected Time-out

0(2¹⁴- 1) machine cycles, 16. 3 ms @ F_OSCA= 12 MHz

1(2¹⁵- 1) machine cycles, 32.7 ms @ F_OSCA= 12 MHz

0 (2¹⁶- 1) machine cycles, 65. 5 ms @ F_OSCA= 12 MHz

1(2¹⁷- 1) machine cycles, 131 ms @ F_OSCA= 12 MHz

0(2¹⁸- 1) machine cycles, 262 ms @ F_OSCA= 12 MHz

1 (2¹⁹- 1) machine cycles, 542 ms @ F_OSCA= 12 MHz

0(2²⁰- 1) machine cycles, 1.05 s @ F_OSCA= 12 MHz

1 (2²¹- 1) machine cycles, 2.09 s @ F_OSCA= 12 MHz

Reset Value = XXXX X000

WDT During Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in

Power-down mode the user does not need to service the WDT. There are two methods

and Idle

of exiting Power-down mode: by a hardware reset or via a level activated external inter-

rupt which is enabled prior to entering Power-down mode. When Power-down is exited

with hardware reset, servicing the WDT should occur as it normally should whenever the

AT89C51RB2/RC2 is reset. Exiting Power-down with an interrupt is significantly differ-

ent. The interrupt is held low long enough for the oscillator to stabilize. When the

interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the

device while the interrupt pin is held low, the WDT is not started until the interrupt is

pulled high. It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of power-down,

it is better to reset the WDT just before entering power-down.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will

periodically exit Idle, service the WDT, and re-enter Idle mode.

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ONCE^™Mode (ON

Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using AT89C51RB2/RC2

without removing the circuit from the board. The ONCE mode is invoked by driving cer-

tain pins of the AT89C51RB2/RC2; the following sequence must be exercised:

•

Pull ALE low while the device is in reset (RST high) and PSEN is high.

Hold ALE low as RST is deactivated.

While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to

drive the circuit. Table 61 shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 61. External Pin Status during ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

XTAL1/2

Weak pull-up Weak pull-up

Float

Weak pull-up Weak pull-up Weak pull-up

Active

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Power Management

Two power reduction modes are implemented in the AT89C51RB2/RC2: the Idle mode

and the Power-down mode. These modes are detailed in the following sections. In addi-

tion to these power reduction modes, the clocks of the core and peripherals can be

dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”.

Reset

In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an

high level has to be applied on the RST pin. A bad level leads to a wrong initialization of

the internal registers like SFRs, Program Counter… and to unpredictable behavior of

the microcontroller. A proper device reset initializes the AT89C51RB2/RC2 and vectors

the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset

by simply connecting an external capacitor to V_DDas shown in Figure 32. A warm reset

can be applied either directly on the RST pin or indirectly by an internal reset source

such as the watchdog timer. Resistor value and input characteristics are discussed in

the Section “DC Characteristics” of the AT89C51RB2/RC2 datasheet.

Figure 32. Reset Circuitry and Power-On Reset

VDD

From Internal

Reset Source

P

VDD

To CPU Core

and Peripherals

RST

+

RST

VSS

RST input circuitry

Power-on Reset

Cold Reset

2 conditions are required before enabling a CPU start-up:

•

V

_DDmust reach the specified V_DDrange

The level on X1 input pin must be outside the specification (V_IH, V_IL)

If one of these 2 conditions are not met, the microcontroller does not start correctly and

can execute an instruction fetch from anywhere in the program space. An active level

applied on the RST pin must be maintained till both of the above conditions are met. A

reset is active when the level V_IH1is reached and when the pulse width covers the

period of time where V_DDand the oscillator are not stabilized. 2 parameters have to be

taken into account to determine the reset pulse width:

•

V_DDrise time,

Oscillator startup time.

To determine the capacitor value to implement, the highest value of these 2 parameters

has to be chosen. Table 1 gives some capacitor values examples for a minimum R_RSTof

50 KΩ and different oscillator startup and V_DDrise times.

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Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor⁽¹⁾

VDD Rise Time

10 ms

Oscillator

Start-Up Time

1 ms

820 nF

2.7 µF

100 ms

12 µF

5 ms

1.2 µF

20 ms

3.9 µF

12 µF

Note:

These values assume V_DDstarts from 0V to the nominal value. If the time between 2

on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully

discharged, leading to a bad reset sequence.

Warm Reset

To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock

periods is mode independent (X2 or X1).

Watchdog Reset

As detailed in Section “Hardware Watchdog Timer”, page 77, the WDT generates a 96-

clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of

the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ

resistor must be added as shown Figure 33.

Figure 33. Reset Circuitry for WDT Reset-out Usage

VDD

From WDT

+

Reset Source

P

RST

To CPU Core

and Peripherals

VDD

1K

RST

VSS

To Other

On-board

VSS

Circuitry

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Reset Recommendation

to Prevent Flash

Corruption

An example of bad initialization situation may occur in an instance where the bit

ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since

this bit allows mapping of the bootloader in the code area, a reset failure can be critical.

If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet

due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program

Counter is accidently in the range of the boot memory addresses then a Flash access

(write or erase) may corrupt the Flash on-chip memory.

It is recommended to use an external reset circuitry featuring power supply monitoring to

prevent system malfunction during periods of insufficient power supply voltage (power

supply failure, power supply switched off).

Idle Mode

An instruction that sets PCON.0 indicates that it is the last instruction to be executed

before going into Idle mode. In Idle mode, the internal clock signal is gated off to the

CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-

served in its entirety: the Stack Pointer, Program Counter, Program Status Word,

Accumulator and all other registers maintain their data during idle. The port pins hold the

logical states they had at the time Idle was activated. ALE and PSEN hold at logic high

level.

There are two ways to terminate the Idle mode. Activation of any enabled interrupt will

cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will

be serviced, and following RETI the next instruction to be executed will be the one fol-

lowing the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-

ing normal operation or during idle. For example, an instruction that activates idle can

also set one or both flag bits. When idle is terminated by an interrupt, the interrupt ser-

vice routine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycles (24 oscillator periods) to complete the reset.

Power-down Mode

To save maximum power, a Power-down mode can be invoked by software (see Table

14, PCON register).

In Power-down mode, the oscillator is stopped and the instruction that invoked Power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the Power-down mode is terminated. V_CCcan be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from Power-

down. To properly terminate Power-down, the reset or external interrupt should not be

executed before V_CCis restored to its normal operating level and must be held active

long enough for the oscillator to restart and stabilize.

Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from

Power-down. For that, interrupt must be enabled and configured as level or edge sensi-

tive interrupt input. When Keyboard Interrupt occurs after a power down mode, 1024

clocks are necessary to exit to power down mode and enter in operating mode.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 34. When both interrupts are enabled, the oscillator restarts as soon

as one of the two inputs is held low and power down exit will be completed when the first

input will be released. In this case, the higher priority interrupt service routine is exe-

cuted. Once the interrupt is serviced, the next instruction to be executed after RETI will

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be the one following the instruction that puts the AT89C51RB2/RC2 into Power-down

mode.

Figure 34. Power-down Exit Waveform

INT0

INT1

XTALA

or

XTALB

Active Phase

Power-down Phase

Oscillator Restart Phase

Active Phase

Exit from Power-down by reset redefines all the SFRs, exit from Power-down by exter-

nal interrupt does no affect the SFRs.

Exit from Power-down by either reset or external interrupt or keyboard interrupt does not

affect the internal RAM content.

Note:

If idle mode is activated with Power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode is not entered.

Table 62 shows the state of ports during idle and power-down modes.

Table 62. State of Ports

Mode

Idle

Program Memory

Internal

ALE

PSEN

PORT0

Port Data⁽¹⁾

Floating

PORT1

PORT2

PORT3

1

0

1

0

Port Data

Address

Port Data

Idle

External

Power Down

Internal

Port Data⁽¹⁾

Floating

External

Port 0 can force a 0 level. A "one" will leave port floating.

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Power-off Flag

The Power-off flag allows the user to distinguish between a “cold start” reset and a

“warm start” reset.

A cold start reset is the one induced by V_CCswitch-on. A warm start reset occurs while

V

_CCis still applied to the device and could be generated by an exit from Power-down.

The Power-off flag (POF) is located in PCON register (Table 63). POF is set by hard-

ware when V_CCrises from 0 to its nominal voltage. The POF can be set or cleared by

software allowing the user to determine the type of reset.

Table 63. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode Bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

Serial port Mode Bit 0

SMOD0 Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Power-off Flag

Cleared to recognize next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by

software.

4

POF

General-purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle Mode Bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

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AT89C51RB2/RC2

Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting

AO bit.

The AO bit is located in AUXR register at bit location 0.As soon as AO is set, ALE is no

longer output but remains active during MOVX and MOVC instructions and external

fetches. During ALE disabling, ALE pin is weakly pulled high.

Table 64. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

-

5

4

-

3

2

1

0

DPU

M0

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Disable Weak Pull-up

7

6

DPU

-

Cleared to activate the permanent weak pull up when latch data is logic 1

Set to disactive the weak pull-up.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse Length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock

periods (default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock

periods.

Reserved

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

XRS1

XRAM Size

XRS1 XRS0

XRAM size

0

1

0

1

0

1

256 Bytes (default)

512 Bytes

768 Bytes

1024 Bytes

2

XRS0

EXTRAM Bit

Cleared to access internal XRAM using movx @ Ri @ DPTR.

EXTRAM Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

1

0

(HSB), default setting, XRAM selected.

ALE Output Bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AO

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Flash EEPROM

Memory

The Flash memory increases EPROM and ROM functionality with in-circuit electrical

erasure and programming. It contains 16K or 32K Bytes of program memory organized

in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Pro-

grammable (ISP). ISP allows devices to alter their own program memory in the actual

end product under software control. A default serial loader (bootloader) program allows

ISP of the Flash.

The programming does not require external dedicated programming voltage. The nec-

essary high programming voltage is generated on-chip using the standard V_CCpins of

the microcontroller.

Features

•

Flash EEPROM internal program memory.

Boot vector allows user provided Flash loader code to reside anywhere in the Flash

memory space. This configuration provides flexibility to the user.

•

Default loader in Boot ROM allows programming via the serial port without the need

of a user-provided loader.

Up to 64K Byte external program memory if the internal program memory is

disabled (EA = 0).

•

Programming and erase voltage with standard 5V or 3V V_CCsupply.

Read/Programming/Erase:

–

Byte-wise read without wait state

Byte or page erase and programming (10 ms)

•

Typical programming time (32K Bytes) in 10 s

Parallel programming with 87C51 compatible hardware interface to programmer

Programmable security for the code in the Flash

100K write cycles

10 years data retention

Flash Programming and The 16K or 32K Bytes Flash is programmed by Bytes or by pages of 128 Bytes. It is not

necessary to erase a Byte or a page before programming. The programming of a Byte

or a page includes a self erase before programming.

Erasure

There are three methods of programming the Flash memory:

•

First, the on-chip ISP bootloader may be invoked which will use low level routines to

program the pages. The interface used for serial downloading of Flash is the UART.

Second, the Flash may be programmed or erased in the end-user application by

calling low-level routines through a common entry point in the Boot ROM.

Third, the Flash may be programmed using the parallel method by using a

conventional EPROM programmer. The parallel programming method used by

these devices is similar to that used by EPROM 87C51 but it is not identical and the

commercially available programmers need to have support for the

AT89C51RB2/RC2. The bootloader and the Application Programming Interface

(API) routines are located in the BOOT ROM.

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Flash Registers and

Memory Map

The AT89C51RB2/RC2 Flash memory uses several registers for its management:

•

Hardware registers can only be accessed through the parallel programming modes

which are handled by the parallel programmer.

•

Software registers are in a special page of the Flash memory which can be

accessed through the API or with the parallel programming modes. This page,

called "Extra Flash Memory", is not in the internal Flash program memory

addressing space.

Hardware Register

The only hardware register of the AT89C51RB2/RC2 is called Hardware Security Byte

(HSB).

Table 65. Hardware Security Byte (HSB)

7

6

5

-

4

-

3

2

1

0

X2

BLJB

XRAM

LB2

LB1

LB0

Bit

Number

Mnemonic Description

X2 Mode

Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.

7

X2

Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset

(Default).

Boot Loader Jump Bit

Unprogrammed (‘1’ value) to start the user’s application on next reset at address

0000h.

6

BLJB

Programmed (‘0’ value) to start the boot loader at address F800h on next reset

(Default).

5

4

-

Reserved

XRAM Config Bit (only programmable by programmer tools)

Programmed to inhibit XRAM after reset.

3

XRAM

LB2-0

Unprogrammed, this bit to valid XRAM after reset (Default).

User Memory Lock Bits (only programmable by programmer tools)

2-0

See Table 66.

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

•

When this bit is programmed (‘1’ value) the boot address is 0000h.

When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,

this bit is unprogrammed and the ISP is enabled.

Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 66.

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Table 66. Program Lock Bits

Program Lock Bits

Security

Level

LB0

LB1

LB2 Protection Description

1

U

No program lock features enabled.

MOVC instruction executed from external program memory is disabled

from fetching code Bytes from internal memory, EA is sampled and

latched on reset, and further parallel programming of the Flash is

disabled. ISP and software programming with API are still allowed.

2

P

U

Same as 2, also verify through parallel programming interface is

disabled.

3

4

X

P

X

U

P

Same as 3, also external execution is disabled. (Default)

Note:

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X: don’t care

WARNING: Security level ‘2’ and ‘3‘ should only be programmed after Flash and code

verification.

These security bits protect the code access through the parallel programming interface.

They are set by default to level 4. The code access through the ISP is still possible and

is controlled by the "software security bits" which are stored in the extra Flash memory

accessed by the ISP firmware.

To load a new application with the parallel programmer, a chip erase must first be done.

This will set the HSB in its inactive state and will erase the Flash memory. The part ref-

erence can always be read using Flash parallel programming modes.

Default Values

The default value of the HSB provides parts ready to be programmed with ISP:

•

BLJB: Programmed force ISP operation.

X2: Unprogrammed to force X1 mode (Standard Mode).

XRAM: Unprogrammed to valid XRAM

LB2-0: Security level four to protect the code from a parallel access with maximum

security.

Software Registers

Several registers are used, in factory and by parallel programmers, to make copies of

hardware registers contents. These values are used by Atmel ISP.

These registers are in the "Extra Flash Memory" part of the Flash memory. This block is

also called "XAF" or eXtra Array Flash. They are accessed in the following ways:

•

Commands issued by the parallel memory programmer.

Commands issued by the ISP software.

Calls of API issued by the application software.

Several software registers are described in Table 67.

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Table 67. Default Values

Mnemonic Definition

Default value Description

SBV

HSB

BSB

SSB

Software Boot Vector

FCh

101x 1011b

0FFh

Hardware security Byte

Boot Status Byte

Software Security Byte

FFh

Copy of the Manufacturer Code

Copy of the Device ID #1: Family Code

Copy of the Device ID #2: memories

size and type

58h

D7h

F7h

FBh

ATMEL

C51 X2, Electrically Erasable

AT89C51RB2/RC2 32KB

AT89C51RB2/RC2 16 KB

Copy of the Device ID #3: name and

revision

AT89C51RB2/RC2 32KB,

Revision 0

EFh

FFh

AT89C51RB2/RC2 16 KB,

Revision 0

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the

application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 67 and Table 69.

To assure code protection from a parallel access, the HSB must also be at the required

level.

Table 68. Software Security Byte

7

-

6

-

5

-

4

-

3

-

2

-

1

0

LB1

LB0

Bit

Number

Mnemonic Description

Reserved

Do not clear this bit.

7

6

5

4

3

2

-

Reserved

Do not clear this bit.

-

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

Reserved

Do not clear this bit.

User Memory Lock Bits

1-0

LB1-0

see Table 69

The two lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 69.

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Table 69. Program Lock Bits of the SSB

Program Lock Bits

Security

level

LB0

U

LB1 Protection Description

1

2

3

U

P

No program lock features enabled.

P

ISP programming of the Flash is disabled.

X

Same as 2, also verify through ISP programming interface is disabled.

Note:

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X: don’t care

WARNING: Security level 2 and 3 should only be programmed after Flash and code

verification.

Flash Memory Status

AT89C51RB2/RC2 parts are delivered in standard with the ISP boot in the Flash mem-

ory. After ISP or parallel programming, the possible contents of the Flash memory are

summarized on Figure 35.

Figure 35. Flash Memory Possible Contents

7FFFh

T89C51RC2 32KB

3FFFh T89C51RB2 16KB

Virgin

or

Application

Virgin

Application

Virgin

or

Application

Dedicated

ISP

Dedicated

ISP

0000h

After Parallel

Programming

After Parallel

Programming

After ISP

Default

After ISP

Memory Organization

In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memory address

space is filled by internal Flash.

When the EA pin is high, the processor fetches instructions from internal program Flash.

Bus expansion for accessing program memory from 16K or 32K upward automatic since

external instruction fetches occur automatically when the program counter exceeds

3FFFh (16K) or 7FFFh (32K). If the EA pin is tied low, all program memory fetches are

from external memory.

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AT89C51RB2/RC2

Bootloader Architecture

Introduction

The bootloader manages a communication according to a specific defined protocol to

provide the whole access and service on Flash memory. Furthermore, all accesses and

routines can be called from the user application.

Figure 36. Diagram Context Description

Access via

Specific

Protocol

Flash Memory

Bootloader

Access From

User

Application

Acronyms

ISP: In-system Programming

SBV: Software Boot Vector

BSB: Boot Status Byte

SSB: Software Security Bit

HW : Hardware Byte

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Functional Description

Figure 37. Bootloader Functional Description

Exernal Host with

Specific Protocol

Communication

User

Application

User Call

Management (API )

ISP Communication

Management

Flash Memory

Management

Flash

Memory

On the above diagram, the on-chip bootloader processes are:

ISP Communication Management

•

The purpose of this process is to manage the communication and its protocol between

the on-chip bootloader and a external device. The on-chip ROM implement a serial pro-

tocol (see section Bootloader Protocol). This process translate serial communication

frame (UART) into Flash memory acess (read, write, erase ...).

•

User Call Management

Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

through a common interface (API calls), included in the ROM bootloader. The program-

ming functions are selected by setting up the microcontroller’s registers before making a

call to a common entry point (0xFFF0). Results are returned in the registers. The pur-

pose on this process is to translate the registers values into internal Flash Memory

Management.

•

Flash Memory Management

This process manages low level access to Flash memory (performs read and write

access).

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Bootloader Functionality

Introduction

The bootloader can be activated by two means: Hardware conditions or regular boot

process.

The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the

on-chip bootloader execution. This allows an application to be built that will normally

execute the end user’s code but can be manually forced into default ISP operation.

As PSEN is an output port in normal operating mode (running user application or boor-

loader code) after reset, it is recommended to release PSEN after falling edge of reset

signal. The hardware conditions are sampled at reset signal falling edge, thus they can

be released at any time when reset input is low.

To ensure correct microcontroller startup, the PSEN pin should not be tied to ground

during power-on (See Figure 38).

Figure 38. Hardware conditions typical sequence during power-on.

VCC

PSEN

RST

The on-chip bootloader boot process is shown in Figure 39.

Purpose

The Hardware Conditions force the bootloader execution whatever BLJB, BSB

and SBV values.

Hardware Conditions

The Boot Loader Jump Bit forces the application execution.

BLJB = 0 => Boot loader execution.

BLJB = 1 => Application execution.

The BLJB is a fuse bit in the Hardware Byte.

BLJB

That can be modified by hardware (programmer) or by software (API).

Note:

The BLJB test is perform by hardware to prevent any program execution.

The Software Boot Vector contains the high address of custumer bootloader

stored in the application.

SBV = FCh (default value) if no custumer bootloader in user Flash.

SBV

Note:

The costumer bootloader is called by JMP [SBV]00h instruction.

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Boot Process

Figure 39. Bootloader process

RESET

If BLJB = 0 then ENBOOT bit (AUXR1) is set

else ENBOOT bit (AUXR1) is cleared

Yes (PSEN = 0, EA = 1, and ALE = 1 or not connected)

FCON = 00h

Hardware

Condition?

FCON = F0h

BLJB = 1

BLJB!= 0

?

ENBOOT = 0

BLJB = 0

ENBOOT = 1

F800h

yes = hardware boot conditions

FCON = 00h

?

BSB = 00h

?

PC = 0000h

USER APPLICATION

SBV = FCh

?

USER BOOT LOADER

Atmel BOOT LOADER

PC= [SBV]00h

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ISP Protocol Description

Physical Layer

The UART used to transmit information has the following configuration:

•

Character: 8-bit data

Parity: none

Stop: 1 bit

Flow control: none

Baud rate: autobaud is performed by the bootloader to compute the baud rate

choosen by the host.

Frame Description

The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and

are summarized below.

Table 70. Intel Hex Type Frame

Record Mark ‘:’

Reclen

Load Offset

Record Type

Data or Info

Checksum

1 byte

2 bytes

1 bytes

n byte

1 byte

•

Record Mark:

Record Mark is the start of frame. This field must contain ’:’.

Reclen:

Reclen specifies the number of Bytes of information or data which follows

the Record Type field of the record.

Load Offset:

–

•

–

Load Offset specifies the 16-bit starting load offset of the data Bytes,

therefore this field is used only for

–

Data Program Record (see Section “ISP Commands Summary”).

•

Record Type:

–

Record Type specifies the command type. This field is used to interpret the

remaining information within the frame. The encoding for all the current

record types is described in Section “ISP Commands Summary”.

Data/Info:

–

Data/Info is a variable length field. It consists of zero or more Bytes encoded

as pairs of hexadecimal digits. The meaning of data depends on the Record

Type.

Checksum:

–

The two’s complement of the 8-bit Bytes that result from converting each pair

of ASCII hexadecimal digits to one Byte of binary, and including the Reclen

field to and including the last Byte of the Data/Info field. Therefore, the sum

of all the ASCII pairs in a record after converting to binary, from the Reclen

field to and including the Checksum field, is zero.

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Functional Description

Software Security Bits (SSB)

The SSB protects any Flash access from ISP command.

The command "Program Software Security bit" can only write a higher priority level.

There are three levels of security:

•

level 0: NO_SECURITY (FFh)

This is the default level.

From level 0, one can write level 1 or level 2.

•

level 1: WRITE_SECURITY (FEh )

For this level it is impossible to write in the Flash memory, BSB and SBV.

The Bootloader returns ’P’ on write access.

From level 1, one can write only level 2.

•

level 2: RD_WR_SECURITY (FCh

The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.

The Bootloader returns ’L’ on read or write access.

Only a full chip erase in parallel mode (using a programmer) or ISP command can reset

the software security bits.

From level 2, one cannot read and write anything.

Table 71. Software Security Byte Behavior

Level 0

Level 1

Level 2

Flash/EEPROM

Fuse Bit

Any access allowed

Read only access allowed

Write level 2 allowed

Any access not allowed

Read only access allowed

BSB & SBV

SSB

Manufacturer

Info

Read only access allowed

Bootloader Info

Erase Block

Read only access allowed

Allowed

Read only access allowed

Not allowed

Read only access allowed

Not allowed

Full-chip Erase

Blank Check

Allowed

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Full Chip Erase

The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and

sets some Bytes used by the bootloader at their default values:

•

BSB = FFh

SBV = FCh

SSB = FFh and finally erase the Software Security Bits

The Full Chip Erase does not affect the bootloader.

Checksum Error

When a checksum error is detected send ‘X’ followed with CR&LF.

Flow Description

Overview

An initialization step must be performed after each Reset. After microcontroller reset,

the bootloader waits for an autobaud sequence ( see section ‘autobaud performance’).

When the communication is initialized the protocol depends on the record type

requested by the host.

FLIP, a software utility to implement ISP programming with a PC, is available from the

Atmel the web site.

Communication Initialization

The host initializes the communication by sending a ’U’ character to help the bootloader

to compute the baudrate (autobaud).

Figure 40. Initialization

Bootloader

Host

Init Communication

"U"

Performs Autobaud

If (not received "U")

Else

Sends Back ‘U’ Character

Communication Opened

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Autobaud Performances

The ISP feature allows a wide range of baud rates in the user application. It is also

adaptable to a wide range of oscillator frequencies. This is accomplished by measuring

the bit-time of a single bit in a received character. This information is then used to pro-

gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP

feature requires that an initial character (an uppercase U) be sent to the

AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capability.

Table 72. Autobaud Performances

Frequency (MHz)

Baudrate (bit/s)

1.8432

2

2.4576

OK

-

3

3.6864

OK

-

4

OK

-

5

6

7.3728

OK

8

2400

OK

-

OK

-

OK

-

OK

4800

-

OK

9600

OK

19200

38400

57600

115200

OK

-

OK

-

OK

-

OK

-

OK

Frequency (MHz)

Baudrate (bit/s)

10

OK

-

11.0592

OK

12

OK

-

14.318

OK

14.746

OK

16

20

24

26.6

OK

-

2400

OK

-

OK

-

OK

-

4800

OK

9600

OK

19200

38400

57600

115200

OK

-

OK

-

OK

-

OK

Command Data Stream

Protocol

All commands are sent using the same flow. Each frame sent by the host is echoed by

the bootloader.

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AT89C51RB2/RC2

Figure 41. Command Flow

Host

Bootloader

":"

If (not received ":")

Sends first character of the

Frame

Else

Sends echo and start

reception

Sends frame (made of 2 ASCII

characters per Byte)

Echo analysis

Gets frame, and sends back ec

for each received Byte

Write/Program Commands

This flow is common to the following frames:

•

Flash/EEPROM Programming Data Frame

EOF or Atmel Frame (only Programming Atmel Frame)

Config Byte Programming Data Frame

Baud Rate Frame

Description

Figure 42. Write/Program Flow

Bootloader

Host

Write Command

’X’ & CR & LF

Send Write Command

Wait Write Command

OR

Checksum error

Wait Checksum Error

COMMAND ABORTED

Send Checksum error

NO_SECURITY

OR

’P’ & CR & LF

’.’ & CR & LF

Wait Security Error

Send Security error

COMMAND ABORTED

Wait Programming

Wait COMMAND_OK

COMMAND FINISHED

Send COMMAND_OK

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Example

Programming Data (write 55h at address 0010h in the Flash)

HOST

: 01 0010 00 55 9A

BOOTLOADER

: 01 0010 00 55 9A . CR LF

Programming Atmel function (write SSB to level 2)

HOST

: 02 0000 03 05 01 F5

BOOTLOADER

: 02 0000 03 05 01 F5. CR LF

Writing Frame (write BSB to 55h)

HOST

: 03 0000 03 06 00 55 9F

BOOTLOADER

: 03 0000 03 06 00 55 9F . CR LF

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Blank Check Command

Description

Figure 43. Blank Check Flow

Bootloader

Host

Blank Check Command

’X’ & CR & LF

Send Blank Check Command

Wait Blank Check Command

OR

Wait Checksum Error

Checksum error

Send Checksum error

COMMAND ABORTED

Flash blank

’.’ & CR & LF

Wait COMMAND_OK

COMMAND FINISHED

OR

Send COMMAND_OK

address & CR & LF

Send first Address

not erased

Wait Address not

erased

COMMAND FINISHED

Example

Blank Check ok

HOST

: 05 0000 04 0000 7FFF 01 78

: 05 0000 04 0000 7FFF 01 78 . CR LF

BOOTLOADER

Blank Check ko at address xxxx

HOST

: 05 0000 04 0000 7FFF 01 78

BOOTLOADER

: 05 0000 04 0000 7FFF 01 78 xxxx CR LF

Blank Check with checksum error

HOST

: 05 0000 04 0000 7FFF 01 70

BOOTLOADER

: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF

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Display Data

Description

Figure 44. Display Flow

Bootloader

Host

Display Command

’X’ & CR & LF

Send Display Command

Wait Display Command

OR

Checksum error

Wait Checksum Error

Send Checksum Error

COMMAND ABORTED

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security Error

COMMAND ABORTED

Read Data

All data read

Complete Frame

"Address = "

"Reading value"

CR & LF

Wait Display Data

Send Display Data

All data read

COMMAND FINISHED

Note:

The maximum size of block is 400h. To read more than 400h Bytes, the Host must send a new command.

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AT89C51RB2/RC2

Example

Display data from address 0000h to 0020h

HOST

: 05 0000 04 0000 0020 00 D7

BOOTLOADER

: 05 0000 04 0000 0020 00 D7

0000=-----data------ CR LF

0010=-----data------ CR LF

0020=data CR LF

(16 data)

( 1 data)

Read Function

This flow is similar for the following frames:

•

Reading Frame

EOF Frame/Atmel Frame (only reading Atmel Frame)

Description

Figure 45. Read Flow

Bootloader

Host

Read Command

’X’ & CR & LF

Send Read Command

Wait Read Command

OR

Checksum error

Wait Checksum Error

COMMAND ABORTED

Send Checksum error

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security error

COMMAND ABORTED

Read Value

’value’ & ’.’ & CR & LF

Wait Value of Data

Send Data Read

COMMAND FINISHED

Example

Read function (read SBV)

HOST

: 02 0000 05 07 02 F0

: 02 0000 05 07 02 F0 Value . CR LF

BOOTLOADER

Atmel Read function (read Bootloader version)

HOST

: 02 0000 01 02 00 FB

BOOTLOADER

: 02 0000 01 02 00 FB Value . CR LF

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ISP Commands Summary

Table 73. ISP Commands Summary

Command

Command Name

Data[0]

Data[1]

Command Effect

Program Nb Data Byte.

Bootloader will accept up to 128 (80h)

data Bytes. The data Bytes should be

128 Byte page Flash boundary.

00h

Program Data

00h

20h

40h

80h

C0h

00h

01h

00h

01h

Erase block0 (0000h-1FFFh)

Erase block1 (2000h-3FFFh)

Erase block2 (4000h-7FFFh)

Erase block3 (8000h- BFFFh)

Erase block4 (C000h- FFFFh)

Hardware Reset

01h

03h

04h

Erase SBV & BSB

Program SSB level 1

05h

Program SSB level 2

03h

Write Function

Program BSB (value to write in data[2])

Program SBV (value to write in data[2])

06h

07h

Full Chip Erase (This command needs

about 6 sec to be executed)

-

Program Osc fuse (value to write in

data[2])

02h

04h

08h

Program BLJB fuse (value to write in

data[2])

0Ah

Program X2 fuse (value to write in

data[2])

Display Data

Data[0:1] = start address

Data [2:3] = end address

Note: The maximum number of data

that can be read with a single

command frame (difference between

start and end address) is 1kbyte.

04h

Display Function

Data[4] = 00h -> Display data

Data[4] = 01h -> Blank check

Blank Check

00h

Manufacturer ID

Device ID #1

01h

00h

02h

Device ID #2

03h

00h

Device ID #3

Read SSB

01h

Read BSB

05h

Read Function

07h

02h

Read SBV

06h

Read Extra Byte

Read Hardware Byte

Read Device Boot ID1

Read Device Boot ID2

Read Bootloader Version

0Bh

0Eh

0Fh

00h

01h

00h

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API Call Description

Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

through a common interface, PGM_MTP. The programming functions are selected by

setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h.

Results are returned in the registers.

When several Bytes have to be programmed, it is highly recommended to use the Atmel

API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 Bytes in a sin-

gle command.

All routines for software access are provided in the C Flash driver available at Atmel’s

web site.

The API calls description and arguments are shown in Table 74.

Table 74. API Call Summary

Command

R1

A

DPTR0

DPTR1

Returned Value

Command Effect

ACC = Manufacturer

Id

READ MANUF ID

00h

XXh

0000h

XXh

Read Manufacturer identifier

READ DEVICE ID1

READ DEVICE ID2

READ DEVICE ID3

00h

XXh

0001h

0002h

XXh

ACC = Device Id 1

ACC = Device Id 2

ACC = Device Id 3

Read Device identifier 1

Read Device identifier 2

Read Device identifier 3

Erase block 0

0003h

DPH = 00h

DPH = 20h

DPH = 40h

ERASE BLOCK

01h

XXh

00h

ACC = DPH

Erase block 1

Erase block 2

Address of

byte to

program

PROGRAM DATA

BYTE

Program up one data byte in the on-chip

flash memory.

02h Vaue to write

XXh

ACC = 0: DONE

DPH = 00h

DPL = 00h

Set SSB level 1

Set SSB level 2

Set SSB level 0

DPH = 00h

DPL = 01h

PROGRAM SSB

05h

XXh

00h

ACC = SSB value

DPH = 00h

DPL = 10h

DPH = 00h

DPL = 11h

Set SSB level 1

New BSB

value

PROGRAM BSB

PROGRAM SBV

06h

0000h

0001h

XXh

none

Program boot status byte

Program software boot vector

New SBV

value

READ SSB

READ BSB

READ SBV

07h

XXh

0000h

0001h

0002h

XXh

ACC = SSB

ACC = BSB

ACC = SBV

Read Software Security Byte

Read Boot Status Byte

Read Software Boot Vector

Program up to 128 bytes in user Flash.

Address of

the first byte

to program in

the Flash

Address in

XRAM of the

first data to

program

Number of

byte to

program

Remark: number of bytes to program is

limited such as the Flash write remains in a

single 128 bytes page. Hence, when ACC

is 128, valid values of DPL are 00h, or, 80h.

ACC = 0: DONE

PROGRAM DATA

PAGE

09h

memory

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4180E–8051–10/06

Table 74. API Call Summary (Continued)

Command

R1

A

DPTR0

DPTR1

Returned Value

Command Effect

Fuse value

00h or 01h

PROGRAM X2 FUSE

0Ah

0008h

XXh

none

Program X2 fuse bit with ACC

Fuse value

00h or 01h

PROGRAM BLJB

FUSE

0Ah

0004h

XXh

none

Program BLJB fuse bit with ACC

READ HSB

0Bh

0Eh

XXh

XXXXh

DPL = 00h

DPL = 01h

XXXXh

XXh

ACC = HSB

ACC = ID1

Read Hardware Byte

Read boot ID1

READ BOOT ID1

READ BOOT ID2

ACC = ID2

Read boot ID2

READ BOOT VERSION 0Fh

ACC = Boot_Version

Read bootloader version

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Electrical Characteristics

Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only and func-

tional operation of the device at these or any other

conditions above those indicated in the operational

sections of this specification is not implied. Expo-

sure to absolute maximum rating conditions may

affect device reliability.

C = commercial......................................................0°C to 70°C

I = industrial ........................................................-40°C to 85°C

Storage Temperature .................................... -65°C to + 150°C

Voltage on V_CCto V_SS(standard voltage).........-0.5V to + 6.5V

Voltage on V_CCto V_SS(low voltage)..................-0.5V to + 4.5V

Voltage on Any Pin to V_SS..........................-0.5V to V_CC+ 0.5V

Power Dissipation.............................................................. 1 W

Power dissipation value is based on the maximum

allowable die temperature and the thermal resis-

tance of the package.

DC Parameters for

Standard Voltage

T_A= -40°C to +85°C; V_SS= 0V;

V_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

V_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)

Symbol Parameter

Min

-0.5

Typ

Max

Unit Test Conditions

V_IL

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V

V_IH

Input High Voltage except RST, XTAL1

Input High Voltage RST, XTAL1

0.2 V_CC+ 0.9

0.7 V_CC

V

(9)

V_IH1

V

VCC = 4.5V to 5.5V

0.3

0.45

1.0

V

I_OL= 100 μA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL

Output Low Voltage, ports 1, 2, 3, 4 ⁽⁶⁾

VCC = 2.7V to 5.5V

I_OL= 0.8 mA⁽⁴⁾

0.45

V

VCC = 4.5V to 5.5V

I_OL= 200 μA⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

I_OL= 7.0 mA⁽⁴⁾

0.3

0.45

1.0

V

V_OL1

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

VCC = 2.7V to 5.5V

I_OL= 1.6 mA⁽⁴⁾

0.45

V

V_CC= 5V 10%

I_OH= -10 μA

I_OH= -30 μA

I_OH= -60 μA

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH

Output High Voltage, ports 1, 2, 3, 4

VCC = 2.7V to 5.5V

0.9 V_CC

V

I_OH= -10 μA

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4180E–8051–10/06

T_A= -40°C to +85°C; V_SS= 0V;

V_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

V_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)

Symbol Parameter

Min

Typ

Max

Unit Test Conditions

V_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -200 μA

I_OH= -3.2 mA

I_OH= -7.0 mA

V_OH1

Output High Voltage, port 0, ALE, PSEN

VCC = 2.7V to 5.5V

0.9 V_CC

50

V

I_OH= -10 μA

R_RST

I_IL

RST Pulldown Resistor

200⁽⁵⁾

250

-50

10

kΩ

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current for P0 only

Logical 1 to 0 Transition Current, ports 1, 2, 3, 4

μA V_IN= 0.45V

I_LI

μA 0.45V < V_IN< V_CC

μA V_IN= 2.0V

I_TL

-650

Fc = 3 MHz

pF

C_IO

Capacitance of I/O Buffer

10

T^A= 25°C

I_PD

Power Down Current

100

150

μA 4.5V < V_{CC <}5.5V⁽³⁾

mA V_CC= 5.5V⁽¹⁾

I_CCOP

I_CCIDLE

Power Supply Current on normal mode

Power Supply Current on idle mode

0.4 x Frequency (MHz) + 5

0.3 x Frequency (MHz) + 5

mA V_CC= 5.5V⁽¹⁾

0.4 x

Frequency

(MHz) + 20

I_CCProg

Power Supply Current during flash Write / Erase

mA V_CC= 5.5V⁽⁸⁾

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 49.), V_IL

=

V

_SS+ 0.5V,

_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used (see Figure

46).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 47).

-

3. Power Down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 48).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and

5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

7. For other values, please contact your sales office.

8. Icc Flash Write operation current while an on-chip flash page write is on going.

9. Flash Retention is guaranteed with the same formula for V_CCMin down to 0.

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DC Parameters for Low

Voltage

TA = 0°C to +70°C; V_SS= 0V; V_CC= 2.7V to 3.6V; F = 0to 40 MHz

T^A= -40°C to +85°C; V_SS= 0V; V_CC= 2.7V to 3.6V; F = 0 to 40 MHz

Symbol Parameter

Min

-0.5

Typ

Max

Unit Test Conditions

V_IL

V_IH

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

0.45

V

Input High Voltage except RST, XTAL1

Input High Voltage, RST, XTAL1

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

V_OL

V_OL1

V_OH

V_OH1

I_IL

Output Low Voltage, ports 1, 2, 3, 4⁽⁶⁾

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

Output High Voltage, ports 1, 2, 3, 4

Output High Voltage, port 0, ALE, PSEN

Logical 0 Input Current ports 1, 2, 3, 4

Input Leakage Current for P0 only

Logical 1 to 0 Transition Current, ports 1, 2, 3,

RST Pulldown Resistor

I_OL= 0.8 mA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OH= -10 μA

I_OH= -40 μA

0.45

0.9 V_CC

-50

10

μA V_IN= 0.45 V

μA 0.45V < V_IN< V_CC

μA V_IN= 2.0V

kΩ

I_LI

I_TL

-650

250

R_RST

50

200 ⁽⁵⁾

Fc = 3 MHz

pF

C_IO

Capacitance of I/O Buffer

10

50

T^A= 25°C

V_CC= 2.7V to

I_PD

Power Down Current

10 ⁽⁵⁾

μA

3.6V⁽³⁾

I_CCOP

Power Supply Current on normal mode

0.4 x Frequency (MHz) + 5

0.3 x Frequency (MHz) + 5

mA V_CC= 3.6 V⁽¹⁾

mA V_CC= 3.6 V⁽²⁾

I_CCIDLEPower Supply Current on idle mode

0.4 x

Frequency

(MHz) +

20

I_CCProgPower Supply Current during flash Write / Erase

mA

V

_CC= 5.5V⁽⁸⁾

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 49.), V_IL

=

V

_SS+ 0.5V,

_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used (see Figure

46).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 47).

-

3. Power Down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 48).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and

5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

109

4180E–8051–10/06

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

7. For other values, please contact your sales office.

8. Icc Flash Write operation current while an on-chip flash page write is on going.

Figure 46. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 47. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

XTAL2

XTAL1

V_SS

(NC)

CLOCK

SIGNAL

Figure 48. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

P0

EA

V_CC

RST

(NC)

XTAL2

XTAL1

V_SS

Figure 49. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

110

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

AC Parameters

Explanation of the AC

Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T

_LLPL= Time for ALE Low to PSEN Low.

(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other

outputs = 80 pF.)

Table 75 Table 78, and Table 80 give the description of each AC symbols.

Table 77, Table 79 and Table 81 give the AC parameterfor each range.

Table 76, Table 77 and Table 82 gives the frequency derating formula of the AC param-

eter for each speed range description. To calculate each AC symbols, take the x value

in the correponding column (-M or -L) and use this value in the formula.

Example: T_LLIUfor -M and 20 MHz, Standard clock.

x = 35 ns

T 50 ns

T_CCIV= 4T - x = 165 ns

External Program Memory

Characteristics

Table 75. Symbol Description

Symbol

T

Parameter

Oscillator clock period

ALE pulse width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold after ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold after PSEN

Input Instruction Float after PSEN

Address to Valid Instruction In

PSEN Low to Address Float

111

4180E–8051–10/06

Table 76. AC Parameters for a Fix Clock

Symbol

-M

-L

Units

Min

25

35

5

Max

Min

25

35

5

Max

T

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

5

n 65

30

65

30

5

50

0

10

80

10

80

10

Table 77. AC Parameters for a Variable Clock

Standard

X Parameter for - X Parameter for

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Clock

2 T - x

T - x

4 T - x

T - x

3 T - x

x

X2 Clock

T - x

M Range

-L Range

Units

15

20

35

15

25

45

0

15

20

35

15

25

45

0

ns

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

Min

Max

Min

T_LLPL

T_PLPH

T_PLIV

Min

Max

Min

T_PXIX

T_PXIZ

T_AVIV

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

15

45

10

15

45

10

T_PLAZ

112

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

External Program Memory

Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

T_PLPH

PSEN

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

External Data Memory

Characteristics

Table 78. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

Address to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

113

4180E–8051–10/06

Table 79. AC Parameters for a Fix Clock

-M

-L

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

125

Max

Min

125

Max

Units

ns

95

0

25

155

160

105

155

160

105

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

45

70

5

45

70

5

155

10

0

155

10

0

T_WHLH

5

45

5

45

114

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Standard

Clock

X Parameter for - X Parameter for -

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

X2 Clock

3 T - x

2.5 T - x

x

M Range

25

30

0

L Range

25

30

0

Units

ns

6 T - x

5 T - x

x

Min

Max

Min

Max

Min

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

25

45

65

30

20

15

0

25

45

65

30

20

15

0

4T -x

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

Max

Min

7 T - x

T - x

Min

Max

Min

x

T - x

0.5 T - x

0.5 T + x

20

Max

T + x

External Data Memory Write

Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

115

4180E–8051–10/06

External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

A0-A7

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

PORT 2

ADDRESS A8-A15 OR SFR P2

Serial Port Timing - Shift

Register Mode

Table 80. Symbol Description

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 81. AC Parameters for a Fix Clock

-M

-L

Symbol

T_XLXL

Min

300

200

30

Max

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

117

ns

Table 82. AC Parameters for a Variable Clock

Standard

Clock

X Parameter for - X Parameter for -L

Symbol

T_XLXL

Type

Min

X2 Clock

6 T

M Range

Range

Units

12 T

10 T - x

2 T - x

x

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

5 T - x

T - x

50

20

0

50

20

0

Min

x

Max

10 T - x

5 T- x

133

116

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Shift Register Timing

Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

External Clock Drive

Waveforms

V_CC-0.5V

0.45V

0.7V_CC

0.2V_CC-0.1

T_CHCX

T_CLCH

T_CLCX

T_CHCL

T_CLCL

AC Testing Input/Output

Waveforms

V

_CC-0.5V

0.2 V_CC+ 0.9

0.2 V_CC- 0.1

INPUT/OUTPUT

0.45 V

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

Float Waveforms

FLOAT

V_OH- 0.1 V

V_OL+ 0.1 V

V_LOAD+ 0.1 V

_LOAD- 0.1 V

V_LOAD

V

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH

≥

20mA.

Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

117

4180E–8051–10/06

Figure 50. Internal Clock Signals

STATE4

INTERNAL

STATE5

P1 P2

STATE6

P1 P2

STATE1

STATE2

P1 P2

STATE3

P1 P2

STATE4

P1 P2

STATE5

P1 P2

CLOCK

P1

P2

P1

P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

DATA

PCL OUT

DATA

PCL OUT

DATA

PCL OUT

SAMPLED

FLOAT

P2 (EXT)

INDICATES ADDRESS TRANSITIONS

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

DATA

SAMPLED

P0

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DATA OUT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

MOV PORT SRC

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

(INCLUDES INTO. INT1. TO T1)

SERIAL PORT SHIFT CLOCK

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-

tion also varies from output to output and component. Typically though (T_A= 25°C fully loaded) RD and WR propagation

delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC

specifications.

118

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Ordering Information

Table 83. Possible Order Entries

Part Number

Memory Size

Supply Voltage

Temperature Range

Industrial

Package

PDIL40

Packing

Stick

Tray

Product Marking

89C51RB2-IM

89C51RB2-CM

89C51RB2-IM

89C51RB2-CM

89C51RB2-IM

89C51RB2-IL

89C51RC2-CM

89C51RC2-IM

89C51RC2-CM

89C51RC2-IM

89C51RC2-CM

89C51RC2-IM

89C51RC2-IL

AT89C51RB2-3CSIM

AT89C51RB2-SLSCM

AT89C51RB2-SLSIM

AT89C51RB2-RLTCM

AT89C51RB2-RLTIM

AT89C51RB2-SLSIL

AT89C51RB2-RLTIL

AT89C51RC2-3CSCM

AT89C51RC2-3CSIM

AT89C51RC2-SLSCM

AT89C51RC2-SLSIM

AT89C51RC2-RLTCM

AT89C51RC2-RLTIM

AT89C51RC2-SLSIL

AT89C51RC2-RLTIL

5V

3V

5V

3V

Commercial

Industrial

PLCC44

VQFP44

PLCC44

VQFP44

PDIL40

16 KBytes

Commercial

Industrial

Tray

Industrial

Stick

Tray

Industrial

Commercial

Industrial

Stick

Tray

PDIL40

Commercial

Industrial

PLCC44

VQFP44

PLCC44

VQFP44

32 KBytes

Commercial

Industrial

Tray

Industrial

Stick

Tray

Industrial

AT89C51RB2-3CSUM

AT89C51RB2-SLSUM

AT89C51RB2-RLTUM

AT89C51RB2-SLSUL

AT89C51RB2-RLTUL

AT89C51RB2-RLTUM

AT89C51RC2-3CSUM

AT89C51RC2-SLSUM

AT89C51RC2-RLTUM

AT89C51RC2-SLSUL

AT89C51RC2-RLTUL

5V

3V

5V

3V

Industrial & Green

PDIL40

PLCC44

VQFP44

PLCC44

VQFP44

PDIL40

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

89C51RB2-UM

89C51RB2-UL

89C51RB2-UM

89C51RC2-UM

89C51RC2-UL

16 KBytes

PLCC44

VQFP44

PLCC44

VQFP44

32 KBytes

119

4180E–8051–10/06

Package Information

PDIL40

120

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

VQFP44

121

4180E–8051–10/06

PLC44

122

AT89C51RB2/RC2

4180E–8051–10/06

AT89C51RB2/RC2

Datasheet Change

Log

Changes from 4180A-

08/02 to 4180B-04/03

1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.

2. Added note on Flash retention formula for V_IH1, in Section “DC Parameters for

Standard Voltage”, page 107.

Changes from 4180B-

04/03 to 4180C-12/03

1. Max frequency update for 4.5 to 5.5V range up to 60 MHz (internal code

execution).

Changes from 4180C-

12/03 - 4180D - 06/05

1. Added Green product ordering information. Page 119.

1. Correction to PDIL40 figure on page 9.

Changes from 4180D -

06/05 to 4180E - 10/06

123

4180E–8051–10/06

Table of Contents

Features ................................................................................................. 1

Description ............................................................................................ 1

Block Diagram ....................................................................................... 3

SFR Mapping ......................................................................................... 4

Pin Configurations ................................................................................ 9

Port Types ........................................................................................... 13

Oscillator ............................................................................................. 14

Registers ............................................................................................................ 14

Functional Block Diagram .................................................................................. 15

Enhanced Features ............................................................................. 16

X2 Feature.......................................................................................................... 16

Dual Data Pointer Register (DPTR) ................................................... 20

Expanded RAM (XRAM) ...................................................................... 23

Registers ............................................................................................................ 25

Timer 2 ................................................................................................. 26

Auto-reload Mode............................................................................................... 26

Programmable Clock-out Mode.......................................................................... 27

Registers ............................................................................................................ 29

Programmable Counter Array (PCA) ................................................. 31

Registers ............................................................................................................ 33

PCA Capture Mode ............................................................................................ 39

16-bit Software Timer/ Compare Mode .............................................................. 40

High-speed Output Mode ................................................................................... 41

Pulse Width Modulator Mode ............................................................................. 42

PCA Watchdog Timer......................................................................................... 42

Serial I/O Port ...................................................................................... 44

Framing Error Detection ..................................................................................... 44

Automatic Address Recognition ......................................................................... 45

i

Registers............................................................................................................. 47

Baud Rate Selection for UART for Mode 1 and 3............................................... 47

UART Registers.................................................................................................. 50

Interrupt System ................................................................................. 55

Registers............................................................................................................. 56

Interrupt Sources and Vector Addresses............................................................ 63

Keyboard Interface ............................................................................. 64

Registers............................................................................................................. 65

Serial Port Interface (SPI) ................................................................... 68

Features.............................................................................................................. 68

Signal Description............................................................................................... 68

Functional Description ........................................................................................ 70

Hardware Watchdog Timer ................................................................ 77

Using the WDT ................................................................................................... 77

WDT During Power-down and Idle ..................................................................... 78

ONCE^™Mode (ON Chip Emulation) .................................................. 79

Power Management ............................................................................ 80

Reset .................................................................................................................. 80

Reset Recommendation to Prevent Flash Corruption ........................................ 82

Idle Mode............................................................................................................ 82

Power-down Mode.............................................................................................. 82

Power-off Flag ..................................................................................... 84

Reduced EMI Mode ............................................................................. 85

Flash EEPROM Memory ..................................................................... 86

Features.............................................................................................................. 86

Flash Programming and Erasure........................................................................ 86

Flash Registers and Memory Map...................................................................... 87

Flash Memory Status.......................................................................................... 90

Memory Organization ......................................................................................... 90

Bootloader Architecture ...................................................................................... 91

ISP Protocol Description..................................................................................... 95

Functional Description ........................................................................................ 96

Flow Description ................................................................................................. 97

API Call Description.......................................................................................... 105

Electrical Characteristics ................................................................. 107

Absolute Maximum Ratings ..............................................................................107

ii

xxxxA–8051–10/06

DC Parameters for Standard Voltage............................................................... 107

DC Parameters for Low Voltage....................................................................... 109

AC Parameters ................................................................................................. 111

Ordering Information ........................................................................ 119

Package Information ........................................................................ 120

PDIL40.............................................................................................................. 120

VQFP44............................................................................................................ 121

PLC44............................................................................................................... 122

Datasheet Change Log ..................................................................... 123

Changes from 4180A-08/02 to 4180B-04/03.................................................... 123

Changes from 4180B-04/03 to 4180C-12/03.................................................... 123

Changes from 4180C-12/03 - 4180D - 06/05 ................................................... 123

Changes from 4180D - 06/05 to 4180E - 10/06................................................ 123

Table of Contents .................................................................................. i

iii

xxxxA–8051–10/06

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Printed on recycled paper.

xxxxA–8051–10/06


型号：	AT89C51RC2-RLTUM
厂家：	ATMEL
描述：	8-bit Microcontroller with 16K/ 32K Bytes Flash 8位微控制器，带有16K / 32K字节的闪存闪存微控制器和处理器外围集成电路异步传输模式 ATM 时钟
文件：	总127页 (文件大小：1478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT89C51RC2-RLTUM [ATMEL]

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