AT89S51-24SL [ATMEL]
Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP42, 0.600 INCH, PLASTIC, MS-011AC, DIP-42;
| 型号： | AT89S51-24SL |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDIP42, 0.600 INCH, PLASTIC, MS-011AC, DIP-42 微控制器 光电二极管 |
| 文件： | 总32页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS®-51Products
• 4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
8-bit
• Two 16-bit Timer/Counters
• Six Interrupt Sources
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Fast Programming Time
• Flexible ISP Programming (Byte and Page Mode)
• Green (Pb/Halide-free) Packaging Option
AT89S51
1. Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of In-System Programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on
a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
2487C–MICRO–03/05
2. Pin Configurations
2.1
40-lead PDIP
2.3
44-lead PLCC
P1.0
P1.1
1
40 VCC
2
3
4
5
6
7
8
9
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
P1.2
P1.3
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
RST 10
(RXD) P3.0 11
NC 12
34 NC
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
30 ALE/PROG
29 PSEN
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
XTAL1 19
GND 20
2.4
42-lead PDIP
2.2
44-lead TQFP
RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
1
2
3
4
5
6
7
8
9
42 P1.7 (SCK)
41 P1.6 (MISO)
40 P1.5 (MOSI)
39 P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
1
2
3
4
5
6
7
8
9
33 P0.4 (AD4)
38 P1.3
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
28 NC
37 P1.2
(T1) P3.5
36 P1.1
(WR) P3.6
(RD) P3.7
35 P1.0
(RXD) P3.0
NC
34 VDD
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
XTAL2 10
XTAL1 11
33 PWRVDD
32 P0.0 (AD0)
31 P0.1 (AD1)
30 P0.2 (AD2)
29 P0.3 (AD3)
28 P0.4 (AD4)
27 P0.5 (AD5)
26 P0.6 (AD6)
25 P0.7 (AD7)
24 EA/VPP
23 ALE/PROG
22 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
GND 12
(T0) P3.4 10
(T1) P3.5 11
PWRGND 13
(A8) P2.0 14
(A9) P2.1 15
(A10) P2.2 16
(A11) P2.3 17
(A12) P2.4 18
(A13) P2.5 19
(A14) P2.6 20
(A15) P2.7 21
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AT89S51
2487C–MICRO–03/05
AT89S51
3. Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
PORT 0
LATCH
PORT 2
LATCH
RAM
FLASH
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DUAL DPTR
WATCH
DOG
PORT 3
LATCH
PORT 1
LATCH
ISP
PORT
OSC
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1 DRIVERS
P1.0 - P1.7
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2487C–MICRO–03/05
4. Pin Description
4.1
VCC
Supply voltage (all packages except 42-PDIP).
4.2
GND
Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the
embedded program memory).
4.3
4.4
4.5
VDD
Supply voltage for the 42-PDIP which connects only the logic core and the embedded program
memory.
PWRVDD
PWRGND
Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board
MUST connect both VDD and PWRVDD to the board supply voltage.
Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are
weakly connected through the common silicon substrate, but not through any metal link. The
application board MUST connect both GND and PWRGND to the board ground.
4.6
4.7
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification. External pull-ups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin
P1.5
Alternate Functions
MOSI (used for In-System Programming)
MISO (used for In-System Programming)
SCK (used for In-System Programming)
P1.6
P1.7
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AT89S51
2487C–MICRO–03/05
AT89S51
4.8
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash program-
ming and verification.
4.9
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol-
lowing table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
4.10 RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets
the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-
RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of
bit DISRTO, the RESET HIGH out feature is enabled.
4.11 ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
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2487C–MICRO–03/05
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.12 PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
4.13 EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.
4.14 XTAL1
4.15 XTAL2
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier
5. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 5-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
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AT89S51
2487C–MICRO–03/05
AT89S51
Table 5-1.
AT89S51 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
0D7H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
B
0F0H
0E8H
0E0H
0D8H
0D0H
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
00000000
ACC
00000000
PSW
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
AUXR1
XXXXXXX0
WDTRST
XXXXXXXX
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
AUXR
XXX00XX0
88H
8FH
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
87H
80H
0XXX0000
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-
tures. In that case, the reset or inactive values of the new bits will always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five
interrupt sources in the IP register.
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2487C–MICRO–03/05
Table 5-2.
AUXR: Auxiliary Register
Address = 8EH
AUXR
Reset Value = XXX00XX0B
Not Bit Addressable
–
7
–
6
–
5
WDIDLE
4
DISRTO
3
–
2
–
1
DISALE
0
Bit
–
Reserved for future expansion
Disable/Enable ALE
DISALE
DISALE
Operating Mode
0
1
ALE is emitted at a constant rate of 1/6 the oscillator frequency
ALE is active only during a MOVX or MOVC instruction
DISRTO
Disable/Enable Reset-out
DISRTO
0
1
Reset pin is driven High after WDT times out
Reset pin is input only
WDIDLE
Disable/Enable WDT in IDLE mode
WDIDLE
0
1
WDT continues to count in IDLE mode
WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and rest under software control and is not affected by
reset.
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AT89S51
2487C–MICRO–03/05
AT89S51
Table 5-3.
AUXR1: Auxiliary Register 1
Address = A2H
AUXR1
Reset Value = XXXXXXX0B
Not Bit Addressable
–
–
6
–
5
–
4
–
3
–
2
–
1
DPS
0
Bit
7
–
Reserved for future expansion
Data Pointer Register Select
DPS
DPS
0
1
Selects DPTR Registers DP0L, DP0H
Selects DPTR Registers DP1L, DP1H
6. Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
6.1
6.2
Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH
are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to
external memory.
Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
7. Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
7.1
Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must reset the WDT at least
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2487C–MICRO–03/05
every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-
tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.
7.2
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt, which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the
user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter
IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
8. UART
The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further
information on the UART operation, please click on the document link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
9. Timer 0 and 1
Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, please click on the document link
below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
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AT89S51
2487C–MICRO–03/05
AT89S51
10. Interrupts
The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 10-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 10-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software
should not write 1s to these bit positions, since they may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle.
Table 10-1. Interrupt Enable (IE) Register
(MSB)
EA
(LSB)
–
–
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its
enable bit.
EA
IE.7
–
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved
–
Reserved
ES
ET1
EX1
ET0
EX0
Serial Port interrupt enable bit
Timer 1 interrupt enable bit
External interrupt 1 enable bit
Timer 0 interrupt enable bit
External interrupt 0 enable bit
User software should never write 1s to reserved bits, because they may be used in future AT89
products.
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2487C–MICRO–03/05
Figure 10-1. Interrupt Sources
0
1
INT0
IE0
TF0
0
1
INT1
IE1
TF1
TI
RI
11. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure 11-1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 11-2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Figure 11-1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Note:
C1, C2
=
=
30 pF 10 pF for Crystals
40 pF 10 pF for Ceramic Resonators
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AT89S51
2487C–MICRO–03/05
AT89S51
Figure 11-2. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
12. Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special function regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
13. Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down mode can be initiated
either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset
redefines the SFRs but does not change the on-chip RAM. The reset should not be activated
before VCC is restored to its normal operating level and must be held active long enough to allow
the oscillator to restart and stabilize.
Table 13-1. Status of External Pins During Idle and Power-down Modes
Mode
Program Memory
Internal
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
External
Float
Data
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
External
Float
Data
Data
Data
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2487C–MICRO–03/05
14. Program Memory Lock Bits
The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P)
to obtain the additional features listed in Table 14-1.
Table 14-1. Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
2
U
U
U
No program lock features
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the Flash memory is disabled
P
U
U
3
4
P
P
P
P
U
P
Same as mode 2, but verify is also disabled
Same as mode 3, but external execution is also disabled
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.
If the device is powered up without a reset, the latch initializes to a random value and holds that
value until reset is activated. The latched value of EA must agree with the current logic level at
that pin in order for the device to function properly.
15. Programming the Flash – Parallel Mode
The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compatible
with conventional third-party Flash or EPROM programmers.
The AT89S51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89S51, the address, data, and control
signals should be set up according to the Flash Programming Modes table (Table 17-1) and Fig-
ure 17-1 and Figure 17-2. To program the AT89S51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle. Dur-
ing a write cycle, an attempted read of the last byte written will result in the complement of the
written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs,
and the next cycle may begin. Data Polling may begin any time after a write cycle has been
initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output
signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is
pulled high again when programming is done to indicate READY.
14
AT89S51
2487C–MICRO–03/05
AT89S51
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individ-
ual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to
a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H indicates AT89S51
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.
16. Programming the Flash – Serial Mode
The Code memory array can be programmed using the serial ISP interface while RST is pulled
to VCC. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is
set high, the Programming Enable instruction needs to be executed first before other operations
can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is
required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than
1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is
2 MHz.
16.1 Serial Programming Algorithm
To program and verify the AT89S51 in the serial programming mode, the following sequence is
recommended:
1. Power-up sequence:
a. Apply power between VCC and GND pins.
b. Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to
XTAL1 pin and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial instruction to pin
MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less
than the CPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
4. Any memory location can be verified by using the Read instruction that returns the con-
tent at the selected address at serial output MISO/P1.6.
15
2487C–MICRO–03/05
5. At the end of a programming session, RST can be set low to commence normal device
operation.
Power-off sequence (if needed):
1. Set XTAL1 to “L” (if a crystal is not used).
2. Set RST to “L”.
3. Turn VCC power off.
Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during
a write cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
16.2 Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the
”Serial Programming Instruction Set” on page 20.
17. Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of
control signals. The write operation cycle is self-timed and once initiated, will automatically time
itself to completion.
Most major worldwide programming vendors offer worldwide support for the Atmel AT89 micro-
controller series. Please contact your local programming vendor for the appropriate software
revision.
Table 17-1. Flash Programming Modes
P2.3-0
P1.7-0
ALE/
EA/
VPP
P0.7-0
Data
Address
Mode
VCC
5V
5V
5V
RST
H
PSEN
PROG
P2.6
P2.7
H
P3.3
H
P3.6
H
P3.7
H
(2)
Write Code Data
Read Code Data
Write Lock Bit 1
L
L
L
12V
H
L
L
DIN
DOUT
X
A11-8
A11-8
X
A7-0
A7-0
X
H
H
L
L
H
H
(3)
H
12V
H
H
H
H
H
(3)
(3)
Write Lock Bit 2
Write Lock Bit 3
5V
5V
H
H
L
L
12V
12V
H
H
H
L
H
H
L
L
L
X
X
X
X
X
X
H
P0.2,
P0.3,
P0.4
Read Lock Bits
1, 2, 3
5V
5V
H
H
L
L
H
H
H
H
H
L
L
H
L
L
L
X
X
X
X
(1)
Chip Erase
12V
H
X
Read Atmel ID
Read Device ID
Read Device ID
5V
5V
5V
H
H
H
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1EH
51H
06H
0000
0001
0010
00H
00H
00H
Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase.
2. Each PROG pulse is 200 ns - 500 ns for Write Code Data.
3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits.
4. RDY/BSY signal is output on P3.0 during programming.
5. X = don’t care.
16
AT89S51
2487C–MICRO–03/05
AT89S51
Figure 17-1. Programming the Flash Memory (Parallel Mode)
VCC
AT89S51
A0 - A7
A8 - A11
VCC
P0
ADDR.
0000H/FFFH
P1.0-P1.7
PGM
DATA
P2.0 - P2.3
P2.6
P2.7
P3.3
P3.6
SEE FLASH
PROGRAMMING
MODES TABLE
ALE
PROG
P3.7
XTAL2
EA
VIH/VPP
3-33 MHz
RDY/
BSY
P3.0
XTAL1
GND
RST
VIH
PSEN
Figure 17-2. Verifying the Flash Memory (Parallel Mode)
VCC
AT89S51
A0 - A7
A8 - A11
VCC
P0
ADDR.
0000H/FFFH
P1.0-P1.7
PGM DATA
(USE 10K
PULLUPS)
P2.0 - P2.3
P2.6
P2.7
ALE
EA
SEE FLASH
PROGRAMMING
MODES TABLE
P3.3
P3.6
P3.7
VIH
XTAL2
3-33 MHz
VIH
XTAL1
GND
RST
PSEN
17
2487C–MICRO–03/05
18. Flash Programming and Verification Characteristics (Parallel Mode)
TA = 20°C to 30°C, VCC = 4.5 to 5.5V
Symbol
VPP
Parameter
Min
Max
12.5
10
Units
V
Programming Supply Voltage
Programming Supply Current
VCC Supply Current
11.5
IPP
mA
mA
MHz
ICC
30
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
Oscillator Frequency
3
33
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
PROG Width
48 tCLCL
48 tCLCL
48 tCLCL
48 tCLCL
48 tCLCL
10
µs
µs
µs
10
0.2
1
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
48tCLCL
48tCLCL
48tCLCL
1.0
0
µs
µs
50
Figure 18-1. Flash Programming and Verification Waveforms – Parallel Mode
PROGRAMMING
P1.0 - P1.7
P2.0 - P2.3
VERIFICATION
ADDRESS
ADDRESS
tAVQV
PORT 0
DATA IN
DATA OUT
tDVGL tGHDX
tAVGL
tSHGL
tGHAX
tGHSL
ALE/PROG
tGLGH
VPP
LOGIC 1
LOGIC 0
EA/VPP
tEHSH
tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.0
(RDY/BSY)
BUSY
tWC
READY
18
AT89S51
2487C–MICRO–03/05
AT89S51
Figure 18-2. Flash Memory Serial Downloading
VCC
AT89S51
VCC
INSTRUCTION
INPUT
P1.5/MOSI
P1.6/MISO
P1.7/SCK
DATA OUTPUT
CLOCK IN
XTAL2
3-33 MHz
XTAL1
GND
RST
VIH
19. Flash Programming and Verification Waveforms – Serial Mode
Figure 19-1. Serial Programming Waveforms
7
6
5
4
3
2
1
0
19
2487C–MICRO–03/05
20. Serial Programming Instruction Set
Instruction Format
Instruction
Byte 1
Byte 2
Byte 3
Byte 4
Operation
xxxx xxxx
0110 1001
(Output on
MISO)
Enable Serial Programming
while RST is high
Programming Enable
1010 1100
0101 0011
xxxx xxxx
Chip Erase Flash memory
array
Chip Erase
1010 1100
0010 0000
100x xxxx
xxxx
xxxx xxxx
xxxx xxxx
Read Program Memory
(Byte Mode)
Read data from Program
memory in the byte mode
Write Program Memory
(Byte Mode)
xxxx
Write data to Program
memory in the byte mode
0100 0000
1010 1100
Write Lock Bits(1)
1110 00
xxxx xxxx
xxxx
xxxx xxxx
xxxx xxxx
xxx xxx0
xxxx xxxx
Write Lock bits. See Note (1).
Read back current status of
the lock bits (a programmed
lock bit reads back as a “1”)
Read Lock Bits
0010 0100
0010 1000
0011 0000
xxx
xx
Read Signature Bytes
Signature Byte
Read Signature Byte
Read data from Program
memory in the Page Mode
(256 bytes)
Read Program Memory
(Page Mode)
xxxx
Byte 1...
Byte 255
Byte 0
Byte 0
Write data to Program
memory in the Page Mode
(256 bytes)
Write Program Memory
(Page Mode)
Byte 1...
Byte 255
0101 0000
xxxx
Note:
1. B1 = 0, B2 = 0 → Mode 1, no lock protection
B1 = 0, B2 = 1 → Mode 2, lock bit 1 activated
B1 = 1, B2 = 0 → Mode 3, lock bit 2 activated
B1 = 1, B2 = 1 → Mode 4, lock bit 3 activated
Each of the lock bit modes need to be activated sequentially be-
fore Mode 4 can be executed.
}
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data
bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready
to be decoded.
20
AT89S51
2487C–MICRO–03/05
AT89S51
21. Serial Programming Characteristics
Figure 21-1. Serial Programming Timing
MOSI
tOVSH
tSLSH
tSHOX
SCK
tSHSL
MISO
tSLIV
Table 21-1. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 4.0 - 5.5V (Unless Otherwise Noted)
Symbol
1/tCLCL
tCLCL
Parameter
Min
3
Typ
Max
Units
MHz
ns
Oscillator Frequency
33
Oscillator Period
30
tSHSL
SCK Pulse Width High
SCK Pulse Width Low
MOSI Setup to SCK High
MOSI Hold after SCK High
SCK Low to MISO Valid
Chip Erase Instruction Cycle Time
Serial Byte Write Cycle Time
8 tCLCL
8 tCLCL
tCLCL
2 tCLCL
10
ns
tSLSH
ns
tOVSH
tSHOX
tSLIV
ns
ns
16
32
500
ns
tERASE
tSWC
ms
µs
64 tCLCL + 400
22. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
21
2487C–MICRO–03/05
23. DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol
VIL
Parameter
Condition
Min
-0.5
Max
0.2 VCC-0.1
0.2 VCC-0.3
VCC+0.5
VCC+0.5
0.45
Units
Input Low Voltage
(Except EA)
V
V
V
V
V
VIL1
Input Low Voltage (EA)
Input High Voltage
-0.5
VIH
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC+0.9
0.7 VCC
VIH1
VOL
Input High Voltage
Output Low Voltage(1) (Ports 1,2,3)
IOL = 1.6 mA
Output Low Voltage(1)
(Port 0, ALE, PSEN)
VOL1
IOL = 3.2 mA
0.45
V
IOH = -60 µA, VCC = 5V 10%
2.4
V
V
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
VOH
I
OH = -25 µA
0.75 VCC
0.9 VCC
2.4
IOH = -10 µA
V
IOH = -800 µA, VCC = 5V 10%
V
Output High Voltage
(Port 0 in External Bus Mode)
VOH1
I
OH = -300 µA
0.75 VCC
0.9 VCC
V
IOH = -80 µA
V
IIL
Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V
Logical 1 to 0 Transition Current
-50
µA
ITL
VIN = 2V, VCC = 5V 10%
-300
µA
(Ports 1,2,3)
ILI
Input Leakage Current (Port 0, EA)
Reset Pulldown Resistor
Pin Capacitance
0.45 < VIN < VCC
10
300
10
µA
KΩ
pF
RRST
CIO
50
Test Freq. = 1 MHz, TA = 25°C
Active Mode, 12 MHz
Idle Mode, 12 MHz
VCC = 5.5V
25
mA
mA
µA
Power Supply Current
Power-down Mode(2)
ICC
6.5
50
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
22
AT89S51
2487C–MICRO–03/05
AT89S51
24. AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
24.1 External Program and Data Memory Characteristics
12 MHz Oscillator
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
Max
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
33
ALE Pulse Width
127
43
2 tCLCL-40
tCLCL-25
tCLCL-25
tAVLL
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
48
233
4 tCLCL-65
tLLPL
43
tCLCL-25
tPLPH
tPLIV
205
3 tCLCL-45
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
145
59
3 tCLCL-60
tCLCL-25
tPXIX
0
0
tPXIZ
tPXAV
tAVIV
75
tCLCL-8
312
10
5 tCLCL-80
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
400
400
6 tCLCL-100
6 tCLCL-100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
252
5 tCLCL-90
0
0
Data Float After RD
97
2 tCLCL-28
8 tCLCL-150
9 tCLCL-165
3 tCLCL+50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
517
585
300
200
203
23
3 tCLCL-50
4 tCLCL-75
tCLCL-30
433
33
7 tCLCL-130
tCLCL-25
RD Low to Address Float
RD or WR High to ALE High
0
0
43
123
tCLCL-25
tCLCL+25
23
2487C–MICRO–03/05
25. External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tPLIV
tLLPL
PSEN
tPXAV
tPLAZ
tPXIZ
tPXIX
INSTR IN
tLLAX
A0 - A7
tAVIV
A0 - A7
PORT 0
PORT 2
A8 - A15
A8 - A15
26. External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD
tLLAX
tRHDZ
tRHDX
tRLDV
tAVLL
tRLAZ
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
PORT 0
tAVWL
tAVDV
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
PORT 2
24
AT89S51
2487C–MICRO–03/05
AT89S51
27. External Data Memory Write Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
PORT 0
PORT 2
tAVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
28. External Clock Drive Waveforms
tCHCX
tCHCX
tCLCH
tCHCL
VCC - 0.5V
0.7 VCC
0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL
29. External Clock Drive
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min
0
Max
Units
MHz
ns
33
30
12
12
tCHCX
tCLCX
ns
Low Time
ns
tCLCH
Rise Time
5
5
ns
tCHCL
Fall Time
ns
25
2487C–MICRO–03/05
30. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc
Variable Oscillator
Symbol
tXLXL
Parameter
Min
Max
Min
12 tCLCL
10 tCLCL-133
2 tCLCL-80
0
Max
Units
µs
Serial Port Clock Cycle Time
1.0
700
50
0
tQVXH
tXHQX
tXHDX
tXHDV
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
ns
ns
ns
700
10 tCLCL-133
ns
31. Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
tXHQX
1
WRITE TO SBUF
0
2
3
4
5
6
7
tXHDX
SET TI
tXHDV
OUTPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
INPUT DATA
32. AC Testing Input/Output Waveforms(1)
VCC - 0.5V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
0.45V
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH
min. for a logic 1 and VIL max. for a logic 0.
33. Float Waveforms(1)
+ 0.1V
- 0.1V
- 0.1V
+ 0.1V
VOL
VLOAD
Timing Reference
Points
VLOAD
VLOAD
VOL
Note:
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded VOH/VOL level occurs.
26
AT89S51
2487C–MICRO–03/05
AT89S51
34. Ordering Information
34.1 Standard Package
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
AT89S51-24AC
AT89S51-24JC
AT89S51-24PC
AT89S51-24SC
44A
44J
Commercial
40P6
42PS6
(0°C to 70°C)
24
33
4.0V to 5.5V
4.5V to 5.5V
AT89S51-24AI
AT89S51-24JI
AT89S51-24PI
AT89S51-24SI
44A
44J
Industrial
40P6
42PS6
(-40°C to 85°C)
AT89S51-33AC
AT89S51-33JC
AT89S51-33PC
AT89S51-33SC
44A
44J
Commercial
40P6
42PS6
(0°C to 70°C)
34.2 Green Package Option (Pb/Halide-free)
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
AT89S51-24AU
AT89S51-24JU
AT89S51-24PU
44A
44J
Industrial
24
4.0V to 5.5V
(-40°C to 85°C)
40P6
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
40P6
42PS6
40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
42-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
27
2487C–MICRO–03/05
35. Packaging Information
35.1 44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
28
AT89S51
2487C–MICRO–03/05
AT89S51
35.2 44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
29
2487C–MICRO–03/05
35.3 40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
40P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
30
AT89S51
2487C–MICRO–03/05
AT89S51
35.4 42PS6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.83
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.51
36.70
15.24
13.46
0.38
0.76
3.05
0.20
–
–
–
36.96 Note 2
15.88
E
–
E1
B
–
13.97 Note 2
0.56
–
B1
L
–
1.27
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.43
C
–
–
0.30
eB
e
18.55
1.78 TYP
11/6/03
DRAWING NO. REV.
42PS6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
42PS6, 42-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
A
R
31
2487C–MICRO–03/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
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Tel: (49) 71-31-67-0
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2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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Tel: 1(719) 576-3300
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2487C–MICRO–03/05
/xM
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