AT89S8252-16PA [ATMEL]
8-Bit Microcontroller with 8K Bytes Flash; 8位微控制器8K字节的Flash
| 型号： | AT89S8252-16PA |
| 厂家： | 
ATMEL |
| 描述： | 8-Bit Microcontroller with 8K Bytes Flash |
| 文件： | 总31页 (文件大小：457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Compatible with MCS-51™ Products
• 8K Bytes of In-System Reprogrammable Downloadable Flash Memory
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 2K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
• 4.0V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
8-Bit
Microcontroller
with 8K Bytes
Flash
• Nine Interrupt Sources
• Programmable UART Serial Channel
• SPI Serial Interface
• Low Power Idle and Power Down Modes
• Interrupt Recovery From Power Down
• Programmable Watchdog Timer
• Dual Data Pointer
• Power Off Flag
AT89S8252
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with
8K bytes of Downloadable Flash programmable and erasable read only memory and
2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvol-
atile memory technology and is compatible with the industry standard 80C51 instruc-
tion set and pinout. The on-chip Downloadable Flash allows the program memory to
be reprogrammed in-system through an SPI serial interface or by a conventional non-
volatile memory programmer. By combining a versatile 8-bit CPU with Downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
The AT89S8252 provides the following standard features: 8K bytes of Downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch-
dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter-
rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89S8252 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset.
The Downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.
0401D-A–12/97
4-105
Pin Configurations
PDIP
PLCC
(T2) P1.0
(T2 EX) P1.1
P1.2
1
2
3
4
5
6
7
8
9
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
P1.3
(SS) P1.4
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
7
8
9
39 P0.4 (AD4)
38 P0.5 (AD5)
37 P0.6 (AD6)
36 P0.7 (AD7)
35 EA/VPP
RST 10
(RXD) P3.0 11
NC 12
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
30 ALE/PROG
29 PSEN
34 NC
(TXD) P3.1 13
(INT0) P3.2 14
(INT1) P3.3 15
(T0) P3.4 16
(T1) P3.5 17
33 ALE/PROG
32 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
31 P2.7 (A15)
30 P2.6 (A14)
29 P2.5 (A13)
XTAL1 19
GND 20
PQFP/TQFP
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
1
33 P0.4 (AD4)
2
3
4
5
6
7
8
9
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
28 NC
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
27 ALE/PROG
26 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
(T0) P3.4 10
(T1) P3.5 11
Port 0 also receives the code bytes during Flash program-
ming and outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Some Port 1 pins provide additional functions. P1.0 and
P1.1 can be configured to be the timer/counter 2 external
count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively.
Port 0 can also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
AT89S8252
4-106
AT89S8252
Block Diagram
P0.0 - P0.7
P2.0 - P2.7
VCC
PORT 0 DRIVERS
PORT 2 DRIVERS
GND
RAM ADDR.
REGISTER
PORT 0
LATCH
PORT 2
LATCH
RAM
FLASH
EEPROM
PROGRAM
ADDRESS
REGISTER
B
STACK
POINTER
ACC
REGISTER
BUFFER
TMP2
TMP1
PC
INCREMENTER
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
COUNTER
PSW
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
INSTRUCTION
REGISTER
DPTR
WATCH
DOG
PORT 3
LATCH
PORT 1
LATCH
SPI
PORT
PROGRAM
LOGIC
OSC
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1 DRIVERS
P1.0 - P1.7
4-107
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift
clock input/output pins as shown in the following table.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Functions
RXD (serial input port)
Port Pin
Alternate Functions
TXD (serial output port)
P1.0
T2 (external count input to Timer/Counter 2),
clock-out
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
P1.1
T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
P1.4
P1.5
SS (Slave port select input)
MOSI (Master data output, slave data input pin
for SPI channel)
P1.6
P1.7
MISO (Master data input, slave data output pin
for SPI channel)
RST
SCK (Master clock output, slave clock input pin
for SPI channel)
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory. This pin is also the program pulse input (PROG) during
Flash programming.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data mem-
ory.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
When the AT89S8252 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
Port 3
Port 3 is an 8 bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
Port 3 also serves the functions of various special features
of the AT89S8252, as shown in the following table.
Port 3 also receives some control signals for Flash pro-
gramming and verification.
EA should be strapped to VCC for internal program execu-
tions. This pin also receives the 12-volt programming
enable voltage (VPP) during Flash programming when 12-
volt programming is selected.
AT89S8252
4-108
AT89S8252
XTAL1
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate
effect.
Output from the inverting oscillator amplifier.
Table 1. AT89S8252 SFR Map and Reset Values
0F8H
0FFH
0F7H
0EFH
0E7H
0DFH
B
0F0H
00000000
0E8H
ACC
0E0H
00000000
0D8H
PSW
0D0H
SPCR
000001XX
0D7H
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0C8H
0C0H
0B8H
0B0H
0A8H
0A0H
98H
0CFH
0C7H
0BFH
0B7H
0AFH
0A7H
9FH
IP
XX000000
P3
11111111
IE
SPSR
00XXXXXX
0X000000
P2
11111111
SCON
00000000
SBUF
XXXXXXXX
P1
11111111
WMCON
00000010
90H
97H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
88H
8FH
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
SPDR
XXXXXXXX
PCON
0XXX0000
80H
87H
4-109
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16 bit cap-
ture mode or 16-bit auto-reload mode.
SPI Registers Control and status bits for the Serial Periph-
eral Interface are contained in registers SPCR (shown in
Table 4) and SPSR (shown in Table 5). The SPI data bits
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff-
ered for writing and the values in SPDR are not changed by
Reset.
Interrupt Registers The global interrupt enable bit and the
individual interrupt enable bits are in the IE register. In addi-
tion, the individual interrupt enable bit for the SPI is in the
SPCR register. Two priorities can be set for each of the six
interrupt sources in the IP register.
Watchdog and Memory Control Register The WMCON
register contains control bits for the Watchdog Timer
(shown in Table 3). The EEMEN and EEMWE bits are used
to select the 2K bytes on-chip EEPROM, and to enable
byte-write. The DPS bit selects one of two DPTR registers
available.
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
TF2
7
EXF2
6
RCLK
5
TCLK
4
EXEN2
3
TR2
2
C/T2
1
CP/RL2
0
Bit
Symbol
Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
TCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
AT89S8252
4-110
AT89S8252
Dual Data Pointer Registers To facilitate accessing both
internal EEPROM and external data memory, two banks of
16 bit Data Pointer Registers are provided: DP0 at SFR
address locations 82H-83H and DP1 at 84H-85H. Bit DPS
= 0 in SFR WMCON selects DP0 and DPS = 1 selects
DP1. The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data
Pointer Register.
Power Off Flag The Power Off Flag (POF) is located at
bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and reset under software control
and is not affected by RESET.
Table 3. WMCON—Watchdog and Memory Control Register
WMCON Address = 96H
Reset Value = 0000 0010B
PS2
7
PS1
6
PS0
5
EEMWE
4
EEMEN
3
DPS
2
WDTRST
1
WDTEN
0
Bit
Symbol
Function
PS2
PS1
PS0
Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16
ms. When all three bits are set to “1”, the nominal period is 2048 ms.
EEMWE
EEMEN
DPS
EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the
MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.
Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory.
Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the
second bank, DP1
WDTRST
RDY/BSY
Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a pulse is
generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle.
The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-Only mode during EEPROM write.
RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed,
the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed.
WDTEN
Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
4-111
Table 4. SPCR—SPI Control Register
SPCR Address = D5H
Reset Value = 0000 01XXB
SPIE
7
SPE
6
DORD
5
MSTR
4
CPOL
3
CPHA
2
SPR1
1
SPR0
0
Bit
Symbol
Function
SPIE
SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES
= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.
SPE
SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and
P1.7. SPI = 0 disables the SPI channel.
DORD
MSTR
CPOL
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not
transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.
CPHA
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and
slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPR0
SPR1
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows:
SPR1
SPR0
SCK = FOSC. divided by
0
0
1
1
0
1
0
1
4
16
64
128
Table 5. SPSR—SPI Status Register
SPSR Address = AAH
Reset Value = 00XX XXXXB
SPIF
7
WCOL
6
—
5
—
4
—
3
—
2
—
1
—
0
Bit
Symbol
Function
SPIF
SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and
ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing
the SPI data register.
WCOL
Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer,
the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF
bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.
AT89S8252
4-112
AT89S8252
Table 6. SPDR—SPI Data Register
SPDR Address = 86H
Reset Value = unchanged
SPD7
7
SPD6
6
SPD5
5
SPD4
4
SPD3
3
SPD2
2
SPD1
1
SPD0
0
Bit
Data Memory—EEPROM and RAM
Programmable Watchdog Timer
The AT89S8252 implements 2K bytes of on-chip EEPROM
for data storage and 256 bytes of RAM. The upper 128
bytes of RAM occupy a parallel space to the Special Func-
tion Registers. That means the upper 128 bytes have the
same addresses as the SFR space but are physically sepa-
rate from SFR space.
The programmable Watchdog Timer (WDT) operates from
an independent oscillator. The prescaler bits, PS0, PS1
and PS2 in SFR WMCON are used to set the period of the
Watchdog Timer from 16 ms to 2048 ms. The available
timer periods are shown in the following table and the
actual timer periods (at VCC = 5V) are within ±30% of the
nominal.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
The WDT is disabled by Power-on Reset and during Power
Down. It is enabled by setting the WDTEN bit in SFR
WMCON (address = 96H). The WDT is reset by setting the
WDTRST bit in WMCON. When the WDT times out without
being reset or disabled, an internal RST pulse is generated
to reset the CPU.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
Table 7. Watchdog Timer Period Selection
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
WDT Prescaler Bits
Period (nominal)
PS2
0
PS1
0
PS0
0
16 ms
32 ms
0
0
1
MOV @R0, #data
0
1
0
64 ms
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail-
able as stack space.
0
1
1
128 ms
256 ms
512 ms
1024 ms
2048 ms
1
0
0
The on-chip EEPROM data memory is selected by setting
the EEMEN bit in the WMCON register at SFR address
location 96H. The EEPROM address range is from 000H to
7FFH. The MOVX instructions are used to access the
EEPROM. To access off-chip data memory with the MOVX
instructions, the EEMEN bit needs to be set to “0”.
1
0
1
1
1
0
1
1
1
The EEMWE bit in the WMCON register needs to be set to
“1” before any byte location in the EEPROM can be written.
User software should reset EEMWE bit to “0” if no further
EEPROM write is required. EEPROM write cycles in the
serial programming mode are self-timed and typically take
2.5 ms. The progress of EEPROM write can be monitored
by reading the RDY/BSY bit (read-only) in SFR WMCON.
RDY/BSY = 0 means programming is still in progress and
RDY/BSY = 1 means EEPROM write cycle is completed
and another write cycle can be initiated.
In addition, during EEPROM programming, an attempted
read from the EEPROM will fetch the byte being written
with the MSB complemented. Once the write cycle is com-
pleted, true data are valid at all bit locations.
4-113
Table 8. Timer 2 Operating Modes
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S8252 operate the same
way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and
AT89C55. For further information, see the October 1995
Microcontroller Data Book, page 2-45, section titled,
“Timer/Counters.”
RCLK + TCLK
CP/RL2
TR2 MODE
0
0
1
X
0
1
1
1
1
0
16-bit Auto-Reload
16-bit Capture
Baud Rate Generator
(Off)
X
X
Timer 2
Timer 2 is a 16 bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2 in the SFR T2CON (shown in Table 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 8.
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a l-
to-0 transition at external input T2EX also causes the cur-
rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at T2EX
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 1.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator fre-
quency.
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi-
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16 bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 9). Upon reset, the DCEN bit
is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
Figure 1. Timer 2 in Capture Mode
÷12
OSC
C/T2 = 0
C/T2 = 1
TH2
TL2
TF2
OVERFLOW
CONTROL
TR2
CAPTURE
T2 PIN
RCAP2H RCAP2L
EXF2
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
CONTROL
EXEN2
AT89S8252
4-114
AT89S8252
0FFFFH and then sets the TF2 bit upon overflow. The over-
flow also causes the timer registers to be reloaded with the
16 bit value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If EXEN2 =
1, a 16 bit reload can be triggered either by an overflow or
RCAP2H and RCAP2L to be reloaded into the timer regis-
ters, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
by a 1-to-0 transition at external input T2EX. This transition
also sets the EXF2 bit. Both the TF2 and EXF2 bits can
generate an interrupt if enabled.
The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.
Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16 bit value in
Figure 2. Timer 2 in Auto Reload Mode (DCEN = 0)
Table 9. T2MOD—Timer 2 Mode Control Register
T2MOD Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
—
7
—
6
—
5
—
4
—
3
—
2
T2OE
1
DCEN
0
Bit
Symbol
—
Function
Not implemented, reserved for future use.
Timer 2 Output Enable bit.
T2OE
DCEN
When set, this bit allows Timer 2 to be configured as an up/down counter.
4-115
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)
Figure 4. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
2
÷
"0"
"0"
"1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1
RCLK
2
OSC
÷
C/T2 = 0
"1"
"1"
TH2
TL2
Rx
CLOCK
CONTROL
TR2
16
÷
C/T2 = 1
"0"
T2 PIN
TCLK
RCAP2H RCAP2L
Tx
CLOCK
TRANSITION
DETECTOR
16
÷
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
AT89S8252
4-116
AT89S8252
Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting
TCLK and/or RCLK in T2CON (Table 2). Note that the baud
rates for transmit and receive can be different if Timer 2 is
used for the receiver or transmitter and Timer 1 is used for
the other function. Setting RCLK and/or TCLK puts Timer 2
into its baud rate generator mode, as shown in Figure 4.
Modes 1 and 3
Baud Rate
Oscillator Frequency
32 × [65536 – (RCAP2H,RCAP2L)]
--------------------------------------- = ----------------------------------------------------------------------------------------------
where (RCAP2H, RCAP2L) is the content of RCAP2H and
RCAP2L taken as a 16 bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This
figure is valid only if RCLK or TCLK = 1 in T2CON. Note
that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer
2 is in use as a baud rate generator, T2EX can be used as
an extra external interrupt.
The baud rate generator mode is similar to the auto-reload
mode, in that a rollover in TH2 causes the Timer 2 registers
to be reloaded with the 16 bit value in registers RCAP2H
and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer
2’s overflow rate according to the following equation.
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates = -----------------------------------------------------------
Note that when Timer 2 is running (TR2 = 1) as a timer in
the baud rate generator mode, TH2 or TL2 should not be
read from or written to. Under these conditions, the Timer is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP2 registers may be
read but should not be written to, because a write might
overlap a reload and cause write and/or reload errors. The
timer should be turned off (clear TR2) before accessing the
Timer 2 or RCAP2 registers.
16
The Timer can be configured for either timer or counter
operation. In most applications, it is configured for timer
operation (CP/T2 = 0). The timer operation is different for
Timer 2 when it is used as a baud rate generator. Normally,
as a timer, it increments every machine cycle (at 1/12 the
oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator fre-
quency). The baud rate formula is given below.
Figure 5. Timer 2 in Clock-Out Mode
4-117
Programmable Clock Out
UART
A 50% duty cycle clock can be programmed to come out on
P1.0, as shown in Figure 5. This pin, besides being a regu-
lar I/0 pin, has two alternate functions. It can be pro-
grammed to input the external clock for Timer/Counter 2 or
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16 MHz operating frequency.
The UART in the AT89S8252 operates the same way as
the UART in the AT89C51, AT89C52 and AT89C55. For
further information, see the October 1995 Microcontroller
Data Book, page 2-49, section titled, “Serial Interface.”
Serial Peripheral Interface
To configure the Timer/Counter 2 as a clock generator, bit
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1)
must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the AT89S8252 and
peripheral devices or between several AT89S8252
devices. The AT89S8252 SPI features include the follow-
ing:
The clock-out frequency depends on the oscillator fre-
quency and the reload value of Timer 2 capture registers
(RCAP2H, RCAP2L), as shown in the following equation.
• Full-Duplex, 3-Wire Synchronous Data Transfer
• Master or Slave Operation
Oscillator Frequency
Clock Out Frequency = ------------------------------------------------------------------------------------------
4 × [65536 – (RCAP2H,RCAP2L)]
• 1.5-MHz Bit Frequency (max.)
• LSB First or MSB First Data Transfer
• Four Programmable Bit Rates
In the clock-out mode, Timer 2 rollovers will not generate
an interrupt. This behavior is similar to when Timer 2 is
used as a baud-rate generator. It is possible to use Timer 2
as a baud-rate generator and a clock generator simulta-
neously. Note, however, that the baud-rate and clock-out
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wakeup from Idle Mode (Slave Mode Only)
Figure 6. SPI Block Diagram
S
MISO
P1.6
M
M
OSCILLATOR
MOSI
P1.5
MSB
8/16-BIT SHIFT REGISTER
READ DATA BUFFER
LSB
S
DIVIDER
÷4÷16÷64÷128
CLOCK
SPI CLOCK (MASTER)
SCK
1.7
CLOCK
LOGIC
S
SELECT
M
SS
P1.4
MSTR
SPE
SPI CONTROL
8
SPI STATUS REGISTER
SPI CONTROL REGISTER
8
8
SPI INTERRUPT
INTERNAL
DATA BUS
REQUEST
AT89S8252
4-118
AT89S8252
The interconnection between master and slave CPUs with
SPI is shown in the following figure. The SCK pin is the
clock output in the master mode but is the clock input in the
slave mode. Writing to the SPI data register of the master
CPU starts the SPI clock generator, and the data written
shifts out of the MOSI pin and into the MOSI pin of the
slave CPU. After shifting one byte, the SPI clock generator
stops, setting the end of transmission flag (SPIF). If both
the SPI interrupt enable bit (SPIE) and the serial port inter-
rupt enable bit (ES) are set, an interrupt is requested.
The Slave Select input, SS/P1.4, is set low to select an
individual SPI device as a slave. When SS/P1.4 is set high,
the SPI port is deactivated and the MOSI/P1.5 pin can be
used as an input.
There are four combinations of SCK phase and polarity
with respect to serial data, which are determined by control
bits CPHA and CPOL. The SPI data transfer formats are
shown in Figures 8 and 9.
Figure 7. SPI Master-Slave Interconnection
MSB
MASTER
LSB
MSB
SLAVE
LSB
MISO MISO
MOSI MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SCK
SS
SCK
SS
SPI
CLOCK GENERATOR
VCC
Figure 8. SPI transfer Format with CPHA = 0
*Not defined but normally MSB of character just received
4-119
Figure 9. SPI Transfer Format with CPHA = 1
SCK CYCLE #
1
2
3
4
5
6
7
8
(FOR REFERENCE)
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(FROM MASTER)
MSB
MSB
6
5
5
4
3
3
2
1
1
LSB
MISO
(FROM SLAVE)
6
4
2
LSB
*
SS (TO SLAVE)
*Not defined but normally LSB of previously transmitted character
Interrupts
The AT89S8252 has a total of six interrupt vectors: two
external interrupts (INT0 and INT1), three timer interrupts
(Timers 0, 1, and 2), and the serial port interrupt. These
interrupts are all shown in Figure 10.
Timer 2 interrupt is generated by the logical OR of bits TF2
and EXF2 in register T2CON. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which
disables all interrupts at once.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag, TF2, is set at S2P2 and is polled in the
same cycle in which the timer overflows.
Note that Table 10 shows that bit position IE.6 is unimple-
mented. In the AT89C51, bit position IE.5 is also unimple-
mented. User software should not write 1s to these bit posi-
tions, since they may be used in future AT89 products.
Table 10. Interrupt Enable (IE) Register
Figure 10. Interrupt Sources
(MSB)
EA
(LSB)
EX0
—
ET2
ES
ET1
EX1
ET0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol
Position
Function
Disables all interrupts. If EA = 0, no interrupt
is acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by
setting or clearing its enable bit.
EA
IE.7
—
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Reserved.
ET2
ES
Timer 2 interrupt enable bit.
SPI and UART interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
ET1
EX1
ET0
EX0
User software should never write 1s to unimplemented bits, because
they may be used in future AT89 products.
AT89S8252
4-120
AT89S8252
Figure 11. Oscillator Connections
Figure 12. External Clock Drive Configuration
Note:
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is termi-
nated by a reset, the instruction following the one that
invokes idle mode should not write to a port pin or to exter-
nal memory.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier that can be configured for use as
an on-chip oscillator, as shown in Figure 11. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in Figure 12.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
Power Down Mode
In the power down mode, the oscillator is stopped and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. Exit from power down can be initiated either by a
hardware reset or by an enabled external interrupt. Reset
redefines the SFRs but does not change the on-chip RAM.
The reset should not be activated before VCC is restored to
its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
To exit power down via an interrupt, the external interrupt
must be enabled as level sensitive before entering power
down. The interrupt service routine starts at 16 ms (nomi-
nal) after the enabled interrupt pin is activated.
Note that when idle mode is terminated by a hardware
reset, the device normally resumes program execution
from where it left off, up to two machine cycles before the
Status of External Pins During Idle and Power Down Modes
Mode
Program Memory
Internal
ALE
PSEN
PORT0
Data
PORT1
Data
PORT2
Data
PORT3
Data
Idle
1
1
0
0
1
1
0
0
Idle
External
Float
Data
Data
Address
Data
Data
Power Down
Power Down
Internal
Data
Data
External
Float
Data
Data
Data
4-121
Program Memory Lock Bits
The AT89S8252 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
Once programmed, the lock bits can only be unpro-
grammed with the Chip Erase operations in either the par-
allel or serial modes.
(1)(2)
Lock Bit Protection Modes
Program Lock Bits
Protection Type
LB1
U
LB2
U
LB3
U
1
2
No internal memory lock feature.
P
U
U
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory. EA is sampled and latched on reset and further programming of the Flash
memory (parallel or serial mode) is disabled.
3
4
P
P
P
P
U
P
Same as Mode 2, but parallel or serial verify are also disabled.
Same as Mode 3, but external execution is also disabled.
Notes: 1. U = Unprogrammed
2. P = Programmed
Parallel Programming Algorithm
To program and verify the AT89S8252 in the parallel pro-
gramming mode, the following sequence is recommended:
Programming the Flash and EEPROM
Atmel’s AT89S8252 Flash Microcontroller offers 8K bytes
of in-system reprogrammable Flash Code memory and 2K
bytes of EEPROM Data memory.
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
The AT89S8252 is normally shipped with the on-chip Flash
Code and EEPROM Data memory arrays in the erased
state (i.e. contents = FFH) and ready to be programmed.
This device supports a High-Voltage (12V) Parallel pro-
gramming mode and a Low-Voltage (5V) Serial program-
ming mode. The serial programming mode provides a con-
venient way to download the AT89S8252 inside the user’s
system. The parallel programming mode is compatible with
conventional third party Flash or EPROM programmers.
Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait
for at least 10 milliseconds.
2. Set PSEN pin to “L”
ALE pin to “H”
EA pin to “H” and all other pins to “H”.
3. Apply the appropriate combination of “H” or “L” logic
levels to pins P2.6, P2.7, P3.6, P3.7 to select one of the
programming operations shown in the Flash Program-
ming Modes table.
The Code and Data memory arrays are mapped via sepa-
rate address spaces in the serial programming mode. In
the parallel programming mode, the two arrays occupy one
contiguous address space: 0000H to 1FFFH for the Code
array and 2000H to 27FFH for the Data array.
4. Apply the desired byte address to pins P1.0 to P1.7
and P2.0 to P2.5.
The Code and Data memory arrays on the AT89S8252 are
programmed byte-by-byte in either programming mode. An
auto-erase cycle is provided with the self-timed program-
ming operation in the serial programming mode. There is
no need to perform the Chip Erase operation to reprogram
any memory location in the serial programming mode
unless any of the lock bits have been programmed.
Apply data to pins P0.0 to P0.7 for Write Code opera-
tion.
5. Raise EA/VPP to 12V to enable Flash programming,
erase or verification.
6. Pulse ALE/PROG once to program a byte in the Code
memory array, the Data memory array or the lock bits.
The byte-write cycle is self-timed and typically takes
1.5 ms.
In the parallel programming mode, there is no auto-erase
cycle. To reprogram any non-blank byte, the user needs to
use the Chip Erase operation first to erase both arrays.
7. To verify the byte just programmed, bring pin P2.7 to
“L” and read the programmed data at pins P0.0 to P0.7.
AT89S8252
4-122
AT89S8252
8. Repeat steps 3 through 7 changing the address and
data for the entire 2K or 8K bytes array or until the end
of the object file is reached.
Serial Programming Fuse
A programmable fuse is available to disable Serial Pro-
gramming if the user needs maximum system security. The
Serial Programming Fuse can only be programmed or
erased in the Parallel Programming Mode.
9. Power-off sequence:
Set XTAL1 to “L”.
The AT89S8252 is shipped with the Serial Programming
Mode enabled.
Set RST and EA pins to “L”.
Tur n VCC power off.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H and 031H, except that P3.6 and P3.7 must
be pulled to a logic low. The values returned are as follows:
In the parallel programming mode, there is no auto-erase
cycle and to reprogram any non-blank byte, the user needs
to use the Chip Erase operation first to erase both arrays.
DATA Polling
(030H) = 1EH indicates manufactured by Atmel
(031H) = 72H indicates 89S8252
The AT89S8252 features DATA Polling to indicate the end
of a write cycle. During a write cycle in the parallel or serial
programming mode, an attempted read of the last byte writ-
ten will result in the complement of the written datum on
P0.7 (parallel mode), and on the MSB of the serial output
byte on MISO (serial mode). Once the write cycle has been
completed, true data are valid on all outputs, and the next
cycle may begin. DATA Polling may begin any time after a
write cycle has been initiated.
Programming Interface
Every code byte in the Flash and EEPROM arrays can be
written, and the entire array can be erased, by using the
appropriate combination of control signals. The write oper-
ation cycle is self-timed and once initiated, will automati-
cally time itself to completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Ready/Busy
The progress of byte programming in the parallel program-
ming mode can also be monitored by the RDY/BSY output
signal. Pin P3.4 is pulled Low after ALE goes High during
programming to indicate BUSY. P3.4 is pulled High again
when programming is done to indicate READY.
Serial Downloading
Both the Code and Data memory arrays can be pro-
grammed using the serial SPI bus while RST is pulled to
VCC. The serial interface consists of pins SCK, MOSI (input)
and MISO (output). After RST is set high, the Programming
Enable instruction needs to be executed first before pro-
gram/erase operations can be executed.
Program Verify
If lock bits LB1 and LB2 have not been programmed, the
programmed Code or Data byte can be read back via the
address and data lines for verification. The state of the lock
bits can also be verified directly in the parallel programming
mode. In the serial programming mode, the state of the lock
bits can only be verified indirectly by observing that the lock
bit features are enabled.
An auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need
to first execute the Chip Erase instruction unless any of the
lock bits have been programmed. The Chip Erase opera-
tion turns the content of every memory location in both the
Code and Data arrays into FFH.
Chip Erase
Both Flash and EEPROM arrays are erased electrically at
the same time. In the parallel programming mode, chip
erase is initiated by using the proper combination of control
signals and by holding ALE/PROG low for 10 ms. The
Code and Data arrays are written with all “1”s in the Chip
Erase operation.
The Code and Data memory arrays have separate address
spaces:
0000H to 1FFFH for Code memory and 000H to 7FFH for
Data memory.
Either an external system clock is supplied at pin XTAL1 or
a crystal needs to be connected across pins XTAL1 and
XTAL2. The maximum serial clock (SCK) frequency should
be less than 1/40 of the crystal frequency. With a 24 MHz
oscillator clock, the maximum SCK frequency is 600 kHz.
In the serial programming mode, a chip erase operation is
initiated by issuing the Chip Erase instruction. In this mode,
chip erase is self-timed and takes about 16 ms.
During chip erase, a serial read from any address location
will return 00H at the data outputs.
4-123
written. The write cycle is self-timed and typically takes
less than 2.5 ms at 5V.
Serial Programming Algorithm
To program and verify the AT89S8252 in the serial pro-
gramming mode, the following sequence is recommended:
4. Any memory location can be verified by using the Read
instruction which returns the content at the selected
address at serial output MISO/P1.6.
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
5. At the end of a programming session, RST can be set
low to commence normal operation.
If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.
Power-off sequence (if needed):
Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.
2. Enable serial programming by sending the Program-
ming Enable serial instruction to pin MOSI/P1.5. The
frequency of the shift clock supplied at pin SCK/P1.7
needs to be less than the CPU clock at XTAL1 divided
by 40.
Tur n VCC power off.
Serial Programming Instruction
The Instruction Set for Serial Programming follows a 3-byte
protocol and is shown in the following table:
3. The Code or Data array is programmed one byte at a
time by supplying the address and data together with
the appropriate Write instruction. The selected memory
location is first automatically erased before new data is
Instruction Set
Instruction
Input Format
Byte 2
Operation
Byte 1
Byte 3
Programming Enable
Chip Erase
1010 1100
1010 1100
aaaa a001
0101 0011
xxxx x100
low addr
xxxx xxxx
xxxx xxxx
xxxx xxxx
Enable serial programming interface after RST goes high.
Chip erase both 8K & 2K memory arrays.
Read Code Memory
Read data from Code memory array at the selected address.
The 5 MSBs of the first byte are the high order address bits.
The low order address bits are in the second byte. Data are
available at pin MISO during the third byte.
Write Code Memory
Read Data Memory
aaaa a010
00aa a101
low addr
low addr
data in
Write data to Code memory location at selected address. The
address bits are the 5 MSBs of the first byte together with the
second byte.
xxxx xxxx
Read data from Data memory array at selected address. Data
are available at pin MISO during the third byte.
Write Data Memory
Write Lock Bits
00aa a110
1010 1100
low addr
x x111
data in
Write data to Data memory location at selected address.
xxxx xxxx
Write lock bits.
Set LB1, LB2 or LB3 = “0” to program lock bits.
Notes: 1. DATA polling is used to indicate the end of a write cycle which typically takes less than 2.5 ms at 5V.
2. “aaaaa” = high order address.
3. “x” = don’t care.
AT89S8252
4-124
AT89S8252
Flash and EEPROM Parallel Programming Modes
Data I/O
Address
Mode
RST
PSEN
ALE/PROG
EA/V
P2.6
P2.7
P3.6
P3.7
P0.7:0
P2.5:0 P1.7:0
PP
(1)
(1)
Serial Prog. Modes
H
h
h
x
(2)
Chip Erase
H
L
12V
H
L
L
L
X
X
Write (10K bytes) Memory
Read (10K bytes) Memory
Write Lock Bits:
H
H
H
L
L
L
12V
12V
12V
L
L
H
L
L
H
H
H
H
H
L
DIN
DOUT
DIN
ADDR
ADDR
X
H
H
Bit - 1
Bit - 2
Bit - 3
P0.7 = 0
P0.6 = 0
P0.5 = 0
DOUT
X
X
X
Read Lock Bits:
H
L
H
12V
H
H
L
L
X
Bit - 1
Bit - 2
Bit - 3
@P0.2
@P0.1
@P0.0
DOUT
X
X
X
Read Atmel Code
Read Device Code
H
H
L
L
H
H
12V
12V
L
L
L
L
L
L
L
L
30H
31H
DOUT
(2)
Serial Prog. Enable
H
L
12V
L
H
L
H
P0.0 = 0
X
(2)
Serial Prog. Disable
H
H
L
L
12V
12V
L
H
H
L
L
H
H
P0.0 = 1
@P0.0
X
X
Read Serial Prog. Fuse
H
H
Notes: 1. “h” = weakly pulled “High” internally.
2. Chip Erase and Serial Programming Fuse require a 10-ms PROG pulse. Chip Erase needs to be performed first before
reprogramming any byte with a content other than FFH.
3. P3.4 is pulled Low during programming to indicate RDY/BSY.
4. “X” = don’t care
4-125
Figure 14. Programming the Flash/EEPROM Memory
Figure 15. Flash/EEPROM Serial Downloading
+4.0V to 6.0V
+5V
AT89S8252
AT89S8252
A0 - A7
VCC
VCC
ADDR.
P1
0000H/27FFH
PGM
DATA
P2.0 - P2.5
P0
A8 - A13
INSTRUCTION
INPUT
P1.5/MOSI
P1.6/MISO
P1.7/SCK
P2.6
P2.7
P3.6
P3.7
ALE
PROG
SEE FLASH
PROGRAMMING
MODES TABLE
DATA OUTPUT
CLOCK IN
XTAL2
EA
VPP
XTAL2
3-24 MHz
3-24 MHz
XTAL1
GND
RST
VIH
XTAL1
GND
RST
VIH
PSEN
Figure 16. Verifying the Flash/EEPROM Memory
+5V
AT89S8252
A0 - A7
VCC
P0
ADDR.
0000H/27FFH
P1
PGM DATA
(USE 10K
PULLUPS)
P2.0 - P2.5
A8 - A13
P2.6
P2.7
ALE
EA
VIH
SEE FLASH
PROGRAMMING
MODES TABLE
P3.6
P3.7
VPP
XTAL2
3-24 MHz
VIH
XTAL1
GND
RST
PSEN
AT89S8252
4-126
AT89S8252
Flash Programming and Verification Characteristics-Parallel Mode
TA = 0°C to 70°C, VCC = 5.0V ± 10%
Symbol
VPP
Parameter
Min
Max
12.5
1.0
Units
V
Programming Enable Voltage
Programming Enable Current
Oscillator Frequency
11.5
IPP
mA
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
3
24
MHz
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
PROG Width
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
µs
µs
1
110
48tCLCL
48tCLCL
48tCLCL
1.0
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
0
µs
2.0
ms
4-127
Flash/EEPROM Programming and Verification Waveforms - Parallel Mode
Serial Downloading Waveforms
SERIAL CLOCK INPUT
SCK/P1.7
7
4
6
5
3
2
1
0
SERIAL DATA INPUT
MOSI/P1.5
LSB
MSB
SERIAL DATA OUTPUT
MISO/P1.6
LSB
MSB
AT89S8252
4-128
AT89S8252
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage............................................. 6.6V
DC Output Current...................................................... 15.0 mA
DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted.
Symbol Parameter
Condition
Min
-0.5
Max
Units
VIL
Input Low Voltage
(Except EA)
0.2 VCC - 0.1
0.2 VCC - 0.3
VCC + 0.5
V
V
V
V
VIL1
VIH
Input Low Voltage (EA)
Input High Voltage
Input High Voltage
-0.5
(Except XTAL1, RST)
(XTAL1, RST)
0.2 VCC + 0.9
0.7 VCC
VIH1
VCC + 0.5
Output Low Voltage (1)
(Ports 1,2,3)
VOL
IOL = 1.6 mA
0.5
0.5
V
V
Output Low Voltage (1)
(Port 0, ALE, PSEN)
VOL1
IOL = 3.2 mA
IOH = -60 µA, VCC = 5V ± 10%
2.4
V
V
Output High Voltage
(Ports 1,2,3, ALE, PSEN)
VOH
IOH = -25 µA
0.75 VCC
0.9 VCC
2.4
IOH = -10 µA
V
I
OH = -800 µA, VCC = 5V ± 10%
OH = -300 µA
V
Output High Voltage
(Port 0 in External Bus Mode)
VOH1
I
0.75 VCC
0.9 VCC
V
IOH = -80 µA
V
IIL
Logical 0 Input Current (Ports 1,2,3)
VIN = 0.45V
-50
µA
µA
ITL
Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10%
-650
Input Leakage Current
0.45 < VIN < VCC
(Port 0, EA)
ILI
±10
µA
RRST
CIO
Reset Pulldown Resistor
50
300
10
KΩ
pF
Pin Capacitance
Test Freq. = 1 MHz, TA = 25°C
Active Mode, 12 MHz
Idle Mode, 12 MHz
VCC = 6V
25
mA
mA
µA
µA
Power Supply Current
6.5
100
40
ICC
Power Down Mode (2)
VCC = 3V
Notes: 1. Under steady state (non-transient) conditions, IOL
must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the
related specification. Pins are not guaranteed to sink
current greater than the listed test conditions.
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
2. Minimum VCC for Power Down is 2V
4-129
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
External Program and Data Memory Characteristics
Variable Oscillator
Symbol
1/tCLCL
tLHLL
Parameter
Min
0
Max
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator Frequency
24
ALE Pulse Width
2tCLCL - 40
tCLCL - 13
tCLCL - 20
tAVLL
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
tLLAX
tLLIV
4tCLCL - 65
tLLPL
tCLCL - 13
tPLPH
tPLIV
3tCLCL - 20
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
3tCLCL - 45
tPXIX
0
tPXIZ
tCLCL - 10
tPXAV
tAVIV
tCLCL - 8
5tCLCL - 55
10
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
6tCLCL - 100
6tCLCL - 100
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
5tCLCL - 90
0
Data Float After RD
2tCLCL - 28
8tCLCL - 150
9tCLCL - 165
3tCLCL + 50
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold After WR
3tCLCL - 50
4tCLCL - 75
tCLCL - 20
7tCLCL - 120
tCLCL - 20
RD Low to Address Float
RD or WR High to ALE High
0
tCLCL - 20
tCLCL + 25
AT89S8252
4-130
AT89S8252
External Program Memory Read Cycle
External Data Memory Read Cycle
4-131
External Data Memory Write Cycle
External Clock Drive Waveforms
External Clock Drive
Symbol
Parameter
VCC = 4.0V to 6.0V
Units
Min
0
Max
1/tCLCL
tCLCL
Oscillator Frequency
Clock Period
High Time
24
MHz
ns
41.6
15
tCHCX
tCLCX
tCLCH
tCHCL
ns
Low Time
15
ns
Rise Time
20
20
ns
Fall Time
ns
AT89S8252
4-132
AT89S8252
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF.
Symbol
Parameter
Variable Oscillator
Units
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
12tCLCL
10tCLCL - 133
2tCLCL - 117
0
µs
ns
ns
ns
ns
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
10tCLCL - 133
Shift Register Mode Timing Waveforms
(1)
(1)
AC Testing Input/Output Waveforms
Float Waveforms
Notes: 1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing mea-
surements are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
Notes: 1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
4-133
AT89S8252
TYPICAL ICC (ACTIVE) at 25°C
24
20
16
12
8
VCC = 6.0V
VCC = 5.0V
I
C
C
m
A
4
0
4
8
12
16
20
24
0
F (MHz)
AT89S8252
TYPICAL ICC (IDLE) at 25°C
4.8
4.0
3.2
2.4
1.6
0.8
0.0
VCC
=
=
6.0V
I
C
C
VCC
5.0V
m
A
4
8
12
16
20
24
0
F (MHz)
Notes: 1. XTAL1 tied to GND for Icc (power down)
2. Lock bits programmed
AT89S8252
4-134
AT89S8252
Ordering Information
Speed
(MHz)
Power
Supply
Ordering Code
Package
Operation Range
16
4.0V to 6.0V
4.0V to 6.0V
4.0V to 6.0V
4.5V to 5.5V
AT89S8252-16AA
AT89S8252-16JA
AT89S8252-16PA
AT89S8252-16QA
44A
44J
Automotive
(-40°C to 105°C)
40P6
44Q
24
AT89S8252-24AC
AT89S8252-24JC
AT89S8252-24PC
AT89S8252-24QC
44A
44J
Commercial
(0°C to 70°C)
40P6
44Q
AT89S8252-24AI
AT89S8252-24JI
AT89S8252-24PI
AT89S8252-24QI
44A
44J
Industrial
(-40°C to 85°C)
40P6
44Q
33
AT89S8252-33AC
AT89S8252-33JC
AT89S8252-33PC
AT89S8252-33QC
44A
44J
Commercial
(0°C to 70°C)
40P6
44Q
= Preliminary Information
Package Type
44A
44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
44J
40P6
44Q
40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)
4-135
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