AT89SND2C-7FTUL [ATMEL]
Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface; 单芯片闪存微控制器与MP3解码器，支持完整的音频接口
| 型号： | AT89SND2C-7FTUL |
| 厂家： | 
ATMEL |
| 描述： | Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
| 文件： | 总235页 (文件大小：2877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• MPEG I/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– CRC Error and MPEG Frame Synchronization Indicators
• 20-bit Stereo Audio DAC
Single-Chip
Flash
Microcontroller
with MP3
– 93 dB SNR playback stereo channel
– 32 Ohm/ 20 mW stereo headset drivers
– Stereo Line Level Input, Differential Mono Auxiliary Input
• Programmable Audio Output for Interfacing with External Audio System
– PCM Format Compatible
– I2S Format Compatible
• Mono Audio Power Amplifier
– 440mW on 8 Ohms Load
• 8-bit MCU C51 Core Based (FMAX = 20 MHz)
• 2304 Bytes of Internal RAM
Decoder with
Full Audio
Interface
• 64K Bytes of Code Memory
– AT89C51SND2C: Flash (100K Erase/Write Cycles)
– AT83SND2C: ROM
• 4K Bytes of Boot Flash Memory (AT89C51SND2C)
– ISP: Download from USB (standard) or UART (option)
• USB Rev 1.1 Controller
AT83SND2C
– Full Speed Data Transmission
• Built-in PLL
AT89C51SND2C
– MP3 Audio Clocks
– USB Clock
• MultiMedia Card® Interface Compatibility
• Atmel DataFlash® SPI Interface Compatibility
• IDE/ATAPI Interface
Preliminary
• Up to 32 Bits of General-purpose I/Os
– 1 Interrupt Keyboard
– SmartMedia® Software Interface
• 2 Standard 16-bit Timers/Counters
• Hardware Watchdog Timer
• Standard Full Duplex UART with Baud Rate Generator
• Two Wire Master and Slave Modes Controller
• SPI Master and Slave Modes Controller
• Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
• Operating Conditions:
– 3V, ±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
– Power amplifier supply 3.2V to 5.5V
• Packages
– CTBGA100
Rev. 4341D–MP3–04/05
Description
The AT8xC51SND2C has been developed for handling MP3 ringing tones in mobile
phones and can replace sound generators while adding SD/MMC card reader, MP3
music decoding, and connection of the cell phone to a PC through USB. Cell phones
can also be used as a thumb drive extending cell phone capabilities.
The AT8xC51SND2C are fully integrated stand-alone hardwired MPEG I/II-Layer 3
decoder with a C51 microcontroller core handling data flow, MP3-player control, Stereo
Audio DAC and Mono Audio Power Amplifier for speaker control.
The AT89C51SND2C includes 64K Bytes of Flash memory and allows In-System Pro-
gramming through an embedded 4K Bytes of Boot Flash memory.
The AT83SND2C includes 64K Bytes of ROM memory.
The AT8xC51SND2C include 2304 Bytes of RAM memory.
The AT8xC51SND2C provides the necessary features for human interface like timers,
keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), I2S output, and all exter-
nal memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
Typical Applications
•
•
•
•
MP3-Player
PDA, Camera, Mobile Phone MP3
Car Audio/Multimedia MP3
Home Audio/Multimedia MP3
2
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Block Diagram
Figure 1. AT8xC51SND2C Block Diagram
ISP ALE
VDD VSS UVDD UVSS
3
FILT
INT0
Interrupt
Handler Unit
Clock and PLL
Unit
X1
X2
3
INT1
C51 (X2 Core)
RST
D+
RAM
2304Bytes
USB
Controller
D-
I/OPorts
IDE
Interface
Flash
ROM
64 KBytes
P0-P4
Flash Boot
4 KBytes
MP3
Decoder
Unit
Keyboard
Interface
KIN0
DOUT
DCLK
I2S/PCM
Audio
Interface
3
3
TXD
RXD
UART
and
BRG
DSEL
SCLK
3
3
T0
T1
Timers 0/1
Watchdog
4
SS
HSR
HSL
AUXP
4
4
4
MISO
SPI/DataFlash
Controller
Audio
DAC
MOSI
SCK
AUXN
LINEL
LINER
MONOP
MONON
SCL
SDA
TWI
Controller
MCLK
MMC
Interface
MDAT
MCMD
PAINP
PAINN
Audio
PA
HPP
HPN
3 Alternate function of Port 3
4 Alternate function of Port 4
3
4341D–MP3–04/05
Pin Description
Pinouts
Figure 2. AT8xC51SND2C 100-pin BGA Package
9
8
7
6
5
4
3
2
1
10
P4.1/
MOSI
P2.0/
A8
VDD
VSS
NC
NC
AUXN
ALE
AUXP
NC
A
P2.2/
A10
P2.1/
A9
P4.0/
MISO
P4.2/
SCK
P0.0/
AD0
ISP
NC
/
MONON
MONOP
VDD
KIN0
B
C
P0.6/
AD6
P0.4/
AD4
P0.3/
AD3
P2.3/
A11
P2.5/
A13
P4.3/
SS
P0.1/
AD1
P0.2/
AD2
P2.4/
A12
NC
P2.7/
A15
P0.7/
AD7
P0.5/
AD5
P2.6/
A14
NC
NC
NC
NC
NC
MCLK
VDD
D
E
F
VDD
AUDVDD
HSVDD
VSS
MDAT
ESDVSS
AUDVREF
SDA
VSS
SCL
PVDD
LINEL
HSL
HSR
EA
P3.2/
INT0
P3.1/
TXD
NC
SCLK
DOUT
CBP
FILT
MCMD
P3.0/
RXD
P3.4/
T0
PVSS
HSVSS
LINER
AUDRST
VSS
DSEL
DCLK
RST
NC
G
P3.5/
T1
X1
X2
D-
TST
INGND
D+
AUDVSS
AUDVCM
H
J
P3.6/
WR
P3.7/
RD
VSS
AUDVSS
LPHN
VDD
P3.3/
INT1
K
AUDVBAT
AUDVSS
VDD
PAINN
HPP
HPN
UVDD
UVSS
PAINP
Notes: 1. ISP pin is only available in AT89C51SND2C product.
Do not connect this pin on AT83SND2C product.
2. NC is Do Not Connect
4
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Signals
All the AT8xC51SND2C signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Alternate
Function
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
P0.7:0
P2.7:0
I/O
AD7:0
polarized to VDD or VSS
.
Port 2
I/O
I/O
A15:8
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0
INT1
T0
T1
WR
RD
Port 3
P3.7:0
P4.3:0
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
MISO
MOSI
SCK
SS
Port 4
I/O
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal
Name
Alternate
Function
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
X1
I
-
Output of the on-chip inverting oscillator amplifier
X2
O
I
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
-
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
FILT
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Alternate
Function
Type
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0
I
P3.2
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is
set by a low level on INT0#.
5
4341D–MP3–04/05
Signal
Name
Alternate
Function
Type
Description
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
INT1
I
P3.3
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is
set by a low level on INT1#.
Timer 0 External Clock Input
T0
T1
I
I
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
P3.5
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
Table 4. Audio Interface Signal Description
Signal
Alternate
Function
Name
DCLK
DOUT
Type
O
Description
DAC Data Bit Clock
DAC Audio Data Output
-
-
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
DSEL
SCLK
O
O
-
-
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
Table 5. USB Controller Signal Description
Signal
Name
Alternate
Function
Type
I/O
Description
USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to VDD for full speed
operation.
D+
-
-
D-
I/O
USB Negative Data Upstream Port
Table 6. MutiMediaCard Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
MMC Clock output
Data or command clock transfer.
MCLK
O
-
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
MCMD
MDAT
I/O
I/O
-
unused MCMD input must be polarized to VDD or VSS
.
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS
-
.
6
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 7. UART Signal Description
Signal
Name
Alternate
Function
Type
Description
Receive Serial Data
RXD
I/O
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
P3.1
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
TXD
O
Table 8. SPI Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
SPI Master Input Slave Output Data Line
MISO
I/O
When in master mode, MISO receives data from the slave peripheral.
When in slave mode, MISO outputs data to the master controller.
P4.0
P4.1
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral.
When in slave mode, MOSI receives data from the master controller.
MOSI
I/O
SPI Clock Line
SCK
SS
I/O
I
When in master mode, SCK outputs clock to the slave peripheral. When
in slave mode, SCK receives clock from the master controller.
P4.2
P4.3
SPI Slave Select Line
When in controlled slave mode, SS enables the slave mode.
Table 9. TWI Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
the slave peripherals. When TWI controller is in slave mode, SCL
receives clock from the master controller.
SCL
I/O
-
-
TWI Serial Data
SDA is the bidirectional Two Wire data line.
SDA
I/O
Table 10. Keypad Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
Keypad Input Line
KIN0
I
Holding this pin high or low for 24 oscillator periods triggers a keypad
interrupt.
-
7
4341D–MP3–04/05
Table 11. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
-
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
ISP
I/O
Read Signal
RD
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
WR
Write signal asserted during external data memory write operation.
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH (RD).
EA(1)
I
-
Note:
1. For ROM/Flash/ROMless Dice product versions only.
Table 12. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
RST
I
-
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
Test Input
TST
I
-
Test mode entry signal. This pin must be set to VDD
.
Table 13. Power Signal Description
Signal
Name
Alternate
Function
Type
Description
Digital Supply Voltage
Connect these pins to +3V supply voltage.
VDD
PWR
-
-
Circuit Ground
Connect these pins to ground.
VSS
GND
8
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Signal
Name
Alternate
Function
Type
Description
PLL Supply voltage
Connect this pin to +3V supply voltage.
PVDD
PVSS
UVDD
UVSS
PWR
-
-
-
-
PLL Circuit Ground
Connect this pin to ground.
GND
PWR
GND
USB Supply Voltage
Connect this pin to +3V supply voltage.
USB Ground
Connect this pin to ground.
Table 14. Audio Power Signal Description
Signal
Name
Alternate
Function
Type
Description
AUDVDD
PWR
Audio Digital Supply Voltage
-
-
Audio Circuit Ground
Connect these pins to ground.
AUDVSS
ESDVSS
GND
GND
Audio Analog Circuit Ground for Electrostatic Discharge.
-
Connect this pin to ground.
AUDVREF
HSVDD
PWR
PWR
Audio Voltage Reference pin for decoupling.
Headset Driver Power Supply.
-
-
Headset Driver Ground.
HSVSS
GND
PWR
-
-
Connect this pin to ground.
AUDVBAT
Audio Amplifier Supply.
Table 15. Stereo Audio Dac and Mono Power Amplifier Signal Description
Signal
Alternate
Function
Name
LPHN
HPN
Type
Description
O
O
O
O
I
Low Power Audio Stage Output
Negative Speaker Output
-
-
-
-
-
-
-
-
-
-
-
-
HPP
Positivie Speaker Output
CBP
Audio Amplifier Common Mode Voltage Decoupling
Audio Amplifier Negative Input
Audio Amplifier Positive Input
Audio Reset (Active Low)
PAINN
PAINP
AUDRST
MONON
MONOP
AUXP
AUXN
HSL
I
I
O
O
I
Audio Negative Monaural Driver Output
Audio Positive Monaural Driver Output
Audio Mono Auxiliary Positive Input
Audio Mono Auxiliary Negative Input
Audio Left Channel Headset Driver Output
I
O
9
4341D–MP3–04/05
Signal
Name
Alternate
Function
Type
Description
HSR
LINEL
O
I
Audio Right Channel Headset Driver Output
Audio Left Channel Line In
-
-
-
-
-
LINER
I
Audio Right Channel Line In
INGND
AUDVCM
I
Audio Line Signal Ground Pin for decoupling.
Audio Common Mode reference for decoupling
I
10
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Internal Pin Structure
Table 16. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
VDD
Input
TST
VDD
Watchdog Output
P
Input/Output
RST
VSS
VDD
VDD
VDD
2 osc
periods
Latch Output
P1
P2
P3
P3
P4
Input/Output
N
VSS
VDD
P0
P
MCMD
MDAT
Input/Output
ISP
N
PSEN
VSS
VDD
ALE
SCLK
DCLK
P
Output
DOUT
DSEL
MCLK
N
VSS
D+
D-
Input/Output
D+
D-
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to
the Section “DC Characteristics”, page 201.
2. When the Two Wire controller is enabled, P3 transistors are disabled allowing pseudo
open-drain structure.
11
4341D–MP3–04/05
Clock Controller
The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-
chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are
generated by this controller.
Oscillator
The AT8xC51SND2C X1 and X2 pins are the input and the output of a single-stage on-
chip inverter (see Figure 3) that can be configured with off-chip components such as a
Pierce oscillator (see Figure 4). Value of capacitors and crystal characteristics are
detailed in the section “DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU
core, and a clock for the peripherals as shown in Figure 3. These clocks are either
enabled or disabled, depending on the power reduction mode as detailed in the section
“Power Management” on page 46. The peripheral clock is used to generate the Timer 0,
Timer 1, MMC, SPI, and Port sampling clocks.
Figure 3. Oscillator Block Diagram and Symbol
0
1
X1
X2
÷ 2
Peripheral
Clock
CPU Core
Clock
X2
CKCON.0
IDL
PCON.0
PD
PCON.1
Oscillator
Clock
PER
CPU
OSC
CLOCK
CLOCK
CLOCK
Peripheral Clock Symbol
CPU Core Clock Symbol
Oscillator Clock Symbol
Figure 4. Crystal Connection
X1
C1
C2
Q
VSS
X2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,
the AT8xC51SND2C need only 6 oscillator clock periods per machine cycle. This fea-
ture called the “X2 feature” can be enabled using the X2 bit(1) in CKCON (see Table 17)
and allows the AT8xC51SND2C to operate in 6 or 12 oscillator clock periods per
machine cycle. As shown in Figure 3, both CPU and peripheral clocks are affected by
this feature. Figure 5 shows the X2 mode switching waveforms. After reset the standard
mode is activated. In standard mode the CPU and peripheral clock frequency is the
oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency.
Note:
1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see
Table 23 on page 22). Using the AT89C51SND2C (Flash Version) the system can
boot either in standard or X2 mode depending on the X2B value. Using AT83SND2C
(ROM Version) the system always boots in standard mode. X2B bit can be changed
to X2 mode later by software.
12
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Figure 5. Mode Switching Waveforms
X1
X1 ÷ 2
X2 Bit
Clock
X2 Mode(1)
STD Mode
STD Mode
Note:
1. In order to prevent any incorrect operation while operating in X2 mode, user must be
aware that all peripherals using clock frequency as time reference (timers, etc.) will
have their time reference divided by 2. For example, a free running timer generating
an interrupt every 20 ms will then generate an interrupt every 10 ms.
PLL
PLL Description
The AT8xC51SND2C PLL is used to generate internal high frequency clock (the PLL
Clock) synchronized with an external low-frequency (the Oscillator Clock). The PLL
clock provides the MP3 decoder, the audio interface, and the USB interface clocks.
Figure 6 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Table 18) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PFILT pin (see
Figure 7). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 6. PLL Block Diagram and Symbol
PFILT
CHP
PLLCON.1
PLLEN
N divider
N6:0
Up
OSC
CLOCK
Vref
PLL
Clock
PFLD
VCO
Down
PLOCK
PLLCON.0
R divider
R9:0
PLL
CLOCK
OSCclk × (R + 1)
PLLclk = ----------------------------------------------
N + 1
PLL Clock Symbol
13
4341D–MP3–04/05
Figure 7. PLL Filter Connection
FILT
R
C2
C1
VSS
VSS
PLL Programming
The PLL is programmed using the flow shown in Figure 8. As soon as clock generation
is enabled, the user must wait until the lock indicator is set to ensure the clock output is
stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface
clock frequencies.
Figure 8. PLL Programming Flow
PLL
Programming
Configure Dividers
N6:0 = xxxxxxb
R9:0 = xxxxxxxxxxb
Enable PLL
PLLRES = 0
PLLEN = 1
PLL Locked?
PLOCK = 1?
14
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Registers
Table 17. CKCON Register
CKCON (S:8Fh) – Clock Control Register
7
6
5
-
4
3
-
2
1
0
TWIX2
WDX2
SIX2
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic Description
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2
independent).
7
TWIX2
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
6
5
4
3
2
WDX2
Reserved
-
The values read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2
independent).
SIX2
-
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
T1X2
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
1
0
T0X2
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER
FOSC/2).
=
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 000Xb (AT89C51SND2C) or 0000 0000b (AT83SND2C)
Table 18. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
7
6
5
-
4
-
3
2
-
1
0
R1
R0
PLLRES
PLLEN
PLOCK
Bit
Bit
Number
Mnemonic Description
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
7 - 6
5 - 4
R1:0
-
Reserved
The values read from these bits are always 0. Do not set these bits.
15
4341D–MP3–04/05
Bit
Bit
Number
Mnemonic Description
PLL Reset Bit
3
2
1
PLLRES Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
Reserved
-
The value read from this bit is always 0. Do not set this bit.
PLL Enable Bit
PLLEN
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
0
PLOCK
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reset Value = 0000 1000b
Table 19. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
7
-
6
5
4
3
2
1
0
N6
N5
N4
N3
N2
N1
N0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bit is always 0. Do not set this bit.
PLL N Divider
7 - bit N divider.
6 - 0
N6:0
Reset Value = 0000 0000b
Table 20. PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
7
6
5
4
3
2
1
0
R9
R8
R7
R6
R5
R4
R3
R2
Bit
Bit
Number
Mnemonic Description
PLL Most Significant Bits R Divider
8 MSB of the 10-bit R divider.
7 - 0
R9:2
Reset Value = 0000 0000b
16
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Program/Code
Memory
The AT8xC51SND2C execute up to 64K Bytes of program/code memory. Figure 9
shows the split of internal and external program/code memory spaces depending on the
product.
The AT83SND2C product provides the internal program/code memory in ROM memory
while the AT89C51SND2C product provides it in Flash memory. These 2 products do
not allow external code memory execution.
The Flash memory increases EPROM and ROM functionality by in-circuit electrical era-
sure and programming. The high voltage needed for programming or erasing Flash cells
is generated on-chip using the standard VDD voltage, made possible by the internal
charge pump. Thus, the AT89C51SND2C can be programmed using only one voltage
and allows In-application software programming. Hardware programming mode is also
available using common programming tools. See the application note ‘Programming
T89C51x and AT89C51x with Device Programmers’.
The AT89C51SND2C implements an additional 4K Bytes of on-chip boot Flash memory
provided in Flash memory. This boot memory is delivered programmed with a standard
boot loader software allowing In-System Programming (ISP). It also contains some
Application Programming Interface routines named API routines allowing In Application
Programming (IAP) by using user’s own boot loader.
Figure 9. Program/Code Memory Organization
FFFFh
FFFFh
F000h
FFFFh
F000h
4K Bytes
Boot Flash
64K Bytes
Code ROM
64K Bytes
Code Flash
0000h
0000h
AT83SND2C
AT89C51SND2C
ROM Memory
Architecture
As shown in Figure 10 the AT83SND2C ROM memory is composed of one space
detailed in the following paragraph.
Figure 10. AT83SND2C Memory Architecture
FFFFh
64K Bytes
User
ROM Memory
0000h
17
4341D–MP3–04/05
User Space
This space is composed of a 64K Bytes ROM memory programmed during the manu-
facturing process. It contains the user’s application code.
Flash Memory
Architecture
As shown in Figure 11 the AT89C51SND2C Flash memory is composed of four spaces
detailed in the following paragraphs.
Figure 11. AT89C51SND2C Memory Architecture
Hardware Security
Extra Row
FFFFh
FFFFh
4K Bytes
Flash Memory
Boot
F000h
64K Bytes
User
Flash Memory
0000h
User Space
Boot Space
This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128
Bytes. It contains the user’s application code.
This space can be read or written by both software and hardware modes.
This space is composed of a 4K Bytes Flash memory. It contains the boot loader for In-
System Programming and the routines for In Application Programming.
This space can only be read or written by hardware mode using a parallel programming
tool.
Hardware Security Space
This space is composed of one Byte: the Hardware Security Byte (HSB see Table 23)
divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the
Boot Loader Jump Bit as detailed in Section “Boot Memory Execution”, page 19 and can
be written by software while the LSN contains the lock system level to protect the mem-
ory content against piracy as detailed in Section “Hardware Security System”, page 19
and can only be written by hardware.
Extra Row Space
This space is composed of 2 Bytes:
•
The Software Boot Vector (SBV, see Table 24).
This Byte is used by the software boot loader to build the boot address.
•
The Software Security Byte (SSB, see Table 25).
This Byte is used to lock the execution of some boot loader commands.
18
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Hardware Security
System
The AT89C51SND2C implements three lock bits LB2:0 in the LSN of HSB (see
Table 23) providing three levels of security for user’s program as described in Table 21
while the AT83SND2C is always set in read disabled mode.
Level 0 is the level of an erased part and does not enable any security feature.
Level 1 locks the hardware programming of both user and boot memories.
Level 2 locks also hardware verifying of both user and boot memories
Level 3 locks also the external execution.
Table 21. Lock Bit Features(1)
Internal
External
Execution
Hardware
Verifying
Hardware
Programming Programming
Software
Level LB2 LB1 LB0 Execution
0
1
U
U
U
P
U
U
P
X
U
P
X
X
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Enable
Enable
Disable
Disable
Enable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
2
3(3)
Notes: 1. U means unprogrammed, P means programmed and X means don’t care (pro-
grammed or unprogrammed).
2. AT89C51SND2C products are delivered with third level programmed to ensure that
the code programmed by software using ISP or user’s boot loader is secured from
any hardware piracy.
Boot Memory Execution As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented
to allow boot memory to be mapped in the code space for execution at addresses from
F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1
(see Figure 22). The three ways to set this bit are detailed in the following sections.
Software Boot Mapping
The software way to set ENBOOT consists in writing to AUXR1 from the user’s soft-
ware. This enables boot loader or API routines execution.
Hardware Condition Boot
Mapping
The hardware condition is based on the ISP pin. When driving this pin to low level, the
chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order
to execute the boot loader software.
As shown in Figure 12 the hardware condition always allows in-system recovery when
user’s memory has been corrupted.
Programmed Condition Boot
Mapping
The programmed condition is based on the Boot Loader Jump Bit (BLJB) in HSB. As
shown in Figure 12 when this bit is programmed (by hardware or software programming
mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of
0000h, in order to execute the boot loader software.
19
4341D–MP3–04/05
Figure 12. Hardware Boot Process Algorithm
RESET
Hard Cond?
ISP = L?
Prog Cond?
BLJB = P?
Hard Cond Init
ENBOOT = 1
PC = F000h
FCON = 00h
Standard Init
ENBOOT = 0
PC = 0000h
FCON = F0h
Prog Cond Init
ENBOOT = 1
PC = F000h
FCON = F0h
User’s
Atmel’s
Application
Boot Loader
The software process (boot loader) is detailed in the “Boot Loader Datasheet”
Document.
Preventing Flash
Corruption
See Section “Reset Recommendation to Prevent Flash Corruption”, page 47.
20
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Registers
Table 22. AUXR1 Register
AUXR1 (S:A2h) – Auxiliary Register 1
7
-
6
-
5
4
-
3
2
0
1
-
0
ENBOOT
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
-
The value read from these bits are indeterminate. Do not set these bits.
Enable Boot Flash
Set this bit to map the boot Flash in the code space between at addresses F000h
to FFFFh.
5
ENBOOT1
Clear this bit to disable boot Flash.
Reserved
4
3
-
The value read from this bit is indeterminate. Do not set this bit.
General Flag
This bit is a general-purpose user flag.
GF3
Always Zero
2
1
0
0
-
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second data pointer: DPTR1.
Clear to select first data pointer: DPTR0.
DPS
Reset Value = XXXX 00X0b
Note: 1. ENBOOT bit is only available in AT89C51SND2C product.
21
4341D–MP3–04/05
Hardware Bytes
Table 23. HSB Byte – Hardware Security Byte
7
6
5
-
4
-
3
-
2
1
0
X2B
BLJB
LB2
LB1
LB0
Bit
Bit
Number
Mnemonic Description
X2 Bit
7
6
X2B(1)
BLJB(2)
-
Program this bit to start in X2 mode.
Unprogram (erase) this bit to start in standard mode.
Boot Loader Jump Bit
Program this bit to execute the boot loader at address F000h on next reset.
Unprogram (erase) this bit to execute user’s application at address 0000h on
next reset.
Reserved
5 - 4
The value read from these bits is always unprogrammed. Do not program these
bits.
Reserved
3
-
The value read from this bit is always unprogrammed. Do not program this bit.
Hardware Lock Bits
Refer to for bits description.
2 - 0
LB2:0
Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.
Note:
1. X2B initializes the X2 bit in CKCON during the reset phase.
2. In order to ensure boot loader activation at first power-up, AT89C51SND2C products
are delivered with BLJB programmed.
3. Bits 0 to 3 (LSN) can only be programmed by hardware mode.
Table 24. SBV Byte – Software Boot Vector
7
6
5
4
3
2
1
0
ADD15
ADD14
ADD13
ADD12
ADD11
ADD10
ADD9
ADD8
Bit
Bit
Number
Mnemonic Description
MSB of the user’s boot loader 16-bit address location
Refer to the boot loader datasheet for usage information (boot loader dependent)
7 - 0
ADD15:8
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
Table 25. SSB Byte – Software Security Byte
7
6
5
4
3
2
1
0
SSB7
SSB6
SSB5
SSB4
SSB3
SSB2
SSB1
SSB0
Bit
Bit
Number
Mnemonic Description
Software Security Byte Data
Refer to the boot loader datasheet for usage information (boot loader dependent)
7 - 0
SSB7:0
Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.
22
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Data Memory
The AT8xC51SND2C provides data memory access in 2 different spaces:
1. The internal space mapped in three separate segments:
–
–
–
The lower 128 Bytes RAM segment
The upper 128 Bytes RAM segment
The expanded 2048 Bytes RAM segment
2. The external space.
A fourth internal segment is available but dedicated to Special Function Registers,
SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information
on this segment, refer to the Section “Special Function Registers”, page 30.
Figure 13 shows the internal and external data memory spaces organization.
Figure 13. Internal and External Data Memory Organization
FFFFh
64K Bytes
External XRAM
7FFh
FFh
FFh
80h
Upper
128 Bytes
Special
Function
Internal RAM
Indirect Addressing
Registers
Direct Addressing
2K Bytes
Internal ERAM
EXTRAM = 0
80h
7Fh
Lower
128 Bytes
Internal RAM
Direct or Indirect
Addressing
0800h
0000h
EXTRAM = 1
00h
00h
Internal Space
Lower 128 Bytes RAM
The lower 128 Bytes of RAM (see Figure 14) are accessible from address 00h to 7Fh
using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
banks of 8 registers (R0 to R7). 2 bits RS0 and RS1 in PSW register (see Table 29)
select which bank is in use according to Table 26. This allows more efficient use of code
space, since register instructions are shorter than instructions that use direct address-
ing, and can be used for context switching in interrupt service routines.
Table 26. Register Bank Selection
RS1
RS0
Description
0
0
1
1
0
1
0
1
Register bank 0 from 00h to 07h
Register bank 1 from 08h to 0Fh
Register bank 2 from 10h to 17h
Register bank 3 from 18h to 1Fh
The next 16 Bytes above the register banks form a block of bit-addressable memory
space. The C51 instruction set includes a wide selection of single-bit instructions, and
the 128 bits in this area can be directly addressed by these instructions. The bit
addresses in this area are 00h to 7Fh.
23
4341D–MP3–04/05
Figure 14. Lower 128 Bytes Internal RAM Organization
7Fh
30h
2Fh
Bit-Addressable Space
(Bit Addresses 0-7Fh)
20h
18h
10h
08h
00h
1Fh
17h
0Fh
07h
4 Banks of
8 Registers
R0-R7
Upper 128 Bytes RAM
Expanded RAM
The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
addressing mode.
The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to
07FFh using indirect addressing mode through MOVX instructions. In this address
range, EXTRAM bit in AUXR register (see Table 30) is used to select the ERAM
(default) or the XRAM. As shown in Figure 13 when EXTRAM = 0, the ERAM is selected
and when EXTRAM = 1, the XRAM is selected (see Section “External Space”).
The ERAM memory can be resized using XRS1:0 bits in AUXR register to dynamically
increase external access to the XRAM space. Table 27 details the selected ERAM size
and address range.
Table 27. ERAM Size Selection
XRS1
XRS0
ERAM Size
256 Bytes
512 Bytes
1K Byte
Address
0
0
1
1
0
1
0
1
0 to 00FFh
0 to 01FFh
0 to 03FFh
0 to 07FFh
2K Bytes
Note:
Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile
memory cells. This means that the RAM content is indeterminate after power-up and
must then be initialized properly.
24
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
External Space
Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 15 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 28
describes the external memory interface signals.
Figure 15. External Data Memory Interface Structure
RAM
AT8xC51SND2C
PERIPHERAL
A15:8
P2
ALE
P0
A15:8
AD7:0
Latch A7:0
A7:0
D7:0
RD
OE
WR
WR
Table 28. External Data Memory Interface Signals
Signal
Name
Alternate
Function
Type Description
Address Lines
Upper address lines for the external bus.
A15:8
O
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
AD7:0
ALE
I/O
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
Read
RD
O
O
P3.7
P3.6
Read signal output to external data memory.
Write
WR
Write signal output to external memory.
Page Access Mode
The AT8xC51SND2C implement a feature called Page Access that disables the output
of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by
setting the DPHDIS bit in AUXR register.
Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In
this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM
and must save it if used in interrupt service routine. Page Access allows external access
above 00FFh address without generating DPH on P2. Thus ERAM is accessed using
MOVX @Ri or MOVX @DPTR with DPTR < 0100h, < 0200h, < 0400h or < 0800h
depending on the XRS1:0 bits value. Then XRAM is accessed using MOVX @DPTR
with DPTR ≥ 0800h regardless of XRS1:0 bits value while keeping P2 for general I/O
usage.
25
4341D–MP3–04/05
External Bus Cycles
This section describes the bus cycles the AT8xC51SND2C executes to read (see
Figure 16), and write data (see Figure 17) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode, refer to the Section “X2 Feature”, page 12.
Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR
signals from 3 to 15 CPU clock periods.
For simplicity, Figure 16 and Figure 17 depict the bus cycle waveforms in idealized form
and do not provide precise timing information. For bus cycle timing parameters refer to
the Section “AC Characteristics”.
Figure 16. External Data Read Waveforms
CPU Clock
ALE
RD(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
Figure 17. External Data Write Waveforms
CPU Clock
ALE
WR(1)
DPL or Ri
D7:0
P0
P2
DPH or P2(2),(3)
P2
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
26
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Dual Data Pointer
Description
The AT8xC51SND2C implement a second data pointer for speeding up code execution
and reducing code size in case of intensive usage of external memory accesses.
DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR
addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1
register (see Table 22) is used to select whether DPTR is the data pointer 0 or the data
pointer 1 (see Figure 18).
Figure 18. Dual Data Pointer Implementation
0
1
DPL0
DPL1
DPL
DPTR0
DPTR1
AUXR1.0
DPTR
DPS
0
1
DPH0
DPH1
DPH
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search …) are well
served by using one data pointer as a “source” pointer and the other one as a “destina-
tion” pointer.
Below is an example of block move implementation using the 2 pointers and coded in
assembler. The latest C compiler also takes advantage of this feature by providing
enhanced algorithm libraries.
The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the
DPS bit in the AUXR1 register. However, note that the INC instruction does not directly
force the DPS bit to a particular state, but simply toggles it. In simple routines, such as
the block move example, only the fact that DPS is toggled in the proper sequence mat-
ters, not its actual value. In other words, the block move routine works the same whether
DPS is '0' or '1' on entry.
; ASCII block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; Ends when encountering NULL character
; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added
AUXR1
move:
EQU
0A2h
mov
inc
mov
DPTR,#SOURCE ; address of SOURCE
AUXR1
DPTR,#DEST
AUXR1
; switch data pointers
; address of DEST
mv_loop: inc
; switch data pointers
; get a Byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the Byte to DEST
; increment DEST address
; check for NULL terminator
movx A,@DPTR
inc
inc
movx @DPTR,A
inc
jnz
DPTR
AUXR1
DPTR
mv_loop
end_move:
27
4341D–MP3–04/05
Registers
Table 29. PSW Register
PSW (S:8Eh) – Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Bit
Number
Mnemonic Description
Carry Flag
Carry out from bit 1 of ALU operands.
7
CY
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
6
5
AC
F0
User Definable Flag 0
Register Bank Select Bits
Refer to Table 26 for bits description.
4 - 3
RS1:0
Overflow Flag
Overflow set by arithmetic operations.
2
1
OV
F1
User Definable Flag 1
Parity Bit
0
P
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
28
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 30. AUXR Register
AUXR (S:8Eh) – Auxiliary Control Register
7
-
6
5
4
3
2
1
0
EXT16
M0
DPHDIS
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is indeterminate. Do not set this bit.
External 16-bit Access Enable Bit
Set to enable 16-bit access mode during MOVX instructions.
Clear to disable 16-bit access mode and enable standard 8-bit access mode
during MOVX instructions.
EXT16
M0
External Memory Access Stretch Bit
Set to stretch RD or WR signals duration to 15 CPU clock periods.
Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.
5
DPH Disable Bit
4
DPHDIS Set to disable DPH output on P2 when executing MOVX @DPTR instruction.
Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.
Expanded RAM Size Bits
XRS1:0
3 - 2
Refer to Table 27 for ERAM size description.
External RAM Enable Bit
Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR
EXTRAM instructions.
1
0
Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX
@DPTR instructions.
ALE Output Enable Bit
AO
Set to output the ALE signal only during MOVX instructions.
Clear to output the ALE signal at a constant rate of FCPU/3.
Reset Value = X000 1101b
29
4341D–MP3–04/05
Special Function
Registers
The Special Function Registers (SFRs) of the AT8xC51SND2C derivatives fall into the
categories detailed in Table 31 to Table 19. The relative addresses of these SFRs are
provided together with their reset values in Table 49. In this table, the bit-addressable
registers are identified by Note 1.
Table 31. C51 Core SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
ACC
B
E0h Accumulator
F0h B Register
PSW
SP
D0h Program Status Word
81h Stack Pointer
CY
AC
F0
RS1
RS0
OV
F1
P
DPL
DPH
82h Data Pointer Low Byte
83h Data Pointer High Byte
Table 32. System Management SFRs
Mnemonic Add Name
7
6
SMOD0
EXT16
-
5
4
3
2
GF0
XRS0
0
1
PD
0
PCON
AUXR
AUXR1
87h Power Control
SMOD1
-
M0
-
DPHDIS
-
GF1
XRS1
GF3
NV3
IDL
AO
8Eh Auxiliary Register 0
A2h Auxiliary Register 1
FBh Version Number
-
-
EXTRAM
-
ENBOOT(1)
NV5
DPS
NV0
NVERS
Note:
NV7
NV6
NV4
NV2
NV1
1. ENBOOT bit is only available in AT89C51SND2C product.
Table 33. PLL and System Clock SFRs
Mnemonic Add Name
7
-
6
-
5
-
4
-
3
2
-
1
-
0
X2
CKCON
8Fh Clock Control
E9h PLL Control
EEh PLL N Divider
EFh PLL R Divider
-
PLLRES
N3
PLLCON
PLLNDIV
PLLRDIV
R1
-
R0
N6
R8
-
-
-
PLLEN
N1
PLOCK
N0
N5
R7
N4
R6
N2
R4
R9
R5
R3
R2
Table 34. Interrupt SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
IEN0
IEN1
IPH0
IPL0
IPH1
IPL1
A8h Interrupt Enable Control 0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
B1h Interrupt Enable Control 1
-
-
-
-
-
EUSB
-
EKB
-
ESPI
EI2C
EMMC
IPHX0
IPLX0
IPHMMC
IPLMMC
B7h Interrupt Priority Control High 0
B8h Interrupt Priority Control Low 0
B3h Interrupt Priority Control High 1
B2h Interrupt Priority Control Low 1
IPHAUD
IPLAUD
IPHUSB
IPLUSB
IPHMP3
IPHS
IPLS
IPHKB
IPLKB
IPHT1
IPHX1
IPLX1
IPHSPI
IPLSPI
IPHT0
IPLT0
IPHI2C
IPLI2C
IPLMP3
IPLT1
-
-
-
-
30
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 35. Port SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
P0
P2
P3
P4
80h 8-bit Port 0
A0h 8-bit Port 2
B0h 8-bit Port 3
C0h 4-bit Port 4
-
-
-
-
Table 36. Auxiliary SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
AUXCON
90h Auxiliary Control
SDA
SCL
-
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Table 37. Flash Memory SFR
Mnemonic Add Name
7
6
5
4
3
2
1
0
FCON(1)
Note:
D1h Flash Control
FPL3
FPL2
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
1. FCON register is only available in AT89C51SND2C product.
Table 38. Timer SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
TCON
TMOD
TL0
88h Timer/Counter 0 and 1 Control
TF1
TR1
TF0
M11
TR0
M01
IE1
IT1
IE0
M10
IT0
M00
89h Timer/Counter 0 and 1 Modes
8Ah Timer/Counter 0 Low Byte
8Ch Timer/Counter 0 High Byte
8Bh Timer/Counter 1 Low Byte
8Dh Timer/Counter 1 High Byte
A6h Watchdog Timer Reset
GATE1
C/T1#
GATE0
C/T0#
TH0
TL1
TH1
WDTRST
WDTPRG
A7h Watchdog Timer Program
-
-
-
-
-
WTO2
WTO1
WTO0
31
4341D–MP3–04/05
Table 39. MP3 Decoder SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
MP3CON
MP3STA
AAh MP3 Control
C8h MP3 Status
MPEN
MPBBST
CRCEN MSKANC MSKREQ MSKLAY MSKSYN MSKCRC
MPANC
MPREQ
ERRLAY ERRSYN ERRCRC
MPFS1
-
MPFS0
-
MPVER
-
MP3STA1 AFh MP3 Status 1
-
-
-
MPFREQ MPBREQ
MP3DAT
MP3ANC
MP3VOL
MP3VOR
MP3BAS
MP3MED
MP3TRE
MP3CLK
ACh MP3 Data
MPD7
MPD6
MPD5
MPD4
AND4
VOL4
VOR4
BAS4
MPD3
AND3
VOL3
VOR3
BAS3
MPD2
AND2
VOL2
VOR2
BAS2
MED2
TRE2
MPCD2
MPD1
AND1
VOL1
VOR1
BAS1
MED1
TRE1
MPCD1
MPD0
AND0
VOL0
VOR0
BAS0
MED0
TRE0
MPCD0
ADh MP3 Ancillary Data
AND7
AND6
AND5
9Eh MP3 Audio Volume Control Left
9Fh MP3 Audio Volume Control Right
B4h MP3 Audio Bass Control
B5h MP3 Audio Medium Control
B6h MP3 Audio Treble Control
EBh MP3 Clock Divider
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MED4
TRE4
MED3
TRE3
MPCD4
MPCD3
Table 40. Audio Interface SFRs
Mnemonic Add Name
7
6
5
4
3
JUST0
-
2
POL
DUP1
-
1
0
AUDCON0 9Ah Audio Control 0
AUDCON1 9Bh Audio Control 1
JUST4
SRC
SREQ
AUD7
-
JUST3
DRQEN
UDRN
AUD6
-
JUST2
MSREQ
AUBUSY
AUD5
-
JUST1
MUDRN
-
DSIZ
DUP0
-
HLR
AUDEN
-
AUDSTA
AUDDAT
AUDCLK
9Ch Audio Status
9Dh Audio Data
-
AUD4
AUCD4
AUD3
AUCD3
AUD2
AUCD2
AUD1
AUCD1
AUD0
AUCD0
ECh Audio Clock Divider
32
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 41. USB Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
USBCON
BCh USB Global Control
USBE
SUSPCLK SDRMWUP
-
UPRSM RMWUPE CONFG
FADDEN
UADD0
SPINT
USBADDR C6h USB Address
FEN
UADD6
UADD5
UADD4
UADD3
SOFINT
UADD2
UADD1
USBINT
USBIEN
UEPNUM
BDh USB Global Interrupt
-
-
-
-
WUPCPU EORINT
-
-
-
BEh USB Global Interrupt Enable
C7h USB Endpoint Number
-
EWUPCPU EEORINT ESOFINT
-
ESPINT
-
-
-
-
-
EPNUM1 EPNUM0
EPTYPE1 EPTYPE0
UEPCONX D4h USB Endpoint X Control
UEPSTAX CEh USB Endpoint X Status
EPEN
NAKIEN NAKOUT
NAKIN
DTGL
EPDIR
DIR
RXOUTB1 STALLRQ TXRDY
STLCRC RXSETUP RXOUTB0 TXCMP
UEPRST
UEPINT
UEPIEN
D5h USB Endpoint Reset
-
-
-
-
-
-
-
EP2RST
EP2INT
EP1RST
EP1INT
EP0RST
EP0INT
F8h USB Endpoint Interrupt
C2h USB Endpoint Interrupt Enable
-
-
-
-
-
FDAT6
BYCT6
FNUM6
-
-
-
-
FDAT3
BYCT3
FNUM3
-
EP2INTE EP1INTE EP0INTE
UEPDATX CFh USB Endpoint X FIFO Data
FDAT7
FDAT5
BYCT5
FNUM5
FDAT4
BYCT4
FNUM4
FDAT2
BYCT2
FNUM2
FNUM10
-
FDAT1
BYCT1
FNUM1
FNUM9
FDAT0
BYCT0
FNUM0
FNUM8
UBYCTX
UFNUML
UFNUMH
USBCLK
E2h USB Endpoint X Byte Counter
BAh USB Frame Number Low
BBh USB Frame Number High
EAh USB Clock Divider
-
FNUM7
-
-
CRCOK CRCERR
-
-
-
-
USBCD1 USBCD0
Table 42. Audio Interface SFRs
Mnemonic Add Name
7
6
5
4
3
JUST0
-
2
POL
DUP1
-
1
0
AUDCON0 9Ah Audio Control 0
AUDCON1 9Bh Audio Control 1
JUST4
SRC
SREQ
AUD7
-
JUST3
DRQEN
UDRN
AUD6
-
JUST2
MSREQ
AUBUSY
AUD5
-
JUST1
MUDRN
-
DSIZ
DUP0
-
HLR
AUDEN
-
AUDSTA
AUDDAT
AUDCLK
9Ch Audio Status
9Dh Audio Data
-
AUD4
AUCD4
AUD3
AUCD3
AUD2
AUCD2
AUD1
AUCD1
AUD0
AUCD0
ECh Audio Clock Divider
Table 43. MMC Controller SFRs
Mnemonic Add Name
7
6
5
4
3
MBLOCK
DATDIR
-
2
1
0
MMCON0
MMCON1
MMCON2
MMSTA
E4h MMC Control 0
E5h MMC Control 1
E6h MMC Control 2
DEh MMC Control and Status
E7h MMC Interrupt
DRPTR
BLEN3
MMCEN
-
DTPTR
BLEN2
DCR
CRPTR
BLEN1
CCR
CTPTR
BLEN0
-
DFMT
DATEN
DATD1
CRC7S
F1FI
RFMT
RESPEN
DATD0
RESPFS
F2EI
CRCDIS
CMDEN
FLOWC
CFLCK
F1EI
-
CBUSY
EOCI
CRC16S
EOFI
DATFS
F2FI
MMINT
MCBI
MCBM
MC7
EORI
EORM
MC6
MMMSK
MMCMD
MMDAT
MMCLK
DFh MMC Interrupt Mask
DDh MMC Command
DCh MMC Data
EOCM
MC5
EOFM
MC4
F2FM
MC3
F1FM
MC2
F2EM
MC1
F1EM
MC0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
EDh MMC Clock Divider
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
33
4341D–MP3–04/05
Table 44. IDE Interface SFR
Mnemonic Add Name
7
6
5
4
3
2
1
0
DAT16H
F9h High Order Data Byte
D15
D14
D13
D12
D11
D10
D9
D8
Table 45. Serial I/O Port SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SCON
SBUF
98h Serial Control
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99h Serial Data Buffer
B9h Slave Address Mask
A9h Slave Address
SADEN
SADDR
BDRCON
BRL
92h Baud Rate Control
91h Baud Rate Reload
BRR
TBCK
RBCK
SPD
SRC
Table 46. SPI Controller SFRs
Mnemonic Add Name
7
6
5
SSDIS
-
4
3
2
1
0
SPCON
SPSTA
SPDAT
C3h SPI Control
C4h SPI Status
C5h SPI Data
SPR2
SPIF
SPD7
SPEN
WCOL
SPD6
MSTR
MODF
SPD4
CPOL
-
CPHA
-
SPR1
-
SPR0
-
SPD5
SPD3
SPD2
SPD1
SPD0
Table 47. Two Wire Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SSCON
SSSTA
SSDAT
SSADR
93h Synchronous Serial Control
94h Synchronous Serial Status
95h Synchronous Serial Data
96h Synchronous Serial Address
SSCR2
SSC4
SSD7
SSA7
SSPE
SSC3
SSD6
SSA6
SSSTA
SSC2
SSD5
SSA5
SSSTO
SSC1
SSD4
SSA4
SSI
SSAA
0
SSCR1
0
SSCR0
0
SSC0
SSD3
SSA3
SSD2
SSA2
SSD1
SSA1
SSD0
SSGC
Table 48. Keyboard Interface SFRs
Mnemonic Add Name
7
-
6
-
5
-
4
KINL0
-
3
-
2
-
1
-
0
KBCON
KBSTA
A3h Keyboard Control
A4h Keyboard Status
KINM0
KINF0
KPDE
-
-
-
-
-
34
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 49. SFR Addresses and Reset Values
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
UEPINT
0000 0000
DAT16H
XXXX XXXX
NVERS
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
XXXX XXXX(2)
B(1)
0000 0000
PLLCON
0000 1000
USBCLK
0000 0000
MP3CLK
0000 0000
AUDCLK
0000 0000
MMCLK
0000 0000
PLLNDIV
0000 0000
PLLRDIV
0000 0000
ACC(1)
UBYCTLX
0000 0000
MMCON0
0000 0000
MMCON1
0000 0000
MMCON2
0000 0000
MMINT
0000 0011
0000 0000
P5(1)
XXXX 1111
MMDAT
1111 1111
MMCMD
1111 1111
MMSTA
0000 0000
MMMSK
1111 1111
PSW(1)
0000 0000
FCON(3)
UEPCONX
1000 0000
UEPRST
0000 0000
1111 0000(4)
MP3STA(1)
0000 0001
UEPSTAX
0000 0000
UEPDATX
XXXX XXXX
P4(1)
1111 1111
UEPIEN
0000 0000
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
USBADDR
0000 0000
UEPNUM
0000 0000
IPL0(1)
X000 0000
SADEN
0000 0000
UFNUML
0000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0001 0000
P3(1)
1111 1111
IEN1
0000 0000
IPL1
0000 0000
IPH1
0000 0000
MP3BAS
0000 0000
MP3MED
0000 0000
MP3TRE
0000 0000
IPH0
X000 0000
IEN0(1)
0000 0000
SADDR
0000 0000
MP3CON
0011 1111
MP3DAT
0000 0000
MP3ANC
0000 0000
MP3STA1
0100 0001
P2(1)
1111 1111
AUXR1
XXXX 00X0
KBCON
0000 1111
KBSTA
0000 0000
WDTRST
XXX XXXX
WDTPRG
XXXX X000
SCON
0000 0000
SBUF
XXXX XXXX
AUDCON0
0000 1000
AUDCON1
1011 0010
AUDSTA
1100 0000
AUDDAT
1111 1111
MP3VOL
0000 0000
MP3VOR
0000 0000
AUXCON(1)
1111 1111
BRL
0000 0000
BDRCON
XXX0 0000
SSCON
0000 0000
SSSTA
1111 1000
SSDAT
1111 1111
SSADR
1111 1110
TCON(1)
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
X000 1101
CKCON
0000 000X(5)
0000 0000
P0(1)
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00XX 0000
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.
2. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND2C product and 0000 0001 for AT83SND2C
product.
3. FCON register is only available in AT89C51SND2C product.
4. FCON reset value is 00h in case of reset with hardware condition.
5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
35
4341D–MP3–04/05
Interrupt System
The AT8xC51SND2C, like other control-oriented computer architectures, employ a pro-
gram interrupt method. This operation branches to a subroutine and performs some
service in response to the interrupt. When the subroutine completes, execution resumes
at the point where the interrupt occurred. Interrupts may occur as a result of internal
AT8xC51SND2C activity (e.g., timer overflow) or at the initiation of electrical signals
external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is pro-
grammed by the system designer, who determines priority of interrupt service relative to
normal code execution and other interrupt service routines. All of the interrupt sources
are enabled or disabled by the system designer and may be manipulated dynamically.
A typical interrupt event chain occurs as follows:
•
•
•
An internal or external device initiates an interrupt-request signal. The
AT8xC51SND2C, latches this event into a flag buffer.
The priority of the flag is compared to the priority of other interrupts by the interrupt
handler. A high priority causes the handler to set an interrupt flag.
This signals the instruction execution unit to execute a context switch. This context
switch breaks the current flow of instruction sequences. The execution unit
completes the current instruction prior to a save of the program counter (PC) and
reloads the PC with the start address of a software service routine.
•
The software service routine executes assigned tasks and as a final activity
performs a RETI (return from interrupt) instruction. This instruction signals
completion of the interrupt, resets the interrupt-in-progress priority and reloads the
program counter. Program operation then continues from the original point of
interruption.
Table 50. Interrupt System Signals
Signal
Name
Alternate
Function
Type Description
External Interrupt 0
See section "External Interrupts", page 39.
INT0
I
I
I
P3.2
P3.3
-
External Interrupt 1
See section “External Interrupts”, page 39.
INT1
KIN0
Keyboard Interrupt Input
See section “Keyboard Interface”, page 198.
Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used
to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 53 and
Table 54).
Four 8-bit registers are used to establish the priority level of the different sources: IPH0,
IPL0, IPH1 and IPL1 registers (see Table 55 to Table 58).
Interrupt System
Priorities
Each of the interrupt sources on the AT8xC51SND2C can be individually programmed
to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High
registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and
IPL1). This provides each interrupt source four possible priority levels according to
Table 51.
36
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 51. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
1
1
0
1
0
1
0 Lowest
1
2
3 Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by
another interrupt of lower or equal priority. Higher priority interrupts are serviced before
lower priority interrupts. The response to simultaneous occurrence of equal priority inter-
rupts is determined by an internal hardware polling sequence detailed in Table 52.
Thus, within each priority level there is a second priority structure determined by the
polling sequence. The interrupt control system is shown in Figure 19.
Table 52. Priority within Same Level
Interrupt Request Flag
Interrupt Address
Vectors
Cleared by Hardware
(H) or by Software (S)
Interrupt Name
INT0
Priority Number
0 (Highest Priority)
C:0003h
C:000Bh
C:0013h
C:001Bh
C:0023h
C:002Bh
C:0033h
C:003Bh
C:0043h
C:004Bh
C:0053h
C:005Bh
C:0063h
C:006Bh
C:0073h
INT0
Timer 0
1
Timer 0
INT1
2
INT1
Timer 1
3
Timer 1
Serial Port
MP3 Decoder
Audio Interface
MMC Interface
Two Wire Controller
SPI Controller
Reserved
4
Serial Port
MP3 Decoder
Audio Interface
MMC Interface
Two Wire Controller
SPI Controller
Reserved
5
6
7
8
9
10
Keyboard
11
Keyboard
Reserved
12
13
Reserved
USB
USB
Reserved
14 (Lowest Priority)
Reserved
37
4341D–MP3–04/05
Figure 19. Interrupt Control System
Highest
Priority
00
01
10
11
External
Interrupts
INT0
Interrupt 0
EX0
IEN0.0
00
01
10
11
Timer 0
ET0
IEN0.1
00
01
10
11
External
Interrupt 1
INT1
EX1
IEN0.2
00
01
10
11
Timer 1
ET1
IEN0.3
00
01
10
11
TXD
Serial
Port
RXD
ES
IEN0.4
00
01
10
11
MP3
Decoder
EMP3
IEN0.5
00
01
10
11
Audio
Interface
EAUD
IEN0.6
00
01
10
11
MCLK
MDAT
MCMD
MMC
Controller
EMMC
IEN1.0
00
01
10
11
SCL
TWI
Controller
SDA
EI2C
IEN1.1
00
01
10
11
SCK
SI
SO
SPI
Controller
ESPI
IEN1.2
00
01
10
11
KIN0
Keyboard
EKB
IEN1.4
00
01
10
11
D+
D-
USB
Controller
EUSB
IEN1.6
EA
IEN0.7
IPH/L
Interrupt Enable
Priority Enable
Lowest Priority Interrupts
38
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
External Interrupts
INT1:0 Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to
be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in
TCON register as shown in Figure 20. If ITn = 0, INTn is triggered by a low level at the
pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits
EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn
in TCON register. If the interrupt is edge-triggered, the request flag is cleared by hard-
ware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the
interrupt service routine must clear the request flag and the interrupt must be deas-
serted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low
level signals as detailed in section “Exiting Power-down Mode”, page 48.
Figure 20. INT1:0 Input Circuitry
0
1
INT0/1
Interrupt
Request
INT0/1
IE0/1
TCON.1/3
EX0/1
IEN0.0/2
IT0/1
TCON.0/2
KIN0 Inputs
External interrupts KIN0 provides the capability to connect a keyboard. For detailed
information on this inputs, refer to section “Keyboard Interface”, page 198.
Input Sampling
External interrupt pins (INT1:0 and KIN0) are sampled once per peripheral cycle (6
peripheral clock periods) (see Figure 21). A level-triggered interrupt pin held low or high
for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator
clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts
must hold the request pin low for at least 6 peripheral clock periods.
Figure 21. Minimum Pulse Timings
Level-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
Edge-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
1 cycle
39
4341D–MP3–04/05
Registers
Table 53. IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
7
6
5
4
3
2
1
0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
7
EA
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
6
5
4
3
2
1
0
EAUD
EMP3
ES
MP3 Decoder Interrupt Enable Bit
Set to enable MP3 decoder interrupt.
Clear to disable MP3 decoder interrupt.
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
Timer 1 Overflow Interrupt Enable Bit
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
ET1
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
EX1
ET0
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
EX0
Reset Value = 0000 0000b
40
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 54. IEN1 Register
IEN1 (S:B1h) – Interrupt Enable Register 1
7
-
6
5
-
4
3
-
2
1
0
EUSB
EKB
ESPI
EI2C
EMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
-
The value read from this bit is always 0. Do not set this bit.
USB Interface Interrupt Enable Bit
Set this bit to enable USB interrupts.
Clear this bit to disable USB interrupts.
EUSB
Reserved
-
The value read from this bit is always 0. Do not set this bit.
Keyboard Interface Interrupt Enable Bit
Set to enable Keyboard interrupt.
Clear to disable Keyboard interrupt.
EKB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Controller Interrupt Enable Bit
Set to enable SPI interrupt.
ESPI
Clear to disable SPI interrupt.
Two Wire Controller Interrupt Enable Bit
Set to enable Two Wire interrupt.
Clear to disable Two Wire interrupt.
1
0
EI2C
MMC Interface Interrupt Enable Bit
Set to enable MMC interrupt.
EMMC
Clear to disable MMC interrupt.
Reset Value = 0000 0000b
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4341D–MP3–04/05
Table 55. IPH0 Register
IPH0 (S:B7h) – Interrupt Priority High Register 0
7
-
6
5
4
3
2
1
0
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Audio Interface Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHAUD
IPHMP3
IPHS
MP3 Decoder Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Serial Port Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Timer 1 Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHT1
IPHX1
IPHT0
IPHX0
External Interrupt 1 Priority Level MSB
Refer to Table 51 for priority level description.
Timer 0 Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
External Interrupt 0 Priority Level MSB
Refer to Table 51 for priority level description.
Reset Value = X000 0000b
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AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 56. IPH1 Register
IPH1 (S:B3h) – Interrupt Priority High Register 1
7
-
6
5
-
4
3
-
2
1
0
IPHUSB
IPHKB
IPHSPI
IPHI2C
IPHMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHUSB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHKB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHSPI
IPHI2C
IPHMMC
Two Wire Controller Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
MMC Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Reset Value = 0000 0000b
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4341D–MP3–04/05
Table 57. IPL0 Register
IPL0 (S:B8h) - Interrupt Priority Low Register 0
7
-
6
5
4
3
2
1
0
IPLAUD
IPLMP3
IPLS
IPLT1
IPLX1
IPLT0
IPLX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Audio Interface Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLAUD
IPLMP3
IPLS
MP3 Decoder Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
Serial Port Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
Timer 1 Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLT1
External Interrupt 1 Priority Level LSB
Refer to Table 51 for priority level description.
IPLX1
IPLT0
Timer 0 Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
External Interrupt 0 Priority Level LSB
Refer to Table 51 for priority level description.
IPLX0
Reset Value = X000 0000b
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AT8xC51SND2C
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AT8xC51SND2C
Table 58. IPL1 Register
IPL1 (S:B2h) – Interrupt Priority Low Register 1
7
-
6
5
-
4
3
-
2
1
0
IPLUSB
IPLKB
IPLSPI
IPLI2C
IPLMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLUSB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLKB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLSPI
IPLI2C
IPLMMC
Two Wire Controller Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
MMC Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
Reset Value = 0000 0000b
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4341D–MP3–04/05
Power Management
2 power reduction modes are implemented in the AT8xC51SND2C: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12.
Reset
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT8xC51SND2C and vectors
the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset
by simply connecting an external capacitor to VDD as shown in Figure 22. A warm reset
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section “DC Characteristics” of the AT8xC51SND2C datasheet. The status of the
Port pins during reset is detailed in Table 59.
Figure 22. Reset Circuitry and Power-On Reset
VDD
From Internal
Reset Source
P
VDD
To CPU Core
and Peripherals
RST
+
RST
VSS
RST input circuitry
Power-on Reset
Table 59. Pin Conditions in Special Operating Modes
Mode
Port 0
Floating
Data
Port 1
High
Port 2
High
Port 3
High
Port 4
High
Port 5
MMC
Floating
Data
Audio
1
Reset
Idle
High
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Power-down
Data
Data
Note:
1. Refer to section “Audio Output Interface”, page 73.
Cold Reset
2 conditions are required before enabling a CPU start-up:
•
•
V
DD must reach the specified VDD range
The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level VIH1 is reached and when the pulse width covers the
period of time where VDD and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
•
•
V
DD rise time,
Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 60 gives some capacitor values examples for a minimum RRST
of 50 KΩ and different oscillator startup and VDD rise times.
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AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 60. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1)
VDD Rise Time
10 ms
Oscillator
Start-Up Time
1 ms
820 nF
2.7 µF
100 ms
12 µF
5 ms
1.2 µF
20 ms
3.9 µF
12 µF
Note:
1. These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be
fully discharged, leading to a bad reset sequence.
Warm Reset
To achieve a valid reset, the reset signal must be maintained for at least 2 machine
cycles (24 oscillator clock periods) while the oscillator is running. The number of clock
periods is mode independent (X2 or X1).
Watchdog Reset
As detailed in section “Watchdog Timer”, page 59, the WDT generates a 96-clock period
pulse on the RST pin. In order to properly propagate this pulse to the rest of the applica-
tion in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must
be added as shown in Figure 23.
Figure 23. Reset Circuitry for WDT Reset-out Usage
VDD
VDD
From WDT
+
Reset Source
P
RST
To CPU Core
and Peripherals
VDD
1K
RST
VSS
To Other
On-board
VSS
Circuitry
Reset Recommendation
to Prevent Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet
due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program
Counter is accidently in the range of the boot memory addresses then a Flash access
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an external reset circuitry featuring power supply monitoring to
prevent system malfunction during periods of insufficient power supply voltage (power
supply failure, power supply switched off).
Idle Mode
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked (refer to section “Oscillator”, page 12). The CPU
status before entering Idle mode is preserved, i.e., the program counter and program
status word register retain their data for the duration of Idle mode. The contents of the
SFRs and RAM are also retained. The status of the Port pins during Idle mode is
detailed in Table 59.
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4341D–MP3–04/05
Entering Idle Mode
Exiting Idle Mode
To enter Idle mode, the user must set the IDL bit in PCON register (see Table 61). The
AT8xC51SND2C enters Idle mode upon execution of the instruction that sets IDL bit.
The instruction that sets IDL bit is the last instruction executed.
Note:
If IDL bit and PD bit are set simultaneously, the AT8xC51SND2C enter Power-down
mode. Then it does not go in Idle mode when exiting Power-down mode.
There are 2 ways to exit Idle mode:
1. Generate an enabled interrupt.
–
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general-purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
2. Generate a reset.
–
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the AT8xC51SND2C and vectors the CPU to address C:0000h.
Note:
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated Idle mode should
not write to a Port pin or to the external RAM.
Power-down Mode
The Power-down mode places the AT8xC51SND2C in a very low power state. Power-
down mode stops the oscillator and freezes all clocks at known states (refer to the Sec-
tion "Oscillator", page 12). The CPU status prior to entering Power-down mode is
preserved, i.e., the program counter, program status word register retain their data for
the duration of Power-down mode. In addition, the SFRs and RAM contents are pre-
served. The status of the Port pins during Power-down mode is detailed in Table 59.
Note:
VDD may be reduced to as low as VRET during Power-down mode to further reduce power
dissipation. Notice, however, that VDD is not reduced until Power-down mode is invoked.
Entering Power-down Mode
Exiting Power-down Mode
To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND2C enters
the Power-down mode upon execution of the instruction that sets PD bit. The instruction
that sets PD bit is the last instruction executed.
If VDD was reduced during the Power-down mode, do not exit Power-down mode until
V
DD is restored to the normal operating level.
There are 2 ways to exit the Power-down mode:
1. Generate an enabled external interrupt.
–
The AT8xC51SND2C provides capability to exit from Power-down using
INT0, INT1, and KIN0 inputs. In addition, using KIN input provides high or
low level exit capability (see section “Keyboard Interface”, page 198).
Hardware clears PD bit in PCON register which starts the oscillator and
restores the clocks to the CPU and peripherals. Using INTn input, execution
48
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
resumes when the input is released (see Figure 24) while using KINx input,
execution resumes after counting 1024 clock ensuring the oscillator is
restarted properly (see Figure 25). This behavior is necessary for decoding
the key while it is still pressed. In both cases, execution resumes with the
interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the
instruction that activated Power-down mode.
Note:
1. The external interrupt used to exit Power-down mode must be configured as level
sensitive (INT0 and INT1) and must be assigned the highest priority. In addition, the
duration of the interrupt must be long enough to allow the oscillator to stabilize. The
execution will only resume when the interrupt is deasserted.
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal
RAM content.
Figure 24. Power-down Exit Waveform Using INT1:0
INT1:0
OSC
Oscillator Restart Phase
Active phase
Power-down Phase
Active Phase
Figure 25. Power-down Exit Waveform Using KIN0
KIN01
OSC
Power-down Phase
Active phase
1024 clock count
Active phase
Note:
1. KIN0 can be high or low-level triggered.
2. Generate a reset.
–
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the AT8xC51SND2C and
vectors the CPU to address 0000h.
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
RAM content.
49
4341D–MP3–04/05
Registers
Table 61. PCON Register
PCON (S:87h) – Power Configuration Register
7
6
5
-
4
-
3
2
1
0
SMOD1
SMOD0
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic Description
Serial Port Mode Bit 1
Set to select double baud rate in mode 1,2 or 3.
7
6
SMOD1
Serial Port Mode Bit 0
SMOD0 Set to select FE bit in SCON register.
Clear to select SM0 bit in SCON register.
Reserved
5 - 4
3
-
The value read from these bits is indeterminate. Do not set these bits.
General-Purpose Flag 1
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
GF1
GF0
General-Purpose Flag 0
One use is to indicate whether an interrupt occurred during normal operation or
during Idle mode.
2
1
Power-Down Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-down mode.
If IDL and PD are both set, PD takes precedence.
PD
Idle Mode Bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
0
IDL
If IDL and PD are both set, PD takes precedence.
Reset Value = 00XX 0000b
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AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Timers/Counters
The AT8xC51SND2C implement 2 general-purpose, 16-bit Timers/Counters. They are
identified as Timer 0 and Timer 1, and can be independently configured to operate in a
variety of modes as a Timer or as an event Counter. When operating as a Timer, the
Timer/Counter runs for a programmed length of time, then issues an interrupt request.
When operating as a Counter, the Timer/Counter counts negative transitions on an
external pin. After a preset number of counts, the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following
sections.
Timer/Counter
Operations
For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in
cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see
Table 62) turns the Timer on by allowing the selected input to increment TLx. When TLx
overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in
TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer
registers can be accessed to obtain the current count or to enter preset values. They
can be read at any time but TRx bit must be cleared to preset their values, otherwise,
the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the
divided-down peripheral clock or external pin Tx as the source for the counted signal.
TRx bit must be cleared when changing the mode of operation, otherwise the behavior
of the Timer/Counter is unpredictable.
For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral
clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock
periods). The Timer clock rate is FPER/6, i.e., FOSC/12 in standard mode or FOSC/6 in X2
mode.
For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every peripheral cycles. When
the sample is high in one cycle and low in the next one, the Counter is incremented.
Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is FPER/12, i.e., FOSC/24 in standard mode or FOSC/12 in X2
mode. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for
at least one full peripheral cycle.
Timer Clock Controller
As shown in Figure 26, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from
either the peripheral clock (FPER) or the oscillator clock (FOSC) depending on the T0X2
and T1X2 bits in CKCON register. These clocks are issued from the Clock Controller
block as detailed in Section “Clock Controller”, page 12. When T0X2 or T1X2 bit is set,
the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock fre-
quency divided by 2. When cleared, the Timer clock frequency is equal to the oscillator
clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2
mode.
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4341D–MP3–04/05
Figure 26. Timer 0 and Timer 1 Clock Controller and Symbols
PER
CLOCK
PER
CLOCK
0
0
1
Timer 0 Clock
Timer 1 Clock
1
OSC
CLOCK
OSC
CLOCK
÷ 2
÷ 2
T0X2
CKCON.1
T1X2
CKCON.2
TIM0
TIM1
CLOCK
CLOCK
Timer 0 Clock Symbol
Timer 1 Clock Symbol
Timer 0
Timer 0 functions as either a Timer or event Counter in four modes of operation.
Figure 27 through Figure 33 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Table 63) and bits 0, 1,
4 and 5 of TCON register (see Table 62). TMOD register selects the method of Timer
gating (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and
M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control
bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).
For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by
the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer
operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-
rupt request.
It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer)
Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-
ister) with a modulo 32 prescaler implemented with the lower five bits of TL0 register
(see Figure 27). The upper three bits of TL0 register are indeterminate and should be
ignored. Prescaler overflow increments TH0 register. Figure 28 gives the overflow
period calculation formula.
Figure 27. Timer/Counter x (x = 0 or 1) in Mode 0
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
TLx
(5 Bits)
THx
(8 Bits)
Overflow
TFx
TCON reg
Tx
C/Tx#
TMOD Reg
INTx
GATEx
TMOD Reg
TRx
TCON Reg
Figure 28. Mode 0 Overflow Period Formula
6 ⋅ (16384 – (THx, TLx))
TFxPER
=
FTIMx
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AT8xC51SND2C
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AT8xC51SND2C
Mode 1 (16-bit Timer)
Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in
cascade (see Figure 29). The selected input increments TL0 register. Figure 30 gives
the overflow period calculation formula when in timer mode.
Figure 29. Timer/Counter x (x = 0 or 1) in Mode 1
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
THx
(8 bits)
TLx
(8 bits)
TFx
TCON Reg
Tx
C/Tx#
TMOD Reg
INTx
GATEx
TMOD Reg
TRx
TCON Reg
Figure 30. Mode 1 Overflow Period Formula
6 ⋅ (65536 – (THx, TLx))
TFxPER
=
FTIMx
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
Reload)
from TH0 register (see Table 64). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, which is preset by software. When the interrupt
request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next
reload value may be changed at any time by writing it to TH0 register. Figure 32 gives
the autoreload period calculation formula when in timer mode.
Figure 31. Timer/Counter x (x = 0 or 1) in Mode 2
TIMx
CLOCK
Timer x
Interrupt
Request
÷ 6
0
1
Overflow
TLx
(8 bits)
TFx
TCON reg
Tx
C/Tx#
TMOD reg
INTx
THx
(8 bits)
GATEx
TMOD reg
TRx
TCON reg
Figure 32. Mode 2 Autoreload Period Formula
6 ⋅ (256 – THx)
TFxPER
=
FTIMx
Mode 3 (2 8-bit Timers)
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (see Figure 33). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting FTF1/6) and takes over use of the Timer 1 interrupt (TF1) and
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
53
4341D–MP3–04/05
3. Figure 32 gives the autoreload period calculation formulas for both TF0 and TF1
flags.
Figure 33. Timer/Counter 0 in Mode 3: 2 8-bit Counters
TIM0
CLOCK
Timer 0
Interrupt
Request
÷ 6
0
1
Overflow
TL0
(8 bits)
TF0
TCON.5
T0
C/T0#
TMOD.2
INT0
GATE0
TMOD.3
TR0
TCON.4
Timer 1
Interrupt
Request
Overflow
TIM0
CLOCK
TH0
(8 bits)
÷ 6
TF1
TCON.7
TR1
TCON.6
Figure 34. Mode 3 Overflow Period Formula
6 ⋅ (256 – TH0)
6 ⋅ (256 – TL0)
TF1PER
=
TF0PER
=
FTIM0
FTIM0
Timer 1
Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-
lowing comments help to understand the differences:
•
Timer 1 functions as either a Timer or event Counter in three modes of operation.
Figure 27 through Figure 31 show the logical configuration for modes 0, 1, and 2.
Timer 1’s mode 3 is a hold-count mode.
•
Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 63)
and bits 2, 3, 6 and 7 of TCON register (see Figure 62). TMOD register selects the
method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of
operation (M11 and M01). TCON register provides Timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type
control bit (IT1).
•
•
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented
by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control
Timer operation.
•
•
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating
an interrupt request.
When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit
(TR1). For this situation, use Timer 1 only for applications that do not require an
interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in
and out of mode 3 to turn it off and on.
•
It is important to stop the Timer/Counter before changing modes.
54
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Mode 0 (13-bit Timer)
Mode 1 (16-bit Timer)
Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-
ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register
(see Figure 27). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-
ments TH1 register.
Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in
cascade (see Figure 29). The selected input increments TL1 register.
Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from
Reload)
TH1 register on overflow (see Figure 31). TL1 overflow sets TF1 flag in TCON register
and reloads TL1 with the contents of TH1, which is preset by software. The reload
leaves TH1 unchanged.
Mode 3 (Halt)
Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt
Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Interrupt
Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This
flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer
interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This
assumes interrupts are globally enabled by setting EA bit in IEN0 register.
Figure 35. Timer Interrupt System
Timer 0
Interrupt Request
TF0
TCON.5
ET0
IEN0.1
Timer 1
Interrupt Request
TF1
TCON.7
ET1
IEN0.3
55
4341D–MP3–04/05
Registers
Table 62. TCON Register
TCON (S:88h) – Timer/Counter Control Register
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Bit
Number
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1 pin.
Interrupt 1 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1).
Set to select falling edge active (edge triggered) for external interrupt 1.
IT1
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0 pin.
IE0
Interrupt 0 Type Control Bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0).
Set to select falling edge active (edge triggered) for external interrupt 0.
IT0
Reset Value = 0000 0000b
56
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 63. TMOD Register
TMOD (S:89h) – Timer/Counter Mode Control Register
7
6
5
4
3
2
1
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Bit
Number Mnemonic Description
Timer 1 Gating Control Bit
GATE1 Clear to enable Timer 1 whenever TR1 bit is set.
7
Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.
Timer 1 Counter/Timer Select Bit
6
5
C/T1#
M11
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
Timer 1 Mode Select Bits
M11 M01
Operating mode
0
0
1
0
1
0
Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).
Mode 1: 16-bit Timer/Counter.
4
3
M01
Mode 2: 8-bit auto-reload Timer/Counter (TL1).(1)
1
1
Mode 3: Timer 1 halted. Retains count.
Timer 0 Gating Control Bit
GATE0 Clear to enable Timer 0 whenever TR0 bit is set.
Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set.
Timer 0 Counter/Timer Select Bit
2
1
C/T0#
M10
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
Timer 0 Mode Select Bit
M10 M00
Operating mode
0
0
1
0
1
0
Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
Mode 1: 16-bit Timer/Counter.
M00
Mode 2: 8-bit auto-reload Timer/Counter (TL0).(2)
0
1
1
Mode 3: TL0 is an 8-bit Timer/Counter.
TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.
Notes: 1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
Reset Value = 0000 0000b
Table 64. TH0 Register
TH0 (S:8Ch) – Timer 0 High Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
High Byte of Timer 0
Reset Value = 0000 0000b
57
4341D–MP3–04/05
Table 65. TL0 Register
TL0 (S:8Ah) – Timer 0 Low Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
Low Byte of Timer 0
Reset Value = 0000 0000b
Table 66. TH1 Register
TH1 (S:8Dh) – Timer 1 High Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
High Byte of Timer 1
Reset Value = 0000 0000b
Table 67. TL1 Register
TL1 (S:8Bh) – Timer 1 Low Byte Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
7:0
Low Byte of Timer 1
Reset Value = 0000 0000b
58
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Watchdog Timer
The AT8xC51SND2C implement a hardware Watchdog Timer (WDT) that automatically
resets the chip if it is allowed to time out. The WDT provides a means of recovering from
routines that do not complete successfully due to software or hardware malfunctions.
Description
The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As
shown in Figure 36, the 14-bit prescaler is fed by the WDT clock detailed in
Section “Watchdog Clock Controller”, page 59.
The Watchdog Timer Reset register (WDTRST, see Table 69) provides control access
to the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 39) pro-
vides time-out period programming.
Three operations control the WDT:
•
•
•
Chip reset clears and disables the WDT.
Programming the time-out value to the WDTPRG register.
Writing a specific 2-Byte sequence to the WDTRST register clears and enables the
WDT.
Figure 36. WDT Block Diagram
14-bit Prescaler
7-bit Counter
WDT
CLOCK
÷ 6
OV
To internal reset
RST
RST
SET
WTO2:0
WDTPRG.2:0
1Eh-E1h Decoder
EN
RST
System Reset
MATCH
OSC
CLOCK
Pulse Generator
RST
WDTRST
Watchdog Clock
Controller
As shown in Figure 37 the WDT clock (FWDT) is derived from either the peripheral clock
(FPER) or the oscillator clock (FOSC) depending on the WTX2 bit in CKCON register.
These clocks are issued from the Clock Controller block as detailed in Section "Clock
Controller", page 12. When WTX2 bit is set, the WDT clock frequency is fixed and equal
to the oscillator clock frequency divided by 2. When cleared, the WDT clock frequency is
equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator
clock frequency in X2 mode.
Figure 37. WDT Clock Controller and Symbol
PER
CLOCK
0
WDT
CLOCK
WDT Clock
1
OSC
CLOCK
÷ 2
WDT Clock Symbol
WTX2
CKCON.6
59
4341D–MP3–04/05
Watchdog Operation
After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and
E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip
reset to disable it. If it is not cleared using the previous sequence, the WDT overflows
and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse
on the RST pin to globally reset the application (refer to Section “Power Management”,
page 46).
The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG
register accordingly to the formula shown in Figure 38. In this formula, WTOval repre-
sents the decimal value of WTO2:0 bits. Table 68 reports the time-out period depending
on the WDT frequency.
Figure 38. WDT Time-Out Formula
6 ⋅ ((214 ⋅ 2WTOval) – 1)
WDTTO
=
FWDT
Table 68. WDT Time-Out Computation
FWDT (ms)
WTO2 WTO1 WTO0
6 MHz(1)
16.38
8 MHz(1)
12.28
24.57
49.14
98.28
196.56
393.1
786.24
1572
10 MHz(1)
12 MHz(2)
8.19
16 MHz(2)
6.14
20 MHz(2)
4.92
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9.83
19.66
39.32
78.64
157.29
314.57
629.15
1258
32.77
16.38
12.28
9.83
65.54
32.77
24.57
19.66
131.07
262.14
524.29
1049
65.54
49.14
39.32
131.07
262.14
524.29
1049
98.28
78.64
196.56
393.12
786.24
157.29
314.57
629.15
2097
Notes: 1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:
FWDT = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode when WTX2 = 0: FWDT = FOSC
.
WDT Behavior during Idle and Operation of the WDT during power reduction modes deserves special attention.
Power-down Modes
The WDT continues to count while the AT8xC51SND2C is in Idle mode. This means
that you must dedicate some internal or external hardware to service the WDT during
Idle mode. One approach is to use a peripheral Timer to generate an interrupt request
when the Timer overflows. The interrupt service routine then clears the WDT, reloads
the peripheral Timer for the next service period and puts the AT8xC51SND2C back into
Idle mode.
The Power-down mode stops all phase clocks. This causes the WDT to stop counting
and to hold its count. The WDT resumes counting from where it left off if the Power-
down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT
does not overflow shortly after exiting the Power-down mode, it is recommended to clear
the WDT just before entering Power-down mode.
The WDT is cleared and disabled if the Power-down mode is terminated by a reset.
60
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Registers
Table 69. WDTRST Register
WDTRST (S:A6h Write only) – Watchdog Timer Reset Register
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic Description
7 - 0
-
Watchdog Control Value
Reset Value = XXXX XXXXb
Figure 39. WDTPRG Register
WDTPRG (S:A7h) – Watchdog Timer Program Register
7
6
5
4
3
2
1
0
-
-
-
-
-
WTO2
WTO1
WTO0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
2 - 0
-
The value read from these bits is indeterminate. Do not set these bits.
Watchdog Timer Time-Out Selection Bits
Refer to Table 68 for time-out periods.
WTO2:0
Reset Value = XXXX X000b
61
4341D–MP3–04/05
MP3 Decoder
The AT8xC51SND2C implement a MPEG I/II audio layer 3 decoder better known as
MP3 decoder.
In MPEG I (ISO 11172-3) three layers of compression have been standardized support-
ing three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3
allows highest compression rate of about 12:1 while still maintaining CD audio quality.
For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about
32M bytes of storage, can be encoded into only 2.7M bytes of MPEG I audio layer 3
data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz
are supported for low bit rates applications.
The AT8xC51SND2C can decode in real-time the MPEG I audio layer 3 encoded data
into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND2C MP3 decoder such as volume
control, bass, medium, and treble controls, bass boost effect and ancillary data
extraction.
Decoder
Description
The C51 core interfaces to the MP3 decoder through nine special function registers:
MP3CON, the MP3 Control register (see Table 74); MP3STA, the MP3 Status register
(see Table 75); MP3DAT, the MP3 Data register (see Table 76); MP3ANC, the Ancillary
Data register (see Table 78); MP3VOL and MP3VOR, the MP3 Volume Left and Right
Control registers (see Table 79 and Table 80); MP3BAS, MP3MED, and MP3TRE, the
MP3 Bass, Medium, and Treble Control registers (see Table 81, Table 82, and
Table 83); and MPCLK, the MP3 Clock Divider register (see Table 84).
Figure 40 shows the MP3 decoder block diagram.
Figure 40. MP3 Decoder Block Diagram
1K Bytes
Frame Buffer
MP3DAT
Audio Data
From C51
Header Checker
Huffman Decoder
8
Dequantizer
Stereo Processor
Side Information
MPxREQ
MP3STA1.n
ERRxxx MPFS1:0 MPVER
MP3STA.5:3 MP3STA.2:1 MP3STA.0
MP3
CLOCK
Ancillary Buffer
MP3ANC
MPEN
MP3CON.7
Sub-band
Synthesis
Decoded Data
To Audio Interface
16
Anti-Aliasing
IMDCT
MPBBST
MP3CON.6
MP3VOL MP3VOR MP3BAS MP3MED MP3TRE
62
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
MP3 Data
The MP3 decoder does not start any frame decoding before having a complete frame in
its input buffer(1). In order to manage the load of MP3 data in the frame buffer, a hard-
ware handshake consisting of data request and data acknowledgment is implemented.
Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and
MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can gen-
erate an interrupt if enabled as explained in Section “Interrupt”. The CPU must then load
data in the buffer by writing it through MP3DAT register thus acknowledging the previ-
ous request. As shown in Figure 41, the MPFREQ flag remains set while data (i.e a
frame) is requested by the decoder. It is cleared when no more data is requested and
set again when new data are requested. MPBREQ flag toggles at every Byte writing.
Note:
1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.
Figure 41. Data Timing Diagram
Cleared when Reading MP3STA
MPREQ Flag
MPFREQ Flag
MPBREQ Flag
Write to MP3DAT
MP3 Clock
The MP3 decoder clock is generated by division of the PLL clock. The division factor is
given by MPCD4:0 bits in MP3CLK register. Figure 42 shows the MP3 decoder clock
generator and its calculation formula. The MP3 decoder clock frequency depends only
on the incoming MP3 frames.
Figure 42. MP3 Clock Generator and Symbol
MP3CLK
PLL
CLOCK
MP3
CLOCK
MPCD4:0
MP3 Decoder Clock
MP3 Clock Symbol
PLLclk
MPCD + 1
MP3clk = ----------------------------
As soon as the frame header has been decoded and the MPEG version extracted, the
minimum MP3 input frequency must be programmed according to Table 70.
Table 70. MP3 Clock Frequency
MPEG Version
Minimum MP3 Clock (MHz)
I
21
II
10.5
63
4341D–MP3–04/05
Audio Controls
Volume Control
The MP3 decoder implements volume control on both right and left channels. The
MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 71.
Table 71. Volume Control
VOL4:0 or VOR4:0
00000
Volume Gain (dB)
Mute
-33
-27
-1.5
0
00001
00010
11110
11111
Equalization Control
Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium
band from 750 Hz to 3300 Hz and a treble band over 3300 Hz. The MP3BAS, MP3MED,
and MP3TRE registers allow a 32-step gain control in each band according to Table 72.
Table 72. Bass, Medium, Treble Control
BAS4:0 or MED4:0 or TRE4:0
Gain (dB)
- ∞
00000
00001
00010
11110
11111
-14
-10
+1
+1.5
Special Effect
The MPBBST bit in MP3CON register allows enabling of a bass boost effect with the fol-
lowing characteristics: gain increase of +9 dB in the frequency under 375 Hz.
Decoding Errors
The three different errors that can appear during frame processing are detailed in the
following sections. All these errors can trigger an interrupt as explained in Section "Inter-
rupt", page 66.
Layer Error
The ERRSYN flag in MP3STA is set when a non-supported layer is decoded in the
header of the frame that has been sent to the decoder.
Synchronization Error
CRC Error
The ERRSYN flag in MP3STA is set when no synchronization pattern is found in the
data that have been sent to the decoder.
When the CRC of a frame does not match the one calculated, the flag ERRCRC in
MP3STA is set. In this case, depending on the CRCEN bit in MP3CON, the frame is
played or rejected. In both cases, noise may appear at audio output.
64
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Frame Information
The MP3 frame header contains information on the audio data contained in the frame.
These informations is made available in the MP3STA register for you information.
MPVER and MPFS1:0 bits allow decoding of the sampling frequency according to
Table 73. MPVER bit gives the MPEG version (2 or 1).
Table 73. MP3 Frame Frequency Sampling
MPVER
MPFS1
MPFS0
Fs (kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
22.05 (MPEG II)
24 (MPEG II)
16 (MPEG II)
Reserved
44.1 (MPEG I)
48 (MPEG I)
32 (MPEG I)
Reserved
Ancillary Data
MP3 frames also contain data bits called ancillary data. These data are made available
in the MP3ANC register for each frame. As shown in Figure 43, the ancillary data are
available by Bytes when MPANC flag in MP3STA register is set. MPANC flag is set
when the ancillary buffer is not empty (at least one ancillary data is available) and is
cleared only when there is no more ancillary data in the buffer. This flag can generate an
interrupt as explained in Section "Interrupt", page 66. When set, software must read all
Bytes to empty the ancillary buffer.
Figure 43. Ancillary Data Block Diagram
Ancillary
Data To C51
7-Byte
Ancillary Buffer
8
8
MP3ANC
MPANC
MP3STA.7
65
4341D–MP3–04/05
Interrupt
Description
As shown in Figure 44, the MP3 decoder implements five interrupt sources reported in
ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register.
All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY,
MSKREQ, and MSKANC mask bits respectively in MP3CON register.
The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes inter-
rupts are globally enabled by setting EA bit in IEN0 register.
All interrupt flags but MPREQ and MPANC are cleared when reading MP3STA register.
The MPREQ flag is cleared by hardware when no more data is requested (see
Figure 41) and MPANC flag is cleared by hardware when the ancillary buffer becomes
empty.
Figure 44. MP3 Decoder Interrupt System
MPANC
MP3STA.7
MSKANC
MP3CON.4
MPREQ
MP3STA.6
MSKREQ
MP3CON.3
MP3 Decoder
Interrupt Request
ERRLAY
MP3STA.5
MSKLAY
MP3CON.2
EMP3
IEN0.5
ERRSYN
MP3STA.4
MSKSYN
MP3CON.1
ERRCRC
MP3STA.3
MSKCRC
MP3CON.0
Management
Reading the MP3STA register automatically clears the interrupt flags (acknowledgment)
except the MPREQ and MPANC flags. This implies that register content must be saved
and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts.
66
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Figure 45. MP3 Interrupt Service Routine Flow
MP3 Decoder
ISR
Read MP3STA
Data Request?
MPFREQ = 1?
Data Request
Handler
Ancillary Data?(1)
MPANC = 1?
Write MP3 Data
to MP3DAT
Ancillary Data
Handler
Sync Error?(1)
ERRSYN = 1?
Read ANN2:0 Ancillary
Bytes From MP3ANC
Synchro Error
Handler
Layer Error?(1)
ERRSYN = 1?
Reload MP3 Frame
Through MP3DAT
Layer Error
Handler
CRC Error
Handler
Load New MP3 Frame
Through MP3DAT
Note:
1. Test these bits only if needed (unmasked interrupt).
67
4341D–MP3–04/05
Registers
Table 74. MP3CON Register
MP3CON (S:AAh) – MP3 Decoder Control Register
7
6
5
4
3
2
1
0
MPEN
MPBBST
CRCEN
MSKANC
MSKREQ
MSKLAY
MSKSYN
MSKCRC
Bit
Bit
Number
Mnemonic Description
MP3 Decoder Enable Bit
7
6
MPEN
Set to enable the MP3 decoder.
Clear to disable the MP3 decoder.
Bass Boost Bit
MPBBST Set to enable the bass boost sound effect.
Clear to disable the bass boost sound effect.
CRC Check Enable Bit
Set to enable processing of frame that contains CRC error. Frame is played
whatever the error.
5
CRCEN
Clear to disable processing of frame that contains CRC error. Frame is skipped.
MPANC Flag Mask Bit
4
3
2
1
0
MSKANC Set to prevent the MPANC flag from generating a MP3 interrupt.
Clear to allow the MPANC flag to generate a MP3 interrupt.
MPREQ Flag Mask Bit
MSKREQ Set to prevent the MPREQ flag from generating a MP3 interrupt.
Clear to allow the MPREQ flag to generate a MP3 interrupt.
ERRLAY Flag Mask Bit
MSKLAY Set to prevent the ERRLAY flag from generating a MP3 interrupt.
Clear to allow the ERRLAY flag to generate a MP3 interrupt.
ERRSYN Flag Mask Bit
MSKSYN Set to prevent the ERRSYN flag from generating a MP3 interrupt.
Clear to allow the ERRSYN flag to generate a MP3 interrupt.
ERRCRC Flag Mask Bit
MSKCRC Set to prevent the ERRCRC flag from generating a MP3 interrupt.
Clear to allow the ERRCRC flag to generate a MP3 interrupt.
Reset Value = 0011 1111b
68
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 75. MP3STA Register
MP3STA (S:C8h Read Only) – MP3 Decoder Status Register
7
6
5
4
3
2
1
0
MPANC
MPREQ
ERRLAY
ERRSYN
ERRCRC
MPFS1
MPFS0
MPVER
Bit
Bit
Number
Mnemonic Description
Ancillary Data Available Flag
7
6
5
4
MPANC Set by hardware as soon as one ancillary data is available (buffer not empty).
Cleared by hardware when no more ancillary data is available (buffer empty).
MP3 Data Request Flag
MPREQ Set by hardware when MP3 decoder request data.
Cleared when reading MP3STA.
Invalid Layer Error Flag
ERRLAY Set by hardware when an invalid layer is encountered.
Cleared when reading MP3STA.
Frame Synchronization Error Flag
ERRSYN Set by hardware when no synchronization pattern is encountered in a frame.
Cleared when reading MP3STA.
CRC Error Flag
3
2 - 1
0
ERRCRC Set by hardware when a frame handling CRC is corrupted.
Cleared when reading MP3STA.
Frequency Sampling Bits
MPFS1:0
Refer to Table 73 for bits description.
MPEG Version Bit
MPVER Set by the MP3 decoder when the loaded frame is a MPEG I frame.
Cleared by the MP3 decoder when the loaded frame is a MPEG II frame.
Reset Value = 0000 0001b
Table 76. MP3DAT Register
MP3DAT (S:ACh) – MP3 Data Register
7
6
5
4
3
2
1
0
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
Bit
Bit
Number
Mnemonic Description
Input Stream Data Buffer
8-bit MP3 stream data input buffer.
7 - 0
MPD7:0
Reset Value = 0000 0000b
69
4341D–MP3–04/05
Table 77. MP3STA1 Register
MP3STA1 (S:AFh) – MP3 Decoder Status Register 1
7
-
6
-
5
-
4
3
2
-
1
-
0
-
MPFREQ
MPFREQ
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4
-
The value read from these bits is always 0. Do not set these bits.
MP3 Frame Data Request Flag
MPFREQ Set by hardware when MP3 decoder request data.
Cleared when MP3 decoder no more request data .
MP3 Byte Data Request Flag
MPBREQ Set by hardware when MP3 decoder request data.
Cleared when writing to MP3DAT.
3
Reserved
2 - 0
-
The value read from these bits is always 0. Do not set these bits.
Reset Value = 0001 0001b
Table 78. MP3ANC Register
MP3ANC (S:ADh Read Only) – MP3 Ancillary Data Register
7
6
5
4
3
2
1
0
AND7
AND6
AND5
AND4
AND3
AND2
AND1
AND0
Bit
Bit
Number
Mnemonic Description
Ancillary Data Buffer
MP3 ancillary data Byte buffer.
7 - 0
AND7:0
Reset Value = 0000 0000b
Table 79. MP3VOL Register
MP3VOL (S:9Eh) – MP3 Volume Left Control Register
7
-
6
-
5
-
4
3
2
1
0
VOL4
VOL3
VOL2
VOL1
VOL0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The value read from these bits is always 0. Do not set these bits.
Volume Left Value
Refer to Table 71 for the left channel volume control description.
VOL4:0
Reset Value = 0000 0000b
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AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 80. MP3VOR Register
MP3VOR (S:9Fh) – MP3 Volume Right Control Register
7
-
6
-
5
-
4
3
2
1
0
VOR4
VOR3
VOR2
VOR1
VOR0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The value read from these bits is always 0. Do not set these bits.
Volume Right Value
Refer to Table 71 for the right channel volume control description.
VOR4:0
Reset Value = 0000 0000b
Table 81. MP3BAS Register
MP3BAS (S:B4h) – MP3 Bass Control Register
7
-
6
-
5
-
4
3
2
1
0
BAS4
BAS3
BAS2
BAS1
BAS0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The value read from these bits is always 0. Do not set these bits.
Bass Gain Value
Refer to Table 72 for the bass control description.
BAS4:0
Reset Value = 0000 0000b
Table 82. MP3MED Register
MP3MED (S:B5h) – MP3 Medium Control Register
7
-
6
-
5
4
3
2
1
0
MED5
MED4
MED3
MED2
MED1
MED0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5-0
-
The value read from these bits is always 0. Do not set these bits.
Medium Gain Value
Refer to Table 72 for the medium control description.
MED5:0
Reset Value = 0000 0000b
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4341D–MP3–04/05
Table 83. MP3TRE Register
MP3TRE (S:B6h) – MP3 Treble Control Register
7
-
6
-
5
4
3
2
1
0
TRE5
TRE4
TRE3
TRE2
TRE1
TRE0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5-0
-
The value read from these bits is always 0. Do not set these bits.
Treble Gain Value
Refer to Table 72 for the treble control description.
TRE5:0
Reset Value = 0000 0000b
Table 84. MP3CLK Register
MP3CLK (S:EBh) – MP3 Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
MPCD4
MPCD3
MPCD2
MPCD1
MPCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4-0
-
The value read from these bits is always 0. Do not set these bits.
MP3 Decoder Clock Divider
5-bit divider for MP3 decoder clock generation.
MPCD4:0
Reset Value = 0000 0000b
72
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Audio Output
Interface
The AT8xC51SND2C implement an audio output interface allowing the audio bitstream
to be output in various formats. It is compatible with right and left justification PCM and
I2S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 12)
allows connection of almost all of the commercial audio DAC families available on the
market.
The audio bitstream can be from 2 different types:
•
•
The MP3 decoded bitstream coming from the MP3 decoder for playing songs.
The audio bitstream coming from the MCU for outputting voice or sounds.
Description
The C51 core interfaces to the audio interface through five special function registers:
AUDCON0 and AUDCON1, the Audio Control registers (see Table 86 and Table 87);
AUDSTA, the Audio Status register (see Table 88); AUDDAT, the Audio Data register
(see Table 89); and AUDCLK, the Audio Clock Divider register (see Table 90).
Figure 46 shows the audio interface block diagram, blocks are detailed in the following
sections.
Figure 46. Audio Interface Block Diagram
SCLK
DCLK
AUD
CLOCK
Clock Generator
0
1
DSEL
AUDEN
AUDCON1.0
HLR
AUDCON0.0
DSIZ
AUDCON0.1
POL
AUDCON0.2
Data Ready
Audio Data
From MP3
Decoder
16
16
16
Data Converter
DOUT
0
1
MP3 Buffer
Sample
Request To
MP3 Decoder
JUST4:0
AUDCON0.7:3
DRQEN
AUDCON1.6
SRC
AUDCON1.7
SREQ
AUDSTA.7
Audio Data
From C51
Audio Buffer
AUDDAT
8
UDRN
AUDSTA.6
AUBUSY
AUDSTA.5
DUP1:0
AUDCON1.2:1
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4341D–MP3–04/05
Clock Generator
The audio interface clock is generated by division of the PLL clock. The division factor is
given by AUCD4:0 bits in CLKAUD register. Figure 47 shows the audio interface clock
generator and its calculation formula. The audio interface clock frequency depends on
the incoming MP3 frames and the audio DAC used.
Figure 47. Audio Clock Generator and Symbol
AUDCLK
PLL
CLOCK
AUD
CLOCK
AUCD4:0
Audio Interface Clock
Audio Clock Symbol
PLLclk
AUCD + 1
AUDclk = ---------------------------
As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the
master clock generated by the PLL is output on the SCLK pin which is the DAC system
clock. This clock is output at 256 or 384 times the sampling frequency depending on the
DAC capabilities. HLR bit in AUDCON0 register must be set according to this rate for
properly generating the audio bit clock on the DCLK pin and the word selection clock on
the DSEL pin. These clocks are not generated when no data is available at the data
converter input.
For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or
32 bits per channel using the DSIZ bit in AUDCON0 register (see Section "Data Con-
verter", page 74), and the word selection signal is programmable for outputting left
channel on low or high level according to POL bit in AUDCON0 register as shown in
Figure 48.
Figure 48. DSEL Output Polarity
Left Channel
Left Channel
Right Channel
Right Channel
POL = 0
POL = 1
Data Converter
The data converter block converts the audio stream input from the 16-bit parallel format
to a serial format. For accepting all PCM formats and I2S format, JUST4:0 bits in
AUDCON0 register are used to shift the data output point. As shown in Figure 49, these
bits allow MSB justification by setting JUST4:0 = 00000, LSB justification by setting
JUST4:0 = 10000, I2S Justification by setting JUST4:0 = 00001, and more than 16-bit
LSB justification by filling the low significant bits with logic 0.
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AT8xC51SND2C
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AT8xC51SND2C
Figure 49. Audio Output Format
Left Channel
Right Channel
DSEL
1
2
3
13
14
15
16
DCLK
DOUT
1
2
3
13
14
18
14
15
16
LSB MSB B14
B1 LSB MSB B14
I2S Format with DSIZ = 0 and JUST4:0 = 00001.
B1
Left Channel
Right Channel
DSEL
DCLK
DOUT
1
2
3
17
18
32
1
2
3
17
32
MSB B14
LSB
MSB B14
LSB
I2S Format with DSIZ = 1 and JUST4:0 = 00001.
Left Channel
Right Channel
DSEL
DCLK
DOUT
1
2
3
13
14
15
16
1
2
3
13
15
16
MSB B14
B1 LSB MSB B15
MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.
B1 LSB
Left Channel
16 17
Right Channel
16 17
DSEL
DCLK
DOUT
1
18
31
32
1
18
31
32
MSB B14
B1 LSB
MSB B14
B1 LSB
16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.
Left Channel
15 16
Right Channel
15 16
DSEL
DCLK
DOUT
1
30
31
32
1
30
31
32
B2
B1 LSB
B2
B1 LSB
MSB B16
MSB B16
18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.
The data converter receives its audio stream from 2 sources selected by the SRC bit in
AUDCON1 register. When cleared, the audio stream comes from the MP3 decoder (see
Section “MP3 Decoder”, page 62) for song playing. When set, the audio stream is com-
ing from the C51 core for voice or sound playing.
As soon as first audio data is input to the data converter, it enables the clock generator
for generating the bit and word clocks.
Audio Buffer
In voice or sound playing mode, the audio stream comes from the C51 core through an
audio buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer
adapts the sample format and rate. The sample format is extended to 16 bits by filling
the LSB to 00h. Rate is adapted to the DAC rate by duplicating the data using DUP1:0
bits in AUDCON1 register according to Table 85.
The audio buffer interfaces to the C51 core through three flags: the sample request flag
(SREQ in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the
busy flag (AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt
request as explained in Section "Interrupt Request", page 76. The buffer size is 8 Bytes
large. SREQ is set when the samples number switches from 4 to 3 and reset when the
samples number switches from 4 to 5; UNDR is set when the buffer becomes empty sig-
naling that the audio interface ran out of samples; and AUBUSY is set when the buffer is
full.
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4341D–MP3–04/05
Table 85. Sample Duplication Factor
DUP1
DUP0
Factor
0
0
1
1
0
1
0
1
No sample duplication, DAC rate = 8 kHz (C51 rate).
One sample duplication, DAC rate = 16 kHz (2 x C51 rate).
2 samples duplication, DAC rate = 32 kHz (4 x C51 rate).
Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).
MP3 Buffer
In song playing mode, the audio stream comes from the MP3 decoder through a buffer.
The MP3 buffer is used to store the decoded MP3 data and interfaces to the decoder
through a 16-bit data input and data request signal. This signal asks for data when the
buffer has enough space to receive new data. Data request is conditioned by the
DREQEN bit in AUDCON1 register. When set, the buffer requests data to the MP3
decoder. When cleared no more data is requested but data are output until the buffer is
empty. This bit can be used to suspend the audio generation (pause mode).
Interrupt Request
The audio interrupt request can be generated by 2 sources when in C51 audio mode: a
sample request when SREQ flag in AUDSTA register is set to logic 1, and an under-run
condition when UDRN flag in AUDSTA register is set to logic 1. Both sources can be
enabled separately by masking one of them using the MSREQ and MUDRN bits in
AUDCON1 register. A global enable of the audio interface is provided by setting the
EAUD bit in IEN0 register.
The interrupt is requested each time one of the 2 sources is set to one. The source flags
are cleared by writing some data in the audio buffer through AUDDAT, but the global
audio interrupt flag is cleared by hardware when the interrupt service routine is
executed.
Figure 50. Audio Interface Interrupt System
UDRN
AUDSTA.6
Audio
Interrupt
Request
MUDRN
AUDCON1.4
SREQ
AUDSTA.7
EAUD
IEN0.6
MSREQ
AUDCON1.5
MP3 Song Playing
In MP3 song playing mode, the operations to do are to configure the PLL and the audio
interface according to the DAC selected. The audio clock is programmed to generate
the 256·Fs or 384·Fs as explained in Section "Clock Generator", page 74. Figure 51
shows the configuration flow of the audio interface when in MP3 song mode.
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AT8xC51SND2C
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AT8xC51SND2C
Figure 51. MP3 Mode Audio Configuration Flow
MP3 Mode
Configuration
Enable DAC System
Clock
Program Audio Clock
AUDEN = 1
Configure Interface
HLR = X
Wait For
DAC Set-up Time
DSIZ = X
POL = X
JUST4:0 = XXXXXb
SRC = 0
Enable Data Request
DRQEN = 1
Voice or Sound Playing
In voice or sound playing mode, the operations required are to configure the PLL and
the audio interface according to the DAC selected. The audio clock is programmed to
generate the 256·Fs or 384·Fs as for the MP3 playing mode. The data flow sent by the
C51 is then regulated by interrupt and data is loaded 4 Bytes by 4 Bytes. Figure 52
shows the configuration flow of the audio interface when in voice or sound mode.
Figure 52. Voice or Sound Mode Audio Flows
Voice/Song Mode
Configuration
Audio Interrupt
Service Routine
Wait for DAC
Enable Time
Program Audio Clock
Sample Request?
SREQ = 1?
Configure Interface
HLR = X
Select Audio
SRC = 1
DSIZ = X
Load 4 Samples in the
Audio Buffer
Under-run Condition1
POL = X
JUST4:0 = XXXXXb
DUP1:0 = XX
Load 8 Samples in the
Audio Buffer
Enable DAC System
Clock
Enable Interrupt
Set MSREQ & MUDRN1
EAUD = 1
AUDEN = 1
Note:
1. An under-run occurrence signifies that C51 core did not respond to the previous sample request interrupt. It may never
occur for a correct voice/sound generation. It is the user’s responsibility to mask it or not.
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4341D–MP3–04/05
Registers
Table 86. AUDCON0 Register
AUDCON0 (S:9Ah) – Audio Interface Control Register 0
7
6
5
4
3
2
1
0
JUST4
JUST3
JUST2
JUST1
JUST0
POL
DSIZ
HLR
Bit
Bit
Number
Mnemonic Description
Audio Stream Justification Bits
Refer to Section "Data Converter", page 74 for bits description.
7 - 3
2
JUST4:0
POL
DSEL Signal Output Polarity
Set to output the left channel on high level of DSEL output (PCM mode).
Clear to output the left channel on the low level of DSEL output (I2S mode).
Audio Data Size
1
0
DSIZ
HLR
Set to select 32-bit data output format.
Clear to select 16-bit data output format.
High/Low Rate Bit
Set by software when the PLL clock frequency is 384·Fs.
Clear by software when the PLL clock frequency is 256·Fs.
Reset Value = 0000 1000b
Table 87. AUDCON1 Register
AUDCON1 (S:9Bh) – Audio Interface Control Register 1
7
6
5
4
3
-
2
1
0
SRC
DRQEN
MSREQ
MUDRN
DUP1
DUP0
AUDEN
Bit
Bit
Number
Mnemonic Description
Audio Source Bit
Set to select C51 as audio source for voice or sound playing.
Clear to select the MP3 decoder output as audio source for song playing.
7
6
5
4
SRC
MP3 Decoded Data Request Enable Bit
DRQEN Set to enable data request to the MP3 decoder and to start playing song.
Clear to disable data request to the MP3 decoder.
Audio Sample Request Flag Mask Bit
MSREQ Set to prevent the SREQ flag from generating an audio interrupt.
Clear to allow the SREQ flag to generate an audio interrupt.
Audio Sample Under-run Flag Mask Bit
MUDRN Set to prevent the UDRN flag from generating an audio interrupt.
Clear to allow the UDRN flag to generate an audio interrupt.
Reserved
3
-
The value read from this bit is always 0. Do not set this bit.
Audio Duplication Factor
DUP1:0
2 - 1
Refer to Table 85 for bits description.
Audio Interface Enable Bit
AUDEN Set to enable the audio interface.
Clear to disable the audio interface.
0
Reset Value = 1011 0010b
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AT8xC51SND2C
Table 88. AUDSTA Register
AUDSTA (S:9Ch Read Only) – Audio Interface Status Register
7
6
5
4
-
3
-
2
-
1
-
0
-
SREQ
UDRN
AUBUSY
Bit
Bit
Number
Mnemonic Description
Audio Sample Request Flag
Set in C51 audio source mode when the audio interface request samples (buffer
half empty). This bit generates an interrupt if not masked and if enabled in IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
7
6
SREQ
UDRN
Audio Sample Under-run Flag
Set in C51 audio source mode when the audio interface runs out of samples
(buffer empty). This bit generates an interrupt if not masked and if enabled in
IEN0.
Cleared by hardware when samples are loaded in AUDDAT.
Audio Interface Busy Bit
Set in C51 audio source mode when the audio interface can not accept more
sample (buffer full).
Cleared by hardware when buffer is no more full.
5
AUBUSY
-
Reserved
4 - 0
The value read from these bits is always 0. Do not set these bits.
Reset Value = 1100 0000b
Table 89. AUDDAT Register
AUDDAT (S:9Dh) – Audio Interface Data Register
7
6
5
4
3
2
1
0
AUD7
AUD6
AUD5
AUD4
AUD3
AUD2
AUD1
AUD0
Bit
Bit
Number
Mnemonic Description
Audio Data
8-bit sampling data for voice or sound playing.
7 - 0
AUD7:0
Reset Value = 1111 1111b
Table 90. AUDCLK Register
AUDCLK (S:ECh) – Audio Clock Divider Register
7
-
6
-
5
-
4
3
2
1
0
AUCD4
AUCD3
AUCD2
AUCD1
AUCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4 - 0
-
The value read from these bits is always 0. Do not set these bits.
Audio Clock Divider
5-bit divider for audio clock generation.
AUCD4:0
Reset Value = 0000 0000b
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4341D–MP3–04/05
DAC and PA Interface The AT8xC51SND2C implements a stereo Audio Digital-to-Analog Converter and Audio
Power Amplifier targeted for Li-Ion or Ni-Mh battery powered devices.
Figure 53. Audio Interface Block Diagram
MP3
Decoder
Unit
DOUT
DCLK
I2S/PCM
Audio
DSEL
Interface
SCLK
HSR
HSL
AUXP
Audio
DAC
AUDCDIN
AUXN
AUDCDOUT
LINEL
LINER
MONOP
MONON
AUDCCLK
AUDCCS
PAINP
PAINN
Audio
PA
HPP
HPN
DAC
The Stereo DAC section is a complete high performance, stereo, audio digital-to-analog
converter delivering 93 dB Dynamic Range. It comprises a multibit sigma-delta modula-
tor with dither, continuous time analog filters and analog output drive circuitry. This
architecture provides a high insensitivity to clock jitter. The digital interpolation filter
increases the sample rate by a factor of 8 using 3 linear phase half-band filters cas-
caded, followed by a first order SINC interpolator with a factor of 8. This filter eliminates
the images of baseband audio, remaining only the image at 64x the input sample rate,
which is eliminated by the analog post filter. Optionally, a dither signal can be added that
may reduce eventual noise tones at the output. However, the use of a multibit sigma-
delta modulator already provides extremely low noise tones energy.
Master clock is 128 up to 512 times the input data rate allowing choice of input data rate
up to 50 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC
section is followed by a volume and mute control and can be simultaneously played
back directly through a Stereo 32Ω Headset pair of drivers. The Stereo 32Ω Headset
pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs as well
as a differential monaural auxiliary input (line level).
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AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
DAC Features
• 20 bit D/A Conversion
• 72dB Dynamic Range, -75dB THD Stereo line-in or microphone interface with 20dB
amplification
• 93dB Dynamic Range, -80dB THD Stereo D/A conversion
• 74dB Dynamic Range / -65dB THD for 20mW output power over 32 Ohm loads
• Stereo, Mono and Reverse Stereo Mixer
• Left/Right speaker short-circuit detection flag
• Differential mono auxiliary input amplifier and PA driver
• Audio sampling rates (Fs): 16, 22.05, 24, 32, 44.1 and 48 kHz.
Figure 54. Stereo DAC functional diagram
PA Gain
MONOP
PADRV
+
MONON
AUXP
AUX
AUXN
AUXG Gain
LINEL
LINER
PGA
LLIG,RLIG Gain
20,12 to -33 dB
(3dB)
PGA
Line Out Gain
LLOG, RLOG
0 to -46.5dB
(1.5dB)
Master Playback
Gain
12 to -34dB (1.5dB)
DSEL
SCLK
SPKR
DRV
32
Volume
Control
Volume
Control
DAC
DAC
Digital Filter
Digital Filter
+
+
+
HSL
HSR
Serial to
Parallel
Interface
DAC_OLC Gain
6 to -6dB (3dB)
DCLK
DOUT
SPKR
DRV
32
Volume
Control
Volume
Control
+
Digital Signals Timing
Data Interface
To avoid noises at the output, the reset state is maintained until proper synchronism is
achieved in the DAC serial interface:
•
•
•
•
DSEL
SCLK
DCLK
DOUT
The data interface allows three different data transfer modes:
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4341D–MP3–04/05
Figure 55. 20 bit I2S justified mode
SCLK
DSEL
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
DOUT
Figure 56. 20 bit MSB justified mode
SCLK
DSEL
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
DOUT
Figure 57. 20 bit LSB justified mode
SCLK
DSEL
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
DOUT
The selection between modes is done using the DINTSEL 1:0 in DAC_MISC register
(Table 112.) according with the following table:
DINTSEL 1:0
Format
00
01
1x
I2S Justified
MSB Justified
LSB Justified
The data interface always works in slave mode. This means that the DSEL and the
DCLK signals are provided by microcontroller audio data interface.
Serial Audio DAC Interface
The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave
mode:
•
•
•
AUDCDIN: is used to transfer data in series from the master to the slave DAC.
It is driven by the master.
AUDCDOUT: is used to transfer data in series from the slave DAC to the master.
It is driven by the selected slave DAC.
Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in
and out the devices through the AUDCDIN and AUDCDOUT lines.
Note:
Refer to Table 101. for DAC SPI Interface Description
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AT8xC51SND2C
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AT8xC51SND2C
Figure 58. Serial Audio Interface
Audio
DAC
AUDCDIN
AUDCDOUT
AUDCCLK
AUDCCS
Audio
PA
Protocol is as following to access DAC registers:
Figure 59. Dac SPI Interface
AUDCCS
AUDCCLK
d6
rw a6 a5 a4 a3 a2 a1 a0 d7
d5 d4 d3 d2 d1 d0
AUDCDIN
d7 d6 d5 d4 d3 d2 d1 d0
AUDCDOUT
DAC Interface SPI Protocol
On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a
read operation. The 7 following bits are used for the register address and the 8 last ones
are the write data. For both address and data, the most significant bit is the first one.
In case of a read operation, AUDCDOUT provides the contents of the read register,
MSB first.
The transfer is enabled by the AUDCCS signal active low. The interface is resetted at
every rising edge of AUDCCS in order to come back to an idle state, even if the transfer
does not succeed. The DAC Interface SPI is synchronized with the serial clock AUDC-
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4341D–MP3–04/05
CLK. Falling edge latches AUDCDIN input and rising edge shifts AUDCDOUT output
bits.
Note that the DLCK must run during any DAC SPI interface access (read or write).
Figure 60. DAC SPI Interface Timings
AUDCCS
Tc
Tssen
Thsen
Twl
AUDCCLK
Twh
Tssdi
Thsdi
AUDCDIN
Thsdo
Tdsdo
AUDCDOUT
Table 91. Dac SPI Interface Timings
Timing parameter
Description
Min
150 ns
Max
Tc
AUDCCLK min period
-
Twl
AUDCCLK min pulse width low
AUDCCLK min pulse width high
50 ns
50 ns
50 ns
50 ns
20 ns
20 ns
-
-
Twh
-
Tssen
Thsen
Tssdi
Thsdi
Tdsdo
Thsdo
Setup time AUDCCS falling to AUDCCLK rising
Hold time AUDCCLK falling to AUDCCS rising
Setup time AUDCDIN valid to AUDCCLK falling
Hold time AUDCCLK falling to AUDCDIN not valid
Delay time AUDCCLK rising to AUDCDOUT valid
Hold time AUDCCLK rising to AUDCDOUT not valid
-
-
-
-
20 ns
-
0 ns
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AT8xC51SND2C
DAC Register Tables
Table 92. DAC Register Address
Address
00h
Register
DAC_CTRL
DAC_LLIG
DAC_RLIG
DAC_LPMG
DAC_RPMG
DAC_LLOG
DAC_RLOG
DAC_OLC
DAC_MC
Name
Access
Reset state
00h
Dac Control
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
01h
Dac Left Line in Gain
Dac Right Line in Gain
Dac Left Master Playback Gain
Dac Right Master Playback Gain
Dac Left Line Out Gain
Dac Right Line Out Gain
Dac Output Level Control
Dac Mixer Control
05h
02h
05h
03h
08h
04h
08h
05h
00h
06h
00h
07h
22h
08h
09h
Dac Clock and Sampling Frequency
Control
09h
DAC_CSFC
Read/Write
00h
0Ah
0Ch
0Dh
10h
11h
DAC_MISC
DAC_PRECH
DAC_AUXG
DAC_RST
Dac Miscellaneous
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
00h
00h
05h
00h
00h
Dac Precharge Control
Dac Auxilary input gain Control
Dac Reset
PA_CRTL
Power Amplifier Control
DAC Gain
The DAC implements severals gain control: line-in (Table 93.), master playback (), line-
out (Table 96.).
Table 93. Line-in gain
LLIG 4:0
RLIG 4:0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Gain (dB)
20
12
9
6
3
0
-3
-6
-9
-12
-15
-18
-21
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4341D–MP3–04/05
Table 93. Line-in gain (Continued)
01101
-24
-27
01110
01111
10000
10001
-30
-33
< -60
Table 94. Master Playback Gain
LMPG 5:0
RMPG 5:0
Gain (dB)
12.0
10.5
9.0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
7.5
6.0
4.5
3.0
1.5
0.0
-1.5
-3.0
-4.5
-6.0
-7.5
-9.0
-10.5
-12.0
-13.5
-15.0
-16.5
-18.0
-19.5
-21.0
-22.5
-24.0
-25.5
86
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AT8xC51SND2C
Table 94. Master Playback Gain (Continued)
LMPG 5:0
RMPG 5:0
Gain (dB)
-27.0
011010
011011
011100
011101
011110
011111
100000
-28.5
-30.0
-31.5
-33.0
-34.5
mute
Table 95. Line-out Gain
LLOG 5:0
RLOG 5:0
Gain (dB)
0.0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
-1.5
-3.0
-4.5
-6.0
-7.5
-9.0
-10.5
-12.0
-13.5
-15.0
-16.5
-18.0
-19.5
-21.0
-22.5
-24.0
-25.5
-27.0
-28.5
-30.0
-31.5
-33.0
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4341D–MP3–04/05
Table 95. Line-out Gain (Continued)
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
-34.5
-36.0
-37.5
-39.0
-40.5
-42.0
-43.5
-45.0
-46.5
mute
Table 96. DAC Output Level Control
LOLC 2:0
ROLC 2:0
Gain (dB)
000
001
010
011
100
6
3
0
-3
-6
Digital Mixer Control
The Audio DAC features a digital mixer that allows the mixing and selection of multiple
input sources.
The mixing / multiplexing functions are described in the following table according with
the next figure:
Figure 61. Mixing / Multiplexing functions
Left channel
1
Volume
Control
Volume
Control
+
2
1
From digital
filters
To DACs
Volume
Control
Volume
Control
+
2
Right channel
Note:
Whenever the two mixer inputs are selected, a –6 dB gain is applied to the output signal.
Whenever only one input is selected, no gain is applied.
88
AT8xC51SND2C
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AT8xC51SND2C
Signal
Description
LMSMIN1
Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
LMSMIN2
RMSMIN1
RMSMIN2
Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to
disable
Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
Note:
Refer to DAC_MC register Table 110. for signal description
Master Clock and Sampling
Frequency Selection
The following table describes the different modes available for master clock and sam-
pling frequency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table
111.).
Table 97. Master Clock selection
OVRSEL
Master Clock
256 x FS
0
1
384 x FS
The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register
(refer to Table 112.) according to Table 98.
Table 98. Input Sample Size Selection
NBITS 1:0
Format
16 bits
18 bits
20 bits
00
01
10
The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer
to Table 112.) according to Table 99.
Table 99. Format Selection
DINTSEL 1:0
Format
00
01
1x
I2S Justified
MSB Justified
LSB Justified
De-emphasis and dither
enable
The circuit features a de-emphasis filter for the playback channel. To enable the de-
emphasis filtering, DEEMPEN must be set to high.
Likewise, the dither option (added in the playback channel) is enabled by setting the
DITHEN signal to High.
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4341D–MP3–04/05
Table 100. DAC Auxlilary Input Gain
AUXG 4:0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Gain (dB)
20
12
9
6
3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
<-60
10000
10001
90
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Register
Table 101. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
-
4
3
2
1
0
SDA
SCL
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Bit
Bit
Number
Mnemonic
Description
TWI Serial Data
7
6
SDA
SDA is the bidirectional Two Wire data line.
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
SCL
-
5
4
3
2
Not used.
AUDCDOUT Audio Dac SPI Data Output.
AUDCDIN Audio Dac SPI Data Input
AUDCCLK Audio Dac SPI clock
Audio Dac Chip select
1
0
AUDCCS
KIN0
Set to deselect DAC
Clear to select DAC
Keyboard Input Interrupt.
Reset Value = 1111 1111b
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4341D–MP3–04/05
Table 102. Dac Control Register Register - DAC_CTRL (00h)
7
6
5
4
3
2
1
0
ONPADRV ONAUXIN
ONDACR
ONDACL
ONLNOR
ONLNOL
ONLNIR
ONLNIL
Bit
Bit
Description
Number
Mnemonic
Differential mono PA driver
7
6
5
4
3
2
1
0
ONPADRV
ONAUXIN
ONDACR
ONDACL
ONLNOR
ONLNOL
ONLNIR
Clear to power down. Set to power up.
Differential mono auxiliary input amplifier
Clear to power down. Set to power up.
Right channel DAC
Clear to power down. Set to power up.
Left channel DAC
Clear to power down. Set to power up.
Right channel line out driver
Clear to power down. Set to power up.
Left channel line out driver
Clear to power down. Set to power up.
Right channel line in amplifier
Clear to power down. Set to power up.
Left channel line in amplifier
ONLNIL
Clear to power down. Set to power up.
Reset Value = 00000000b
Table 103. DAC Left Line In Gain Register - DAC_LLIG (01h)
7
6
5
4
3
2
1
0
-
-
-
LLIG4
LLIG3
LLIG2
LLIG1
LLIG0
Bit
Bit
Description
Number
7:5
Mnemonic
-
Not used
4:0
LLIG 4:0
Left channel line in analog gain selector
Reset Value = 00000101b
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AT8xC51SND2C
Table 104. DAC Right Line In Gain Register - DAC_RLIG (02h)
7
6
5
4
3
2
1
0
-
-
-
RLIG4
RLIG3
RLIG2
RLIG1
RLIG0
Bit
Number
7:5
4:0
Description
Bit Mnemonic
-
Not used
Right channel line in analog gain selector
RLIG 4:0
Reset Value = 0000101b
Table 105. DAC Left Master Playback Gain Register - DAC_LMPG (03h)
7
6
5
4
3
2
1
0
-
-
LMPG5
LMPG4
LMPG3
LMPG2
LMPG1
LMPG0
Bit
Bit
Description
Mnemonic
Number
7:6
5:0
-
Not used
Left channel master playback digital gain selector
LMPG 5:0
Reset Value = 00001000b
Table 106. DAC Right Master Playback Gain Register - DAC_RMPG (04h)
7
6
5
4
3
2
1
0
-
-
RMPG5
RMPG4
RMPG3
RMPG2
RMPG1
RMPG0
Bit
Bit
Description
Mnemonic
Number
7:6
5:0
-
Not used
Right channel master playback digital gain selector
RMPG 5:0
Reset Value = 00001000b
Table 107. DAC Left Line Out Gain Register - DAC_LLOG (05h)
7
6
5
4
3
2
1
0
-
-
LLOG5
LLOG4
LLOG3
LLOG2
LLOG1
LLOG0
Bit
Bit
Description
Mnemonic
Number
7:6
-
Not used
Left channel line out digital gain selector
5:0
LLOG 5:0
Reset Value = 00000000b
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4341D–MP3–04/05
Table 108. DAC Rigth Line Out Gain Register - DAC_RLOG (06h)
7
6
5
4
3
2
1
0
-
-
RLOG5
RLOG4
RLOG3
RLOG2
RLOG1
RLOG0
Bit
Number
7:6
5:0
Bit
Mnemonic
Description
-
Not used
Right channel line out digital gain selector
RLOG 5:0
Reset Value = 00000000b
Table 109. DAC Output Level Control Register - DAC_OLC (07h)
7
6
5
4
3
2
1
0
RSHORT
ROLC2
RLOC1
RLOC0
LSHORT
LOLC2
LOLC1
LOLC0
Bit
Bit
Mnemonic Description
Number
Right channel short circuit indicator (persistent; after being set, bit is not
cleared automatically even after the short circuit is eliminated; must be
cleared by reset cycle or direct register write operation)
7
RSHORT
ROLC 2:0
LSHORT
LOLC 2:0
6:4
3
Right channel output level control selector
Left channel short circuit indicator (persistent; after being set, bit is not
cleared automatically even after the short circuit is eliminated; must be
cleared by reset cycle or direct register write operation)
2:0
Left channel output level control selector
Reset Value = 00100010b
94
AT8xC51SND2C
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AT8xC51SND2C
Table 110. Dac Mixer Control Register - DAC_MC (08h)
7
6
5
4
3
2
1
0
-
-
INVR
INVL
RMSMIN2
RMSMIN1
LMSMIN2
LMSMIN1
Bit
Bit
Mnemonic Description
Number
7:6
-
Not used
Right channel mixer output invert
Set to enable. Clear to disable.
5
4
3
2
1
0
INVR
Left channel mixer output invert.
Set to enable. Clear to disable.
INVL
Right Channel Mono/Stereo Mixer Right Mixed input enable
Set to enable. Clear to disable.
RMSMIN2
RMSMIN1
LMSMIN2
LMSMIN1
Right Channel Mono/Stereo Mixer Left Mixed input enable
Set to enable. Clear to disable.
Left Channel Mono/Stereo Mixer Right Mixed input enable
Set to enable. Clear to disable.
Left Channel Mono/Stereo Mixer Left Mixed input enable
Set to enable. Clear to disable.
Reset Value = 00001001b
Table 111. DAC Mixer Control Register - DAC_CSFC (09h)
7
6
5
4
3
2
1
0
-
-
-
OVRSEL
-
-
-
-
Bit
Bit
Mnemonic Description
Number
7:5
-
Not used
Master clock selector
Clear for 256 x Fs.
Set for 384 x Fs.
4
OVRSEL
-
3:0
Not Used
Reset Value = 00000000b
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4341D–MP3–04/05
Table 112. Dac Miscellaneous Register - DAC_ MISC (0Ah)
7
6
5
4
3
2
1
0
-
-
DINTSEL1 DINTSEL0
DITHEN
DEEMPEN
NBITS1
NBITS0
Bit
Bit
Mnemonic Description
Number
7
-
-
Not used
6
5:4
3
Not used
DINTSEL1:0 I2S data format selector
DITHEN
Dither enable (Clear this bit to disable, set to enable)
2
DEEMPEN
NBITS 1:0
De-emphasis enable (clear this bit to disable, set to enable)
Data interface word length
1:0
Reset Value = 00000010b
Table 113. DAC Precharge Control Register - DAC_ PRECH (0Ch)
7
6
5
4
3
2
1
0
-
-
PRCHAR
GEPADRV
PRCHAR
GELNOL
PRCHAR
GELNIL
PRCHAR
GELNIL
PRCHAR
GE
PRCHAR
GEAUXIN
PRCHAR
GELNOR
ONMSTR
Bit
Bit
Mnemonic
Description
Number
Differential mono PA driver pre-charge.
Set to charge.
PRCHARGEPAD
RV
7
6
5
4
3
2
1
0
Differential mono auxiliary input pre-charge.
Set to charge.
PRCHARGEAUX
IN
Right channel line out pre-charge.
Set to charge.
PRCHARGELNO
R
Left channel line out pre-charge.
Set to charge.
PRCHARGELNO
L
Right channel line in pre-charge.
Set to charge.
PRCHARGELNI
R
Left channel line in pre-charge
Set to charge.
PRCHARGELNIL
PRCHARGE
ONMSTR
Master pre-charge
Set to charge.
Master power on control
Clear to power down. Set to to power up.
Reset Value = 00000000b
96
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 114. DAC Auxilary input gain Register - DAC_ AUXG (0Dh)l
7
6
5
4
3
2
1
0
-
-
-
AUXG4
AUXG3
AUXG2
AUXG1
AUXG0
Bit
Bit
Mnemonic Description
Number
7:5
-
Not used
Differential mono auxiliary input analog gain selector
4:0
AUXG 4:0
Reset Value = 0000101b
DAC Reset Register - DAC_ RST (10h)
7
6
5
4
3
2
1
0
-
-
-
-
-
RESMASK
RESFILZ
RSTZ
Bit
Bit
Description
Mnemonic
Number
7:3
-
Not Used.
2
1
0
RESMASK
RESFILZ
RSTZ
Active high reset mask of the audio codec
Active low reset of the audio codec filter
Active low reset of the audio codec
Reset Value = 00000000b
Note: Refer to Audio DAC Startup sequence.
97
4341D–MP3–04/05
Power Amplifier
High quality mono output is provided. The DAC output is connected through a buffer
stage to the input of the Audio Power Amplifier, using two coupling capacitors The
mono buffer stage also includes a mixer of the LINEL and LINER inputs as well as a dif-
ferential monaural auxiliary input (line level) which can be, for example, the output of a
voice CODEC output driver in mobile phones.
In the full power mode, the Power Amplifier is capable of driving an 8Ω Loudspeaker at
maximum power of 440mW, making it suitable as a handsfree speaker driver in Wire-
less Handset Application.
The Low Power Mode is designed to be switched from the handsfree mode to the nor-
mal earphone/speaker mode of a telephone handset.
The audio power amplifier is not internally protected against short-circuit. The user
should avoid any short-circuit on the load.
PA Features
• 0.44W on 8Ω Load
• Low Power Mode for Earphone
• Programmable Gain (-22 to +20 dB)
• Fully Differential Structure, Input and Output
Table 115. PA Gain
APAGAIN 3:0
0000
0001
0010
0011
Gain (db)
-22
20
17
14
11
8
0100
0101
0110
5
0111
2
1000
1001
1010
1011
-1
-4
-7
-10
-13
-16
-19
-22
1100
1101
1110
1111
98
AT8xC51SND2C
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AT8xC51SND2C
Table 116. PA Operating Mode
APAON
APAPRECH
Operating Mode
Stand-By
0
0
1
1
0
1
0
1
Input Capacitors Precharge
Active Mode
Forbidden State
Table 117. PA Low Power Mode
APALP
Power Mode
0
1
Low power mode
High power mode
Audio Supplies and
Start-up
In operating mode AUDVBAT (supply of the audio power amplifier) must be between 3V
and 5,5V.
AUDVDD, HSVDD and VDD must be inferior or equal to AUDVBAT.
A typical application is AUDVBAT connected to a battery and AUDVDD, HSVDD and
VDD supplied by regulators.
AUDVBAT must be present at the same time or before AUDVDD, HSVDD and VDD.
AUDRST must be active low (0) until the voltages are not etablished and reach the
proper values.
To avoid noise issues, it is recommended to use ceramic decoupling capacitors for each
supply closed to the package. The track of the supplies must be optimized to minimize
the resistance especially on AUDVBAT where all the current from the power amplifier
comes from.
Note:
Refer to the application diagram.
Audio DAC Start-up Sequence In order to minimize any audio output noise during the start-up, the following sequence
should be applied.
Example of power-on: Path DAC
to Headset Output
•
•
•
•
•
•
•
Desassert the Reset: write 07h at address 10h.
All precharge and Master on: write FFh at address 0Ch.
Line Out On: write 30h at address 00h.
Delay 500 ms.
Precharge off: write 0Ch at address 01h.
Delay 1 ms.
Line Out on, DAC On: write 3Ch at address 00h.
Example of power-off: Path DAC
to Headset Output
•
•
•
•
DAC off: write 30h at address 00h.
Master off: write 00h at address 0Ch.
Delay 1 ms.
All off: write 00h at address 00h
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4341D–MP3–04/05
Example Start I2S
•
•
•
•
•
•
•
•
Start DCLK.
RSTMASK=1.
RESFILZ=0 and RSTZ=0.
RESFILZ=1 and RSTZ=1.
RSTMASK=0.
Delay 5 ms.
ONDACL=1 and ONDACR=1.
Program all DAC settings: audio format, gains...
Example Stop I2S:
•
•
DAC off: ONDACL=0 and ONDACR=0.
Stop I2S and DLCK.
Audio PA Sequence
PA Power-On Sequence
To avoid an audible ‘click’ at start-up, the input capacitors have to be pre-charged
before the Power Amplifier.
PA Power-Off Sequence
To avoid an audible ‘click’ at power-off, the gain should be set to the minimum gain (-
22dB) before setting the Power Amplifier.
Precharge Control
The power up of the circuit can be performed independently for several blocks. The
sequence flow starts by setting to High the block specific fastcharge control bit and sub-
sequently the associated power control bit. Once the power control bit is set to High, the
fast charging starts. This action begins a user controlled fastcharge cycle. When the
fastcharge period is over, the user must reset the associated fastcharge bit and the
block is ready for use. If a power control bit is cleared a new power up sequence is
needed.
The several blocks with independent power control are identified in Table 118. The table
describes the power on control and fastcharge bits for each block.
Table 118. Precharge and Power Control
Powered up block
Power on control bit
Precharge Control Bit
PRCHARGE
(reg 12; bit 1)
Vref & Vcm generator
ONMSTR
Left line in amplifier
Right line in amplifier
Left line out amplifier
Right line out amplifier
Left D-to-A converter
Right D-to-A converter
Auxiliary input amplifier
PA Driver output
ONLNIL
ONLNIR
PRCHARGELNIL
PRCHARGELNIR
PRCHARGELNOL
PRCHARGELNOR
Not needed
ONLNOL
ONLNOR
ONDACL
ONDACR
ONAUXIN
ONPADRV
Not needed
PRCHARGEAUXIN
PRCHARGEPADRV
Note:
Note that all block can be precharged simultaneously.
100
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Register
Table 119. PA Control Register - PA_CTRL (11h)l
7
6
5
4
3
2
1
0
APAPREC
H
-
APAON
APALP
APAGAIN3
APAGAIN2
APAGAIN1 APAGAIN0
Bit
Number
Bit Mnemonic Description
7
6
-
Not used
Audio power amplifier on bit
APAON
5
APAPRECH Audio power amplifier precharge bit
APALP Audio power amplifier low power bit
APAGAIN3:0 Audio power amplifier gain
4
3:0
Reset Value = 00000000b
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4341D–MP3–04/05
Universal Serial Bus The AT8xC51SND2C implements a USB device controller supporting full speed data
transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which
can be configured in control, bulk, interrupt or isochronous modes:
•
•
Endpoint 0: 32-Byte FIFO, default control endpoint
Endpoint 1, 2: 64-Byte Ping-pong FIFO,
This allows the firmware to be developed conforming to most USB device classes, for
example:
•
•
•
USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999
USB Human Interface Device Class, Version 1.1 - April 7, 1999
USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999
USB Mass Storage Class
Bulk-Only Transport
Within the Bulk-only framework, the Control endpoint is only used to transport class-
specific and standard USB requests for device set-up and configuration. One Bulk-out
endpoint is used to transport commands and data from the host to the device. One Bulk
in endpoint is used to transport status and data from the device to the host.
The following AT8xC51SND2C configuration adheres to those requirements:
•
•
•
Endpoint 0: 32 Bytes, Control In-Out
Endpoint 1: 64 Bytes, Bulk-in
Endpoint 2: 64 Bytes, Bulk-out
USB Device Firmware
Upgrade (DFU)
The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip
Flash memory of the AT89C51SND2C. This allows installing product enhancements
and patches to devices that are already in the field. 2 different configurations and
descriptor sets are used to support DFU functions. The Run-Time configuration co-exist
with the usual functions of the device, which is USB Mass Storage for AT89C51SND2C.
It is used to initiate DFU from the normal operating mode. The DFU configuration is
used to perform the firmware update after device re-configuration and USB reset. It
excludes any other function. Only the default control pipe (endpoint 0) is used to support
DFU services in both configurations.
The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes,
which is the size of the FIFO implemented for endpoint 0.
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AT8xC51SND2C
Description
The USB device controller provides the hardware that the AT8xC51SND2C needs to
interface a USB link to a data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Sec-
tion "", page 103. This clock is used to generate a 12 MHz Full Speed bit clock from the
received USB differential data flow and to transmit data according to full speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-
ing, CRC generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and
the Dual Port RAM, but also the interface with the C51 core itself.
Figure 64 shows how to connect the AT8xC51SND2C to the USB connector. D+ and D-
pins are connected through 2 termination resistors. Value of these resistors is detailed in
the section “DC Characteristics”.
Figure 62. USB Device Controller Block Diagram
USB
CLOCK
48 MHz
12 MHz
DPLL
D+
D-
USB
Buffer
To/From
C51 Core
UFI
SIE
Figure 63. USB Connection
To Power Supply
VBUS
RUSB
RUSB
D+
D-
D+
D-
GND
VSS
Clock Controller
The USB controller clock is generated by division of the PLL clock. The division factor is
given by USBCD1:0 bits in USBCLK register (see Table 135). Figure 64 shows the USB
controller clock generator and its calculation formula. The USB controller clock fre-
quency must always be 48 MHz.
Figure 64. USB Clock Generator and Symbol
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4341D–MP3–04/05
USBCLK
PLL
CLOCK
USB
CLOCK
USBCD1:0
48 MHz USB Clock
PLLclk
USB Clock Symbol
USBclk = --------------------------------
USBCD + 1
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Serial Interface Engine (SIE)
The SIE performs the following functions:
•
•
•
•
•
•
•
NRZI data encoding and decoding.
Bit stuffing and unstuffing.
CRC generation and checking.
ACKs and NACKs automatic generation.
TOKEN type identifying.
Address checking.
Clock recovery (using DPLL).
Figure 65. SIE Block Diagram
End of Packet
Detector
SYNC Detector
PID Decoder
Start of Packet
Detector
NRZI ‘ NRZ
Bit Unstuffing
Packet Bit Counter
Address Decoder
Serial to Parallel
Converter
D+
D-
8
Data Out
Clock
Recover
SysClk
(12 MHz)
USB
CLOCK
48 MHz
CRC5 & CRC16
Generator/Check
USB Pattern Generator
Parallel to Serial Converter
Bit Stuffing
8
Data In
NRZI Converter
CRC16 Generator
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Function Interface Unit (UFI)
The Function Interface Unit provides the interface between the AT8xC51SND2C and
the SIE. It manages transactions at the packet level with minimal intervention from the
device firmware, which reads and writes the endpoint FIFOs.
Figure 67 shows typical USB IN and OUT transactions reporting the split in the hard-
ware (UFI) and software (C51) load.
Figure 66. UFI Block Diagram
USBCON
USBADDR
USBINT
USBIEN
UEPNUM
UEPCONX
Transfer
Control
FSM
Asynchronous Information
UEPSTAX
UEPRST
UEPINT
12 MHz DPLL
To/From C51 Core
UEPIEN
UEPDATX
UBYCTX
UFNUMH
UFNUML
Endpoint 2
Endpoint 1
Endpoint 0
Endpoint Control
USB side
Endpoint Control
C51 side
To/From SIE
Figure 67. USB Typical Transaction Load
OUT Transactions:
OUT DATA0 (n Bytes)
OUT
DATA1
OUT
ACK
DATA1
HOST
UFI
ACK C51 interrupt
NACK
ACK
Endpoint FIFO read (n Bytes)
C51
IN Transactions:
IN
IN
IN
HOST
NACK
Endpoint FIFO Write
DATA1
DATA1
UFI
C51 interrupt
Endpoint FIFO write
C51
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Configuration
General Configuration
•
•
USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be
correctly generated (See “Clock Controller” on page 19).
The USB controller should be then enabled by setting the EUSB bit in the USBCON
register.
Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit
in the USBADDR register. This action will allow the USB controller to answer to the
requests sent at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only
answer to the address defined by the request. The new address should be stored in
the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register
should be set to allow the USB controller to answer only to requests sent at the new
address.
•
•
Set configuration
The CONFG bit in the USBCON register should be set after a
SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should
be cleared.
Endpoint Configuration
Selection of an Endpoint
The endpoint register access is performed using the UEPNUM register. The
registers
–
–
–
–
UEPSTAX
UEPCONX
UEPDATX
UBYCTX
Theses registers correspond to the endpoint whose number is stored in the UEP-
NUM register. To select an Endpoint, the firmware has to write the endpoint number
in the UEPNUM register.
Figure 68. Endpoint Selection
SFR Registers
UEPSTA0
UEPCON0
UEPDAT0
UEPDAT2
0
1
Endpoint 0
UBYCT0
UEPSTAX
UEPCONX
UBYCTX
UEPDATX
X
UEPSTA2
UEPCON2
2
Endpoint 2
UBYCT2
UEPNUM
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•
•
Endpoint enable
Before using an endpoint, this must be enabled by setting the EPEN bit in the UEP-
CONX register.
An endpoint which is not enabled won’t answer to any USB request. The Default
Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB
standard requests.
Endpoint type configuration
All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous
mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous
mode. The configuration of an endpoint is performed by setting the field EPTYPE
with the following values:
–
–
–
–
Control:
EPTYPE = 00b
Isochronous:EPTYPE = 01b
Bulk:
EPTYPE = 10b
EPTYPE = 11b
Interrupt:
The Endpoint 0 is the Default Control Endpoint and should always be configured in
Control type.
•
•
Endpoint direction configuration
For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the
EPDIR bit of the UEPCONX register with the following values:
–
–
IN:
EPDIR = 1b
EPDIR = 0b
OUT:
For Control endpoints, the EPDIR bit has no effect.
Summary of Endpoint Configuration:
Do not forget to select the correct endpoint number in the UEPNUM register before
accessing endpoint specific registers.
Table 120. Summary of Endpoint Configuration
Endpoint Configuration
EPEN
EPDIR
Xb
EPTYPE
XXb
00b
UEPCONX
0XXX XXXb
80h
Disabled
0b
Control
1b
Xb
Bulk-in
1b
1b
10b
86h
Bulk-out
1b
0b
10b
82h
Interrupt-In
1b
1b
11b
87h
Interrupt-Out
Isochronous-In
Isochronous-Out
1b
0b
11b
83h
1b
1b
01b
85h
1b
0b
01b
81h
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•
Endpoint FIFO reset
Before using an endpoint, its FIFO should be reset. This action resets the FIFO
pointer to its original value, resets the Byte counter of the endpoint (UBYCTX regis-
ter), and resets the data toggle bit (DTGL bit in UEPCONX).
The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the
corresponding bit in the UEPRST register.
For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then
0000 0000b in the UEPRST register.
Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.
Read/Write Data FIFO
Read Data FIFO
The read access for each OUT endpoint is performed using the UEPDATX register.
After a new valid packet has been received on an Endpoint, the data are stored into the
FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware
has to store the endpoint Byte counter before any access to the endpoint FIFO. The
Byte counter is not updated when reading the FIFO.
To read data from an endpoint, select the correct endpoint number in UEPNUM and
read the UEPDATX register. This action automatically decreases the corresponding
address vector, and the next data is then available in the UEPDATX register.
Write Data FIFO
The write access for each IN endpoint is performed using the UEPDATX register.
To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEP-
NUM and write into the UEPDATX register. The corresponding address vector is
automatically increased, and another write can be carried out.
Warning 1: The Byte counter is not updated.
Warning 2: Do not write more Bytes than supported by the corresponding endpoint.
FIFO Mapping
Figure 69. Endpoint FIFO Configuration
SFR Registers
UEPSTA0
UEPSTA2
UEPCON0
UEPDAT0
UEPDAT2
0
1
2
Endpoint 0
Endpoint 2
UBYCT0
UEPSTAX
UEPCONX
UBYCTX
UEPDATX
X
UEPCON2
UBYCT2
UEPNUM
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Bulk/Interrupt
Transactions
Bulk and Interrupt transactions are managed in the same way.
Bulk/Interrupt OUT
Transactions in Standard
Mode
Figure 70. Bulk/Interrupt OUT transactions in Standard Mode
UFI
C51
HOST
OUT DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
Endpoint FIFO Read Byte 2
OUT DATA1
OUT DATA1
NAK
NAK
Endpoint FIFO Read Byte n
Clear RXOUTB0
DATA1
OUT
ACK
RXOUTB0
Endpoint FIFO Read Byte 1
An endpoint should be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data Bytes by reading the UBYCTX register. If
the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal
to 0 and no data has to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-
point. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will
answer a NAK handshake for each OUT requests.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct and the endpoint Byte counter contains the number of Bytes sent by the Host.
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Bulk/Interrupt OUT
Transactions in Ping-pong
Mode
Figure 71. Bulk/Interrupt OUT Transactions in Ping-pong Mode
HOST
UFI
C51
OUT DATA0 (n Bytes)
ACK
RXOUTB0
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
DATA1 (m Bytes)
OUT
ACK
ACK
Endpoint FIFO bank 0 - Read Byte n
Clear RXOUTB0
RXOUTB1
RXOUTB0
OUT DATA0 (p Bytes)
Endpoint FIFO bank 1 - Read Byte 1
Endpoint FIFO bank 1 - Read Byte 2
Endpoint FIFO bank 1 - Read Byte m
Clear RXOUTB1
Endpoint FIFO bank 0 - Read Byte 1
Endpoint FIFO bank 0 - Read Byte 2
Endpoint FIFO bank 0 - Read Byte p
Clear RXOUTB0
An endpoint should be first enabled and configured before being able to receive Bulk or
Interrupt packets.
When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware has to select the
corresponding endpoint, store the number of data Bytes by reading the UBYCTX regis-
ter. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is
equal to 0 and no data has to be read.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint
bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has
been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests on the bank 0 endpoint FIFO.
When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is
set by the USB controller. This triggers an interrupt if enabled. The firmware empties the
bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has
been cleared by the firmware, the USB controller will answer a NAK handshake for each
OUT requests on the bank 1 endpoint FIFO.
The RXOUTB0 and RXOUTB1 bits are, alternatively, set by the USB controller at each
new valid packet receipt.
The firmware has to clear one of these 2 bits after having read all the data FIFO to allow
a new valid packet to be stored in the corresponding bank.
A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been
released by the firmware.
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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Bulk/Interrupt IN Transactions Figure 72. Bulk/Interrupt IN Transactions in Standard Mode
in Standard Mode
HOST
UFI
C51
Endpoint FIFO Write Byte 1
Endpoint FIFO Write Byte 2
IN
NAK
Endpoint FIFO Write Byte n
Set TXRDY
IN
DATA0 (n Bytes)
TXCMPL
ACK
Clear TXCMPL
Endpoint FIFO Write Byte 1
An endpoint should be first enabled and configured before being able to send Bulk or
Interrupt packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint. To send a Zero Length Packet, the firmware
should set the TXRDY bit without writing any data into the endpoint FIFO.
Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK
handshake for each IN requests.
To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The
packet stored in the endpoint FIFO is then cleared and a new packet can be written and
sent.
When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in
the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with
new data.
The firmware should never write more Bytes than supported by the endpoint FIFO.
All USB retry mechanisms are automatically managed by the USB controller.
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Bulk/Interrupt IN Transactions Figure 73. Bulk/Interrupt IN transactions in Ping-pong mode
in Ping-pong Mode
HOST
UFI
C51
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
IN
NACK
Endpoint FIFO bank 0 - Write Byte n
Set TXRDY
IN
Endpoint FIFO bank 1 - Write Byte 1
Endpoint FIFO bank 1 - Write Byte 2
DATA0 (n Bytes)
ACK
Endpoint FIFO bank 1 - Write Byte m
Clear TXCMPL
TXCMPL
Set TXRDY
IN
Endpoint FIFO bank 0 - Write Byte 1
Endpoint FIFO bank 0 - Write Byte 2
DATA1 (m Bytes)
ACK
Endpoint FIFO bank 0 - Write Byte p
Clear TXCMPL
TXCMPL
Set TXRDY
IN
Endpoint FIFO bank 1 - Write Byte 1
DATA0 (p Bytes)
ACK
An endpoint should be first enabled and configured before being able to send Bulk or
Interrupt packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit
in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO
bank 0 with new data. The FIFO banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO
bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller will answer a NAK handshake for each IN requests concerning this
bank.
Note that in the example above, the firmware clears the Transmit Complete bit
(TXCBulk-outMPL) before setting the Transmit Ready bit (TXRDY). This is done in order
to avoid the firmware to clear at the same time the TXCMPL bit for for bank 0 and the
bank 1.
The firmware should never write more Bytes than supported by the endpoint FIFO.
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Control Transactions
Setup Stage
The DIR bit in the UEPSTAX register should be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the
RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the
RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the
Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP-
STAX register are cleared and an interrupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before
clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.
Data Stage: Control Endpoint The data stage management is similar to Bulk management.
Direction
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and
OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The
firmware has to specify the control endpoint direction for the data stage using the DIR bit
in the UEPSTAX register.
•
If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX
register before writing into the FIFO and sending the data by setting to 1 the TXRDY
bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has
been set by the hardware. The firmware should clear the TXCMPL bit before any
other transaction.
•
If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The
RXOUTB0 bit is set by hardware when a new valid packet has been received on the
endpoint. The firmware must read the data stored into the FIFO and then clear the
RXOUTB0 bit to reset the FIFO and to allow the next transaction.
To send a STALL handshake, see “STALL Handshake” on page 117.
Status Stage
The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
•
For a Control Write transaction or a No-Data Control transaction, the status stage
consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in
Standard Mode” on page 112). To send a STALL handshake, see “STALL
Handshake” on page 117.
•
For a Control Read transaction, the status stage consists of a OUT Zero Length
Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 110).
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Isochronous Transactions
Isochronous OUT
Transactions in Standard
Mode
An endpoint should be first enabled and configured before being able to receive Isochro-
nous packets.
When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmware has to select the corre
Bulk-outsponding endpoint, store the number of data Bytes by reading the UBYCTX
register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register
value is equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the
endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent
by the Host at each OUT transaction will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will
store only the remaining Bytes into the FIFO.
If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous OUT
Transactions in Ping-pong
Mode
An endpoint should be first enabled and configured before being able to receive Isochro-
nous packets.
When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data Bytes by reading the UBYCTX register. If
the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal
to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO Bytes have been read, the firmware should clear the
RXOUB0 bit to allow the USB controller to store the next OUT packet data into the end-
point FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0
bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint
FIFO will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the
USB controller will store only the remaining Bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank
1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been
cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be
lost.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new packet receipt.
The firmware has to clear one of these 2 bits after having read all the data FIFO to allow
a new packet to be stored in the corresponding bank.
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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous IN Transactions
in Standard Mode
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by
the USB controller. This triggers a USB interrupt if enabled. The firmware should clear
the TXCMPL bit before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO
Isochronous IN Transactions
in Ping-pong Mode
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit
in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are
then automatically switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller won’t send anything at each IN requests concerning this bank.
The firmware should never write more Bytes than supported by the endpoint FIFO.
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Miscellaneous
USB Reset
The EORINT bit in the USBINT register is set by hardware when a End Of Reset has
been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con-
troller is still enabled, but all the USB registers are reset by hardware. The firmware
should clear the EORINT bit to allow the next USB reset detection.
STALL Handshake
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL
handshake at the next request of the Host on the endpoint selected with the UEPNUM
register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first
resseted to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been
sent. This triggers an interrupt if enabled.
The firmware should clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is
received on a CONTROL type endpoint.
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should
reset this endpoint using the UEPRST resgister in order to reset the data toggle
management.
Start of Frame Detection
Frame Number
The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of
Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT
bit to allow the next Start of Frame detection.
When receiving a Start Of Frame, the frame number is automatically stored in the
UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of
the last Start Of Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The
UFNUML and UFNUMH registers are automatically updated when receiving a new Start
of Frame.
Data Toggle Bit
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted
by the USB controller and cleared by hardware when a DATA1 packet is received and
accepted by the USB controller. This bit is reset when the firmware resets the endpoint
FIFO using the UEPRST register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling
is then used as for Bulk endpoints until the end of the Data stage (for a control write
transfer). The Status stage completes the data transfer with a DATA1 (for a control read
transfer).
For Isochronous endpoints, the device firmware should ignore the data-toggle.
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Suspend/Resume Management
Suspend
The Suspend state can be detected by the USB controller if all the clocks are enabled
and if the USB controller is enabled. The bit SPINT is set by hardware when an idle
state is detected for more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode,
stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is
still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to
avoid a new suspend detection 3ms later, the firmware has to disable the USB clock
input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically
exits of idle mode when a wake-up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-
PCLK bit in the USBCON register.
2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.
Resume
When the USB controller is in Suspend state, the Resume detection is active even if all
the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit
is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter-
rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and
the interrupt function is then executed. The firmware will first enable the 48 MHz gener-
ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.
The firmware has to clear the SPINT bit in the USBINT register before any other USB
operation in order to wake up the USB controller from its Suspend mode.
The USB controller is then re-activated.
Figure 74. Example of a Suspend/Resume Management
USB Controller Init
SPINT
Detection of a SUSPEND State
Clear SPINT
Set SUSPCLK
Disable PLL
microcontroller in Power-down
WUPCPU
Detection of a RESUME State
Enable PLL
Clear SUSPCLK
Clear WUPCPU Bit
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Upstream Resume
A USB device can be allowed by the Host to send an upstream resume for Remote
Wake-up purpose.
When the USB controller receives the SET_FEATURE request:
DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the
USBCON register to enable this functionality. RMWUPE value should be 0 in the other
cases.
If the device is in SUSPEND mode, the USB controller can send an upstream resume by
clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRM-
WUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the
USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the
USB bus was in Suspend state for at least 5ms. When the upstream resume is com-
pleted, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the
SDRMWUP bit.
Figure 75. Example of REMOTE WAKEUP Management
USB Controller Init
SET_FEATURE: DEVICE_REMOTE_WAKEUP
Set RMWUPE
SPINT
Detection of a SUSPEND state
Suspend Management
need USB resume
enable clocks
Clear SPINT
Set SDMWUP
UPRSM = 1
UPRSM
upstream RESUME sent
Clear SDRMWUP
119
4341D–MP3–04/05
USB Interrupt System
Interrupt System Priorities
Figure 76. USB Interrupt Control System
00
01
10
11
D+
USB
Controller
D-
EUSB
IE1.6
EA
IE0.7
IPH/L
Interrupt Enable
Priority Enable
Lowest Priority Interrupts
Table 1. Priority Levels
IPHUSB
IPLUSB
USB Priority Level
0
0
1
1
0
1
0
1
0..................Lowest
1
2
3..................Highest
USB Interrupt Control System As shown in Figure 77, many events can produce a USB interrupt:
•
•
•
TXCMPL: Transmitted In Data (Table 127 on page 126). This bit is set by hardware
when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (Table 127 on page 126). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 127 on
page 126). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
•
•
RXSETUP: Received Setup (Table 127 on page 126). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 127 on
page 126). This bit is set by hardware when a STALL handshake has been sent as
requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
•
•
•
SOFINT: Start of Frame Interrupt (Table 123 on page 123). This bit is set by
hardware when a USB start of frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (Table 123 on page 123). This bit is set by
hardware when a USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (Table 123 on page 123). This bit is set by hardware
when a USB suspend is detected on the USB bus.
120
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AT8xC51SND2C
Figure 77. USB Interrupt Control Block Diagram
Endpoint X (X = 0..2)
TXCMP
UEPSTAX.0
RXOUTB0
UEPSTAX.1
RXOUTB1
UEPSTAX.6
EPXINT
UEPINT.X
RXSETUP
UEPSTAX.2
EPXIE
UEPIEN.X
STLCRC
UEPSTAX.3
NAKOUT
UEPCONX.5
NAKIN
UEPCONX.4
NAKIEN
UEPCONX.6
WUPCPU
USBINT.5
EUSB
IE1.6
EWUPCPU
USBIEN.5
EORINT
USBINT.4
EEORINT
USBIEN.4
SOFINT
USBINT.3
ESOFINT
USBIEN.3
SPINT
USBINT.0
ESPINT
USBIEN.0
121
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Registers
Table 121. USBCON Register
USBCON (S:BCh) – USB Global Control Register
7
6
5
4
-
3
2
1
0
USBE
SUSPCLK SDRMWUP
UPRSM
RMWUPE
CONFG
FADDEN
Bit
Bit
Number
Mnemonic Description
USB Enable Bit
Set this bit to enable the USB controller.
Clear this bit to disable and reset the USB controller, to disable the USB
transceiver an to disable the USB controllor clock inputs.
7
6
USBE
Suspend USB Clock Bit
SUSPCLK Set to disable the 48 MHz clock input (Resume Detection is still active).
Clear to enable the 48 MHz clock input.
Send Remote Wake-Up Bit
Set to force an external interrupt on the USB controller for Remote Wake UP
purpose.
5
SDRMWUP An upstream resume is send only if the bit RMWUPE is set, all USB clocks are
enabled AND the USB bus was in SUSPEND state for at least 5 ms. See
UPRSM below.
Cleared by software.
Reserved
4
3
-
The value read from this bit is always 0. Do not set this bit.
Upstream Resume Bit (read only)
Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.
Cleared by hardware after the upstream resume has been sent.
UPRSM
Remote Wake-Up Enable Bit
Set to enabled request an upstream resume signaling to the host.
Clear after the upstream resume has been indicated by RSMINPR.
2
1
RMWUPE
Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP
feature for the device.
Configuration Bit
This bit should be set by the device firmware after a SET_CONFIGURATION
request with a non-zero value has been correctly processed.
It should be cleared by the device firmware when a SET_CONFIGURATION
request with a zero value is received. It is cleared by hardware on hardware
reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full
Speed bit times: typically 2.7 µs).
CONFG
Function Address Enable Bit
This bit should be set by the device firmware after a successful status phase of a
SET_ADDRESS transaction.
It should not be cleared afterwards by the device firmware. It is cleared by
hardware on hardware reset or when an USB reset is received (see above).
When this bit is cleared, the default function address is used (0).
0
FADDEN
Reset Value = 0000 0000b
122
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Table 122. USBADDR Register
USBADDR (S:C6h) – USB Address Register
7
6
5
4
3
2
1
0
FEN
UADD6
UADD5
UADD4
UADD3
UADD2
UADD1
UADD0
Bit
Bit
Number
Mnemonic Description
Function Enable Bit
Set to enable the function. The device firmware should set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
7
FEN
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It should be written with the value set by a SET_ADDRESS request received by
the device firmware.
6 - 0
UADD6:0
Reset Value = 0000 0000b
Table 123. USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
7
-
6
-
5
4
3
2
-
1
-
0
WUPCPU
EORINT
SOFINT
SPINT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
-
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-
WUPCPU activated by a non-idle signal from USB line (not by an upstream resume). This
triggers a USB interrupt when EWUPCPU is set in the USBIEN.
5
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller.
This triggers a USB interrupt when EEORINT is set in USBIEN.
4
EORINT
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when an USB Start of Frame packet (SOF) has been properly
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
3
SOFINT
Cleared by software.
Reserved
2 - 1
-
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J
0
SPINT
state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in
USBIEN.
Cleared by software.
Reset Value = 0000 0000b
123
4341D–MP3–04/05
Table 124. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
7
-
6
-
5
4
3
2
-
1
-
0
EWUPCPU EEORINT
ESOFINT
ESPINT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The value read from these bits is always 0. Do not set these bits.
Wake Up CPU Interrupt Enable Bit
EWUPCPU Set to enable the Wake Up CPU interrupt.
Clear to disable the Wake Up CPU interrupt.
End Of Reset Interrupt Enable Bit
4
EEOFINT Set to enable the End Of Reset interrupt. This bit is set after reset.
Clear to disable End Of Reset interrupt.
Start Of Frame Interrupt Enable Bit
ESOFINT Set to enable the SOF interrupt.
Clear to disable the SOF interrupt.
3
2 - 1
0
Reserved
-
The value read from these bits is always 0. Do not set these bits.
Suspend Interrupt Enable Bit
ESPINT
Set to enable Suspend interrupt.
Clear to disable Suspend interrupt.
Reset Value = 0001 0000b
Table 125. UEPNUM Register
UEPNUM (S:C7h) – USB Endpoint Number
7
-
6
-
5
-
4
-
3
-
2
-
1
0
EPNUM1
EPNUM0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The value read from these bits is always 0. Do not set these bits.
Endpoint Number Bits
EPNUM1:0 Set this field with the number of the endpoint which should be accessed when
reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.
Reset Value = 0000 0000b
124
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AT8xC51SND2C
Table 126. UEPCONX Register
UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
EPEN
NAKIEN
NAKOUT
NAKIN
DTGL
EPDIR
EPTYPE1
EPTYPE0
Bit
Bit
Number
Mnemonic Description
Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0
should always be enabled after a hardware or USB bus reset and participate in
the device configuration.
7
6
5
EPEN
Clear to disable the endpoint according to the device configuration.
NAK Interrupt enable
Set this bit to enable NAK IN or NAK OUT interrupt.
Clear this bit to disable NAK IN or NAK OUT Interrupt.
NAKIEN
NAK OUT received
This bit is set by hardware when an NAK handshake has been sent in response
NAKOUT of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is
set.
This bit should be cleared by software.
NAK IN received
This bit is set by hardware when an NAK handshake has been sent in response
of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set.
This bit should be cleared by software.
4
3
2
NAKIN
Data Toggle Status Bit (Read-only)
Set by hardware when a DATA1 packet is received.
Cleared by hardware when a DATA0 packet is received.
DTGL
Endpoint Direction Bit
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
EPDIR
Endpoint Type Bits
Set this field according to the endpoint configuration (Endpoint 0 should always
be configured as Control):
1-0
EPTYPE1:0 00 Control endpoint
01 Isochronous endpoint
10 Bulk endpoint
11 Interrupt endpoint
Reset Value = 1000 0000b
125
4341D–MP3–04/05
Table 127. UEPSTAX Register
UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
DIR
RXOUTB1 STALLRQ
TXRDY
STLCRC
RXSETUP RXOUTB0
TXCMP
Bit
Bit
Number
Mnemonic Description
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
7
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is
changed. This also determines the status phase (IN for a control write and OUT
for a control read). This bit should be cleared for status stage of a Control Out
transaction.
Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode)
This bit is set by hardware after a new packet has been stored in the endpoint
FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is
triggered if enabled and all the following OUT packets to the endpoint bank 1 are
rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous
Endpoints.
6
RXOUTB1
This bit should be cleared by the device firmware after reading the OUT data
from the endpoint FIFO.
126
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AT8xC51SND2C
Bit
Bit
Number
Mnemonic Description
Stall Handshake Request Bit
Set to send a STALL answer to the host for the next handshake. Clear otherwise.
5
STALLRQ
TX Packet Ready Control Bit
Set after a packet has been written into the endpoint FIFO for IN data transfers.
Data should be written into the endpoint FIFO only after this bit has been cleared.
Set this bit without writing data to the endpoint FIFO to send a Zero Length
Packet, which is generally recommended and may be required to terminate a
transfer when the length of the last data packet is equal to MaxPacketSize (e.g.
for control read transfers).
4
TXRDY
Cleared by hardware, as soon as the packet has been sent for Isochronous
endpoints, or after the host has acknowledged the packet for Control, Bulk and
Interrupt endpoints.
Stall Sent Interrupt Flag/CRC Error Interrupt Flag
For Control, Bulk and Interrupt Endpoints:
Set by hardware after a STALL handshake has been sent as requested by
STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN.
3
2
1
STLCRC Cleared by hardware when a SETUP packet is received (see RXSETUP).
For Isochronous Endpoints:
Set by hardware if the last data received is corrupted (CRC error on data). Then,
the endpoint interrupt is triggered if enabled in UEPIEN.
Cleared by hardware when a non corrupted data is received.
Received SETUP Interrupt Flag
Set by hardware when a valid SETUP packet has been received from the host.
RXSETUP Then, all the other bits of the register are cleared by hardware and the endpoint
interrupt is triggered if enabled in UEPIEN.
Clear by software after reading the SETUP data from the endpoint FIFO.
Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)
This bit is set by hardware after a new packet has been stored in the endpoint
FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled and all the
following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit
RXOUTB0 has been cleared, excepted for Isochronous Endpoints. However, for control
endpoints, an early SETUP transaction may overwrite the content of the endpoint
FIFO, even if its Data packet is received while this bit is set.
This bit should be cleared by the device firmware after reading the OUT data
from the endpoint FIFO.
Transmitted IN Data Complete Interrupt Flag
Set by hardware after an IN packet has been transmitted for Isochronous
endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk
and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in
0
TXCMP
UEPIEN.
Clear by software before setting again TXRDY.
Reset Value = 0000 0000b
127
4341D–MP3–04/05
Table 128. UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2RST
EP1RST
EP0RST
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
2
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 FIFO Reset
EP2RST Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 1 FIFO Reset
1
0
EP1RST Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
EP0RST Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reset Value = 0000 0000b
Table 129. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2INTE
EP1INTE
EP0INTE
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
2
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Enable Bit
EP2INTE Set to enable the interrupts for endpoint 2.
Clear this bit to disable the interrupts for endpoint 2.
Endpoint 1 Interrupt Enable Bit
1
0
EP1INTE Set to enable the interrupts for the endpoint 1.
Clear to disable the interrupts for the endpoint 1.
Endpoint 0 Interrupt Enable Bit
EP0INTE Set to enable the interrupts for the endpoint 0.
Clear to disable the interrupts for the endpoint 0.
Reset Value = 0000 0000b
128
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AT8xC51SND2C
Table 130. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
7
-
6
-
5
-
4
-
3
-
2
1
0
EP2INT
EP1INT
EP0INT
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
-
The value read from these bits is always 0. Do not set these bits.
Endpoint 2 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 2. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
2
EP2INT
EP1INT
EP0INT
A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 1 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 1. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
1
A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Endpoint 0 Interrupt Flag
This bit is set by hardware when an endpoint interrupt source has been detected
on the endpoint 0. The endpoint interrupt sources are in the UEPSTAX register
and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.
0
A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.
This bit is cleared by hardware when all the endpoint interrupt sources are
cleared.
Reset Value = 0000 0000b
Table 131. UEPDATX Register
UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)
7
6
5
4
3
2
1
0
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
Bit
Bit
Number
Mnemonic Description
Endpoint X FIFO Data
7 - 0
FDAT7:0 Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the
Endpoint X (see EPNUM).
Reset Value = XXh
129
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Table 132. UBYCTX Register
UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)
7
-
6
5
4
3
2
1
0
BYCT6
BYCT5
BYCT4
BYCT3
BYCT2
BYCT1
BYCT0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bits is always 0. Do not set this bit.
Byte Count
6 - 0
BYCT7:0 Byte count of a received data packet. This Byte count is equal to the number of
data Bytes received after the Data PID.
Reset Value = 0000 0000b
Table 133. UFNUML Register
UFNUML (S:BAh, Read-only) – USB Frame Number Low Register
7
6
5
4
3
2
1
0
FNUM7
FNUM6
FNUM5
FNUM4
FNUM3
FNUM2
FNUM1
FNUM0
Bit
Bit
Number
Mnemonic Description
Frame Number
Lower 8 bits of the 11-bit Frame Number.
7 - 0
FNUM7:0
Reset Value = 00h
130
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AT8xC51SND2C
Table 134. UFNUMH Register
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
7
-
6
-
5
4
3
-
2
1
0
CRCOK
CRCERR
FNUM10
FNUM9
FNUM8
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 3
-
The value read from these bits is always 0. Do not set these bits.
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
5
CRCOK
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is
received.
4
CRCERR
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
Reserved
3
-
The value read from this bits is always 0. Do not set this bit.
Frame Number
2-0
FNUM10:8 Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF
packet. FNUM does not change if a corrupted SOF is received.
Reset Value = 00h
Table 135. USBCLK Register
USBCLK (S:EAh) – USB Clock Divider Register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
USBCD1
USBCD0
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 2
1 - 0
-
The value read from these bits is always 0. Do not set these bits.
USB Controller Clock Divider
2-bit divider for USB controller clock generation.
USBCD1:0
Reset Value = 0000 0000b
131
4341D–MP3–04/05
IDE/ATAPI Interface
The AT8xC51SND2C provides an IDE/ATAPI interface allowing connection of devices
such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-
bit data transfer (read or write) between the AT8xC51SND2C and the IDE device.
Description
The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 30,
page 29). As soon as this bit is set, all MOVX instructions read or write are done in a 16-
bit mode compare to the standard 8-bit mode. P0 carries the low order multiplexed
address and data bus (A7:0, D7:0) while P2 carries the high order multiplexed address
and data bus (A15:8, D15:8). When writing data in IDE mode, the ACC contains D7:0
data (as in 8-bit mode) while DAT16H register (see Table 137) contains D15:8 data.
When reading data in IDE mode, D7:0 data is returned in ACC while D15:8 data is
returned in DAT16H.
Figure 78 shows the IDE read bus cycle while Figure 79 shows the IDE write bus cycle.
For simplicity, these figures depict the bus cycle waveforms in idealized form and do not
provide precise timing information. For IDE bus cycle timing parameters refer to the
Section “AC Characteristics”.
IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in
standard mode or 6 oscillator clock periods in X2 mode. For further information on X2
mode, refer to the Section “X2 Feature”, page 12.
Slow IDE devices can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals
from 3 to 15 CPU clock periods.
Figure 78. IDE Read Waveforms
CPU Clock
ALE
RD(1)
DPL or Ri
D7:0
P0
P2
P2
DPH or P2(2),(3)
D15:8
P2
Notes: 1. RD signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
132
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Figure 79. IDE Write Waveforms
CPU Clock
ALE
WR(1)
DPL or Ri
D7:0
P0
P2
P2
DPH or P2(2),(3)
D15:8
P2
Notes: 1. WR signal may be stretched using M0 bit in AUXR register.
2. When executing MOVX @Ri instruction, P2 outputs SFR content.
3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),
P2 outputs SFR content instead of DPH.
IDE Device Connection
Figure 80 and Figure 81 show 2 examples on how to interface up to 2 IDE devices to the
AT8xC51SND2C. In both examples P0 carries IDE low order data bits D7:0, P2 carries
IDE high order data bits D15:8, while RD and WR signals are respectively connected to
the IDE nIOR and nIOW signals. Other IDE control signals are generated by the exter-
nal address latch outputs in the first example while they are generated by some port
I/Os in the second one. Using an external latch will achieve higher transfer rate.
Figure 80. IDE Device Connection Example 1
AT8xC51SND2C
P2
IDE Device 0
IDE Device 1
D15-8
D7:0
A2:0
D15-8
D7:0
A2:0
P0
Latch
nCS1:0
nCS1:0
ALE
Px.y
nRESET
nRESET
RD
nIOR
nIOW
nIOR
nIOW
WR
Figure 81. IDE Device Connection Example 2
AT8xC51SND2C
IDE Device 0
IDE Device 1
P2/A15:8
P0/AD7:0
D15-8
D7:0
D15-8
D7:0
P4.2:0
P4.4:3
P4.5
RD
A2:0
A2:0
nCS1:0
nRESET
nIOR
nCS1:0
nRESET
nIOR
WR
nIOW
nIOW
133
4341D–MP3–04/05
Table 136. External Data Memory Interface Signals
Signal
Name
Alternate
Function
Type Description
Address Lines
A15:8
I/O Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
-
Address/Data Lines
Multiplexed lower address and data lines for the IDE interface.
AD7:0
ALE
I/O
Address Latch Enable
O
ALE signals indicates that valid address information is available on lines
AD7:0.
Read
RD
O
O
P3.7
P3.6
Read signal output to external data memory.
Write
WR
Write signal output to external memory.
Registers
Table 137. DAT16H Register
DAT16H (S:F9h) – Data 16 High Order Byte
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
Bit
Bit
Number
Mnemonic Description
Data 16 High Order Byte
When EXT16 bit is set, DAT16H is set by software with the high order data Byte
prior any MOVX write instruction.
7 - 0
D15:8
When EXT16 bit is set, DAT16H contains the high order data Byte after any
MOVX read instruction.
Reset Value =XXXX XXXXb
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AT8xC51SND2C
MultiMedia Card
Controller
The AT8xC51SND2C implements a MultiMedia Card (MMC) controller. The MMC is
used to store MP3 encoded audio files in removable Flash memory cards that can be
easily plugged or removed from the application.
Card Concept
The basic MultiMedia Card concept is based on transferring data via a minimum number
of signals.
Card Signals
The communication signals are:
•
CLK: with each cycle of this signal a one bit transfer on the command and data lines
is done. The frequency may vary from zero to the maximum clock frequency.
•
CMD: is a bi-directional command channel used for card initialization and data
transfer commands. The CMD signal has 2 operation modes: open-drain for
initialization mode and push-pull for fast command transfer. Commands are sent
from the MultiMedia Card bus master to the card and responses from the cards to
the host.
•
DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode.
Only one card or the host is driving this signal at a time.
Card Registers
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR.
These can be accessed only by the corresponding commands.
The 32-bit Operation Conditions Register (OCR) stores the VDD voltage profile of the
card. The register is optional and can be read only.
The 128-bit wide CID register carries the card identification information (Card ID) used
during the card identification procedure.
The 128-bit wide Card-Specific Data register (CSD) provides information on how to
access the card contents. The CSD defines the data format, error correction type, maxi-
mum data access time, data transfer speed, and whether the DSR register can be used.
The 16-bit Relative Card Address register (RCA) carries the card address assigned by
the host during the card identification. This address is used for the addressed host-card
communication after the card identification procedure.
The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus per-
formance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of cards).
Bus Concept
The MultiMedia Card bus is designed to connect either solid-state mass-storage mem-
ory or I/O-devices in a card format to multimedia applications. The bus implementation
allows the coverage of application fields from low-cost systems to systems with a fast
data transfer rate. It is a single master bus with a variable number of slaves. The Multi-
Media Card bus master is the bus controller and each slave is either a single mass
storage card (with possibly different technologies such as ROM, OTP, Flash etc.) or an
I/O-card with its own controlling unit (on card) to perform the data transfer.
The MultiMedia Card bus also includes power connections to supply the cards.
The bus communication uses a special protocol (MultiMedia Card bus protocol) which is
applicable for all devices. Therefore, the payload data transfer between the host and the
cards can be bi-directional.
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Bus Lines
The MultiMedia Card bus architecture requires all cards to be connected to the same set
of lines. No card has an individual connection to the host or other devices, which
reduces the connection costs of the MultiMedia Card system.
The bus lines can be divided into three groups:
•
•
•
Power supply: VSS1 and VSS2, VDD – used to supply the cards.
Data transfer: MCMD, MDAT – used for bi-directional communication.
Clock: MCLK – used to synchronize data transfer across the bus.
Bus Protocol
After a power-on reset, the host must initialize the cards by a special message-based
MultiMedia Card bus protocol. Each message is represented by one of the following
tokens:
•
Command: a command is a token which starts an operation. A command is
transferred serially from the host to the card on the MCMD line.
•
Response: a response is a token which is sent from an addressed card (or all
connected cards) to the host as an answer to a previously received command. It is
transferred serially on the MCMD line.
•
Data: data can be transferred from the card to the host or vice-versa. Data is
transferred serially on the MDAT line.
Card addressing is implemented using a session address assigned during the initializa-
tion phase, by the bus controller to all currently connected cards. Individual cards are
identified by their CID number. This method requires that every card will have an unique
CID number. To ensure uniqueness of CIDs the CID register contains 24 bits (MID and
OID fields) which are defined by the MMCA. Every card manufacturers is required to
apply for an unique MID (and optionally OID) number.
MultiMedia Card bus data transfers are composed of these tokens. One data transfer is
a bus operation. There are different types of operations. Addressed operations always
contain a command and a response token. In addition, some operations have a data
token, the others transfer their information directly within the command or response
structure. In this case no data token is present in an operation. The bits on the MDAT
and the MCMD lines are transferred synchronous to the host clock.
2 types of data transfer commands are defined:
•
Sequential commands: These commands initiate a continuous data stream, they
are terminated only when a stop command follows on the MCMD line. This mode
reduces the command overhead to an absolute minimum.
•
Block-oriented commands: These commands send a data block succeeded by CRC
bits. Both read and write operations allow either single or multiple block
transmission. A multiple block transmission is terminated when a stop command
follows on the MCMD line similarly to the stream read.
Figure 82 through Figure 86 show the different types of operations, on these figures,
grayed tokens are from host to card(s) while white tokens are from card(s) to host.
Figure 82. Sequential Read Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Stream
Data Transfer Operation
Data Stop Operation
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AT8xC51SND2C
Figure 83. (Multiple) Block Read Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Stop Operation
Data Block CRC Data Block CRC Data Block CRC
Block Read Operation
Multiple Block Read Operation
As shown in Figure 84 and Figure 85 the data write operation uses a simple busy signal-
ling of the write operation duration on the data line (MDAT).
Figure 84. Sequential Write Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Stream
Busy
Data Transfer Operation
Data Stop Operation
Figure 85. Multiple Block Write Operation
Stop Command
MCMD
MDAT
Command Response
Command Response
Data Block CRC Status Busy
Data Block CRC Status Busy
Data Stop Operation
Block Write Operation
Multiple Block Write Operation
Figure 86. No Response and No Data Operation
MCMD
MDAT
Command
Command Response
No Response Operation
No Data Operation
Command Token Format
As shown in Figure 87, commands have a fixed code length of 48 bits. Each command
token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit:
a high level on MCMD line. The command content is preceded by a Transmission bit: a
high level on MCMD line for a command token (host to card) and succeeded by a 7 - bit
CRC so that transmission errors can be detected and the operation may be repeated.
Command content contains the command index and address information or parameters.
Figure 87. Command Token Format
0
1
Content
CRC
1
Total Length = 48 bits
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Table 138. Command Token Format
Bit Position
Width (Bits)
Value
47
1
46
1
45:40
39:8
32
-
7:1
7
0
6
-
1
‘0’
‘1’
-
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Response Token Format
There are five types of response tokens (R1 to R5). As shown in Figure 88, responses
have a code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a
low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The
command content is preceded by a Transmission bit: a low level on MCMD line for a
response token (card to host) and succeeded (R1,R2,R4,R5) or not (R3) by a 7 - bit
CRC.
Response content contains mirrored command and status information (R1 response),
CID register or CSD register (R2 response), OCR register (R3 response), or RCA regis-
ter (R4 and R5 response).
Figure 88. Response Token Format
R1, R4, R5
0
0
0
0
0
0
Content
CRC
1
1
Total Length = 48 bits
R3
R2
Content
Total Length = 48 bits
Content = CID or CSD
Total Length = 136 bits
CRC
1
Table 139. R1 Response Format (Normal Response)
Bit Position
Width (bits)
Value
47
1
46
1
45:40
39:8
32
-
7:1
7
0
6
-
1
‘0’
‘0’
-
‘1’
Transmission
bit
Command
Index
Start bit
Card Status
CRC7
End bit
Description
Table 140. R2 Response Format (CID and CSD registers)
Bit Position
Width (bits)
Value
135
1
134
1
[133:128]
6
[127:1]
0
32
-
1
‘0’
‘0’
‘111111’
‘1’
Transmission
bit
Start bit
Reserved
Argument
End bit
Description
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AT8xC51SND2C
Table 141. R3 Response Format (OCR Register)
Bit Position
Width (bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
7
0
32
-
1
‘0’
‘0’
‘111111’
‘1111111’
‘1’
Transmission
bit
OCR
register
Start bit
Reserved
Reserved
End bit
Description
Table 142. R4 Response Format (Fast I/O)
Bit Position
Width (bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
0
32
-
7
-
1
‘0’
‘0’
‘100111’
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Table 143. R5 Response Format
Bit Position
Width (bits)
Value
47
1
46
1
[45:40]
6
[39:8]
[7:1]
0
32
-
7
-
1
‘0’
‘0’
‘101000’
‘1’
Transmission
bit
Command
Index
Start bit
Argument
CRC7
End bit
Description
Data Packet Format
There are 2 types of data packets: stream and block. As shown in Figure 89, stream
data packets have an indeterminate length while block packets have a fixed length
depending on the block length. Each data packet is preceded by a Start bit: a low level
on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact
that there is no predefined end in stream packets, CRC protection is not included in this
case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial.
Figure 89. Data Token Format
Sequential Data
0
0
Content
1
1
Block Data
Content
CRC
Block Length
Clock Control
The MMC bus clock signal can be used by the host to turn the cards into energy saving
mode or to control the data flow (to avoid under-run or over-run conditions) on the bus.
The host is allowed to lower the clock frequency or shut it down.
There are a few restrictions the host must follow:
•
The bus frequency can be changed at any time (under the restrictions of maximum
data transfer frequency, defined by the cards, and the identification frequency
defined by the specification document).
•
It is an obvious requirement that the clock must be running for the card to output
data or response tokens. After the last MultiMedia Card bus transaction, the host is
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required, to provide 8 (eight) clock cycles for the card to complete the operation
before shutting down the clock. Following is a list of the various bus transactions:
•
•
•
•
•
A command with no response. 8 clocks after the host command End bit.
A command with response. 8 clocks after the card command End bit.
A read data transaction. 8 clocks after the End bit of the last data block.
A write data transaction. 8 clocks after the CRC status token.
The host is allowed to shut down the clock of a “busy” card. The card will complete
the programming operation regardless of the host clock. However, the host must
provide a clock edge for the card to turn off its busy signal. Without a clock edge the
card (unless previously disconnected by a deselect command-CMD7) will force the
MDAT line down, forever.
Description
The MMC controller interfaces to the C51 core through the following eight special func-
tion registers:
MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 145 to
Table 153); MMSTA, the MMC status register (see Table 148); MMINT, the MMC inter-
rupt register (see Table 149); MMMSK, the MMC interrupt mask register (see
Table 150); MMCMD, the MMC command register (see Table 151); MMDAT, the MMC
data register (see Table 152); and MMCLK, the MMC clock register (see Table 153).
As shown in Figure 90, the MMC controller is divided in four blocks: the clock generator
that handles the MCLK (formally the MMC CLK) output to the card, the command line
controller that handles the MCMD (formally the MMC CMD) line traffic to or from the
card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic
to or from the card, and the interrupt controller that handles the MMC controller interrupt
sources. These blocks are detailed in the following sections.
Figure 90. MMC Controller Block Diagram
MCLK
OSC
CLOCK
Clock
Generator
Command Line
Controller
MCMD
MMC
Interrupt
Request
Interrupt
Controller
Data Line
Controller
MDAT
Internal
8
Bus
Clock Generator
The MMC clock is generated by division of the oscillator clock (FOSC) issued from the
Clock Controller block as detailed in Section "Oscillator", page 12. The division factor is
given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock.
Figure 91 shows the MMC clock generator and its output clock calculation formula.
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AT8xC51SND2C
Figure 91. MMC Clock Generator and Symbol
OSCclk
MMCD + 1
OSC
CLOCK
MMCclk = ----------------------------
Controller Clock
MMC Clock
MMCLK
MMC
CLOCK
MMCEN
MMCON2.7
MMCD7:0
MMC Clock Symbol
As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system
clock. The MMC command and data clock is generated on MCLK output and sent to the
command line and data line controllers. Figure 92 shows the MMC controller configura-
tion flow.
As exposed in Section “Clock Control”, page 139, MMCD7:0 bits can be used to dynam-
ically increase or reduce the MMC clock.
Figure 92. Configuration Flow
MMC Controller
Configuration
Configure MMC Clock
MMCLK = XXh
MMCEN = 1
FLOWC = 0
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Command Line
Controller
As shown in Figure 93, the command line controller is divided in 2 channels: the com-
mand transmitter channel that handles the command transmission to the card through
the MCMD line and the command receiver channel that handles the response reception
from the card through the MCMD line. These channels are detailed in the following
sections.
Figure 93. Command Line Controller Block Diagram
Data Converter
// -> Serial
CRC7
Generator
TX Pointer
5-Byte FIFO
MMCMD
Write
CTPTR
MMCON0.4
TX COMMAND Line
Finished State Machine
MMINT.5
EOCI
CFLCK
MMSTA.0
CMDEN
MMCON1.0
MCMD
Command Transmitter
MMSTA.2
MMSTA.1
CRC7S RESPFS
Data Converter
Serial -> //
CRC7 and Format
Checker
RX Pointer
17 - Byte FIFO
MMCMD
Read
CRPTR
MMCON0.5
RX COMMAND Line
Finished State Machine
MMINT.6
EORI
RESPEN RFMT CRCDIS
MMCON1.1 MMCON0.1 MMCON0.0
Command Receiver
Command Transmitter
For sending a command to the card, user must load the command index (1 Byte) and
argument (4 Bytes) in the command transmit FIFO using the MMCMD register. Before
starting transmission by setting and clearing the CMDEN bit in MMCON1 register, user
must first configure:
•
•
•
RESPEN bit in MMCON1 register to indicate whether a response is expected or not.
RFMT bit in MMCON0 register to indicate the response size expected.
CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the
response will be computed or not. In order to avoid CRC error, CRCDIS may be set
for response that do not include CRC7.
Figure 94 summarizes the command transmission flow.
As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicat-
ing that write to the FIFO is locked. This mechanism is implemented to avoid command
overrun.
The end of the command transmission is signalled to you by the EOCI flag in MMINT
register becoming set. This flag may generate an MMC interrupt request as detailed in
Section "Interrupt", page 150. The end of the command transmission also resets the
CFLCK flag.
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AT8xC51SND2C
User may abort command loading by setting and clearing the CTPTR bit in MMCON0
register which resets the write pointer to the transmit FIFO.
Figure 94. Command Transmission Flow
Command
Transmission
Load Command in
Buffer
MMCMD = index
MMCMD = argument
Configure Response
RESPEN = X
RFMT = X
CRCDIS = X
Transmit Command
CMDEN = 1
CMDEN = 0
Command Receiver
The end of the response reception is signalled to you by the EORI flag in MMINT regis-
ter. This flag may generate an MMC interrupt request as detailed in Section "Interrupt",
page 150. When this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S
give a status on the response received. RESPFS indicates if the response format is cor-
rect or not: the size is the one expected (48 bits or 136 bits) and a valid End bit has been
received, and CRC7S indicates if the CRC7 computation is correct or not. These Flags
are cleared when a command is sent to the card and updated when the response has
been received.
User may abort response reading by setting and clearing the CRPTR bit in MMCON0
register which resets the read pointer to the receive FIFO.
According to the MMC specification delay between a command and a response (for-
mally NCR parameter) can not exceed 64 MMC clock periods. To avoid any locking of
the MMC controller when card does not send its response (e.g. physically removed from
the bus), user must launch a time-out period to exit from such situation. In case of time-
out user may reset the command controller and its internal state machine by setting and
clearing the CCR bit in MMCON2 register.
This time-out may be disarmed when receiving the response.
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Data Line Controller
The data line controller is based on a 16-Byte FIFO used both by the data transmitter
channel and by the data receiver channel.
Figure 95. Data Line Controller Block Diagram
MMINT.0
MMINT.2
MMSTA.3
MMSTA.4
F1EI
F1FI
DATFS CRC16S
CRC16 and Format
Checker
Data Converter
Serial -> //
8-Byte
TX Pointer
FIFO 1
MCBI
MMINT.1
CBUSY
MMSTA.5
MDAT
DTPTR
MMCON0.6
16-Byte FIFO
MMDAT
Data Converter
// -> Serial
CRC16
Generator
RX Pointer
DRPTR
MMCON0.7
8-Byte
FIFO 2
MMINT.4
DATA Line
Finished State Machine
EOFI
DFMT
MBLOCK DATEN DATDIR BLEN3:0
MMCON0.2 MMCON0.3 MMCON1.2 MMCON1.3 MMCON1.7:4
F2EI
MMINT.1
F2FI
MMINT.3
FIFO Implementation
The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four
flags indicating the status full and empty of each FIFO.
Pointers are not accessible to user but can be reset at any time by setting and clearing
DRPTR and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to
abort the writing or reading of data.
F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and
FIFO2 are empty. F1FI and F2FI flags in MMINT register signal when set that respec-
tively FIFO1 and FIFO2 are full. These flags may generate an MMC interrupt request as
detailed in Section “Interrupt”.
Data Configuration
Before sending or receiving any data, the data line controller must be configured accord-
ing to the type of the data transfer considered. This is achieved using the Data Format
bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format
while setting DFMT bit enables the data block format. In data block format, user must
also configure the single or multi-block mode by clearing or setting the MBLOCK bit in
MMCON0 register and the block length using BLEN3:0 bits in MMCON1 according to
Table 144. Figure 96 summarizes the data modes configuration flows.
Table 144. Block Length Programming
BLEN3:0
BLEN = 0000 to 1011
> 1011
Block Length (Byte)
Length = 2BLEN: 1 to 2048
Reserved: do not program BLEN3:0 > 1011
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AT8xC51SND2C
Figure 96. Data Controller Configuration Flows
Data Stream
Configuration
Data Single Block
Configuration
Data Multi-Block
Configuration
Configure Format
Configure Format
DFMT = 1
Configure Format
DFMT = 1
DFMT = 0
MBLOCK = 0
MBLOCK = 1
BLEN3:0 = XXXXb
BLEN3:0 = XXXXb
Data Transmitter
Configuration
For transmitting data to the card user must first configure the data controller in transmis-
sion mode by setting the DATDIR bit in MMCON1 register.
Figure 97 summarizes the data stream transmission flows in both polling and interrupt
modes while Figure 98 summarizes the data block transmission flows in both polling
and interrupt modes, these flows assume that block length is greater than 16 data.
Data Loading
Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may
vary from 1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait
that one FIFO becomes empty (F1EI or F2EI set) before loading 8 new data.
Data Transmission
Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.
Data is transmitted immediately if the response has already been received, or is delayed
after the response reception if its status is correct. In both cases transmission is delayed
if a card sends a busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not
start sooner than 2 MMC clock periods after the card response was received (formally
NWR parameter). To address all card types, this delay can be programmed using
DATD1:0 bits in MMCON2 register from 3 MMC clock periods when DATD1:0 bits are
cleared to 9 MMC clock periods when DATD1:0 bits are set, by step of 2 MMC clock
periods.
End of Transmission
The end of a data frame (block or stream) transmission is signalled to you by the EOFI
flag in MMINT register. This flag may generate an MMC interrupt request as detailed in
Section "Interrupt", page 150.
In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user
has previously sent the STOP command to the card, which is the only way to stop
stream transfer.
In data block mode, EOFI flag is set, after reception of the CRC status token (see
Figure 88). 2 other flags in MMSTA register: DATFS and CRC16S report a status on the
frame sent. DATFS indicates if the CRC status token format is correct or not, and
CRC16S indicates if the card has found the CRC16 of the block correct or not.
Busy Status
As shown in Figure 88 the card uses a busy token during a block write operation. This
busy status is reported to you by the CBUSY flag in MMSTA register and by the MCBI
flag in MMINT which is set every time CBUSY toggles, i.e. when the card enters and
exits its busy state. This flag may generate an MMC interrupt request as detailed in Sec-
tion "Interrupt", page 150.
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Figure 97. Data Stream Transmission Flows
Data Stream
Transmission
Data Stream
Initialization
Data Stream
Transmission ISR
FIFOs Filling
write 16 data to MMDAT
FIFOs Filling
write 16 data to MMDAT
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
Unmask FIFOs Empty
F1EM = 0
DATEN = 0
F2EM = 0
FIFO Filling
write 8 data to MMDAT
Start Transmission
DATEN = 1
FIFO Empty?
F1EI or F2EI = 1?
No More Data
To Send?
DATEN = 0
FIFO Filling
write 8 data to MMDAT
Mask FIFOs Empty
F1EM = 1
F2EM = 1
No More Data
To Send?
Send
STOP Command
Send
STOP Command
b. Interrupt mode
a. Polling mode
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AT8xC51SND2C
Figure 98. Data Block Transmission Flows
Data Block
Data Block
Data Block
Transmission
Initialization
Transmission ISR
FIFOs Filling
write 16 data to MMDAT
FIFOs Filling
write 16 data to MMDAT
FIFO Empty?
F1EI or F2EI = 1?
Start Transmission
DATEN = 1
Unmask FIFOs Empty
F1EM = 0
DATEN = 0
F2EM = 0
FIFO Filling
write 8 data to MMDAT
Start Transmission
DATEN = 1
FIFO Empty?
F1EI or F2EI = 1?
No More Data
To Send?
DATEN = 0
FIFO Filling
write 8 data to MMDAT
Mask FIFOs Empty
F1EM = 1
F2EM = 1
No More Data
To Send?
b. Interrupt mode
a. Polling mode
Data Receiver
Configuration
To receive data from the card you must first configure the data controller in reception
mode by clearing the DATDIR bit in MMCON1 register.
Figure 99 summarizes the data stream reception flows in both polling and interrupt
modes while Figure 100 summarizes the data block reception flows in both polling and
interrupt modes, these flows assume that block length is greater than 16 Bytes.
Data Reception
The end of a data frame (block or stream) reception is signalled to you by the EOFI flag
in MMINT register. This flag may generate an MMC interrupt request as detailed in Sec-
tion "Interrupt", page 150. When this flag is set, 2 other flags in MMSTA register: DATFS
and CRC16S give a status on the frame received. DATFS indicates if the frame format
is correct or not: a valid End bit has been received, and CRC16S indicates if the CRC16
computation is correct or not. In case of data stream CRC16S has no meaning and
stays cleared.
According to the MMC specification data transmission from the card starts after the
access time delay (formally NAC parameter) beginning from the End bit of the read com-
mand. To avoid any locking of the MMC controller when card does not send its data
(e.g. physically removed from the bus), you must launch a time-out period to exit from
such situation. In case of time-out you may reset the data controller and its internal state
machine by setting and clearing the DCR bit in MMCON2 register.
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This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving
end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4).
Data Reading
Data is read from the FIFO by reading to MMDAT register. Each time one FIFO
becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.
Figure 99. Data Stream Reception Flows
Data Stream
Reception
Data Stream
Initialization
Data Stream
Reception ISR
Unmask FIFOs Full
F1FM = 0
FIFO Full?
F1FI or F2FI = 1?
FIFO Full?
F1FI or F2FI = 1?
F2FM = 0
FIFO Reading
read 8 data from MMDAT
FIFO Reading
read 8 data from MMDAT
No More Data
To Receive?
No More Data
To Receive?
Mask FIFOs Full
F1FM = 1
Send
STOP Command
F2FM = 1
Send
a. Polling mode
STOP Command
b. Interrupt mode
148
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Figure 100. Data Block Reception Flows
Data Block
Reception
Data Block
Initialization
Data Block
Reception ISR
Start Transmission
DATEN = 1
Unmask FIFOs Full
F1FM = 0
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
F2FM = 0
Start Transmission
DATEN = 1
FIFO Reading
read 8 data from MMDAT
FIFO Full?
F1EI or F2EI = 1?
DATEN = 0
No More Data
To Receive?
FIFO Reading
read 8 data from MMDAT
Mask FIFOs Full
F1FM = 1
No More Data
To Receive?
F2FM = 1
a. Polling mode
b. Interrupt mode
Flow Control
To allow transfer at high speed without taking care of CPU oscillator frequency, the
FLOWC bit in MMCON2 allows control of the data flow in both transmission and
reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
During reception, setting the FLOWC bit has the following effects:
•
•
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the
clock is restored by writing or reading data in MMDAT.
149
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Interrupt
Description
As shown in Figure 101, the MMC controller implements eight interrupt sources reported
in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These
flags are detailed in the previous sections.
All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM,
F1FM, and F2EM mask bits respectively in MMMSK register.
The interrupt request is generated each time an unmasked flag is set, and the global
MMC controller interrupt enable bit is set (EMMC in IEN1 register).
Reading the MMINT register automatically clears the interrupt flags (acknowledgment).
This implies that register content must be saved and tested interrupt flag by interrupt
flag to be sure not to forget any interrupts.
Figure 101. MMC Controller Interrupt System
MCBI
MMINT.7
MCBM
MMMSK.7
EORI
MMINT.6
EORM
MMMSK.6
EOCI
MMINT.5
EOCM
MMMSK.5
EOFI
MMINT.4
MMC Interface
Interrupt Request
EOFM
MMMSK.4
F2FI
MMINT.3
EMMC
IEN1.0
F2FM
MMMSK.3
F1FI
MMINT.2
F1FM
MMMSK.2
F2EI
MMINT.1
F2EM
MMMSK.1
F1EI
MMINT.0
F1EM
MMMSK.0
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Registers
Table 145. MMCON0 Register
MMCON0 (S:E4h) – MMC Control Register 0
7
6
5
4
3
2
1
0
DRPTR
DTPTR
CRPTR
CTPTR
MBLOCK
DFMT
RFMT
CRCDIS
Bit
Bit
Number
Mnemonic Description
Data Receive Pointer Reset Bit
7
6
5
4
3
2
1
0
DRPTR Set to reset the read pointer of the data FIFO.
Clear to release the read pointer of the data FIFO.
Data Transmit Pointer Reset Bit
DTPTR
Set to reset the write pointer of the data FIFO.
Clear to release the write pointer of the data FIFO.
Command Receive Pointer Reset Bit
CRPTR Set to reset the read pointer of the receive command FIFO.
Clear to release the read pointer of the receive command FIFO.
Command Transmit Pointer Reset Bit
CTPTR
Set to reset the write pointer of the transmit command FIFO.
Clear to release the read pointer of the transmit command FIFO.
Multi-block Enable Bit
MBLOCK Set to select multi-block data format.
Clear to select single block data format.
Data Format Bit
DFMT
RFMT
Set to select the block-oriented data format.
Clear to select the stream data format.
Response Format Bit
Set to select the 48-bit response format.
Clear to select the 136-bit response format.
CRC7 Disable Bit
CRCDIS Set to disable the CRC7 computation when receiving a response.
Clear to enable the CRC7 computation when receiving a response.
Reset Value = 0000 0000b
151
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Table 146. MMCON1 Register
MMCON1 (S:E5h) – MMC Control Register 1
7
6
5
4
3
2
1
0
BLEN3
BLEN2
BLEN1
BLEN0
DATDIR
DATEN
RESPEN
CMDEN
Bit
Bit
Number
Mnemonic Description
Block Length Bits
Refer to Table 144 for bits description. Do not program value > 1011b
7 - 4
3
BLEN3:0
Data Direction Bit
DATDIR Set to select data transfer from host to card (write mode).
Clear to select data transfer from card to host (read mode).
Data Transmission Enable Bit
2
DATEN
Set and clear to enable data transmission immediately or after response has
been received.
Response Enable Bit
1
0
RESPEN Set and clear to enable the reception of a response following a command
transmission.
Command Transmission Enable Bit
CMDEN
Set and clear to enable transmission of the command FIFO to the card.
Reset Value = 0000 0000b
Table 147. MMCON2 Register
MMCON2 (S:E6h) – MMC Control Register 2
7
6
5
4
-
3
-
2
1
0
MMCEN
DCR
CCR
DATD1
DATD0
FLOWC
Bit
Bit
Number
Mnemonic Description
MMC Clock Enable Bit
7
MMCEN Set to enable the MCLK clocks and activate the MMC controller.
Clear to disable the MMC clocks and freeze the MMC controller.
Data Controller Reset Bit
Set and clear to reset the data line controller in case of transfer abort.
6
5
DCR
Command Controller Reset Bit
Set and clear to reset the command line controller in case of transfer abort.
CCR
Reserved
4-3
-
The value read from these bits is always 0. Do not set these bits.
Data Transmission Delay Bits
Used to delay the data transmission after a response from 3 MMC clock periods
(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock
periods.
2-1
0
DATD1:0
MMC Flow Control Bit
FLOWC Set to enable the flow control during data transfers.
Clear to disable the flow control during data transfers.
Reset Value = 0000 0000b
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Table 148. MMSTA Register
MMSTA (S:DEh Read Only) – MMC Control and Status Register
7
-
6
-
5
4
3
2
1
0
CBUSY
CRC16S
DATFS
CRC7S
RESPFS
CFLCK
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 6
5
-
The value read from these bits is always 0. Do not set these bits.
Card Busy Flag
CBUSY Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
CRC16 Status Bit
Transmission mode
Set by hardware when the token response reports a good CRC.
CRC16S Cleared by hardware when the token response reports a bad CRC.
Reception mode
4
3
Set by hardware when the CRC16 received in the data block is correct.
Cleared by hardware when the CRC16 received in the data block is not correct.
Data Format Status Bit
Transmission mode
Set by hardware when the format of the token response is correct.
DATFS
CRC7S
Cleared by hardware when the format of the token response is not correct.
Reception mode
Set by hardware when the format of the frame is correct.
Cleared by hardware when the format of the frame is not correct.
CRC7 Status Bit
Set by hardware when the CRC7 computed in the response is correct.
Cleared by hardware when the CRC7 computed in the response is not correct.
2
1
This bit is not relevant when CRCDIS is set.
Response Format Status Bit
RESPFS Set by hardware when the format of a response is correct.
Cleared by hardware when the format of a response is not correct.
Command FIFO Lock Bit
Set by hardware to signal user not to write in the transmit command FIFO: busy
0
CFLCK
state.
Cleared by hardware to signal user the transmit command FIFO is available: idle
state.
Reset Value = 0000 0000b
153
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Table 149. MMINT Register
MMINT (S:E7h Read Only) – MMC Interrupt Register
7
6
5
4
3
2
1
0
MCBI
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
Bit
Bit
Number
Mnemonic Description
MMC Card Busy Interrupt Flag
Set by hardware when the card enters or exits its busy state (when the busy
signal is asserted or deasserted on the data line).
Cleared when reading MMINT.
7
MCBI
End of Response Interrupt Flag
6
5
4
3
2
1
0
EORI
EOCI
EOFI
F2FI
F1FI
F2EI
F1EI
Set by hardware at the end of response reception.
Cleared when reading MMINT.
End of Command Interrupt Flag
Set by hardware at the end of command transmission.
Clear when reading MMINT.
End of Frame Interrupt Flag
Set by hardware at the end of frame (stream or block) transfer.
Clear when reading MMINT.
FIFO 2 Full Interrupt Flag
Set by hardware when second FIFO becomes full.
Cleared by hardware when second FIFO becomes empty.
FIFO 1 Full Interrupt Flag
Set by hardware when first FIFO becomes full.
Cleared by hardware when first FIFO becomes empty.
FIFO 2 Empty Interrupt Flag
Set by hardware when second FIFO becomes empty.
Cleared by hardware when second FIFO becomes full.
FIFO 1 Empty Interrupt Flag
Set by hardware when first FIFO becomes empty.
Cleared by hardware when first FIFO becomes full.
Reset Value = 0000 0011b
154
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AT8xC51SND2C
Table 150. MMMSK Register
MMMSK (S:DFh) – MMC Interrupt Mask Register
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Bit
Bit
Number
Mnemonic Description
MMC Card Busy Interrupt Mask Bit
7
6
5
4
3
2
1
0
MCBM
EORM
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
Set to prevent MCBI flag from generating an MMC interrupt.
Clear to allow MCBI flag to generate an MMC interrupt.
End Of Response Interrupt Mask Bit
Set to prevent EORI flag from generating an MMC interrupt.
Clear to allow EORI flag to generate an MMC interrupt.
End Of Command Interrupt Mask Bit
Set to prevent EOCI flag from generating an MMC interrupt.
Clear to allow EOCI flag to generate an MMC interrupt.
End Of Frame Interrupt Mask Bit
Set to prevent EOFI flag from generating an MMC interrupt.
Clear to allow EOFI flag to generate an MMC interrupt.
FIFO 2 Full Interrupt Mask Bit
Set to prevent F2FI flag from generating an MMC interrupt.
Clear to allow F2FI flag to generate an MMC interrupt.
FIFO 1 Full Interrupt Mask Bit
Set to prevent F1FI flag from generating an MMC interrupt.
Clear to allow F1FI flag to generate an MMC interrupt.
FIFO 2 Empty Interrupt Mask Bit
Set to prevent F2EI flag from generating an MMC interrupt.
Clear to allow F2EI flag to generate an MMC interrupt.
FIFO 1 Empty Interrupt Mask Bit
Set to prevent F1EI flag from generating an MMC interrupt.
Clear to allow F1EI flag to generate an MMC interrupt.
Reset Value = 1111 1111b
Table 151. MMCMD Register
MMCMD (S:DDh) – MMC Command Register
7
6
5
4
3
2
1
0
MC7
MC6
MC5
MC4
MC3
MC2
MC1
MC0
Bit
Bit
Number
Mnemonic Description
MMC Command Receive Byte
Output (read) register of the response FIFO.
7 - 0
MC7:0
MMC Command Transmit Byte
Input (write) register of the command FIFO.
Reset Value = 1111 1111b
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Table 152. MMDAT Register
MMDAT (S:DCh) – MMC Data Register
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit
Bit
Number
Mnemonic Description
MMC Data Byte
Input (write) or output (read) register of the data FIFO.
7 - 0
MD7:0
Reset Value = 1111 1111b
Table 153. MMCLK Register
MMCLK (S:EDh) – MMC Clock Divider Register
7
6
5
4
3
2
1
0
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Bit
Bit
Number
Mnemonic Description
MMC Clock Divider
8-bit divider for MMC clock generation.
7 - 0
MMCD7:0
Reset Value = 0000 0000b
156
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Synchronous
Peripheral Interface
The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and
slave modes capability.
Figure 102 shows an SPI bus configuration using the AT8xC51SND2C as master con-
nected to slave peripherals while Figure 103 shows an SPI bus configuration using the
AT8xC51SND2C as slave of an other master.
The bus is made of three wires connecting all the devices together:
•
•
•
Master Output Slave Input (MOSI): it is used to transfer data in series from the
master to a slave.
It is driven by the master.
Master Input Slave Output (MISO): it is used to transfer data in series from a slave
to the master.
It is driven by the selected slave.
Serial Clock (SCK): it is used to synchronize the data transmission both in and out
the devices through their MOSI and MISO lines. It is driven by the master for eight
clock cycles which allows to exchange one Byte on the serial lines.
Each slave peripheral is selected by one Slave Select pin (SS). If there is only one
slave, it may be continuously selected with SS tied to a low level. Otherwise, the
AT8xC51SND2C may select each device by software through port pins (Pn.x). Special
care should be taken not to select 2 slaves at the same time to avoid bus conflicts.
Figure 102. Typical Master SPI Bus Configuration
Pn.z
Pn.y
LCD
Controller
Pn.x
SS
SS
SS
DataFlash 1
DataFlash 2
SO
SI
SCK
SO
SI
SCK
SO
SI
SCK
AT8xC51SND2C
MISO
P4.0
P4.1
P4.2
MOSI
SCK
Figure 103. Typical Slave SPI Bus Configuration
SSn
SS1
SS
AT8xC51SND2C
Slave n
SS0
SS
SS
Slave 1
Slave 2
SO
SI
SCK
SO
SI
SCK
MISO MOSI SCK
MASTER
MISO
MOSI
SCK
157
4341D–MP3–04/05
Description
The SPI controller interfaces with the C51 core through three special function registers:
SPCON, the SPI control register (see Table 155); SPSTA, the SPI status register (see
Table 156); and SPDAT, the SPI data register (see Table 157).
Master Mode
The SPI operates in master mode when the MSTR bit in SPCON is set.
Figure 104 shows the SPI block diagram in master mode. Only a master SPI module
can initiate transmissions. Software begins the transmission by writing to SPDAT. Writ-
ing to SPDAT writes to the shift register while reading SPDAT reads an intermediate
register updated at the end of each transfer.
The Byte begins shifting out on the MOSI pin under the control of the bit rate generator.
This generator also controls the shift register of the slave peripheral through the SCK
output pin. As the Byte shifts out, another Byte shifts in from the slave peripheral on the
MISO pin. The Byte is transmitted most significant bit (MSB) first. The end of transfer is
signaled by SPIF being set.
When the AT8xC51SND2C is the only master on the bus, it can be useful not to use
SS# pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in
SPCON.
Figure 104. SPI Master Mode Block Diagram
MOSI/P4.1
I
Q
MISO/P4.0
SCK/P4.2
SS#/P4.3
8-bit Shift Register
SPDAT WR
SPDAT RD
MODF
SSDIS
SPCON.5
SPSTA.4
Control and Clock Logic
WCOL
SPSTA.6
PER
Bit Rate Generator
CLOCK
SPIF
SPSTA.7
SPEN
SPCON.6
SPR2:0
SPCON
CPHA
SPCON.2
CPOL
SPCON.3
Note:
MSTR bit in SPCON is set to select master mode.
158
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AT8xC51SND2C
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Figure 105 shows the SPI block diagram in slave mode. In slave mode, before a data
transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must
remain low until the transmission of the Byte is complete. In the slave SPI module, data
enters the shift register through the MOSI pin under the control of the serial clock pro-
vided by the master SPI module on the SCK input pin. When the master starts a
transmission, the data in the shift register begins shifting out on the MISO pin. The end
of transfer is signaled by SPIF being set.
When the AT8xC51SND2C is the only slave on the bus, it can be useful not to use SS#
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
This bit has no effect when CPHA is cleared (see Section "SS Management",
page 161).
Figure 105. SPI Slave Mode Block Diagram
MISO/P4.2
I
Q
MOSI/P4.1
8-bit Shift Register
SPDAT WR
SPDAT RD
SCK/P4.2
SS/P4.3
Control and Clock Logic
SPIF
SPSTA.7
SSDIS
SPCON.5
CPHA
SPCON.2
CPOL
SPCON.3
Note:
1. MSTR bit in SPCON is cleared to select slave mode.
Bit Rate
The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and
SPR0 control bits in SPCON according to Table 154. These bit rates are derived from
the peripheral clock (FPER) issued from the Clock Controller block as detailed in Section
"Oscillator", page 12.
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Table 154. Serial Bit Rates
Bit Rate (kHz) Vs FPER
SPR2 SPR1 SPR0 6 MHz(1) 8 MHz(1) 10 MHz(1) 12 MHz(2) 16 MHz(2) 20 MHz(2) FPER Divider
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3000
1500
750
4000
2000
1000
500
5000
2500
6000
3000
1500
750
8000
4000
2000
1000
500
10000
5000
2
4
1250
2500
8
375
625
1250
16
32
64
128
1
187.5
93.75
46.875
6000
250
312.5
156.25
78.125
10000
375
625
125
187.5
93.75
12000
250
312.5
156.25
20000
62.5
8000
125
16000
Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC
.
Data Transfer
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle
state(1) while the Clock Phase bit (CPHA in SPCON) defines the edges on which the
input data are sampled and the edges on which the output data are shifted (see
Figure 106 and Figure 107). The SI signal is output from the selected slave and the SO
signal is the output from the master. The AT8xC51SND2C captures data from the SI line
while the selected slave captures data from the SO line.
For simplicity, Figure 106 and Figure 107 depict the SPI waveforms in idealized form
and do not provide precise timing information. For timing parameters refer to the Section
“AC Characteristics”.
Note:
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
Figure 106. Data Transmission Format (CPHA = 0)
1
2
3
4
5
6
7
8
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
LSB
MOSI (From Master)
MISO (From Slave)
MSB
SS (to slave)
Capture point
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AT8xC51SND2C
Figure 107. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
LSB
MOSI (from master)
MISO (from slave)
SS (to slave)
Capture point
SS Management
Figure 106 shows an SPI transmission with CPHA = 0, where the first SCK edge is the
MSB capture point. Therefore the slave starts to output its MSB as soon as it is
selected: SS asserted to low level. SS must then be deasserted between each Byte
transmission (see Figure 108). SPDAT must be loaded with a data before SS is
asserted again.
Figure 107 shows an SPI transmission with CPHA = 1, where the first SCK edge is used
by the slave as a start of transmission signal. Therefore, SS may remain asserted
between each Byte transmission (see Figure 108).
Figure 108. SS Timing Diagram
Byte 1
Byte 2
Byte 3
SI/SO
SS (CPHA = 0)
SS (CPHA = 1)
Error Conditions
The following flags signal the SPI error conditions:
•
•
•
MODF in SPSTA signals a mode fault.
MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit
cleared). It signals when set that an other master on the bus has asserted SS pin
and so, may create a conflict on the bus with 2 master sending data at the same
time.
A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI
in slave mode (MSTR cleared).
MODF flag can trigger an interrupt as explained in Section "Interrupt", page 162.
MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to
SPCON.
WCOL in SPSTA signals a write collision.
WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case
data is not written to SPDAT and transfer continue uninterrupted. WCOL flag does
not trigger any interrupt and is relevant jointly with SPIF flag.
WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no
transfer is on-going.
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4341D–MP3–04/05
Interrupt
The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault”
flags.
As shown in Figure 109, these flags are combined toghether to appear as a single inter-
rupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out
and is cleared by reading SPSTA and then reading from or writing to SPDAT.
The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and
then writing to SPCON.
The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-
rupts are globally enabled by setting EA bit in IEN0 register.
Figure 109. SPI Interrupt System
SPIF
SPI Controller
Interrupt Request
SPSTA.7
MODF
SPSTA.4
ESPI
IEN1.2
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AT8xC51SND2C
Configuration
The SPI configuration is made through SPCON.
Master Configuration
Slave Configuration
The SPI operates in master mode when the MSTR bit in SPCON is set.
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded is SPDAT.
Data Exchange
There are 2 possible methods to exchange data in master and slave modes:
•
•
polling
interrupts
Master Mode with Polling
Policy
Figure 110 shows the initialization phase and the transfer phase flows using the polling
method. Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 154. The transfer format depends on the
slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of
transfer” check).
This polling method provides the fastest effective transmission and is well adapted when
communicating at high speed with other microcontrollers. However, the procedure may
then be interrupted at any time by higher priority tasks.
Figure 110. Master SPI Polling Flows
SPI Initialization
Polling Policy
SPI Transfer
Polling Policy
Disable interrupt
Select Slave
SPIE = 0
Pn.x = L
Select Master Mode
Start Transfer
MSTR = 1
write data in SPDAT
Select Bit Rate
program SPR2:0
End Of Transfer?
SPIF = 1?
Select Format
program CPOL & CPHA
Get Data Received
read SPDAT
Enable SPI
SPEN = 1
Last Transfer?
Deselect Slave
Pn.x = H
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Master Mode with Interrupt
Figure 111 shows the initialization phase and the transfer phase flows using the inter-
rupt. Using this flow prevents any overrun error occurrence.
The bit rate is selected according to Table 154.
The transfer format depends on the slave peripheral.
SS may be deasserted between transfers depending also on the slave peripheral.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 111. Master SPI Interrupt Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Master Mode
Read Status
MSTR = 1
Read SPSTA
Select Bit Rate
Get Data Received
program SPR2:0
read SPDAT
Select Format
Start New Transfer
program CPOL & CPHA
write data in SPDAT
Enable interrupt
ESPI =1
Last Transfer?
Enable SPI
SPEN = 1
Deselect Slave
Pn.x = H
Select Slave
Pn.x = L
Disable interrupt
SPIE = 0
Start Transfer
write data in SPDAT
164
AT8xC51SND2C
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AT8xC51SND2C
Slave Mode with Polling
Policy
Figure 112 shows the initialization phase and the transfer phase flows using the polling.
The transfer format depends on the master controller.
SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of
reception” check).
This provides the fastest effective transmission and is well adapted when communicat-
ing at high speed with other Microcontrollers. However, the process may then be
interrupted at any time by higher priority tasks.
Figure 112. Slave SPI Polling Flows
SPI Initialization
Polling Policy
SPI Transfer
Polling Policy
Disable interrupt
Data Received?
SPIE = 0
SPIF = 1?
Select Slave Mode
MSTR = 0
Get Data Received
read SPDAT
Select Format
program CPOL & CPHA
Prepare Next Transfer
write data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
write data in SPDAT
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Slave Mode with Interrupt
Policy
Figure 111 shows the initialization phase and the transfer phase flows using the
interrupt.
The transfer format depends on the master controller.
Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.
Clear is effective when reading SPDAT.
Figure 113. Slave SPI Interrupt Policy Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Slave Mode
Get Status
MSTR = 0
Read SPSTA
Select Format
Get Data Received
program CPOL & CPHA
read SPDAT
Enable interrupt
Prepare New Transfer
ESPI =1
write data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
write data in SPDAT
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AT8xC51SND2C
Registers
Table 155. SPCON Register
SPCON (S:C3h) – SPI Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Bit
Number
Mnemonic Description
SPI Rate Bit 2
Refer to Table 154 for bit rate description.
7
6
SPR2
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
SPEN
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no
effect if CPHA = 0.
5
SSDIS
Clear to enable SS in both master and slave modes.
Master Mode Select
4
3
MSTR
CPOL
Set to select the master mode.
Clear to select the slave mode.
SPI Clock Polarity Bit(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
2
CPHA
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
SPI Rate Bits 0 and 1
Refer to Table 154 for bit rate description.
1 - 0
SPR1:0
Reset Value = 0001 0100b
Note: 1. When the SPI is disabled, SCK outputs high level.
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Table 156. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
7
6
5
-
4
3
-
2
-
1
-
0
-
SPIF
WCOL
MODF
Bit
Bit
Number
Mnemonic Description
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
7
SPIF
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
Write Collision Flag
6
5
WCOL
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Mode Fault
4
MODF
-
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
Reserved
3 - 0
The value read from these bits is indeterminate. Do not set these bits.
Reset Value = 00000 0000b
Table 157. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Bit
Bit
Number
Mnemonic Description
7 - 0
SPD7:0 Synchronous Serial Data.
Reset Value = XXXX XXXXb
168
AT8xC51SND2C
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AT8xC51SND2C
Serial I/O Port
The serial I/O port in the AT8xC51SND2C provides both synchronous and asynchro-
nous communication modes. It operates as a Synchronous Receiver and Transmitter in
one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and
Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous
modes support framing error detection and multiprocessor communication with auto-
matic address recognition.
Mode Selection
SM0 and SM1 bits in SCON register (see Figure 160) are used to select a mode among
the single synchronous and the three asynchronous modes according to Table 158.
Table 158. Serial I/O Port Mode Selection
SM0
SM1
Mode
Description
Baud Rate
Fixed/Variable
Variable
0
0
1
1
0
1
0
1
0
1
2
3
Synchronous Shift Register
8-bit UART
9-bit UART
Fixed
9-bit UART
Variable
Baud Rate Generator
Depending on the mode and the source selection, the baud rate can be generated from
either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in
Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1
and 3.
The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other
purposes in the application. It is highly recommended to use the Internal Baud Rate
Generator as it allows higher and more accurate baud rates than Timer 1.
Baud rate formulas depend on the modes selected and are given in the following mode
sections.
Timer 1
When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown
in Figure 114 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2
(8-bit Timer with Auto-Reload)", page 53). SMOD1 bit in PCON register allows doubling
of the generated baud rate.
Figure 114. Timer 1 Baud Rate Generator Block Diagram
PER
CLOCK
÷ 6
0
1
Overflow
TL1
(8 bits)
÷ 2
0
1
To serial
Port
T1
C/T1#
TMOD.6
SMOD1
PCON.7
INT1
TH1
(8 bits)
GATE1
TMOD.7
T1
CLOCK
TR1
TCON.6
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Internal Baud Rate Generator When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-
flow of the timer. As shown in Figure 115 the Internal Baud Rate Generator is an 8-bit
auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6
depending on the SPD bit in BDRCON register (see Table 164). The Internal Baud Rate
Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON reg-
ister allows doubling of the generated baud rate.
Figure 115. Internal Baud Rate Generator Block Diagram
PER
CLOCK
÷ 6
0
1
Overflow
BRG
(8 bits)
÷ 2
0
1
To serial
Port
SPD
BDRCON.1
BRR
BDRCON.4
SMOD1
PCON.7
BRL
(8 bits)
IBRG
CLOCK
Synchronous Mode
(Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0
capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of
eight clock pulses while the receive data (RXD) pin transmits or receives a Byte of data.
The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur
at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 171).
Figure 116 shows the serial port block diagram in Mode 0.
Figure 116. Serial I/O Port Block Diagram (Mode 0)
SCON.6
SCON.7
SM1
SM0
SBUF Tx SR
SBUF Rx SR
RXD
Mode Decoder
M3 M2 M1 M0
Mode
Controller
PER
CLOCK
Baud Rate
Controller
TI
SCON.1
RI
SCON.0
TXD
BRG
CLOCK
Transmission (Mode 0)
To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.
As shown in Figure 117, writing the Byte to transmit to SBUF register starts the trans-
mission. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle
composed of a high level then low level signal on TXD. During the eighth clock cycle the
MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to
indicate the end of the transmission.
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AT8xC51SND2C
Figure 117. Transmission Waveforms (Mode 0)
TXD
Write to SBUF
RXD
TI
D0
D1
D2
D3
D4
D5
D6
D7
Reception (Mode 0)
To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits
and setting the REN bit.
As shown in Figure 118, Clock is pulsed and the LSB (D0) is sampled on the RXD pin.
The D0 bit is then shifted into the shift register. After eight samplings, the MSB (D7) is
shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-
tion. Software can then read the received Byte from SBUF register.
Figure 118. Reception Waveforms (Mode 0)
TXD
Set REN, Clear RI
D0 D1 D2
Write to SCON
RXD
RI
D3
D4
D5
D6
D7
Baud Rate Selection (Mode 0) In mode 0, the baud rate can be either, fixed or variable.
As shown in Figure 119, the selection is done using M0SRC bit in BDRCON register.
Figure 120 gives the baud rate calculation formulas for each baud rate source.
Figure 119. Baud Rate Source Selection (mode 0)
PER
CLOCK
÷ 6
0
To Serial Port
1
IBRG
CLOCK
M0SRC
BDRCON.0
Figure 120. Baud Rate Formulas (Mode 0)
2SMOD1 ⋅ FPER
Baud_Rate=
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
FPER
2SMOD1 ⋅ FPER
Baud_Rate=
6
BRL= 256 -
6(1-SPD) ⋅ 32 ⋅ Baud_Rate
a. Fixed Formula
b. Variable Formula
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Asynchronous Modes
(Modes 1, 2 and 3)
The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 121
shows the Serial Port block diagram in such asynchronous modes.
Figure 121. Serial I/O Port Block Diagram (Modes 1, 2 and 3)
SCON.6
SCON.7
SCON.3
SM1
SM0
TB8
SBUF Tx SR
Rx SR
TXD
RXD
Mode Decoder
M3 M2 M1 M0
T1
CLOCK
IBRG
CLOCK
Mode & Clock
Controller
SBUF Rx
RB8
SCON.2
PER
CLOCK
SM2
SCON.4
TI
SCON.1
RI
SCON.0
Mode 1
Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 122) consists
of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the
TXD pin and received on the RXD pin. When a data is received, the stop bit is read in
the RB8 bit in SCON register.
Figure 122. Data Frame Format (Mode 1)
Mode 1
D0
D1
D2
D3
D4
D5
D6
D7
Start bit
8-bit data
Stop bit
Modes 2 and 3
Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 123)
consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one
programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin
and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON
register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-
tively, you can use the ninth bit can be used as a command/data flag.
Figure 123. Data Frame Format (Modes 2 and 3)
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start bit
9-bit data
Stop bit
Transmission (Modes 1, 2
and 3)
To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according
to Table 158, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be
transmitted to SBUF register starts the transmission.
Reception (Modes 1, 2 and 3)
To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to
Table 158, and set the REN bit. The actual reception is then initiated by a detected high-
to-low transition on the RXD pin.
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AT8xC51SND2C
Framing Error Detection
(Modes 1, 2 and 3)
Framing error detection is provided for the three asynchronous modes. To enable the
framing bit error detection feature, set SMOD0 bit in PCON register as shown in
Figure 124.
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in
SCON register.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a chip reset clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on
stop bit instead of the last data bit as detailed in Figure 130.
Figure 124. Framing Error Block Diagram
Framing Error
Controller
FE
1
0
SM0/FE
SCON.7
SM0
SMOD0
PCON.6
Baud Rate Selection (Modes 1 In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud
and 3)
Rate Generator and allows different baud rate in reception and transmission.
As shown in Figure 125 the selection is done using RBCK and TBCK bits in BDRCON
register.
Figure 126 gives the baud rate calculation formulas for each baud rate source while
Table 159 details Internal Baud Rate Generator configuration for different peripheral
clock frequencies and giving baud rates closer to the standard baud rates.
Figure 125. Baud Rate Source Selection (Modes 1 and 3)
T1
T1
CLOCK
CLOCK
0
0
1
To Serial
Rx Port
To Serial
Tx Port
÷ 16
÷ 16
1
IBRG
CLOCK
IBRG
CLOCK
RBCK
BDRCON.2
TBCK
BDRCON.3
Figure 126. Baud Rate Formulas (Modes 1 and 3)
2SMOD1 ⋅ FPER
2SMOD1 ⋅ FPER
6 ⋅ 32 ⋅ (256 -TH1)
Baud_Rate=
Baud_Rate=
TH1= 256 -
6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
192 ⋅ Baud_Rate
BRL= 256 -
a. IBRG Formula
b. T1 Formula
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Table 159. Internal Baud Rate Generator Value
FPER = 6 MHz(1)
FPER = 8 MHz(1)
FPER = 10 MHz(1)
Baud Rate
115200
57600
38400
19200
9600
SPD
SMOD1
BRL
-
Error %
-
SPD
SMOD1
BRL
-
Error %
-
SPD
SMOD1
BRL
-
Error %
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
247
243
230
204
152
3.55
0.16
0.16
0.16
0.16
1
1
1
1
1
1
1
1
1
1
245
240
223
191
126
1.36
1.73
1.36
0.16
0.16
1
1
1
1
1
1
1
1
246
236
217
178
2.34
2.34
0.16
0.16
4800
F
PER = 12 MHz(2)
FPER = 16 MHz(2)
FPER = 20 MHz(2)
Baud Rate
115200
57600
38400
19200
9600
SPD
SMOD1
BRL
-
Error %
-
SPD
SMOD1
BRL
247
239
230
204
152
48
Error %
3.55
SPD
SMOD1
BRL
245
234
223
191
126
126
Error %
1.36
-
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
243
236
217
178
100
0.16
2.34
0.16
0.16
0.16
2.12
1.36
0.16
1.36
0.16
0.16
0.16
0.16
4800
0.16
0.16
Notes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.
2. These frequencies are achieved in X2 mode, FPER = FOSC
.
Baud Rate Selection (Mode 2) In mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the
peripheral clock frequency.
As shown in Figure 127 the selection is done using SMOD1 bit in PCON register.
Figure 128 gives the baud rate calculation formula depending on the selection.
Figure 127. Baud Rate Generator Selection (Mode 2)
PER
CLOCK
÷ 2
0
1
÷ 16
To Serial Port
SMOD1
PCON.7
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AT8xC51SND2C
Figure 128. Baud Rate Formula (Mode 2)
2SMOD1 ⋅ FPER
Baud_Rate=
32
Multiprocessor
Communication (Modes
2 and 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To
enable this feature, set SM2 bit in SCON register. When the multiprocessor communica-
tion feature is enabled, the serial Port can differentiate between data frames (ninth bit
clear) and address frames (ninth bit set). This allows the AT8xC51SND2C to function as
a slave processor in an environment where multiple slave processors share a single
serial line.
When the multiprocessor communication feature is enabled, the receiver ignores frames
with the ninth bit clear. The receiver examines frames with the ninth bit set for an
address match. If the received address matches the slaves address, the receiver hard-
ware sets RB8 and RI bits in SCON register, generating an interrupt.
The addressed slave’s software then clears SM2 bit in SCON register and prepares to
receive the data Bytes. The other slaves are unaffected by these data Bytes because
they are waiting to respond to their own addresses.
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the Serial Port to examine the address of each
incoming command frame. Only when the Serial Port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, the automatic address recognition feature in mode 1 may be enabled. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask Byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask Byte must be
1111 1111b.
For example:
SADDR = 0101 0110b
SADEN = 1111 1100b
Given = 0101 01XXb
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The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR = 1111 0001b
SADEN = 1111 1010b
Given = 1111 0X0Xb
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 0XX1b
Slave C:SADDR = 1111 0011b
SADEN = 1111 1101b
Given = 1111 00X1b
The SADEN Byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-
municate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000B).
For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011B).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001B).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR = 0101 0110b
SADEN = 1111 1100b
(SADDR | SADEN)=1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh.
The following is an example of using broadcast addresses:
Slave A:SADDR = 1111 0001b
SADEN = 1111 1010b
Given = 1111 1X11b,
Slave B:SADDR = 1111 0011b
SADEN = 1111 1001b
Given = 1111 1X11b,
Slave C:SADDR = 1111 0010b
SADEN = 1111 1101b
Given = 1111 1111b,
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send the address FFh.
To communicate with slaves A and B, but not slave C, the master must send the
address FBh.
Reset Address
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb(all don’t care bits). This ensures that the Serial
Port is backwards compatible with the 80C51 microcontrollers that do not support auto-
matic address recognition.
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AT8xC51SND2C
Interrupt
The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in
SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 129 these
flags are combined together to appear as a single interrupt source for the C51 core.
Flags must be cleared by software when executing the serial interrupt service routine.
The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts
are globally enabled by setting EA bit in IEN0 register.
Depending on the selected mode and weather the framing error detection is enabled or
disabled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 130.
Figure 129. Serial I/O Interrupt System
SCON.0
RI
Serial I/O
Interrupt Request
TI
ES
IEN0.4
SCON.1
Figure 130. Interrupt Waveforms
a. Mode 1
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start Bit
8-bit Data
Stop Bit
RI
SMOD0 = X
FE
SMOD0 = 1
b. Mode 2 and 3
RXD
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start bit
9-bit data
Stop bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
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Registers
Table 160. SCON Register
SCON (S:98h) – Serial Control Register
7
6
5
4
3
2
1
0
FE/SM0
OVR/SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic Description
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
FE
7
Serial Port Mode Bit 0
Refer to Table 158 for mode selection.
SM0
SM1
Serial Port Mode Bit 1
Refer to Table 158 for mode selection.
6
5
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address
recognition features.
SM2
Clear to disable the multiprocessor communication and automatic address
recognition features.
Receiver Enable Bit
4
3
REN
TB8
Set to enable reception.
Clear to disable reception.
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit
received.
2
RB8
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
Transmit Interrupt Flag
1
0
TI
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
RI
Reset Value = 0000 0000b
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Table 161. SBUF Register
SBUF (S:99h) – Serial Buffer Register
7
6
5
4
3
2
1
0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Bit
Bit
Number
Mnemonic Description
Serial Data Byte
7 - 0
SD7:0
Read the last data received by the serial I/O Port.
Write the data to be transmitted by the serial I/O Port.
Reset value = XXXX XXXXb
Table 162. SADDR Register
SADDR (S:A9h) – Slave Individual Address Register
7
6
5
4
3
2
1
0
SAD7
SAD6
SAD5
SAD4
SAD3
SAD2
SAD1
SAD0
Bit
Bit
Number
Mnemonic Description
7 - 0
SAD7:0 Slave Individual Address
Reset Value = 0000 0000b
Table 163. SADEN Register
SADEN (S:B9h) – Slave Individual Address Mask Byte Register
7
6
5
4
3
2
1
0
SAE7
SAE6
SAE5
SAE4
SAE3
SAE2
SAE1
SAE0
Bit
Bit
Number
Mnemonic Description
7 - 0
SAE7:0 Slave Address Mask Byte
Reset Value = 0000 0000b
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Table 164. BDRCON Register
BDRCON (S:92h) – Baud Rate Generator Control Register
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
M0SRC
Bit
Bit
Number
Mnemonic Description
Reserved
7 - 5
4
-
The value read from these bits are indeterminate. Do not set these bits.
Baud Rate Run Bit
Set to enable the baud rate generator.
Clear to disable the baud rate generator.
BRR
TBCK
RBCK
SPD
Transmission Baud Rate Selection Bit
Set to select the baud rate generator as transmission baud rate generator.
Clear to select the Timer 1 as transmission baud rate generator.
3
2
1
0
Reception Baud Rate Selection Bit
Set to select the baud rate generator as reception baud rate generator.
Clear to select the Timer 1 as reception baud rate generator.
Baud Rate Speed Bit
Set to select high speed baud rate generation.
Clear to select low speed baud rate generation.
Mode 0 Baud Rate Source Bit
M0SRC Set to select the variable baud rate generator in Mode 0.
Clear to select fixed baud rate in Mode 0.
Reset Value = XXX0 0000b
Table 165. BRL Register
BRL (S:91h) – Baud Rate Generator Reload Register
7
6
5
4
3
2
1
0
BRL7
BRL6
BRL5
BRL4
BRL3
BRL2
BRL1
BRL0
Bit
Bit
Number
Mnemonic Description
7 - 0
BRL7:0 Baud Rate Reload Value
Reset Value = 0000 0000b
180
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Two-wire Interface
(TWI) Controller
The AT8xC51SND2C implements a TWI controller supporting the four standard master
and slave modes with multimaster capability. Thus, it allows connection of slave devices
like LCD controller, audio DAC, etc., but also external master controlling where the
AT8xC51SND2C is used as a peripheral of a host.
The TWI bus is a bi-directional TWI serial communication standard. It is designed prima-
rily for simple but efficient integrated circuit control. The system is comprised of 2 lines,
SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs con-
nected to them. The serial data transfer is limited to 100 Kbit/s in low speed mode,
however, some higher bit rates can be achieved depending on the oscillator frequency.
Various communication configurations can be designed using this bus. Figure 131
shows a typical TWI bus configuration using the AT8xC51SND2C in master and slave
modes. All the devices connected to the bus can be master and slave.
Figure 131. Typical TWI Bus Configuration
HOST
Microprocessor
AT8xC51SND2C
Master/Slave
LCD
Display
Audio
DAC
Rp Rp
SCL
SDA
SCL
SDA
Description
The CPU interfaces to the TWI logic via the following four 8-bit special function regis-
ters: the Synchronous Serial Control register (SSCON SFR, see Table 174), the
Synchronous Serial Data register (SSDAT SFR, see Table 176), the Synchronous
Serial Status register (SSSTA SFR, see Table 175) and the Synchronous Serial
Address register (SSADR SFR, see Table 177).
SSCON is used to enable the controller, to program the bit rate (see Table 174), to
enable slave modes, to acknowledge or not a received data, to send a START or a
STOP condition on the TWI bus, and to acknowledge a serial interrupt. A hardware
reset disables the TWI controller.
SSSTA contains a status code which reflects the status of the TWI logic and the TWI
bus. The three least significant bits are always zero. The five most significant bits con-
tains the status code. There are 26 possible status codes. When SSSTA contains F8h,
no relevant state information is available and no serial interrupt is requested. A valid sta-
tus code is available in SSSTA after SSI is set by hardware and is still present until SSI
has been reset by software. Table 167 to Table 136 give the status for both master and
slave modes and miscellaneous states.
SSDAT contains a Byte of serial data to be transmitted or a Byte which has just been
received. It is addressable while it is not in process of shifting a Byte. This occurs when
TWI logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains
stable as long as SSI is set. While data is being shifted out, data on the bus is simulta-
neously shifted in; SSDAT always contains the last Byte present on the bus.
SSADR may be loaded with the 7 - bit slave address (7 most significant bits) to which
the controller will respond when programmed as a slave transmitter or receiver. The
LSB is used to enable general call address (00h) recognition.
Figure 132 shows how a data transfer is accomplished on the TWI bus.
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Figure 132. Complete Data Transfer on TWI Bus
SDA
MSB
Slave Address
R/W
ACK
Nth data Byte
ACK
signal
from
direction signal
bit
from
receiver
receiver
1
2
8
9
1
2
8
9
SCL
S
P/S
Clock Line Held Low While Serial Interrupts Are Serviced
The four operating modes are:
•
•
•
•
Master transmitter
Master receiver
Slave transmitter
Slave receiver
Data transfer in each mode of operation are shown in Figure 133 through Figure 136.
These figures contain the following abbreviations:
A
Acknowledge bit (low level at SDA)
Not acknowledge bit (high level on SDA)
8-bit data Byte
A
Data
S
START condition
P
STOP condition
MR
MT
SLA
GCA
R
Master Receive
Master Transmit
Slave Address
General Call Address (00h)
Read bit (high level at SDA)
Write bit (low level at SDA)
W
In Figure 133 through Figure 136, circles are used to indicate when the serial interrupt
flag is set. The numbers in the circles show the status code held in SSSTA. At these
points, a service routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is suspended until the
serial interrupt flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSSTA is used to branch
to the appropriate service routine. For each status code, the required software action
and details of the following serial transfer are given in Table 167 through Table 136.
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AT8xC51SND2C
Bit Rate
The bit rate can be selected from seven predefined bit rates or from a programmable bit
rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see
Table 174). The predefined bit rates are derived from the peripheral clock (FPER) issued
from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate
generator is based on timer 1 overflow output.
Table 166. Serial Clock Rates
SSCRx
Bit Frequency (kHz)
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
FPER = 6 MHz
FPER = 8 MHz
62.5
FPER = 10 MHz
78.125
89.3
F
PER Divided By
47
53.5
62.5
75
128
112
96
71.5
83
104.2(1)
125(1)
100
80
12.5
100
16.5
20.83
480
60
133.3(1)
266.7(1)
166.7(1)
333.3(1)
200(1)
30
0.5 < ⋅ < 125(1) 0.67 < ⋅ < 166.7(1) 0.81 < ⋅ < 208.3(1) 96 ⋅ (256 – reload value Timer 1)
Note:
1. These bit rates are outside of the low speed standard specification limited to 100 kHz
but can be used with high speed TWI components limited to 400 kHz.
Master Transmitter Mode
In the master transmitter mode, a number of data Bytes are transmitted to a slave
receiver (see Figure 133). Before the master transmitter mode can be entered, SSCON
must be initialized as follows:
SSCR2
Bit Rate
SSPE
1
SSSTA
0
SSSTO
0
SSI
0
SSAA
X
SSCR1
Bit Rate
SSCR0
Bit Rate
SSCR2:0 define the serial bit rate (see Table 166). SSPE must be set to enable the con-
troller. SSSTA, SSSTO and SSI must be cleared.
The master transmitter mode may now be entered by setting the SSSTA bit. The TWI
logic will now monitor the TWI bus and generate a START condition as soon as the bus
becomes free. When a START condition is transmitted, the serial interrupt flag (SSI bit
in SSCON) is set, and the status code in SSSTA is 08h. This status must be used to
vector to an interrupt routine that loads SSDAT with the slave address and the data
direction bit (SLA+W). The serial interrupt flag (SSI) must then be cleared before the
serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowl-
edgment bit has been received, SSI is set again and a number of status code in SSSTA
are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if
the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for
each of these status code is detailed in Table 167. This scheme is repeated until a
STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in
Table 167. After a repeated START condition (state 10h) the controller may switch to
the master receiver mode by loading SSDAT with SLA+R.
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Master Receiver Mode
In the master receiver mode, a number of data Bytes are received from a slave transmit-
ter (see Figure 134). The transfer is initialized as in the master transmitter mode. When
the START condition has been transmitted, the interrupt routine must load SSDAT with
the 7 - bit slave address and the data direction bit (SLA+R). The serial interrupt flag
(SSI) must then be cleared before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowl-
edgment bit has been received, the serial interrupt flag is set again and a number of
status code in SSSTA are possible. There are 40h, 48h or 38h for the master mode and
also 68h, 78h or B0h if the slave mode was enabled (SSAA = logic 1). The appropriate
action to be taken for each of these status code is detailed in Table 136. This scheme is
repeated until a STOP condition is transmitted.
SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in
Table 136. After a repeated START condition (state 10h) the controller may switch to
the master transmitter mode by loading SSDAT with SLA+W.
Slave Receiver Mode
In the slave receiver mode, a number of data Bytes are received from a master transmit-
ter (see Figure 135). To initiate the slave receiver mode, SSADR and SSCON must be
loaded as follows:
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
SSGC
X
←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Own Slave Address
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→
The upper 7 bits are the addresses to which the controller will respond when addressed
by a master. If the LSB (SSGC) is set, the controller will respond to the general call
address (00h); otherwise, it ignores the general call address.
SSCR2
X
SSPE
1
SSSTA
0
SSSTO
0
SSI
0
SSAA
1
SSCR1
X
SSCR0
X
SSCR2:0 have no effect in the slave mode. SSPE must be set to enable the controller.
The SSAA bit must be set to enable the own slave address or the general call address
acknowledgment. SSSTA, SSSTO and SSI must be cleared.
When SSADR and SSCON have been initialized, the controller waits until it is
addressed by its own slave address followed by the data direction bit which must be
logic 0 (W) for operating in the slave receiver mode. After its own slave address and the
W bit has been received, the serial interrupt flag is set and a valid status code can be
read from SSSTA. This status code is used to vector to an interrupt service routine, and
the appropriate action to be taken for each of these status code is detailed in Table 136
and Table 171. The slave receiver mode may also be entered if arbitration is lost while
the controller is in the master mode (see states 68h and 78h).
If the SSAA bit is reset during a transfer, the controller will return a not acknowledge
(logic 1) to SDA after the next received data Byte. While SSAA is reset, the controller
does not respond to its own slave address. However, the TWI bus is still monitored and
address recognition may be resumed at any time by setting SSAA. This means that the
SSAA bit may be used to temporarily isolate the controller from the TWI bus.
184
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AT8xC51SND2C
Slave Transmitter Mode
In the slave transmitter mode, a number of data Bytes are transmitted to a master
receiver (see Figure 136). Data transfer is initialized as in the slave receiver mode.
When SSADR and SSCON have been initialized, the controller waits until it is
addressed by its own slave address followed by the data direction bit which must be
logic 1 (R) for operating in the slave transmitter mode. After its own slave address and
the R bit have been received, the serial interrupt flag is set and a valid status code can
be read from SSSTA. This status code is used to vector to an interrupt service routine,
and the appropriate action to be taken for each of these status code is detailed in
Table 171. The slave transmitter mode may also be entered if arbitration is lost while the
controller is in the master mode (see state B0h).
If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the
transfer and enter state C0h or C8h. The controller is switched to the not addressed
slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-
ter receiver receives all 1’s as serial data. While SSAA is reset, the controller does not
respond to its own slave address. However, the TWI bus is still monitored and address
recognition may be resumed at any time by setting SSAA. This means that the SSAA bit
may be used to temporarily isolate the controller from the TWI bus.
Miscellaneous States
There are 2 SSSTA codes that do not correspond to a defined TWI hardware state (see
Table 172). These are discussed below.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not yet set. This occurs between other states and when the controller is not
involved in a serial transfer.
Status 00h indicates that a bus error has occurred during a serial transfer. A bus error is
caused when a START or a STOP condition occurs at an illegal position in the format
frame. Examples of such illegal positions are during the serial transfer of an address
Byte, a data Byte, or an acknowledge bit. When a bus error occurs, SSI is set. To
recover from a bus error, the SSSTO flag must be set and SSI must be cleared. This
causes the controller to enter the not addressed slave mode and to clear the SSSTO
flag (no other bits in S1CON are affected). The SDA and SCL lines are released and no
STOP condition is transmitted.
Note:
The TWI controller interfaces to the external TWI bus via 2 port 1 pins: P1.6/SCL (serial
clock line) and P1.7/SDA (serial data line). To avoid low level asserting and conflict on
these lines when the TWI controller is enabled, the output latches of P1.6 and P1.7 must
be set to logic 1.
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Figure 133. Format and States in the Master Transmitter Mode
MT
Successful transmis-
sion to a slave receiver
S
SLA
W
A
Data
A
P
08h
18h
28h
Next transfer started with
a repeated start condition
S
SLA
W
R
10h
Not acknowledge received
after the slave address
A
P
MR
20h
Not acknowledge received
after a data Byte
A
P
30h
Arbitration lost in slave
address or data Byte
Other master
continues
Other master
continues
A or A
A or A
38h
A
38h
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
68h 78h B0h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
nnh
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
186
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AT8xC51SND2C
Figure 134. Format and States in the Master Receiver Mode
MR
Successful reception
from a slave transmitter
S
SLA
R
A
Data
A
Data
A
P
08h
40h
50h
58h
Next transfer started with
a repeated start condition
S
SLA
R
10h
W
Not acknowledge received
after the slave address
A
P
MT
48h
Arbitration lost in slave
address or data Byte
Other master
continues
Other master
continues
A or A
A
38h
A
38h
Arbitration lost and
addressed as slave
Other master
continues
To corresponding
states in slave mode
68h 78h B0h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
nnh
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
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Figure 135. Format and States in the Slave Receiver Mode
Reception of the own slave
address and one or more
S
SLA
W
A
Data
A
Data
A
P or S
data Bytes.
All are acknowledged
60h
80h
80h A0h
Last data Byte received
is not acknowledged
A
P or S
88h
Arbitration lost as master and
addressed as slave
A
68h
A
Reception of the general call
address and one or more data Bytes
General Call
Data
A
Data
A
P or S
70h
90h
90h A0h
Last data Byte received
is not acknowledged
A
P or S
98h
Arbitration lost as master and
addressed as slave by general call
A
78h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
nnh
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
188
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4341D–MP3–04/05
AT8xC51SND2C
Figure 136. Format and States in the Slave Transmitter Mode
Reception of the own slave
address and transmission
of one or more data Bytes.
S
SLA
R
A
Data
A
Data
A
P or S
A8h
A
B8h
C0h
Arbitration lost as master and
addressed as slave
B0h
Last data Byte transmitted.
Switched to not addressed
slave (SSAA = 0).
A
All 1’s P or S
C8h
Any number of data Bytes and their associated
acknowledge bits
From master to slave
From slave to master
Data
A
This number (contained in SSSTA) corresponds
to a defined state of the TWI bus
nnh
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Table 167. Status for Master Transmitter Mode
Application Software Response
To SSCON
SSSTO SSI
Status
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
A START condition has Write SLA+W
been transmitted
SLA+W will be transmitted.
X
08h
X
0
0
Write SLA+W
SLA+W will be transmitted.
X
X
X
0
0
0
0
A repeated START
condition has been
10h
Write SLA+R
transmitted
SLA+R will be transmitted.
X
Logic will switch to master receiver mode
Write data Byte
Data Byte will be transmitted.
X
0
1
0
0
0
1
0
0
0
No SSDAT action
SLA+W has been
Repeated START will be transmitted.
X
No SSDAT action
STOP condition will be transmitted and SSSTO flag
will be reset.
18h
20h
28h
transmitted; ACK has
been received
X
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
Write data Byte
Data Byte will be transmitted.
X
0
1
0
0
0
1
0
0
0
No SSDAT action
SLA+W has been
Repeated START will be transmitted.
X
No SSDAT action
STOP condition will be transmitted and SSSTO flag
will be reset.
transmitted; NOT ACK
X
has been received
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
Write data Byte
Data Byte will be transmitted.
X
0
1
0
0
0
1
0
0
0
No SSDAT action
Repeated START will be transmitted.
X
Data Byte has been
transmitted; ACK has
been received
No SSDAT action
STOP condition will be transmitted and SSSTO flag
will be reset.
X
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
Write data Byte
Data Byte will be transmitted.
X
0
1
0
0
0
1
0
0
0
No SSDAT action
Repeated START will be transmitted.
X
Data Byte has been
transmitted; NOT ACK
No SSDAT action
STOP condition will be transmitted and SSSTO flag
will be reset.
30h
38h
X
has been received
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
No SSDAT action
Arbitration lost in
TWI bus will be released and not addressed slave
mode will be entered.
0
1
0
0
0
0
X
SLA+W or data Bytes
No SSDAT action
A START condition will be transmitted when the bus
becomes free.
X
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AT8xC51SND2C
Table 168. Status for Master Receiver Mode
Application Software Response
To SSCON
SSSTO SSI
Status
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
A START condition has Write SLA+R
been transmitted
SLA+R will be transmitted.
08h
X
0
0
X
Write SLA+R
SLA+R will be transmitted.
X
X
0
0
0
0
X
X
A repeated START
condition has been
10h
Write SLA+W
transmitted
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
No SSDAT action
Arbitration lost in
TWI bus will be released and not addressed slave
mode will be entered.
0
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
38h
40h
SLA+R or NOT ACK
No SSDAT action
bit
A START condition will be transmitted when the bus
becomes free.
No SSDAT action
No SSDAT action
Data Byte will be received and NOT ACK will be
returned.
SLA+R has been
transmitted; ACK has
been received
Data Byte will be received and ACK will be returned.
No SSDAT action
No SSDAT action
Repeated START will be transmitted.
1
0
0
1
0
0
X
X
SLA+R has been
transmitted; NOT ACK
has been received
STOP condition will be transmitted and SSSTO flag
will be reset.
48h
50h
58h
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
0
0
1
0
0
0
0
0
X
0
1
Read data Byte
Read data Byte
Data Byte will be received and NOT ACK will be
returned.
Data Byte has been
received; ACK has
been returned
Data Byte will be received and ACK will be returned.
Read data Byte
Read data Byte
Repeated START will be transmitted.
1
0
0
1
0
0
X
X
Data Byte has been
received; NOT ACK
has been returned
STOP condition will be transmitted and SSSTO flag
will be reset.
Read data Byte
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
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Table 169. Status for Slave Receiver Mode with Own Slave Address
Application Software Response
Status
To SSCON
SSSTO SSI
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
No SSDAT action
X
0
0
0
0
0
1
Data Byte will be received and NOT ACK will be
returned.
Own SLA+W has been
received; ACK has
been returned
60h
68h
No SSDAT action
No SSDAT action
X
Data Byte will be received and ACK will be returned.
Arbitration lost in
Data Byte will be received and NOT ACK will be
returned.
X
X
0
0
0
0
0
1
SLA+R/W as master;
own SLA+W has been
received; ACK has
been returned
No SSDAT action
Data Byte will be received and ACK will be returned.
Previously addressed Read data Byte
with own SLA+W; data
Data Byte will be received and NOT ACK will be
returned.
X
X
0
0
0
0
0
1
80h
has been received;
ACK has been
returned
Read data Byte
Data Byte will be received and ACK will be returned.
Read data Byte
Read data Byte
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Previously addressed
with own SLA+W; data
has been received;
NOT ACK has been
returned
Read data Byte
Read data Byte
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
88h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
A STOP condition or
repeated START
condition has been
received while still
addressed as slave
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
A0h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
192
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 170. Status for Slave Receiver Mode with General Call Address
Application Software Response
Status
To SSCON
SSSTO SSI
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
General call address
has been received;
ACK has been
returned
No SSDAT action
Data Byte will be received and NOT ACK will be
returned.
X
X
0
0
0
0
0
1
70h
No SSDAT action
Data Byte will be received and ACK will be returned.
Arbitration lost in
SLA+R/W as master;
general call address
has been received;
ACK has been
returned
No SSDAT action
No SSDAT action
Data Byte will be received and NOT ACK will be
returned.
X
X
0
0
0
0
0
1
Data Byte will be received and ACK will be returned.
78h
Previously addressed Read data Byte
with general call; data
Data Byte will be received and NOT ACK will be
returned.
X
X
0
0
0
0
0
1
90h
has been received;
ACK has been
returned
Read data Byte
Data Byte will be received and ACK will be returned.
Read data Byte
Read data Byte
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Previously addressed
with general call; data
has been received;
NOT ACK has been
returned
Read data Byte
Read data Byte
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
98h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
A STOP condition or
repeated START
condition has been
received while still
addressed as slave
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
A0h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
193
4341D–MP3–04/05
Table 171. Status for Slave Transmitter Mode
Application Software Response
To SSCON
SSSTO SSI
Status of the TWI Bus
and TWI Hardware
Status
Code
SSSTA
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
Write data Byte
X
0
0
0
0
0
1
Last data Byte will be transmitted.
Own SLA+R has been
received; ACK has
been returned
A8h
B0h
Write data Byte
Write data Byte
X
Data Byte will be transmitted.
Arbitration lost in
Last data Byte will be transmitted.
X
X
0
0
0
0
0
1
SLA+R/W as master;
own SLA+R has been
received; ACK has
been returned
Write data Byte
Data Byte will be transmitted.
Data Byte in SSDAT
has been transmitted;
ACK has been
Write data Byte
Write data Byte
Last data Byte will be transmitted.
Data Byte will be transmitted.
X
X
0
0
0
0
0
1
B8h
received
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Data Byte in SSDAT
has been transmitted;
NOT ACK has been
received
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
C0h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA.
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1.
Last data Byte in
SSDAT has been
transmitted
(SSAA= 0); ACK has
been received
No SSDAT action
No SSDAT action
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START condition
will be transmitted when the bus becomes free.
C8h
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own
SLA will be recognized; GCA will be recognized if
SSGC = logic 1. A START condition will be
transmitted when the bus becomes free.
Table 172. Status for Miscellaneous States
Application Software Response
Status
To SSCON
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSSTO
SSI
SSAA Next Action Taken by TWI Hardware
No relevant state
No SSDAT action
Wait or proceed current transfer.
F8h
00h
information available;
SSI = 0
No SSCON action
Bus error due to an
illegal START or STOP
condition
No SSDAT action
Only the internal hardware is affected, no STOP
condition is sent on the bus. In all cases, the bus is
released and SSSTO is reset.
0
1
0
X
194
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Registers
Table 173. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
-
4
3
2
1
0
SDA
SCL
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Bit
Bit
Number
Mnemonic
Description
TWI Serial Data
7
6
SDA
SDA is the bidirectional Two Wire data line.
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
SCL
Audio DAC Control
5:1
0
Refer to Audio DAC interface section
KIN0
Keyboard Input Line
Reset Value = 1111 1111b
Table 174. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
7
6
5
4
3
2
1
0
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
195
4341D–MP3–04/05
Bit
Bit
Number
Mnemonic Description
Synchronous Serial Control Rate Bit 2
Refer to Table 166 for rate description.
7
6
SSCR2
SSPE
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
5
4
3
SSSTA
SSSTO
SSI
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if
SSGC set) is recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Master Transmitter Mode in progress
2
SSAA
This bit has no specific effect when in master transmitter mode.
Slave Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Slave Transmitter Mode in progress
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
Synchronous Serial Control Rate Bit 1
Refer to Table 166 for rate description.
1
0
SSCR1
SSCR0
Synchronous Serial Control Rate Bit 0
Refer to Table 166 for rate description.
Reset Value = 0000 0000b
196
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Table 175. SSSTA Register
SSSTA (S:94h) – Synchronous Serial Status Register
7
6
5
4
3
2
0
1
0
0
0
SSC4
SSC3
SSC2
SSC1
SSC0
Bit
Bit
Number
Mnemonic Description
Synchronous Serial Status Code Bits 0 to 4
Refer to Table 167 to Table 136 for status description.
7:3
2:0
SSC4:0
0
Always 0.
Reset Value = F8h
Table 176. SSDAT Register
SSDAT (S:95h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SSD7
SSD6
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Bit
Bit
Number
Mnemonic Description
Synchronous Serial Address bits 7 to 1 or Synchronous Serial Data Bits 7
to 1
7:1
0
SSD7:1
SSD0
Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0
Reset Value = 1111 1111b
Table 177. SSADR Register
SSADR (S:96h) – Synchronous Serial Address Register
7
6
5
4
3
2
1
0
SSA7
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSGC
Bit
Bit
Number
Mnemonic Description
7:1
0
SSA7:1
SSGC
Synchronous Serial Slave Address Bits 7 to 1
Synchronous Serial General Call Bit
Set to enable the general call address recognition.
Clear to disable the general call address recognition.
Reset Value = 1111 1110b
197
4341D–MP3–04/05
Keyboard Interface
The AT8xC51SND2C implement a keyboard interface allowing the connection of a key-
pad. It is based on one input with programmable interrupt capability on both high or low
level. This input allows exit from idle and power down modes.
Description
The keyboard interfaces with the C51 core through 2 special function registers: KBCON,
the keyboard control register (see Table 179); and KBSTA, the keyboard control and
status register (see Table 180).
An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the key-
board interrupt (see Figure 137). As detailed in Figure 138 this keyboard input has the
capability to detect a programmable level according to KINL0 bit value in KBCON regis-
ter. Level detection is then reported in interrupt flag KINF0 in KBSTA register.
A keyboard interrupt is requested each time this flag is set. This flag can be masked by
software using KINM0 bits in KBCON register and is cleared by reading KBSTA register.
Figure 137. Keyboard Interface Block Diagram
Keyboard Interface
Interrupt Request
KIN0
Input Circuitry
EKB
IEN1.4
Figure 138. Keyboard Input Circuitry
0
1
KIN0
KINF0
KBSTA.0
KINM0
KBCON.0
KINL0
KBCON.4
Power Reduction Mode
KIN0 inputs allow exit from idle and power-down modes as detailed in section “Power
Management”, page 46. To enable this feature, KPDE bit in KBSTA register must be set
to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are
stopped), exit may happen on parasitic key press. In this case, no key is detected and
software must enter power down again.
198
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Registers
Table 178. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
-
4
3
2
1
0
SDA
SCL
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Bit
Bit
Number
Mnemonic
Description
TWI Lines
7:6
Refer to TWI section.
Audio DAC Control
5:1
0
Refer to Audio DAC section.
KIN0
Keyboard Input Interrupt.
Reset Value = 1111 1111b
Table 179. KBCON Register
KBCON (S:A3h) – Keyboard Control Register
7
-
6
-
5
-
4
3
-
2
-
1
-
0
KINL0
KINM0
Bit
Bit
Number
Mnemonic Description
Reserved
Do not set these bits.
7 - 5
4
-
Keyboard Input Level Bit
Set to enable a high level detection on the respective KIN0 input.
Clear to enable a low level detection on the respective KIN0 input.
KINL0
-
Reserved
Do not reset these bits.
3 - 1
0
Keyboard Input Mask Bit
Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.
Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.
KINM0
Reset Value = 0000 1111b
Table 180. KBSTA Register
KBSTA (S:A4h) – Keyboard Control and Status Register
7
6
-
5
-
4
-
3
-
2
-
1
-
0
KPDE
KINF0
Bit
Bit
Number
Mnemonic Description
Keyboard Power Down Enable Bit
7
KPDE
Set to enable exit of power down mode by the keyboard interrupt.
Clear to disable exit of power down mode by the keyboard interrupt.
199
4341D–MP3–04/05
Bit
Bit
Number
Mnemonic Description
Reserved
6 - 1
0
-
The value read from these bits is always 0. Do not set these bits.
Keyboard Input Interrupt Flag
Set by hardware when the KIN0 input detects a programmed level.
Cleared when reading KBSTA.
KINF0
Reset Value = 0000 0000b
200
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Electrical Characteristics
Absolute Maximum Rating
*NOTICE:
Stressing the device beyond the “Absolute Maxi-
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Storage Temperature......................................... -65 to +150°C
Voltage on any other Pin to VSS .................................... -0.3 to +4.0 V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation............................................................. 1 W
Operating Conditions
Ambient Temperature Under Bias........................ -40 to +85°C
VDD ......................................................................................................... 2.7 to 3.3V
DC Characteristics
Digital Logic
Table 181. Digital DC Characteristics
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
-0.5
Typ(1)
Max
0.2·VDD - 0.1
VDD
Units
Test Conditions
VIL
Input Low Voltage
V
V
V
(2)
VIH1
Input High Voltage (except RST, X1)
Input High Voltage (RST, X1)
0.2·VDD + 1.1
0.7·VDD
VIH2
VDD + 0.5
Output Low Voltage
VOL1
(except P0, ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
0.45
0.45
V
I
I
OL= 1.6 mA
OL= 3.2 mA
Output Low Voltage
(P0, ALE, MCMD, MDAT, MCLK, SCLK,
DCLK, DSEL, DOUT)
VOL2
V
V
Output High Voltage
(P1, P2, P3, P4 and P5)
VOH1
V
V
DD - 0.7
IOH= -30 µA
Output High Voltage
(P0, P2 address mode, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT, D+, D-)
VOH2
DD - 0.7
V
IOH= -3.2 mA
Logical 0 Input Current (P1, P2, P3, P4
and P5)
IIL
-50
10
µA
µA
µA
VIN= 0.45 V
0.45< VIN< VDD
VIN= 2.0 V
Input Leakage Current (P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT)
ILI
Logical 1 to 0 Transition Current
(P1, P2, P3, P4 and P5)
ITL
-650
200
RRST
CIO
Pull-Down Resistor
Pin Capacitance
50
90
10
kΩ
pF
V
TA= 25°C
VRET
VDD Data Retention Limit
1.8
201
4341D–MP3–04/05
Table 181. Digital DC Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
Parameter
Min
Typ(1)
Max
Units
Test Conditions
V
DD < 3.3 V
X1 / X2 mode
7/ 11.5
9/ 14.5
10.5 / 18
AT89C51SND2C
Operating Current
12 MHz
16 MHz
20 MHz
(3)
mA
IDD
V
DD < 3.3 V
X1 / X2 mode
7/ 11.5
9/ 14.5
10.5 / 18
AT83SND2C
Operating Current
12 MHz
16 MHz
20 MHz
mA
mA
mA
V
DD < 3.3 V
X1 / X2 mode
6.3 / 9.1
7.4 / 11.3
8.5 / 14
AT89C51SND2C
Idle Mode Current
12 MHz
16 MHz
20 MHz
(3)
IDL
V
DD < 3.3 V
X1 / X2 mode
6.3 / 9.1
7.4 / 11.3
8.5 / 14
AT83SND2C
Idle Mode Current
12 MHz
16 MHz
20 MHz
AT89C51SND2C
Power-Down Mode Current
20
20
500
500
+15
µA
µA
V
V
V
RET < VDD < 3.3 V
RET < VDD < 3.3 V
DD < 3.3 V
IPD
AT83SND2C
Power-Down Mode Current
AT89C51SND2C
Flash Programming Current
IFP
mA
Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and
there is no guarantee on these values.
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.
3. See Table 182 for typical consumption in player mode.
Table 182. Typical Reference Design AT89C51SND2C Power Consumption
Player Mode
IDD
Test Conditions
AT89C51SND2C at 16 MHz, X2 mode, VDD= 3 V
No song playing.
Stop
10 mA
This consumption does not include AUDVBAT current.
AT89C51SND2C at 16 MHz, X2 mode, VDD= 3 V
MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
Playing
37 mA
This consumption does not include AUDVBAT current.
202
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
IDD, IDL and IPD Test Conditions
Figure 139. IDD Test Condition, Active Mode
VDD
VDD
RST
VDD
PVDD
IDD
UVDD
AUDVDD
(NC)
Clock Signal
X2
X1
VDD
P0
VSS
PVSS
UVSS
AUDVSS
TST
VSS
All other pins are unconnected
Figure 140. IDL Test Condition, Idle Mode
VDD
VDD
PVDD
UVDD
IDL
RST
VSS
AUDVDD
(NC)
Clock Signal
X2
X1
VDD
P0
VSS
PVSS
UVSS
AUDVSS
TST
VSS
All other pins are unconnected
Figure 141. IPD Test Condition, Power-Down Mode
VDD
VDD
PVDD
UVDD
IPD
RST
VSS
AUDVDD
VDD
(NC)
X2
X1
P0
MCMD
MDAT
TST
VSS
PVSS
UVSS
AUDVSS
VSS
All other pins are unconnected
203
4341D–MP3–04/05
Oscillator & Crystal
Schematic
Figure 142. Crystal Connection
X1
X2
C1
C2
Q
VSS
Note:
For operation with most standard crystals, no external components are needed on X1
and X2. It may be necessary to add external capacitors on X1 and X2 to ground in spe-
cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 183. Oscillator & Crystal Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
CX1
CX2
CL
Parameter
Internal Capacitance (X1 - VSS)
Internal Capacitance (X2 - VSS)
Equivalent Load Capacitance (X1 - X2)
Drive Level
Min
Typ
10
10
5
Max
Unit
pF
pF
pF
DL
50
20
40
6
µW
MHz
Ω
F
Crystal Frequency
RS
Crystal Series Resistance
Crystal Shunt Capacitance
CS
pF
Phase Lock Loop
Schematic
Figure 143. PLL Filter Connection
FILT
R
C2
C1
VSS
VSS
Parameters
Table 184. PLL Filter Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
R
Parameter
Min
Typ
100
10
Max
Unit
Ω
Filter Resistor
C1
Filter Capacitance 1
Filter Capacitance 2
nF
nF
C2
2.2
204
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
USB Connection
Schematic
Figure 144. USB Connection
To Power Supply
RUSB
VBUS
D+
D-
D+
D-
RUSB
GND
VSS
Parameters
Table 185. USB Termination Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
Parameter
USB Termination Resistor
Min
Typ
Max
Unit
RUSB
27
Ω
DAC and PA
Electrical Specifications
PA
AUDVBAT = 3.6V, TA = 25°C unless otherwise noted.
High power mode, 100nF capacitor connected between CBP and AUDVSS, 470nF input
capacitors, Load = 8 ohms.
Figure 145. PA Specification
Symbol
Parameter
Conditions
Min
3.2
-
Typ
Max
5.5
8
Unit
V
AUDVBAT Supply Voltage
-
IDD
IDDstby
VCBP
VOS
ZIN
Quiescent Current
Standby Current
DC Reference
Inputs shorted, no load
6
mA
µA
V
Capacitance
-
-
2
-
AUDVBAT/2
-
Output differential offset
Input impedance
Output load
full gain
-20
12K
6
0
20k
8
20
30k
32
300
100
mV
W
Active state
ZLFP
ZLLP
CL
Full Power mode
Low-Power mode
W
Output load
100
-
150
-
W
Capacitive load
pF
200 – 2kHz
PSRR
BW
Power supply rejection ratio
Output Frequency bandwidth
-
60
-
-
dB
Hz
Differential output
1KHz reference frequency
3dB attenuation.
50
20000
470nF input coupling capacitors
Off to on mode. Voltage already settled.
Input capacitors precharged
tUP
VN
Output setup time
Output noise
-
-
-
10
ms
Max gain, A weighted
120
500
µVRMS
205
4341D–MP3–04/05
Symbol
Parameter
Output distortion
Conditions
Min
Typ
Max
Unit
High power mode, VDD = 3.2V, 1KHz,
Pout=100mW, gain=0dB
THDHP
-
50
-
dB
Low power mode, VDD = 3.2V , 1KHz,
Vout= 100mVpp, Max gain, load 8 ohms in
serie with 200 ohms
THDLP
Output distortion
-
1
-
%
GACC
Overall Gain accuracy
Gain Step Accuracy
-2
0
0
2
dB
dB
GSTEP
-0.7
0.7
Figure 146. Maximum Dissipated Power Versus Power Supply
600
550
500
450
400
350
300
250
200
8 Ohms load
6.5 Ohms load
3,2
3,4
3,6
3,8
4
4,2
Supply Voltage AUDVBAT [V]
Figure 147. Dissipated Power vs Output Power, AUDVBAT = 3.2V
600
550
500
450
400
350
300
250
200
150
100
50
8 Ohms load
6.5 Ohms load
0
0
100 200
300
400 500
600 700
800
Output Power [mW]
206
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
DAC
AUDVDD, HSVDD = 2.8 V, Ta=25°C, typical case, unless otherwise noted
All noise and distortion specifications are measured in the 20 Hz to 0.425xFs and A-
weighted filtered.
Full Scale levels scale proportionally with the analog supply voltage.
Figure 148. Audio DAC Specification
OVERALL
MIN
-40
2.7
2.4
3.2
TYP
+25
2.8
2.8
-
MAX
+125
3.3
UNITS
Operating Temperature
Analog Supply Voltage (AUDVDD, HSVDD)
Digital Supply Voltage (VDD)
Audio Amplifier Supply (AUDVBAT)
DIGITAL INPUTS/OUTPUTS
Resolution
°C
V
3.3
V
5.5
V
20
Bits
Logic Family
CMOS
Logic Coding
2’s Complement
ANALOG PERFORMANCE – DAC to Line-out/Headphone Output
Output level for full scale input
1.65
Vpp
V
(for AUDVDD, HSVDD = 2.8 V)
Output common mode voltage
0.5xHSVDD
Output load resistance (on HSL, HSR)
- Headphone load
- Line load
16
32
10
Ohm
kOhm
Output load capacitance (on HSL, HSR)
- Headphone load
30
30
1000
150
pF
pF
- Line load
Signal to Noise Ratio
(–1dBFS @ 1kHz input and 0dB Gain)
- Line and Headphone loads
87
92
dB
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0dB
Gain)
- Line Load
-80
-65
-40
dB
dB
dB
-76
-60
- Headphone Load
- Headphone Load (16 Ohm)
Dynamic Range (measured with -60 dBFS @ 1kHz input,
extrapolated to full-scale)
- Line Load
88
70
93
74
dB
dB
- Headphone Load
Interchannel mismatch
0.1
-90
-
1
dB
dB
dB
dB
Left-channel to right-channel crosstalk (@ 1kHz)
Output Power Level Control Range
Output Power Level Control Step
-80
6
-6
3
207
4341D–MP3–04/05
OVERALL
MIN
TYP
MAX
UNITS
PSRR
- 1kHz
- 20kHz
55
50
dB
dB
Maximum output slope at power up (100 to 220F coupling
capacitor)
3
V/s
ANALOG PERFORMANCE – Line-in/Microphone Input to Line-out/Headphone Output
Input level for full scale output - 0dBFS Level
1.65
Vpp
@ AUDVDD, HSVDD = 2.8 V and 0 dB gain
583
mVrms
Vpp
0.165
@ AUDVDD, HSVDD = 2.8 V and 20 dB gain
58.3
mVrms
0.5xAUDVD
D
Input common mode voltage
V
Input impedance
7
10
kOhm
Signal to Noise Ratio
-1 dBFS @ 1kHz input and 0 dB gain
-21 dBFS @ 1kHz input and 20 dB gain
81
85
71
dB
dB
dB
Dynamic Range (extrapolated to full scale level)
-60 dBFS @ 1kHz input and 0 dB gain
-60 dBFS @ 1kHz input and 20 dB gain
82
86
72
Total Harmonic Distortion
–1dBFS @ 1kHz input and 0 dB gain
–1dBFS @ 1kHz input and 20 dB gain
-80
-75
-76
-68
Interchannel mismatch
0.1
-90
1
dB
dB
Left-channel to right-channel crosstalk (@ 1kHz)
-80
ANALOG PERFORMANCE – Differential mono input amplifier
Differential input level for full scale output - 0dBFS Level
1.65
583
Vppdif
@ AUDVDD, HSVDD = 2.8 V and 0 dB gain
mVrms
0.5xAUDVD
D
Input common mode voltage
V
Input impedance
7
10
80
kOhm
dB
Signal to Noise Ratio (-1 dBFS @ 1kHz input and 0 dB
gain)
76
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0 dB
gain)
-85
-81
dB
ANALOG PERFORMANCE – PA Driver
Differential output level for full scale input (for AUDVDD,
HSVDD = 3 V)
3.3
Vppdif
V
Output common mode voltage
Output load
0.5xHSVDD
kOhm
pF
10
30
208
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
OVERALL
MIN
TYP
MAX
UNITS
Signal to Noise Ratio (–1dBFS @ 1kHz input and 0dB
Gain)
76
80
dB
Total Harmonic Distortion (–1dBFS @ 1kHz input and 0dB
Gain)
-75
-71
1.5
dB
MASTER CLOCK
Master clock Maximum Long Term Jitter
DIGITAL FILTER PERFORMANCE
Frequency response (10 Hz to 20 kHz)
Deviation from linear phase (10 Hz to 20 kHz)
Passband 0.1 dB corner
nspp
+/- 0.1
+/- 0.1
0.4535
dB
deg
Fs
Stopband
0.5465
65
Fs
Stopband Attenuation
dB
DE-EMPHASIS FILTER PERFORMANCE (for 44.1kHz Fs)
Frequency
Gain
Margin
-1dB
Pass band
0Hz to 3180Hz
1dB
1dB
1dB
Logarithm
decay
Transition band
Stop Band
3180Hz to 10600Hz
10600Hz to 20kHz
-10.45dB
Power Performance
Current consumption from Audio Analog supply AVDD,
HSVDD in power on
9.5
mA
Current consumption from Audio Analog supply AVDD,
HSVDD in power down
10
µA
Power on Settling Time
- From full Power Down to Full Power Up (AUDVREF and
AUDVCM decoupling capacitors charge)
500
50
ms
ms
ms
- Linein amplifier (Line-in coupling capacitors charge)
- Driver amplifier (out driver DC blocking capacitors
charge)
500
209
4341D–MP3–04/05
Digital Filters Transfer
Function
Figure 149. Channel Filter
Figure 150. De-emphasis Filter
0
-2
-4
Gain
-6
(dB)
-8
-10
-12
103
104
Frequency (Hz)
210
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Audio DAC and PA Connection
Figure 151. DAC and PA Connection
PAINN
Audio Dac and
PA Connection
3V from LDO
C17
VDD
AUDVSS
AUDVSS
AUDVBAT
CBP
Battery
3.2V
to
5.5V
C16
VSS
3V from LDO
AUDVDD
C7
HPP
AUDVSS
C18
8 Ohm
Loud Speaker
AUDVSS
HPN
HSVDD
C19
LPHN
R1
C15
HSVSS
C9
PAINP
MONOP
MONON
LINER
AUDVREF
AUDVCM
VSS
C11
AUDVSS
C12
C8
C3
R
L
Stereo
Line Input
LINEL
mono input
(+)
Mono
AUXP
AUXN
HSR
Differential
Input
AUDVSS
mono input
(-)
C1
C6
C4
32 Ohm
32 Ohm
32 Ohm
C5
Headset
HSL
or Line Out
INGND
AUDVSS
C10
AUDVSS
VSS
VSS
ESDVSS
ESDVSS
211
4341D–MP3–04/05
Table 186. DAC and PA Characteristics
Symbol
C1
Parameter
Typ
470
470
470
100
100
100
470
100n
10
Unit
nF
nF
nF
µF
µF
nF
nF
µF
µF
µF
nF
nF
µF
nF
nF
nF
Ω
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Capacitance
Resistor
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C15
C16
C17
C18
C19
R1
10
470
470
22
100
100
100
200
In System Programming
Schematic
Figure 152. ISP Pull-Down Connection
ISP
RISP
VSS
Parameters
Table 187. ISP Pull-Down Characteristics
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
ISP Pull-Down Resistor
Min
Typ
Max
Unit
RISP
2.2
KΩ
212
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
AC Characteristics
External Program Bus Cycles
Definition of Symbols
Table 188. External Program Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
High
A
I
H
L
Instruction In
ALE
Low
L
P
V
X
Z
Valid
PSEN
No Longer Valid
Floating
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 189. External Program Bus Cycle - Read AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
4·TCLCL-35
3·TCLCL-25
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
2·TCLCL-35
1.5·TCLCL-25
ns
TLLAX Address hold after ALE Low
ns
TLLIV
TPLPH PSEN Pulse Width
ALE Low to Valid Instruction
ns
ns
TPLIV
TPXIX
TPXIZ
TAVIV
PSEN Low to Valid Instruction
3·TCLCL-35
1.5·TCLCL-35 ns
ns
Instruction Hold After PSEN High
Instruction Float After PSEN High
Address Valid to Valid Instruction
0
0
TCLCL-10
5·TCLCL-35
10
0.5·TCLCL-10 ns
2.5·TCLCL-35 ns
TPLAZ PSEN Low to Address Float
10
ns
213
4341D–MP3–04/05
Waveforms
Figure 153. External Program Bus Cycle - Read Waveforms
ALE
TLHLL
TPLPH
TLLPL
PSEN
TPLIV
TPXAV
TPXIZ
TPLAZ
TAVLL TLLAX
TPXIX
P0
P2
D7:0
A7:0
D7:0
Instruction In
A7:0
D7:0
Instruction In
A15:8
A15:8
External Data 8-bit Bus Cycles
Definition of Symbols
Table 190. External Data 8-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
A
D
L
H
L
High
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 191. External Data 8-bit Bus Cycle - Read AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
ns
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
ns
ns
214
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
TRLRH RD Pulse Width
6·TCLCL-25
TCLCL-20
3·TCLCL-25
ns
TRHLH RD high to ALE High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
4.5·TCLCL-65 ns
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TRHDZ Instruction Float After RD High
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
ns
5·TCLCL-30
0
2.5·TCLCL-30 ns
0
ns
ns
ns
0
0
2·TCLCL-25
TCLCL-25
215
4341D–MP3–04/05
Table 192. External Data 8-bit Bus Cycle - Write AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
Waveforms
Figure 154. External Data 8-bit Bus Cycle - Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
216
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Figure 155. External Data 8-bit Bus Cycle - Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
External IDE 16-bit Bus Cycles
Definition of Symbols
Table 193. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
High
A
D
L
H
L
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
217
4341D–MP3–04/05
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 194. External IDE 16-bit Bus Cycle - Data Read AC Timings
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
TRLRH RD Pulse Width
ns
ns
ns
TRHLH RD high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TRHDZ Instruction Float After RD High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
4.5·TCLCL-65 ns
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
ns
5·TCLCL-30
0
2.5·TCLCL-30 ns
0
ns
ns
ns
0
0
2·TCLCL-25
TCLCL-25
Table 195. External IDE 16-bit Bus Cycle - Data Write AC Timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
218
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Waveforms
Figure 156. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
D15:8(1)
Data In
Note:
1. D15:8 is written in DAT16H SFR.
Figure 157. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
D15:8(1)
Data Out
Note:
1. D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols
Table 196. SPI Interface Timing Symbol Definitions
Signals
Conditions
High
C
I
Clock
H
L
Data In
Data Out
Low
O
V
X
Z
Valid
No Longer Valid
Floating
219
4341D–MP3–04/05
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 197. SPI Interface Master AC Timing
V
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Slave Mode
Min
Max
Unit
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
Clock Low Time
SS Low to Clock edge
0.8
0.8
100
40
TCLCX
TSLCH, TSLCL
TIVCL, TIVCH
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
TCLSH, TCHSH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS High after Clock Edge
SS Low to Output Data Valid
Output Data Hold after SS High
SS High to SS Low
ns
40
ns
40
ns
0
0
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
50
50
ns
ns
(1)
Input Rise Time
2
µs
µs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise time
100
100
Output Fall Time
Master Mode
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
0.8
0.8
20
20
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
ns
40
ns
0
ns
TILIH
TIHIL
2
2
µs
Input Data Fall Time
µs
TOLOH
TOHOL
Note:
Output Data Rise time
50
50
ns
Output Data Fall Time
ns
1. Value of this parameter depends on software.
220
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Waveforms
Figure 158. SPI Slave Waveforms (SSCPHA= 0)
SS
(input)
TCLSH
TSLCH
TSLCL
TCHCH
TSHSL
TCHSH
TCLCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
SLAVE MSB OUT
TSHOX
MISO
(output)
(1)
BIT 6
SLAVE LSB OUT
TCHIX
TCLIX
TIVCH
TIVCL
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the MSB of the character which has just been received.
Figure 159. SPI Slave Waveforms (SSCPHA= 1)
SS
(input)
TSLCH
TSLCL
TCLSH
TCHSH
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCHOV
TCLOV
TCHOX
TCLOX
TSLOV
TSHOX
MISO
(output)
(1)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
TIVCH
TIVCL
TCHIX
TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
221
4341D–MP3–04/05
Figure 160. SPI Master Waveforms (SSCPHA= 0)
SS
(output)
TCHCH
TCLCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
TCLOV
TCHOV
LSB IN
TCLOX
TCHOX
MISO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS handled by software using general purpose port pin.
Figure 161. SPI Master Waveforms (SSCPHA= 1)
SS(1)
(output)
TCHCH
TCLCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
TCLOV
BIT 6
LSB IN
TCLOX
TCHOX
TCHOV
MISO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS handled by software using general purpose port pin.
222
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Two-wire Interface
Timings
Table 198. TWI Interface AC Timing
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
INPUT
Min
OUTPUT
Min
Symbol
THD; STA
TLOW
Parameter
Max
Max
4.0 µs(1)
4.7 µs(1)
4.0 µs(1)
(4)
Start condition hold time
SCL low time
14·TCLCL
16·TCLCL
14·TCLCL
1 µs
(4)
(4)
THIGH
SCL high time
(2)
TRC
SCL rise time
-
TFC
SCL fall time
0.3 µs
0.3 µs(3)
20·TCLCL(4)- TRD
1 µs(1)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
Data set-up time
250 ns
250 ns
250 ns
0 ns
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
(4)
8·TCLCL
8·TCLCL(4) - TFC
4.7 µs(1)
(4)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
1 µs
4.0 µs(1)
(4)
(4)
4.7 µs(1)
(2)
TRD
SDA rise time
-
TFD
SDA fall time
0.3 µs
0.3 µs(3)
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
Waveforms
Figure 162. Two Wire Waveforms
Repeated START condition
START or Repeated START condition
Trd
START condition
Tsu;STA
STOP condition
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
Tsu;STO
Tbuf
Tfd
Tsu;DAT3
Trc
Tfc
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thigh
Tsu;DAT2
Tlow
Thd;STA
Thd;DAT
Tsu;DAT1
223
4341D–MP3–04/05
MMC Interface
Definition of symbols
Table 199. MMC Interface Timing Symbol Definitions
Signals
Conditions
High
C
D
O
Clock
H
L
Data In
Data Out
Low
V
X
Valid
No Longer Valid
Timings
Table 200. MMC Interface AC timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards)
V
Symbol
TCHCH
Parameter
Min
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
TCHCX
TCLCX
TCLCH
TCHCL
TDVCH
TCHDX
TCHOX
TOVCH
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
10
10
10
10
Input Data Valid to Clock High
Input Data Hold after Clock High
Output Data Hold after Clock High
Output Data Valid to Clock High
3
3
5
5
Waveforms
Figure 163. MMC Input-Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCLCH
TIVCH
TCHIX
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
224
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Audio Interface
Definition of symbols
Table 201. Audio Interface Timing Symbol Definitions
Signals
Conditions
High
C
O
S
Clock
H
L
Data Out
Data Select
Low
V
X
Valid
No Longer Valid
Timings
Table 202. Audio Interface AC timings
DD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF
V
Symbol
Parameter
Clock Period
Min
Max
Unit
ns
TCHCH
325.5(1)
TCHCX
TCLCX
TCLCH
TCHCL
TCLSV
TCLOV
Clock High Time
30
30
ns
Clock Low Time
ns
Clock Rise Time
10
10
10
10
ns
Clock Fall Time
ns
Clock Low to Select Valid
Clock Low to Data Valid
ns
ns
Note:
1. 32-bit format with Fs= 48 KHz.
Waveforms
Figure 164. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
DDAT
Right
Left
TCLOV
225
4341D–MP3–04/05
Flash Memory
Definition of symbols
Table 203. Flash Memory Timing Symbol Definitions
Signals
Conditions
Low
S
R
B
ISP
L
RST
V
X
Valid
FBUSY flag
No Longer Valid
Timings
Table 204. Flash Memory AC Timing
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
TSVRL
Parameter
Min
Typ
Max
Unit
ns
Input ISP Valid to RST Edge
Input ISP Hold after RST Edge
FLASH Internal Busy (Programming) Time
Number of Flash Write Cycles
Flash Data Retention Time
50
50
TRLSX
TBHBL
NFCY
TFDR
ns
10
ms
100K
10
Cycle
Years
Waveforms
Figure 165. FLASH Memory - ISP Waveforms
RST
TSVRL
TRLSX
ISP(1)
Note:
1. ISP must be driven through a pull-down resistor (see Section “In System Program-
ming”, page 212).
Figure 166. FLASH Memory - Internal Busy Waveforms
FBUSY bit
TBHBL
External Clock Drive and Logic Level References
Definition of symbols
Table 205. External Clock Timing Symbol Definitions
Signals
Clock
Conditions
High
C
H
L
Low
X
No Longer Valid
Timings
Table 206. External Clock AC Timings
226
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
TCLCL
TCHCX
TCLCX
TCLCH
TCHCL
TCR
Parameter
Min
50
10
10
3
Max
Unit
ns
ns
ns
ns
ns
%
Clock Period
High Time
Low Time
Rise Time
Fall Time
3
Cyclic Ratio in X2 mode
40
60
Waveforms
Figure 167. External Clock Waveform
TCLCH
TCHCX
VDD - 0.5
VIH1
TCLCX
VIL
0.45 V
TCHCL
TCLCL
Figure 168. AC Testing Input/Output Waveforms
INPUTS
OUTPUTS
VIH min
VIL max
VDD - 0.5
0.7 VDD
0.3 VDD
0.45 V
Note:
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a
logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for
a logic 0.
Figure 169. Float Waveforms
VLOAD + 0.1 V
VLOAD
VOH - 0.1 V
OL + 0.1 V
Timing Reference Points
V
LOAD - 0.1 V
V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level
occurs with IOL/IOH= ±20 mA.
227
4341D–MP3–04/05
Ordering Information
Temperature
Range
Memory
Size
Supply
Voltage
Max
Frequency
RoHS
Compliant
Part Number
Package
Packing
Product Marking
AT89C51SND2C-7FTIL
64K Flash
3V
3V
Industrial
40 MHz
40 MHz
BGA100
Tray
89C51SND2C-IL
No
Industrial &
ROHS
AT89SND2C-7FTUL
64K Flash
64K ROM
BGA100
BGA100
Tray
Tray
89C51SND2C-JL
83C51SND2C-JL
Yes
Industrial &
ROHS
AT83SND2Cxxx-7FTUL
3V
40 MHz
Yes
228
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Package Information
CTBGA100
229
4341D–MP3–04/05
Datasheet Change
Log
Changes from 4341A -
10/04 to 4341B - 01/05
1. Update Power Amplifier DC characteristics, Section “Electrical Characteristics”,
page 201.
2. Fix minor bugs.
3. Update power consumption measures, Table 182 on page 202.
Changes from 4341B -
01/05 to 4341C - 03/05
1. Change to hardware security system description. Section “Hardware Security
System”, page 19.
Changes from 4341C -
03/05 to 4341D - 04/05
1. Update to DAC gain information, Figure 54 on page 81.
2. Correction to BGA package pinout, Figure 2 on page 4.
3. Updated Ordering Information, Green product version changed to ROHS.
(Green version not yet available)
230
AT8xC51SND2C
4341D–MP3–04/05
Table of Contents
Features ................................................................................................. 1
Description ............................................................................................ 2
Typical Applications ............................................................................. 2
Block Diagram ....................................................................................... 3
Pin Description ...................................................................................... 4
Pinouts ................................................................................................................. 4
Signals................................................................................................................... 5
Internal Pin Structure.......................................................................................... 11
Clock Controller .................................................................................. 12
Oscillator ............................................................................................................ 12
X2 Feature.......................................................................................................... 12
PLL..................................................................................................................... 13
Registers ............................................................................................................. 15
Program/Code Memory ...................................................................... 17
ROM Memory Architecture................................................................................. 17
Flash Memory Architecture ................................................................................ 18
Hardware Security System.................................................................................. 19
Boot Memory Execution ..................................................................................... 19
Preventing Flash Corruption............................................................................... 20
Registers ............................................................................................................. 21
Hardware Bytes................................................................................................... 22
Data Memory ....................................................................................... 23
Internal Space .................................................................................................... 23
External Space.................................................................................................... 25
Dual Data Pointer............................................................................................... 27
Registers ............................................................................................................ 28
Special Function Registers ................................................................ 30
Interrupt System ................................................................................. 36
Interrupt System Priorities.................................................................................. 36
External Interrupts.............................................................................................. 39
Registers ............................................................................................................. 40
231
Power Management ............................................................................ 46
Reset .................................................................................................................. 46
Reset Recommendation to Prevent Flash Corruption ........................................ 47
Idle Mode............................................................................................................ 47
Power-down Mode.............................................................................................. 48
Registers..............................................................................................................50
Timers/Counters ................................................................................. 51
Timer/Counter Operations .................................................................................. 51
Timer Clock Controller........................................................................................ 51
Timer 0................................................................................................................ 52
Timer 1................................................................................................................ 54
Interrupt .............................................................................................................. 55
Registers..............................................................................................................56
Watchdog Timer .................................................................................. 59
Description.......................................................................................................... 59
Watchdog Clock Controller................................................................................. 59
Watchdog Operation............................................................................................60
Registers..............................................................................................................61
MP3 Decoder ....................................................................................... 62
Decoder .............................................................................................................. 62
Audio Controls .....................................................................................................64
Decoding Errors.................................................................................................. 64
Frame Information ...............................................................................................65
Ancillary Data...................................................................................................... 65
Interrupt ...............................................................................................................66
Registers..............................................................................................................68
Audio Output Interface ....................................................................... 73
Description.......................................................................................................... 73
Clock Generator...................................................................................................74
Data Converter ................................................................................................... 74
Audio Buffer........................................................................................................ 75
MP3 Buffer.......................................................................................................... 76
Interrupt Request................................................................................................ 76
MP3 Song Playing .............................................................................................. 76
Voice or Sound Playing ...................................................................................... 77
Registers..............................................................................................................78
DAC and PA Interface ......................................................................... 80
DAC .................................................................................................................... 80
Power Amplifier....................................................................................................98
Audio Supplies and Start-up............................................................................... 99
232
AT8xC51SND2C
4341D–MP3–04/05
AT8xC51SND2C
Universal Serial Bus ......................................................................... 102
Description.........................................................................................................103
Configuration .................................................................................................... 107
Read/Write Data FIFO...................................................................................... 109
Bulk/Interrupt Transactions............................................................................... 110
Control Transactions......................................................................................... 114
Isochronous Transactions..................................................................................115
Miscellaneous....................................................................................................117
Suspend/Resume Management ........................................................................118
USB Interrupt System....................................................................................... 120
Registers............................................................................................................122
IDE/ATAPI Interface .......................................................................... 132
Description........................................................................................................ 132
Registers........................................................................................................... 134
MultiMedia Card Controller .............................................................. 135
Card Concept.................................................................................................... 135
Bus Concept ..................................................................................................... 135
Description........................................................................................................ 140
Clock Generator................................................................................................ 140
Command Line Controller................................................................................. 142
Data Line Controller...........................................................................................144
Interrupt .............................................................................................................150
Registers............................................................................................................151
Synchronous Peripheral Interface .................................................. 157
Description.........................................................................................................158
Interrupt ............................................................................................................ 162
Configuration .....................................................................................................163
Registers............................................................................................................167
Serial I/O Port .................................................................................... 169
Mode Selection................................................................................................. 169
Baud Rate Generator........................................................................................ 169
Synchronous Mode (Mode 0) ........................................................................... 170
Asynchronous Modes (Modes 1, 2 and 3).........................................................172
Multiprocessor Communication (Modes 2 and 3) ............................................. 175
Automatic Address Recognition........................................................................ 175
Interrupt .............................................................................................................177
Registers............................................................................................................178
Two-wire Interface (TWI) Controller ................................................ 181
Description........................................................................................................ 181
Registers........................................................................................................... 195
233
4341D–MP3–04/05
Keyboard Interface ........................................................................... 198
Description........................................................................................................ 198
Registers............................................................................................................199
Electrical Characteristics ................................................................. 201
Absolute Maximum Rating................................................................................ 201
DC Characteristics............................................................................................ 201
AC Characteristics............................................................................................ 213
SPI Interface..................................................................................................... 219
Ordering Information ........................................................................ 228
Package Information ........................................................................ 229
CTBGA100 ....................................................................................................... 229
Datasheet Change Log..................................................................... 230
Changes from 4341A - 10/04 to 4341B - 01/05................................................ 230
Changes from 4341B - 01/05 to 4341C - 03/05................................................ 230
Changes from 4341C - 03/05 to 4341D - 04/05................................................ 230
234
AT8xC51SND2C
4341D–MP3–04/05
Atmel Corporation
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Tel: 1(408) 441-0311
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Printed on recycled paper.
4341D–MP3–04/05
/0M
相关型号：
AT89SND2CMP3B-7FTUL
Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface
ATMEL
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