AT90PWM3B中文资料_数据手册_规格书

Features

High Performance, Low Power AVR ® 8-bit Microcontroller

•

Advanced RISC Architecture

– 129 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 1 MIPS throughput per MHz

– On-chip 2-cycle Multiplier

•

Data and Non-Volatile Program Memory

8-bit

– 8K Bytes Flash of In-System Programmable Program Memory

• Endurance: 10,000 Write/Erase Cycles

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

•

– 512 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

•

– 512 Bytes Internal SRAM

– Programming Lock for Flash Program and EEPROM Data Security

On Chip Debug Interface (debugWIRE)

•

Peripheral Features

– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit

Resolution Enhancement

AT90PWM2

AT90PWM3

• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time

• Variable PWM duty Cycle and Frequency

• Synchronous Update of all PWM Registers

• Auto Stop Function for Event Driven PFC Implementation

• Less than 25 Hz Step Width at 150 kHz Output Frequency

• PSC2 with four Output Pins and Output Matrix

– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture

Mode

AT90PWM2B

AT90PWM3B

– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare

Mode and Capture Mode

– Programmable Serial USART

• Standard UART mode

• 16/17 bit Biphase Mode for DALI Communications

– Master/Slave SPI Serial Interface

– 10-bit ADC

Summary

• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs

• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)

• Internal Reference Voltage

– 10-bit DAC

– Two or three Analog Comparator with Resistor-Array to Adjust Comparison

Voltage

– 4 External Interrupts

– Programmable Watchdog Timer with Separate On-Chip Oscillator

Special Microcontroller Features

•

– Low Power Idle, Noise Reduction, and Power Down Modes

– Power On Reset and Programmable Brown Out Detection

– Flag Array in Bit-programmable I/O Space (4 bytes)

4317IS–AVR–01/08

– In-System Programmable via SPI Port

– Internal Calibrated RC Oscillator ( 8 MHz)

– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)

Operating Voltage: 2.7V - 5.5V

•

Extended Operating Temperature:

– -40°C to +105°

12 bit PWM with

deadtime

ADC

Input

ADC

Diff

Analog

Compar

Product

Package

Application

AT90PWM2

SO24

2 x 2

3 x 2

8

1

2

3

One fluorescent ballast

AT90PWM2B

AT90PWM3

SO32,

QFN32

HID ballast, fluorescent ballast,

Motor control

11

AT90PWM3B

1. History

Product

Revision

AT90PWM2

AT90PWM3

First revision of parts, only for running production.

Second revision of parts, for all new developments.

The major changes are :

• complement the PSCOUT01, PSCOUT11, PSCOUT21 polarity in

centered mode - See “PSCn0 & PSCn1 Basic Waveforms in Center

Aligned Mode” on page 139.

• Add the PSC software triggering capture - See “PSC 0 Input Capture

Register – PICR0H and PICR0L” on page 170.

AT90PWM2B

AT90PWM3B

• Add bits to read the PSC output activity - See “PSC0 Interrupt Flag

Register – PIFR0” on page 172.

• Add some clock configurations - See “Device Clocking Options Select

AT90PWM2B/3B” on page 31.

• Change Amplifier Synchonization - See “Amplifier” on page 252. and

See “” on page 254.

• Correction of the Errata - See “Errata” on page 23.

This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated

as soon as characterization will be done.

2. Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max val-

ues will be available after the device is characterized.

2

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

3. Pin Configurations

Figure 3-1. SOIC 24-pin Package

AT90PWM2/2B

SOIC24

(PSCOUT00/XCK/SS_A) PD0

(RESET/OCD) PE0

PB7(ADC4/PSCOUT01/SCK)

PB6 (ADC7/ICP1B)

PB5 (ADC6/INT2)

PB4 (AMP0+)

1

24

23

22

21

20

19

18

17

16

15

14

13

2

(PSCIN0/CLKO) PD1

3

(PSCIN2/OC1A/MISO_A) PD2

(TXD/DALI/OC0A/SS/MOSI_A) PD3

4

PB3 (AMP0-)

5

VCC

GND

(MISO/PSCOUT20) PB0

AREF

6

GND

7

AVCC

8

(MOSI/PSCOUT21) PB1

(OC0B/XTAL1) PE1

PB2 (ADC5/INT1)

PD7 (ACMP0)

9

10

11

12

(ADC0/XTAL2) PE2

PD6 (ADC3/ACMPM/INT0)

PD5 (ADC2/ACMP2)

(ADC1/RXD/DALI/ICP1A/SCK_A) PD4

Figure 3-2. SOIC 32-pin Package

AT90PWM3/3B

SOIC 32

(PSCOUT00/XCK/SS_A) PD0

(INT3/PSCOUT10) PC0

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PB7(ADC4/PSCOUT01/SCK)

PB6 (ADC7/PSCOUT11/ICP1B)

PB5 (ADC6/INT2)

PC7 (D2A)

1

2

(RESET/OCD) PE0

3

(PSCIN0/CLKO) PD1

4

(PSCIN2/OC1A/MISO_A) PD2

(TXD/DALI/OC0A/SS/MOSI_A) PD3

(PSCIN1/OC1B) PC1

PB4 (AMP0+)

5

PB3 (AMP0-)

6

PC6 (ADC10/ACMP1)

AREF

7

VCC

GND

(T0/PSCOUT22) PC2

8

GND

9

AVCC

10

11

12

13

14

15

16

(T1/PSCOUT23) PC3

(MISO/PSCOUT20) PB0

PC5 (ADC9/AMP1+)

PC4 (ADC8/AMP1-)

PB2 (ADC5/INT1)

PD7 (ACMP0)

(MOSI/PSCOUT21) PB1

(OC0B/XTAL1) PE1

(ADC0/XTAL2) PE2

PD6 (ADC3/ACMPM/INT0)

PD5 (ADC2/ACMP2)

(ADC1/RXD/DALI/ICP1A/SCK_A) PD4

3

4317IS–AVR–01/08

Figure 3-3. QFN32 (7*7 mm) Package.

AT90PWM3/3B QFN 32

24

23

22

21

20

19

18

17

(PSCIN2/OC1A/MISO_A) PD2

(TXD/DALI/OC0A/SS/MOSI_A) PD3

(PSCIN1/OC1B) PC1

VCC

1

2

3

4

5

6

7

8

PB4 (AMP0+)

PB3 (AMP0-)

PC6 (ADC10/ACMP1)

AREF

AGND

GND

AVCC

(T0/PSCOUT22) PC2

(T1/PSCOUT23) PC3

(MISO/PSCOUT20) PB0

PC5 (ADC9/AMP1+)

PC4 (ADC8/AMP1-)

3.1

Pin Descriptions

:

Table 3-1.

Pin out description

S024 Pin

Number

SO32 Pin

Number

QFN32 Pin

Number

Mnemonic

GND

Type

Power

Name, Function & Alternate Function

Ground: 0V reference

Analog Ground: 0V reference for analog part

7

9

5

18

24

20

AGND

4

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

Table 3-1.

Pin out description (Continued)

S024 Pin

Number

SO32 Pin

Number

QFN32 Pin

Number

Mnemonic

Type

Name, Function & Alternate Function

6

8

4

VCC

power

Power Supply:

Analog Power Supply: This is the power supply voltage for analog

part

17

23

19

AVCC

AREF

Power

For a normal use this pin must be connected.

Analog Reference : reference for analog converter . This is the

reference voltage of the A/D converter. As output, can be used by

external analog

19

25

21

MISO (SPI Master In Slave Out)

PSCOUT20 output

8

9

12

13

20

8

9

PBO

PB1

PB2

I/O

MOSI (SPI Master Out Slave In)

PSCOUT21 output

ADC5 (Analog Input Channel5 )

INT1

16

20

21

27

28

23

24

PB3

PB4

I/O

AMP0- (Analog Differential Amplifier 0 Input Channel )

AMP0+ (Analog Differential Amplifier 0 Input Channel )

ADC6 (Analog Input Channel 6)

INT 2

22

23

30

31

26

27

PB5

PB6

I/O

ADC7 (Analog Input Channel 7)

ICP1B (Timer 1 input capture alternate input)

PSCOUT11 output (see note 1)

PSCOUT01 output

24

32

28

PB7

I/O

ADC4 (Analog Input Channel 4)

SCK (SPI Clock)

PSCOUT10 output (see note 1)

INT3

2

30

3

PC0

PC1

PC2

PC3

PC4

PC5

I/O

PSCIN1 (PSC 1 Digital Input)

7

OC1B (Timer 1 Output Compare B)

T0 (Timer 0 clock input)

PSCOUT22 output

10

11

21

22

6

T1 (Timer 1 clock input)

PSCOUT23 output

7

I/O

NA

ADC8 (Analog Input Channel 8)

17

18

AMP1- (Analog Differential Amplifier 1 Input Channel )

ADC9 (Analog Input Channel 9)

I/O

AMP1+ (Analog Differential Amplifier 1 Input Channel )

ADC10 (Analog Input Channel 10)

26

29

22

25

PC6

PC7

I/O

ACMP1 (Analog Comparator 1 Positive Input )

D2A : DAC output

5

4317IS–AVR–01/08

Table 3-1.

Pin out description (Continued)

S024 Pin

Number

SO32 Pin

Number

QFN32 Pin

Number

Mnemonic

Type

Name, Function & Alternate Function

PSCOUT00 output

1

3

4

1

4

5

29

32

1

PD0

I/O

XCK (UART Transfer Clock)

SS_A (Alternate SPI Slave Select)

PSCIN0 (PSC 0 Digital Input )

CLKO (System Clock Output)

PD1

PD2

I/O

PSCIN2 (PSC 2 Digital Input)

OC1A (Timer 1 Output Compare A)

MISO_A (Programming & alternate SPI Master In Slave Out)

TXD (Dali/UART Tx data)

OC0A (Timer 0 Output Compare A)

SS (SPI Slave Select)

5

6

2

PD3

PD4

I/O

MOSI_A (Programming & alternate Master Out SPI Slave In)

ADC1 (Analog Input Channel 1)

RXD (Dali/UART Rx data)

12

16

12

ICP1A (Timer 1 input capture)

SCK_A (Programming & alternate SPI Clock)

ADC2 (Analog Input Channel 2)

13

14

17

18

13

14

PD5

PD6

I/O

ACMP2 (Analog Comparator 2 Positive Input )

ADC3 (Analog Input Channel 3 )

ACMPM reference for analog comparators

INT0

15

2

19

3

15

31

PD7

PE0

I/O

ACMP0 (Analog Comparator 0 Positive Input )

RESET (Reset Input)

I/O or I

OCD (On Chip Debug I/O)

XTAL1: XTAL Input

10

11

14

15

10

11

PE1

PE2

I/O

OC0B (Timer 0 Output Compare B)

XTAL2: XTAL OuTput

ADC0 (Analog Input Channel 0)

1. PSCOUT10 & PSCOUT11 are not present on 24 pins package

4. Overview

The AT90PWM2/2B/3/3B is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

AT90PWM2/2B/3/3B achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

6

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

4.1

Block Diagram

Figure 4-1. Block Diagram

Data Bus 8-bit

Interrupt

Unit

Program

Counter

Status

and Control

8Kx8 Flash

Program

Memory

SPI

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

Watchdog

Timer

3 Analog

Comparators

Instruction

Decoder

ALU

DALI USART

Timer 0

Timer 1

ADC

Control Lines

Data

SRAM

512 bytes

EEPROM

512 bytes

DAC

PSC 2/1/0

I/O Lines

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The AT90PWM2/2B/3/3B provides the following features: 8K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general

purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex-

ible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11-

channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a

programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug

system and four software selectable power saving modes.

7

4317IS–AVR–01/08

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt

system to continue functioning. The Power-down mode saves the register contents but freezes

the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The

ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switch-

ing noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running

while the rest of the device is sleeping. This allows very fast start-up combined with low power

consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel AT90PWM2/3 is a powerful microcontroller that provides a highly flexible and cost

effective solution to many embedded control applications.

The AT90PWM2/3 AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,

and evaluation kits.

4.2

Pin Descriptions

4.2.1

VCC

Digital supply voltage.

Ground.

4.2.2

4.2.3

GND

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed

on page 69.

4.2.4

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C is not available on 24 pins package.

Port C also serves the functions of special features of the AT90PWM2/2B/3/3B as listed on page

71.

8

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

4.2.5

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the AT90PWM2/2B/3/3B as listed

on page 74.

4.2.6

Port E (PE2..0) RESET/ XTAL1/

XTAL2

Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-

acteristics of PE0 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 9-1 on page 47. Shorter pulses are not guaranteed

to generate a Reset.

Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PE2 can be used as output from the inverting

Oscillator amplifier.

The various special features of Port E are elaborated in “Alternate Functions of Port E” on page

77 and “Clock Systems and their Distribution” on page 29.

4.2.7

AVCC

AREF

AVCC is the supply voltage pin for the A/D Converter. It should be externally connected to V_CC

,

even if the ADC is not used. If the ADC is used, it should be connected to V_CCthrough a low-

pass filter.

4.2.8

This is the analog reference pin for the A/D Converter.

4.3

About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

9

4317IS–AVR–01/08

5. Register Summary

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

PICR2H

PICR2L

page 170

page 169

page 168

page 167

page 164

page 163

page 171

page 162

page 170

page 169

page 168

page 166

page 164

page 163

PFRC2B

PFRC2A

PCTL2

PCAE2B

PCAE2A

PPRE21

PFIFTY2

PISEL2B

PISEL2A

PPRE20

PALOCK2

PELEV2B

PELEV2A

PBFM2

PFLTE2B

PFLTE2A

PAOC2B

PRFM2B3

PRFM2A3

PAOC2A

PRFM2B2

PRFM2A2

PARUN2

POP2

PRFM2B1

PRFM2A1

PCCYC2

PRFM2B0

PRFM2A0

PRUN2

PCNF2

PLOCK2

PMODE21

PMODE20

PCLKSEL2

POME2

OCR2RBH

OCR2RBL

OCR2SBH

OCR2SBL

OCR2RAH

OCR2RAL

OCR2SAH

OCR2SAL

POM2

POMV2B3

POS23

POMV2B2

POS22

POMV2B1

PSYNC21

POMV2B0

PSYNC20

POMV2A3

POEN2D

POMV2A2

POEN2B

POMV2A1

POEN2C

POMV2A0

POEN2A

PSOC2

PICR1H

PICR1L

PFRC1B

PFRC1A

PCTL1

PCAE1B

PCAE1A

PPRE11

PFIFTY1

PISEL1B

PISEL1A

PPRE10

PALOCK1

PELEV1B

PELEV1A

PBFM1

PFLTE1B

PFLTE1A

PAOC1B

PMODE11

PRFM1B3

PRFM1A3

PAOC1A

PRFM1B2

PRFM1A2

PARUN1

POP1

PRFM1B1

PRFM1A1

PCCYC1

PRFM1B0

PRFM1A0

PRUN1

-

PCNF1

PLOCK1

PMODE10

PCLKSEL1

OCR1RBH

OCR1RBL

OCR1SBH

OCR1SBL

OCR1RAH

OCR1RAL

OCR1SAH

OCR1SAL

Reserved

PSOC1

–

PSYNC11

PSYNC10

POEN1B

POEN1A

page 162

page 170

page 169

page 168

page 165

page 164

page 163

PICR0H

PICR0L

PFRC0B

PFRC0A

PCTL0

PCAE0B

PCAE0A

PPRE01

PFIFTY0

PISEL0B

PISEL0A

PPRE00

PALOCK0

PELEV0B

PELEV0A

PBFM0

PFLTE0B

PFLTE0A

PAOC0B

PRFM0B3

PRFM0A3

PAOC0A

PRFM0B2

PRFM0A2

PARUN0

POP0

PRFM0B1

PRFM0A1

PCCYC0

PRFM0B0

PRFM0A0

PRUN0

-

PCNF0

PLOCK0

PMODE01

PMODE00

PCLKSEL0

OCR0RBH

OCR0RBL

OCR0SBH

OCR0SBL

OCR0RAH

OCR0RAL

OCR0SAH

OCR0SAL

Reserved

PSOC0

–

PSYNC00

–

POEN0B

–

PSYNC01

POEN0A

–

page 162

Reserved

EUDR

–

EUDR7

EUDR6

EUDR5

EUDR4

MUBRR12

MUBRR4

–

EUDR3

MUBRR011

MUBRR3

–

EUDR2

MUBRR010

MUBRR2

–

EUDR1

MUBRR9

MUBRR1

–

EUDR0

MUBRR8

MUBRR0

–

page 221

page 226

MUBRRH

MUBRRL

Reserved

EUCSRC

EUCSRB

EUCSRA

Reserved

UDR

MUBRR15

MUBRR014

MUBRR13

MUBRR7

MUBRR6

MUBRR5

–

FEM

F1617

–

STP1

EMCH

URxS1

–

STP0

BODR

URxS0

–

page 225

page 224

page 223

–

UTxS2

–

UTxS1

–

EUSART

UTxS0

–

EUSBS

URxS3

–

UTxS3

URxS2

–

UDR07

UDR06

–

UDR05

–

UDR04

–

UDR03

UBRR011

UBRR03

–

UDR02

UBRR010

UBRR02

–

UDR01

UBRR09

UBRR01

–

UDR00

UBRR08

UBRR00

–

page 221 & page 202

page 207

UBRRH

–

UBRRL

UBRR07

UBRR06

–

UBRR05

–

UBRR04

–

page 207

Reserved

UCSRC

–

UMSEL0

TXCIE0

TXC0

–

UPM01

UDRIE0

UDRE0

–

UPM00

RXEN0

FE0

USBS0

TXEN0

DOR0

–

UCSZ01

UCSZ02

UPE0

–

UCSZ00

RXB80

U2X0

–

UCPOL0

TXB80

MPCM0

–

page 205

page 204

page 203

UCSRB

RXCIE0

RXC0

–

UCSRA

Reserved

–

10

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

Reserved

AC2CON

AC1CON

AC0CON

DACH

–

AC2SADE-

AC1ICE

-

–

AC2EN

AC1EN

AC0EN

- / DAC9

AC2IE

AC1IE

AC0IE

- / DAC8

AC2IS1

AC1IS1

AC0IS1

- / DAC7

DAC5 / -

DATS1

–

AC2IS0

AC1IS0

AC0IS0

- / DAC6

DAC4 / -

DATS0

–

AC2M2

AC2M1

AC2M0

AC1M0

AC0M0

DAC8 / DAC2

DAC0 /

DAEN

–

page 230

page 229

page 228

page 262

page 261

AC1M2

AC1M1

AC0M2

AC0M1

- / DAC5

DAC3 / -

-

- / DAC4

DAC9 / DAC3

DACL

DAC7 / DAC1 DAC6 /DAC0

DAC2 / -

DAC1 / -

DACON

DAATE

DATS2

DALA

DAOE

Reserved

PIM2

–

-

–

-

–

PSEIE2

PSEI2

PSEIE1

PSEI1

PSEIE0

PSEI0

PEVE2B

PEV2B

PEVE1B

PEV1B

PEVE0B

PEV0B

PEVE2A

PEV2A

PEVE1A

PEV1A

PEVE0A

PEV0A

-

PEOPE2

PEOP2

PEOPE1

PEOP1

PEOPE0

PEOP0

page 172

page 171

page 172

page 171

page 172

-

PRN21

-

PRN20

-

PIFR2

-

PIM1

-

PRN11

-

PRN10

-

PIFR1

-

PIM0

-

PRN01

PRN00

PIFR0

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

–

OCR1B15

OCR1B7

OCR1A15

OCR1A7

ICR115

ICR17

TCNT115

TCNT17

–

OCR1B14

OCR1B6

OCR1A14

OCR1A6

ICR114

ICR16

TCNT114

TCNT16

–

OCR1B13

OCR1B5

OCR1A13

OCR1A5

ICR113

ICR15

TCNT113

TCNT15

–

OCR1B12

OCR1B4

OCR1A12

OCR1A4

ICR112

ICR14

TCNT112

TCNT14

–

OCR1B11

OCR1B3

OCR1A11

OCR1A3

ICR111

ICR13

TCNT111

TCNT13

–

OCR1B10

OCR1B2

OCR1A10

OCR1A2

ICR110

ICR12

TCNT110

TCNT12

–

OCR1B9

OCR1B1

OCR1A9

OCR1A1

ICR19

ICR11

TCNT19

TCNT11

–

OCR1B8

OCR1B0

OCR1A8

OCR1A0

ICR18

ICR10

TCNT18

TCNT10

–

page 127

page 128

page 127

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

page 127

page 126

page 123

page 252

page 251

–

WGM13

COM1B0

AMP0PD

ADC4D

–

WGM12

–

CS12

CS11

WGM11

ADC9D/AMP1PD

ADC1D

–

CS10

WGM10

ADC8D/AMP1ND

ADC0D

–

COM1B1

ACMP0D

ADC5D

–

AMP0ND

ADC10D/ACMP1D

DIDR0

ADC7D

–

ADC6D

–

ADC3D/ACMPMD ADC2D/ACMP2D

Reserved

–

11

4317IS–AVR–01/08

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7C)

(0x7B)

ADMUX

ADCSRB

ADCSRA

ADCH

REFS1

ADHSM

ADEN

REFS0

–

ADLAR

–

MUX3

MUX2

MUX1

MUX0

page 247

page 249

page 248

page 251

page 257

page 256

–

ADASCR

ADTS3

ADTS2

ADTS1

ADTS0

(0x7A)

ADSC

- / ADC8

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

(0x79)

- / ADC9

- / ADC7

- / ADC6

- / ADC5

- / ADC4

ADC9 / ADC3

ADC8 / ADC2

(0x78)

ADCL

ADC7 / ADC1 ADC6 / ADC0

ADC5 / -

ADC4 / -

ADC3 / -

ADC2 / -

ADC1 / -

ADC0 /

(0x77)

AMP1CSR

AMP0CSR

Reserved

TIMSK1

TIMSK0

Reserved

EICRA

AMP1EN

-

AMP1G1

AMP1G0

-

AMP1TS2

AMP1TS1

AMP1TS0

(0x76)

AMP0EN

-

AMP0G1

AMP0G0

-

AMP0TS2

AMP0TS1

AMP0TS0

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

(0x6F)

–

ICIE1

–

OCIE1B

OCIE1A

TOIE1

page 128

page 101

(0x6E)

–

OCIE0B

OCIE0A

TOIE0

(0x6D)

–

(0x6C)

–

(0x6B)

–

(0x6A)

–

(0x69)

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

page 81

(0x68)

Reserved

OSCCAL

Reserved

PRR

–

(0x67)

–

(0x66)

–

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

page 34

page 43

(0x65)

–

(0x64)

PRPSC2

PRPSC1

PRPSC0

PRTIM1

PRTIM0

PRSPI

PRUSART

PRADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

page 39

page 54

page 13

page 15

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

I

T

H

S

V

N

Z

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPL

SP7

SP6

SP5

–

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

BLBSET

–

PGWRT

–

SPMIE

RWWSB

–

RWWSRE

PGERS

–

SPMEN

–

page 271

–

PUD

–

SPIPS

–

IVSEL

EXTRF

SM0

IVCE

PORF

SE

page 60 & page 68

page 50

–

WDRF

SM2

BORF

SM1

–

page 41

MSMCR

MONDR

ACSR

Monitor Stop Mode Control Register

Monitor Data Register

reserved

ACCKDIV

–

AC2IF

–

AC1IF

AC0IF

–

AC2O

–

AC1O

–

AC0O

–

page 231

Reserved

SPDR

–

SPD7

SPIF

SPIE

–

SPD6

WCOL

SPE

SPD5

SPD4

SPD3

–

SPD2

–

SPD1

–

SPD0

page 181

page 179

SPSR

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

–

CPHA

–

SPR1

–

Reserved

PLLCSR

OCR0B

OCR0A

TCNT0

–

-

PLLF

OCR0B2

OCR0A2

TCNT02

CS02

–

PLLE

OCR0B1

OCR0A1

TCNT01

CS01

WGM01

–

PLOCK

OCR0B0

OCR0A0

TCNT00

CS00

page 37

page 101

page 100

page 99

page 96

page 84

page 21

page 22

page 27

page 82

page 28

OCR0B7

OCR0A7

TCNT07

FOC0A

COM0A1

TSM

OCR0B6

OCR0A6

TCNT06

FOC0B

COM0A0

ICPSEL1

–

OCR0B5

OCR0B4

OCR0B3

OCR0A3

TCNT03

WGM02

–

OCR0A5

OCR0A4

TCNT05

TCNT04

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

–

COM0B1

COM0B0

WGM00

PSRSYNC

EEAR8

EEAR0

EEDR0

EERE

GPIOR00

INT0

–

EEAR5

EEDR5

–

EEAR4

EEDR4

–

EEAR11

EEAR3

EEDR3

EERIE

GPIOR03

INT3

EEAR10

EEAR2

EEDR2

EEMWE

GPIOR02

INT2

EEAR9

EEAR1

EEDR1

EEWE

GPIOR01

INT1

EEAR7

EEDR7

–

EEAR6

EEDR6

–

EEDR

EECR

GPIOR0

EIMSK

GPIOR07

–

GPIOR06

–

GPIOR05

–

GPIOR04

–

EIFR

–

INTF3

GPIOR33

INTF2

GPIOR32

INTF1

GPIOR31

INTF0

GPIOR30

GPIOR3

GPIOR37

GPIOR36

GPIOR35

GPIOR34

12

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

GPIOR2

GPIOR1

Reserved

TIFR1

GPIOR27

GPIOR26

GPIOR25

GPIOR24

GPIOR23

GPIOR22

GPIOR21

GPIOR20

page 27

GPIOR17

GPIOR16

GPIOR15

GPIOR14

GPIOR13

GPIOR12

GPIOR11

GPIOR10

–

ICF1

–

OCF1B

OCF0B

–

OCF1A

OCF0A

–

TOV1

TOV0

–

page 129

page 101

TIFR0

–

Reserved

PORTE

DDRE

–

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

page 79

page 80

page 79

page 78

page 79

–

PINE

–

PORTD

DDRD

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

–

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM2/2B/3/3B is

a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for

the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

13

4317IS–AVR–01/08

6. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Clear Register

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

PC ← PC + k + 1

PC ← Z

None

I

2

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

14

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd ← (X)

Rd, X

Load Indirect

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

15

4317IS–AVR–01/08

Mnemonics

Operands

Description

Operation

Flags

#Clocks

NOP

SLEEP

WDR

No Operation

Sleep

None

1

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

16

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

7. Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

Extended (-40°C to

105°C)

16

2.7 - 5.5V

AT90PWM3-16SQ

SO32

Extended (-40°C to

105°C)

16

2.7 - 5.5V

AT90PWM3-16MQT

AT90PWM2-16SQ

QFN32

SO24

Extended (-40°C to

105°C)

16

2.7 - 5.5V

AT90PWM3B-16SE

AT90PWM3B-16ME

AT90PWM2B-16SE

SO32

QFN32

SO24

Engineering Samples

Extended (-40°C to

105°C)

16

2.7 - 5.5V

AT90PWM3B-16SU

AT90PWM3B-16MU

AT90PWM2B-16SU

SO32

QFN32

SO24

Extended (-40°C to

105°C)

Extended (-40°C to

105°C)

Note:

All packages are Pb free, fully LHF

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and

minimum quantities.

Note:

Parts numbers are for shipping in sticks (SO) or in trays (QFN). Thes devices can also be supplied in Tape and Reel. Please

contact your local Atmel sales office for detailed ordering information and minimum quantities.

Note: PWM2 is not recommended for new designs, use PWM2B for your developments

Note: PWM3 is not recommended for new designs, use PWM3B for your developments

17

4317IS–AVR–01/08

8. Package Information

Package Type

SO24

SO32

QFN32

24-Lead, Small Outline Package

32-Lead, Small Outline Package

32-Lead, Quad Flat No lead

18

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

8.1

SO24

19

4317IS–AVR–01/08

8.2

SO32

20

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

8.3

QFN32

21

4317IS–AVR–01/08

22

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

9. Errata

9.1

AT90PWM2&3 Rev. A (Mask Revision)

•

PGM: PSCxRB Fuse

PSC: Prescaler

PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control)

PSC: PEVxA/B Flag Bits

PSC: Output Polarity in Centered Mode

PSC: Output Activity

VREF

DALI

DAC: Register Update

DAC: Output spikes

DAC driver: Output Voltage linearity

ADC: Conversion accuracy

Analog comparator: Offset value

Analog comparator: Output signal

PSC: Autolock modes

DALI: 17th bit detection

PSC: One ramp mode with PSC input mode 8

1. PGM: PSCnRB Fuse

The use of PSCnRB fuse can make the parallel ISP fail.

Workaround:

When PSCnRB fuses are used, use the serial programming mode to load a new program

version.

2. PSC: Prescaler

The use of PSC's prescaler have the following effects :

It blocks the sample of PSC inputs until the two first cycles following the set of PSC run bit.

A fault is not properly transferred to other (slave) PSC.

Workaround:

Clear the prescaler PPREx bit when stopping the PSC (prun = 0), and set them to appropri-

ate value when starting the PSC (prun = 1), these bits are in the same PCTL register

Do not use the prescaler when a fault on one PSC should affect other PSC’s

3. PSC: PAOCnA and PAOCnB Register Bits (Asynchronous output control)

These register bits are malfunctioning.

Workaround:

Do not use this feature.

4. PSC: PEVnA/B flag bits

These flags are set when a fault arises, but can also be set again during the fault itself.

Workaround:

Don't clear these flags before the fault disappears.

23

4317IS–AVR–01/08

5. PSC: Output Polarity in Centered Mode

In centered mode, PSCOUTn1 outputs are not inverted, so they are active at the same time

as PSCOUTn0.

Workaround:

Use an external inverter (or a driver with inverting output) to drive the load on

PSCOUTn1.

6. PSC : POACnA/B Output Activity

These register bits are not implemented in rev A.

Workaround:

Do not use this feature.

7. VREF

Remark: To have Internal Vref on AREF pin select an internal analog feature such as DAC

or ADC.

Some stand by power consuption may be observed if Vref equals AVcc

8. DALI

Some troubles on Dali extension when edges are not symmetric.

Workaround:

Use an optocoupler providing symmetric edges on Rx and Tx DALI lines (only recom-

manded for software validation purpose).

9. DAC: Register Update

Registers DACL & DACH are not written when the DAC is not enabled.

Workaround:

Enable DAC with DAEN before writing in DACL & DACH. To prevent an unwanted zero out-

put on DAC pin, enable DAC output, with DAOE afterwards.

10. DAC : Output spikes

During transition between two codes, a spike may appears

Work around:

Filter spike or wait for steady state

No spike appears if the 4 last signifiant bits remain zero.

11. DAC driver: Output Voltage linearity

The voltage linearity of the DAC driver is limited when the DAC output goes above Vcc - 1V.

Work around:

Do not use AVcc as Vref ; internal Vref gives good results

12. ADC : Conversion accuracy

The conversion accuracy degrades when the ADC clock is 1 & 2 MHz.

Work around:

When a 10 bit conversion accuracy is required, use an ADC clock of 500 kHz or below.

13. Analog comparator: Offset value

The offset value increases when the common mode voltage is above Vcc - 1.5V.

Work around:

Limit common mode voltage

14. Analog comparator: Output signal

24

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

The comparator output toggles at the comparator clock frequency when the voltage differ-

ence between both inputs is lower than the offset. This may occur when comparing signal

with small slew rate.

Work around:

This effect normally do not impact the PSC, as the transition is sampled once per PSC cycle

Be carefull when using the comparator as an interrupt source.

15. PSC : Autolock mode

This mode is not properly handled when CLKPSC is different from CLK IO.

Work around:

With CLKPSC equals 64/32 MHz (CLKPLL), use LOCK mode

16. DALI : 17th bit detection

17th bit detection do not occurs if the signal arrives after the sampling point.

Workaround:

Use this feature only for sofware development and not in field conditions

17. PSC : One ramp mode with PSC input mode 8

The retriggering is not properly handled in this case.

Work around:

Do not program this case.

18. PSC : Desactivation of outputs in mode 14

See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output” on

page 155.

Work around:

Do not use this mode to desactivate output if retrigger event do not occurs during On-Time.

9.2

AT90PWM2B/3B

•

PSC : Double End-Of-Cycle Interrupt Request in Centered Mode

ADC : Conversion accuracy

•

1. PSC : Double End-Of-Cycle Interrupt Request in Centered Mode

In centered mode, after the “expected” End-Of-Cycle Interrupt, a second unexpected Inter-

rupt occurs 1 PSC cycle after the previous interrupt.

Work around:

While CPU cycle is lower than PSC clock, the CPU sees only one interrupt request. For PSC

clock period greater than CPU cycle, the second interrupt request must be cleared by

software.

2. ADC : Conversion accuracy

The conversion accuracy degrades when the ADC clock is 2 MHz.

Work around:

When a 10 bit conversion accuracy is required, use an ADC clock of 1 MHz or below.

At 2 Mhz the ADC can be used as a 7 bits ADC.

3. DAC Driver linearity above 3.6V

With 5V Vcc, the DAC driver linearity is poor when DAC output level is above Vcc-1V. At 5V,

DAC output for 1023 will be around 5V - 40mV.

Work around: .

25

4317IS–AVR–01/08

Use, when Vcc=5V, Vref below Vcc-1V.

Or, when Vref=Vcc=5V, do not uses codes above 800.

4. DAC Update in Autotrig mode

If the cpu writes in DACH register at the same instant that the selected trigger source occurs

and DAC Auto Trigger is enabled, the DACH register is not updated by the new value.

Work around: .

When using the autotrig mode, write twice in the DACH register. The time between the two

CPU writes, must be different than the trigger source frequency.

26

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

AT90PWM2/3/2B/3B

10. Datasheet Revision History for AT90PWM2/2B/3/3B

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

10.1 Changes from 4317A- to 4317B

1. PSC section has been rewritten.

2. Suppression of description of RAMPZ which does not exist.

10.2 Changes from 4317B- to 4317C

1. Added AT90PWM2B/3B Advance Information.

2. Various updates throughout the document.

10.3 Changes from 4317C- to 4317D

1. Update of Electrical and Typical Characteristics.

10.4 Changes from 4317D to 4317E

1. Changed product status from “Advanced Information” to “Preliminary”.

10.5 Changes from 4317E to 4317F

1. Remove JMP and CALL instruction in the Instruction Set Summary

2. Daisy chain of PSC input is only done in mode 7 - See “Fault events in Autorun mode”

on page 160.

3. Updated “Output Compare SA Register – OCRnSAH and OCRnSAL” on page 163

4. Updated “Output Compare RA Register – OCRnRAH and OCRnRAL” on page 163

5. Updated “Output Compare SB Register – OCRnSBH and OCRnSBL” on page 163

6. Updated “Output Compare RB Register – OCRnRBH and OCRnRBL” on page 164

7. Specify the “Analog Comparator Propagation Delay” - See “DC Characteristics” on

page 300.

8. Specify the “Reset Characteristics” - See “Reset Characteristics(1)” on page 47.

9. Specify the “Brown-out Characteristics” - See “Brown-out Characteristics(1)” on page

49.

10. Specify the “Internal Voltage Reference Characteristics - See “Internal Voltage Refer-

ence Characteristics(1)” on page 51.

10.6 Changes from 4317F to 4317G

1. Describe the amplifier operation for Rev B.

2. Clarify the fact that the DAC load given is the worst case.

3. Specify the ADC Min and Max clock frequency.

4. Describe the retrigger mode 8 in one ramp mode.

5. Specify that the amplifier only provides a 8 bits accuracy.

10.7 Changes from 4317G to 4317H

1. Updated “History” on page 2

2. Specify the “AREF Voltage vs. Temperature” on page 329

27

4317IS–AVR–01/08

3. PSC : the Balance Flank Width Modulation is done On-Time 1 rather than On-Time 0

(correction of figures)

4. Updated “Maximum Speed vs. VCC” on page 303 (formulas are removed)

5. Update of the “Errata” on page 23

10.8 Changes from 4317H to 4317I

1. Updated “History” on page 2

2. Updated “Device Clocking Options Select AT90PWM2B/3B” on page 31

3. Updated “Start-up Times when the PLL is selected as system clock” on page 35

4. Updated “ADC Noise Canceler” on page 241

5. Updated “ADC Auto Trigger Source Selection for non amplified conversions” on page

250.

6. Added “ADC Auto Trigger Source Selection for amplified conversions” on page 250

7. Updated “Amplifier” on page 252

8. Updated “Amplifier 0 Control and Status register – AMP0CSR” on page 256

9. Updated “AMP0 Auto Trigger Source Selection” on page 257

10. Updated “Amplifier 1Control and Status register – AMP1CSR” on page 257

11. Updated “AMP1 Auto Trigger source selection” on page 258

12. Updated DAC “Features” on page 259 (Output Impedance)

13. Updated temperature range in “DC Characteristics” on page 300

14. Updated Vhysr in “DC Characteristics” on page 300

15. Updated “ADC Characteristics” on page 306

16. Updated “Example 1” on page 315

17. Updated “Example 2” on page 315

18. Updated “Example 3” on page 316

19. Added “I/O Pin Input HysteresisVoltage vs. VCC” on page 322

20. Updated “Ordering Information” on page 17

21. Added Errata for “AT90PWM2B/3B” on page 25

22. Updated Package Drawings “Package Information” on page 18.

23. Updated table on page 2.

24. Updated “Calibrated Internal RC Oscillator” on page 33.

25. Added “Calibrated Internal RC Oscillator Accuracy” on page 302.

26. Updated Figure 27-35 on page 329.

27. Updated Figure 27-36 on page 330.

28. Updated Figure 27-37 on page 330.

28

AT90PWM2/3/2B/3B

4317IS–AVR–01/08

Headquarters

International

Atmel Corporation

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San Jose, CA 95131

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4317IS–AVR–01/08

型号	制造商	描述	价格	文档
AT90PWM3B-16ME	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
AT90PWM3B-16MU	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
AT90PWM3B-16MU	MICROCHIP	IC MCU 8BIT 8KB FLASH 32QFN	获取价格
AT90PWM3B-16SE	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
AT90PWM3B-16SU	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
AT90PWM3_08	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
AT90PWM81	ATMEL	8-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash	获取价格
AT90PWM81-16ME	ATMEL	8-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash	获取价格
AT90PWM81-16MF	ATMEL	8-bit AVR Microcontroller with 8K Bytes In- System Programmable Flash	获取价格
AT90PWM81-16MF	MICROCHIP	IC MCU 8BIT 8KB FLASH 32QFN	获取价格

AT90PWM3B

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