AT90USB646-16MU [ATMEL]
8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller; 8位微控制器具有ISP功能的Flash和USB控制器64 / 128K字节
| 型号： | AT90USB646-16MU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller |
| 文件： | 总30页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
•
•
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
•
Non-volatile Program and Data Memories
8-bit
– 64/128K Bytes of In-System Self-Programmable Flash
• Endurance: 100,000 Write/Erase Cycles
Microcontroller
with
– Optional Boot Code Section with Independent Lock Bits
• USB Bootloader programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
reset
64/128K Bytes
of ISP Flash
and USB
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
– 2K/4K (64K/128K Flash version) Bytes EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 4K/8K (64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
Controller
•
•
JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
•
Summary
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
USB OTG Reduced Host :
•
•
– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
7593GS–AVR–03/08
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channels, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
•
•
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
I/O and Packages
– 48 Programmable I/O Lines
– 64-lead TQFP and 64-lead QFN
•
•
•
Operating Voltages
– 2.7 - 5.5V
Operating temperature
– Industrial (-40°C to +85°C)
Maximum Frequency
– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range
2
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
1. Pin Configurations
Figure 1-1. Pinout AT90USB64/128-TQFP
1
2
PA3 (AD3)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
(INT.6/AIN.0) PE6
(INT.7/AIN.1/UVcon) PE7
UVcc
PA4 (AD4)
INDEX CORNER
3
PA5 (AD5)
4
D-
PA6 (AD6)
5
D+
PA7 (AD7)
6
UGnd
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
7
UCap
8
VBus
AVR USB
TQFP64
9
(IUID) PE3
10
11
12
13
14
15
16
(SS/PCINT0) PB0
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
3
7593GS–AVR–03/08
Figure 1-2. Pinout AT90USB64/128-QFN
(INT.6/AIN.0) PE6
PA3 (AD3)
(INT.7/AIN.1/UVcon) PE7
PA4 (AD4)
UVcc
PA5 (AD5)
INDEX CORNER
D-
PA6 (AD6)
D+
UGnd
UCap
VBus
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
AT90USB128
(64-lead QFN top view)
(IUID) PE3
(SS/PCINT0) PB0
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
Note:
The large center pad underneath the MLF packages is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
1.1
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2. Overview
The AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
4
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
PF7 - PF0
PA7 - PA0
PC7 - PC0
VCC
GND
PORTA DRIVERS
PORTF DRIVERS
PORTC DRIVERS
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTF
DATA DIR.
REG. PORTF
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
POR - BOD
RESET
INTERNAL
OSCILLATOR
AVCC
CALIB. OSC
ADC
AGND
AREF
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
COUNTER
STACK
POINTER
JTAG TAP
TIMING AND
CONTROL
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
ON-CHIP DEBUG
BOUNDARY-
SCAN
INSTRUCTION
REGISTER
TIMER/
COUNTERS
GENERAL
PURPOSE
REGISTERS
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
PLL
STATUS
REGISTER
TWO-WIRE SERIAL
INTERFACE
USB
USART0
SPI
DATA REGISTER
PORTE
DATA DIR.
REG. PORTE
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTB DRIVERS
PORTD DRIVERS
PORTE DRIVERS
PE7 - PE0
PB7 - PB0
PD7 - PD0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
5
7593GS–AVR–03/08
The AT90USB64/128 provides the following features: 64/128K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 2K/4K bytes EEPROM, 4K/8K bytes SRAM, 48
general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four
flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented 2-wire
Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programma-
ble gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.
1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and
programming and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue function-
ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-
chronous timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode,
both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.
The AT90USB64/128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula-
tors, and evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Digital supply voltage.
Ground.
2.2.2
2.2.3
GND
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the AT90USB64/128 as listed on
page 79.
6
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
2.2.4
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the AT90USB64/128 as listed on
page 80.
2.2.5
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the AT90USB64/128 as listed on page 83.
2.2.6
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90USB64/128 as listed on
page 84.
2.2.7
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
page 87.
2.2.8
Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
7
7593GS–AVR–03/08
2.2.9
D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22 Ohms resistor.
2.2.10
D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.
2.2.11
2.2.12
2.2.13
UGND
UVCC
UCAP
USB Pads Ground.
USB Pads Internal Regulator Input supply voltage.
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-
itor (1µF).
2.2.14
2.2.15
VBUS
USB VBUS monitor and OTG negociations.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.16
2.2.17
2.2.18
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.2.19
AREF
This is the analog reference pin for the A/D Converter.
3. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
8
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
9
7593GS–AVR–03/08
4. Register Summary
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OTGTCON
UPINT
PAGE
VALUE
PINT7:0
UPBCHX
UPBCLX
UPERRX
UEINT
-
-
-
-
-
-
-
PBYCT10:8
DATAPID
BYCT10:8
PBYCT7:0
TIMEOUT
COUNTER1:0
CRC16
-
PID
DATATGL
EPINT6:0
-
UEBCHX
UEBCLX
UEDATX
UEIENX
-
-
BYCT7:0
DAT7:0
RXSTPE
FLERRE
-
NAKINE
-
-
NAKOUTE
RXOUTE
CTRLDIR
STALLEDE
TXINE
UESTA1X
UESTA0X
UECFG1X
UECFG0X
UECONX
UERST
-
-
-
-
CURRBK1:0
NBUSYBK1:0
ALLOC
CFGOK
OVERFI
UNDERFI
EPSIZE2:0
DTSEQ1:0
EPBK1:0
EPTYPE1:0
-
-
EPDIR
EPEN
STALLRQ
STALLRQC
RSTDT
EPRST6:0
UENUM
EPNUM2:0
STALLEDI
UEINTX
FIFOCON
NAKINI
RWAL
-
NAKOUTI
-
RXSTPI
-
RXOUTI
-
TXINI
Reserved
UDMFN
FNCERR
UDFNUMH
UDFNUML
UDADDR
UDIEN
FNUM10:8
FNUM7:0
ADDEN
UADD6:0
EORSTE
EORSTI
UPRSME
UPRSMI
EORSME
EORSMI
WAKEUPE
WAKEUPI
SOFE
SOFI
MSOFE
MSOFI
SUSPE
SUSPI
UDINT
UDCON
LSM
RMWKUP
VBERRI
DETACH
SRPI
OTGINT
OTGIEN
OTGCON
Reserved
Reserved
USBINT
STOI
STOE
HNPERRI
HNPERRE
SRPREQ
ROLEEXI
ROLEEXE
SRPSEL
BCERRI
BCERRE
VBUSHWC
VBERRE
VBUSREQ
SRPE
HNPREQ
VBUSRQC
IDTI
ID
VBUSTI
VBUS
USBSTA
USBCON
UHWCON
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR1
SPEED
USBE
HOST
UIDE
FRZCLK
OTGPADE
UVCONE
IDTE
VBUSTE
UVREGE
UIMOD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
USART1 I/O Data Register
- USART1 Baud Rate Register High Byte
UBRR1H
UBRR1L
Reserved
UCSR1C
UCSR1B
UCSR1A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
USART1 Baud Rate Register Low Byte
-
-
-
-
-
-
-
-
UMSEL11
UMSEL10
UPM11
UPM10
USBS1
UCSZ11
UCSZ10
UCPOL1
RXCIE1
TXCIE1
UDRIE1
RXEN1
TXEN1
UCSZ12
RXB81
TXB81
RXC1
TXC1
UDRE1
FE1
DOR1
PE1
U2X1
MPCM1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
-
-
-
-
-
-
-
-
-
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
Reserved
TWAMR
TWCR
TWAM6
TWINT
TWAM5
TWEA
TWAM4
TWSTA
TWAM3
TWSTO
TWAM2
TWWC
TWAM1
TWEN
TWAM0
-
TWIE
TWDR
2-wire Serial Interface Data Register
TWAR
TWA6
TWS7
TWA5
TWS6
TWA4
TWS5
TWA3
TWS4
TWA2
TWS3
TWA1
-
TWA0
TWGCE
TWPS0
TWSR
TWPS1
TWBR
2-wire Serial Interface Bit Rate Register
-
-
-
-
-
AS2
-
-
-
-
-
-
Reserved
ASSR
EXCLK
-
TCN2UB
-
OCR2AUB
-
OCR2BUB
-
TCR2AUB
-
TCR2BUB
-
Reserved
OCR2B
OCR2A
TCNT2
Timer/Counter2 Output Compare Register B
Timer/Counter2 Output Compare Register A
Timer/Counter2 (8 Bit)
TCCR2B
TCCR2A
UPDATX
UPIENX
UPCFG2X
UPSTAX
UPCFG1X
UPCFG0X
UPCONX
UPRST
FOC2A
FOC2B
-
-
WGM22
-
CS22
-
CS21
CS20
COM2A1
COM2A0
COM2B1
COM2B0
WGM21
WGM20
PDAT7:0
TXSTPE
INTFRQ7:0
FLERRE
CFGOK
NAKEDE
OVERFI
-
PERRE
TXOUTE
RXSTALLE
RXINE
UNDERFI
PSIZE2:0
DTSEQ1:0
PBK1:0
NBUSYBK1:0
ALLOC
PEPNUM3:0
PTYPE1:0
PTOKEN1:0
PFREEZE
INMODE
RSTDT
PEN
PRST6:0
UPNUM
UPINTX
UPINRQX
UHFLEN
UHFNUMH
UHFNUML
UHADDR
UHIEN
PNUM2:0
RXSTALLI
FIFOCON
NAKEDI
RWAL
PERRI
TXSTPI
TXOUTI
RXINI
INRQ7:0
FLEN7:0
FNUM10:8
FNUM7:0
HADD6:0
HWUPE
HWUPI
HSOFE
HSOFI
RXRSME
RXRSMI
RSMEDE
RSMEDI
RSTE
RSTI
DDISCE
DDISCI
RESET
DCONNE
DCONNI
SOFEN
UHINT
UHCON
OCR3CH
OCR3CL
OCR3BH
OCR3BL
OCR3AH
OCR3AL
ICR3H
RESUME
Timer/Counter3 - Output Compare Register C High Byte
Timer/Counter3 - Output Compare Register C Low Byte
Timer/Counter3 - Output Compare Register B High Byte
Timer/Counter3 - Output Compare Register B Low Byte
Timer/Counter3 - Output Compare Register A High Byte
Timer/Counter3 - Output Compare Register A Low Byte
Timer/Counter3 - Input Capture Register High Byte
Timer/Counter3 - Input Capture Register Low Byte
Timer/Counter3 - Counter Register High Byte
ICR3L
TCNT3H
TCNT3L
Reserved
TCCR3C
TCCR3B
TCCR3A
Reserved
Reserved
OCR1CH
OCR1CL
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
Timer/Counter3 - Counter Register Low Byte
-
-
-
-
-
-
-
-
FOC3A
FOC3B
FOC3C
-
-
-
-
-
ICNC3
ICES3
-
WGM33
WGM32
CS32
CS31
CS30
COM3A1
COM3A0
COM3B1
COM3B0
COM3C1
COM3C0
WGM31
WGM30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter1 - Output Compare Register C High Byte
Timer/Counter1 - Output Compare Register C Low Byte
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
Timer/Counter1 - Counter Register High Byte
ICR1L
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
Timer/Counter1 - Counter Register Low Byte
-
FOC1A
ICNC1
COM1A1
-
-
FOC1B
ICES1
COM1A0
-
-
-
-
-
-
-
-
-
FOC1C
-
-
-
-
WGM13
WGM12
CS12
CS11
WGM11
AIN1D
ADC1D
-
CS10
WGM10
AIN0D
ADC0D
-
COM1B1
COM1B0
COM1C1
COM1C0
-
-
-
-
DIDR0
ADC7D
-
ADC6D
-
ADC5D
-
ADC4D
-
ADC3D
-
ADC2D
-
-
11
7593GS–AVR–03/08
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7C)
(0x7B)
ADMUX
ADCSRB
ADCSRA
ADCH
REFS1
ADHSM
ADEN
REFS0
ACME
ADSC
ADLAR
-
MUX4
-
MUX3
-
MUX2
ADTS2
ADPS2
MUX1
ADTS1
ADPS1
MUX0
ADTS0
ADPS0
(0x7A)
ADATE
ADIF
ADIE
(0x79)
ADC Data Register High byte
ADC Data Register Low byte
(0x78)
ADCL
-
-
-
-
-
-
-
-
-
(0x77)
Reserved
Reserved
XMCRB
XMCRA
Reserved
Reserved
TIMSK3
TIMSK2
TIMSK1
TIMSK0
Reserved
Reserved
PCMSK0
EICRB
-
-
-
-
-
-
-
(0x76)
(0x75)
XMBK
-
-
-
-
XMM2
XMM1
XMM0
SRW00
-
(0x74)
SRE
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
-
-
-
-
-
-
-
(0x73)
-
-
-
-
-
-
-
-
(0x72)
(0x71)
-
-
ICIE3
-
OCIE3C
OCIE3B
OCIE2B
OCIE1B
OCIE0B
-
OCIE3A
OCIE2A
OCIE1A
OCIE0A
-
TOIE3
TOIE2
TOIE1
TOIE0
-
(0x70)
-
-
-
-
-
(0x6F)
-
-
ICIE1
-
OCIE1C
(0x6E)
-
-
-
-
-
(0x6D)
-
-
-
-
-
-
PCINT7
ISC71
ISC31
-
-
PCINT6
ISC70
ISC30
-
-
PCINT5
ISC61
ISC21
-
-
PCINT4
ISC60
ISC20
-
-
PCINT3
ISC51
ISC11
-
-
-
-
(0x6C)
(0x6B)
PCINT2
ISC50
ISC10
-
PCINT1
ISC41
ISC01
-
PCINT0
ISC40
ISC00
PCIE0
-
(0x6A)
(0x69)
EICRA
(0x68)
PCICR
(0x67)
Reserved
OSCCAL
PRR1
-
-
-
-
-
-
-
(0x66)
Oscillator Calibration Register
(0x65)
PRUSB
-
-
-
PRTIM3
-
-
PRUSART1
(0x64)
PRR0
PRTWI
PRTIM2
PRTIM0
-
PRTIM1
PRSPI
-
PRADC
(0x63)
Reserved
Reserved
CLKPR
-
-
-
-
-
-
-
-
(0x62)
-
-
-
-
-
-
-
-
(0x61)
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
(0x60)
WDTCSR
SREG
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
I
T
H
S
V
N
Z
C
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Reserved
RAMPZ
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RAMPZ1
RAMPZ0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SPMEN
-
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
-
-
-
-
-
PUD
JTRF
-
-
-
-
-
JTD
-
-
IVSEL
EXTRF
SM0
-
IVCE
PORF
SE
-
-
-
WDRF
SM2
-
BORF
SM1
-
-
-
-
Reserved
-
-
-
-
-
OCDR/
MONDR
OCDR7
OCDR6
OCDR5
OCDR4
OCDR3
OCDR2
OCDR1
OCDR0
0x31 (0x51)
Monitor Data Register
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
ACSR
Reserved
SPDR
ACD
-
ACBG
-
ACO
-
ACI
-
ACIE
-
ACIC
-
ACIS1
-
ACIS0
-
SPI Data Register
-
SPSR
SPIF
SPIE
WCOL
SPE
-
-
-
-
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
CPHA
SPR1
GPIOR2
GPIOR1
PLLCSR
OCR0B
OCR0A
TCNT0
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
EEDR
General Purpose I/O Register 2
General Purpose I/O Register 1
-
-
-
PLLP2
PLLP1
PLLP0
PLLE
PLOCK
Timer/Counter0 Output Compare Register B
Timer/Counter0 Output Compare Register A
Timer/Counter0 (8 Bit)
FOC0A
COM0A1
TSM
FOC0B
-
-
WGM02
CS02
CS01
CS00
COM0A0
COM0B1
COM0B0
-
-
-
-
WGM01
PSRASY
WGM00
-
-
-
-
-
-
PSRSYNC
-
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
EEPROM Data Register
EECR
-
-
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
GPIOR0
EIMSK
EIFR
General Purpose I/O Register 0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
12
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
-
-
-
-
-
-
-
-
-
-
PCIF0
-
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
PCIFR
Reserved
Reserved
TIFR3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICF3
-
-
OCF3C
-
OCF3B
OCF2B
OCF1B
OCF0B
-
OCF3A
OCF2A
OCF1A
OCF0A
-
TOV3
TOV2
TOV1
TOV0
-
TIFR2
-
-
-
TIFR1
-
-
ICF1
-
-
OCF1C
-
TIFR0
-
-
-
Reserved
Reserved
Reserved
PORTF
DDRF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTF7
DDF7
PINF7
PORTE7
DDE7
PINE7
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PORTF6
DDF6
PINF6
PORTE6
DDE6
PINE6
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PORTF5
DDF5
PINF5
PORTE5
DDE5
PINE5
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
PORTA5
DDA5
PINA5
PORTF4
DDF4
PINF4
PORTE4
DDE4
PINE4
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
PORTA4
DDA4
PINA4
PORTF3
DDF3
PINF3
PORTE3
DDE3
PINE3
PORTD3
DDD3
PIND3
PORTC3
DDC3
PINC3
PORTB3
DDB3
PINB3
PORTA3
DDA3
PINA3
PORTF2
DDF2
PINF2
PORTE2
DDE2
PINE2
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
PORTA2
DDA2
PINA2
PORTF1
DDF1
PINF1
PORTE1
DDE1
PINE1
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
PORTA1
DDA1
PINA1
PORTF0
DDF0
PINF0
PORTE0
DDE0
PINE0
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
PORTA0
DDA0
PINA0
PINF
PORTE
DDRE
PINE
PORTD
DDRD
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
PORTA
DDRA
PINA
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O reg-
isters as data space using LD and ST instructions, $20 must be added to these addresses. The AT90USB64/128 is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
13
7593GS–AVR–03/08
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADIW
SUB
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
Indirect Jump to (Z)
PC ← PC + k + 1
PC ← Z
None
None
None
None
None
None
None
None
None
I
2
2
PC ←(EIND:Z)
EIJMP
JMP
Extended Indirect Jump to (Z)
Direct Jump
2
k
k
PC ← k
PC ← PC + k + 1
PC ← Z
3
RCALL
ICALL
EICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
4
4
PC ←(EIND:Z)
Extended Indirect Call to (Z)
Direct Subroutine Call
Subroutine Return
4
k
PC ← k
5
PC ← STACK
5
RETI
Interrupt Return
PC ← STACK
5
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
k
14
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
BRIE
BRID
k
k
k
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
None
1/2
1/2
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd ← (X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
LD
LDD
LD
Rd ← (Z)
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
LD
LDD
LDS
ST
Rd ← (k)
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
ELPM
ELPM
ELPM
(k) ← Rr
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Extended Load Program Memory
Extended Load Program Memory
Extended Load Program Memory
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
R0 ← (RAMPZ:Z)
Rd ← (Z)
Rd, Z
Rd, Z+
Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1
15
7593GS–AVR–03/08
Mnemonics
Operands
Description
Operation
Flags
#Clocks
SPM
IN
Store Program Memory
In Port
(Z) ← R1:R0
Rd ← P
None
None
None
None
None
-
Rd, P
P, Rr
Rr
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
None
None
None
None
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
16
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
6. Ordering Information
Table 6-1.
Possible Order Entries
USB
interface
Speed
(MHz)
Power Supply
(V)
Ordering Code
Package
Operation Range
Product Marking
Industrial (-40°to +85°C)
Green
AT90USB1287-16AU
AT90USB1287-16MU
AT90USB1286-16MU
AT90USB647-16AU
AT90USB647-16MU
AT90USB646-16MU
OTG
OTG
8-16
8-16
8-16
8-16
8-16
8-16
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
2.7 - 5.5
MD
PS
PS
MD
PS
PS
90USB1287-16AU
90USB1287-16MU
90USB1286-16MU
90USB647-16AU
90USB647-16MU
90USB646-16MU
Industrial (-40°to +85°C)
Green
Device
only
Industrial (-40°to +85°C)
Green
Industrial (-40°to +85°C)
Green
OTG
OTG
Industrial (-40°to +85°C)
Green
Device
only
Industrial (-40°to +85°C)
Green
MD
PS
64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
17
7593GS–AVR–03/08
6.1
TQFP64
18
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
19
7593GS–AVR–03/08
6.2
QFN64
20
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
21
7593GS–AVR–03/08
7. Errata
8. AT90USB1287/6 Errata.
8.1 AT90USB1287/6 Errata History
Silicon
90USB1286-16MU
Release
90USB1287-16AU
90USB1287-16MU
Date Code up to 0714
and lots 0735 6H2726*
First Release
Second Release
Third Release
Date Code up to 0648
Date Code up to 0701
from Date Code 0722 to 0806
except lots 0735 6H2726*
Date Code from 0709 to 0801
except lots 0801 7H5103*
Date Code from 0714 to 0810
except lots 0748 7H5103*
Lots 0801 7H5103* and
Date Code from 0814
Lots 0748 7H5103* and
Date Code from 0814
Date Code from 0814
Note ‘*’ means a blank or any alphanumeric string
8.2
AT90USB1287/6 First Release
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• USB signal rate
• VBUS residual level
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
8.
USB Eye Diagram violation in low-speed mode
The low to high transition of D- violates the USB eye diagram specification when transmitting
with low-speed signaling.
Problem fix/workaround
None.
7.
Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state following the perturbation does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
6.
VBUS Session valid threshold voltage
22
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
5.
UBS signal rate
The average USB signal rate may sometime be measured out of the USB specifications
(12MHz 30kHz) with short frames. When measured on a long period, the average signal
rate value complies with the specifications. This bit rate deviation does not generates com-
munication or functional errors.
Problem fix/workaround
None.
4.
VBUS residual level
In USB device and host mode, once a 5V level has been detected to the VBUS pad, a resid-
ual level (about 3V) can be measured on the VBUS pin.
Problem fix/workaround
None.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the
TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
23
7593GS–AVR–03/08
8.3
AT90USB1287/6 Second Release
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
6.
USB Eye Diagram violation in low-speed mode
The low to high transition of D- violates the USB eye diagram specification when transmitting
with low-speed signaling.
Problem fix/workaround
None.
5.
Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state following the perturbation does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
4.
VBUS Session valid threshold voltage
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the
TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
24
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
25
7593GS–AVR–03/08
8.4
AT90USB1287/6 Third Release
• Transient perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts4
4. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state following the perturbation does
not set the SUSPI bit. The internal USB engine remains in suspend mode but the USB differ-
ential receiver is still enabled and generates a typical 300µA extra-power consumption.
Detection of the suspend state after the transient perturbation should be performed by soft-
ware (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable AT90USB64/128 TWI first, before the others nodes of the
TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from sleep mode should be
disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and
then goes back into sleep mode, it may wake up multiple times.
26
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
Problem Fix/workaround
A software workaround is to wait beforeperforming the sleep instruction: until
TCNT2>OCR2+1.
9. AT90USB647/6 Errata.
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
5. USB Eye Diagram violation in low-speed mode
The low to high transition of D- violates the USB eye diagram specification when transmitting
with low-speed signaling.
Problem fix/workaround
None.
4. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state following the perturbation does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power con-
sumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable AT90USB64/128 TWI first versus the others nodes of the
TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mode, the current consump-
tion will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
27
7593GS–AVR–03/08
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep mode again it may wake up several times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
28
AT90USB64/128
7593GS–AVR–03/08
AT90USB64/128
10. Datasheet Revision History for AT90USB64/128
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
10.1 Changes from 7593A to 7593B
1. Changed default configuration for fuse bytes and security byte.
2. Suppression of timer 4,5 registers which does not exist.
3. Updated typical application schematics in USB section
10.2 Changes from 7593B to 7593C
1. Update to package drawings, MQFP64 and TQFP64.
10.3 Changes from 7593C to 7593D
1. For further product compatibility, changed USB PLL possible prescaler configurations.
Only 8MHz and 16MHz crystal frequencies allows USB operation (See Table 6-11 on
page 49).
10.4 Changes from 7593D to 7593E
1. Updated PLL Prescaler table: configuration words are different between AT90USB64x
and AT90USB128x to enable the PLL with a 16 MHz source.
2. Cleaned up some bits from USB registers, and updated information about OTG timers,
remote wake-up, reset and connection timings.
3. Updated clock distribution tree diagram (USB prescaler source and configuration
register).
4. Cleaned up register summary.
5. Suppressed PCINT23:8 that do not exist from External Interrupts.
6. Updated Electrical Characteristics.
7. Added Typical Characteristics.
8. Update Errata section.
10.5 Changes from 7593E to 7593F
1. Removed ’Preliminary’ from document status.
2. Clarification in Stand by mode concerning USB. See “Standby Mode” on page 53.
10.6 Changes from 7593F to 7593G
1. Updated Errata section.
29
7593GS–AVR–03/08
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