AT91M63200-12AL-1.8_技术文档

Features

• Utilizes the ARM7TDMI^™ARM^®Thumb^®Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-Circuit Emulation)

• 2K Bytes Internal RAM

• Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 64M Bytes

– Up to 8 Chip Selects

– Software Programmable 8/16-bit External Data Bus

• Multi-processor Interface (MPI)

AT91

ARM^®Thumb^®

Microcontrollers

– High-performance External Processor Interface

– 512 x 16-bit Dual-port RAM

• 8-channel Peripheral Data Controller

• 8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request

• 58 Programmable I/O Lines

• 6-channel 16-bit Timer/Counter

AT91M63200

Summary

– 6 External Clock Inputs

– 2 Multi-purpose I/O Pins per Channel

• 3 USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

– Support for up to 9-bit Data Transfers

• Master/Slave SPI Interface

– 2 Dedicated Peripheral Data Controller (PDC) Channels

– 8- to 16-bit Programmable Data Length

– 4 External Slave Chip Selects

• Programmable Watchdog Timer

• Power Management Controller (PMC)

– CPU and Peripherals Can be Deactivated Individually

• IEEE 1149.1 JTAG Boundary Scan on All Active Pins

• Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V)

• 1.8V to 3.6V Core Operating Voltage Range

• 2.7V to 5.5V I/O Operating Voltage Range

• -40°C to +85°C Operating Temperature Range

• Available in a 176-lead TQFP Package

Description

The AT91M63200 is a member of the Atmel AT91 16/32-bit microcontroller family

which is based on the ARM7TDMI processor core.

This processor has a high-performance 32-bit RISC architecture with a high-density

16-bit instruction set and very low power consumption. In addition, a large number of

internally banked registers result in very fast exception handling, making the device

ideal for real-time control applications. The AT91 ARM-based MCU family also fea-

tures Atmel’s high-density, in-system programmable, nonvolatile memory technology.

The AT91M63200 has a direct connection to off-chip memory, including Flash,

through the External Bus Interface.

The Multi-processor Interface (MPI) provides a high-performance interface with an

external coprocessor or a high bandwidth peripheral.

The AT91M63200 is manufactured using the Atmel high-density CMOS technology.

By combining the ARM7TDMI microcontroller core with on-chip SRAM, a multi-pro-

cessor interface and a wide range of peripheral functions on a monolithic chip, the

AT91M63200 provides a highly flexible and cost-effective solution to many compute-

intensive multi-processor applications.

Rev. 1028CS–01/00

1

Pin Configuration

Table 1. AT91M63200 Pinout

1

AT91M63200

GND

NCS0

NCS1

NCS2

NCS3

NLB/A0

A1

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

AT91M63200

GND

89

AT91M63200

GND

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

AT91M63200

GND

2

GND

90

GND

3

D8

91

PA19 / RXD1

PA20 / SCK2

PA21 / TXD2

PA22 / RXD2

PA23 / SPCK

PA24/MISO

PA25/MOSI

PA26/NPCS0/NSS

PA27/NPCS1

PA28/NPCS2

PA29/NPCS3

MPI_A1

MPI_D12

MPI_D13

MPI_D14

MPI_D15

PB0/MPI_NOE

PB1/MPI_NLB

PB2/MPI_NUB

PB3

4

D9

92

5

D10

93

6

D11

94

7

D12

95

8

D13

96

9

A2

D14

97

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

A3

D15

98

A4

PB19/TCLK0

PB20/TIOA0

PB21/TIOB0

PB22/TCLK1

VDDIO

99

PB4

A5

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

PB5

A6

PB6

A7

PB7

VDDIO

GND

A8

VDDIO

GND

PB23/TIOA1

PB24/TIOB1

PB25/TCLK2

PB26/TIOA2

PB27/TIOB2

PA0/TCLK3

PA1/TIOA3

PA2/TIOB3

PA3/TCLK4

PA4/TIOA4

PA5/TIOB4

PA6/TCLK5

VDDIO

MPI_A2

PB8

A9

MPI_A3

PB9

A10

MPI_A4

PB10

A11

MPI_A5

PB11

A12

MPI_A6

PB12

A13

MPI_A7

PB13

A14

MPI_A8

PB14

A15

MPI_A9

PB15

A16

MPI_NCS

MPI_RNW

MPI_BR

PB16

A17

PB17/MCKO

NWDOVF

MCKI

A18

A19

MPI_BG

VDDIO

GND

A20/CS7

A21/CS6

A22/CS5

A23/CS4

D0

VDDIO

GND

PA7/TIOA5

PA8/TIOB5

PA9/IRQ0

PA10/IRQ1

PA11/IRQ2

PA12/IRQ3

PA13/FIQ

PA14/SCK0

PA15/TXD0

PA16/RXD0

PA17/SCK1

PA18/TXD1/NTRI

VDDCORE

VDDIO

MPI_D0

PB18/BMS

JTAGSEL

TMS

MPI_D1

MPI_D2

MPI_D3

TDI

MPI_D4

TDO

D1

MPI_D5

TCK

D2

MPI_D6

NTRST

NRST

D3

MPI_D7

D4

MPI_D8

NWAIT

NOE/NRD

NWE/NWR0

NUB/NWR1

VDDCORE

VDDIO

D5

MPI_D9

D6

MPI_D10

MPI_D11

VDDCORE

VDDIO

D7

VDDCORE

VDDIO

AT91M63200

2

AT91M63200

Pin Description

Table 2. AT91M63200 Pin Description

Active

Level

Module

Name

Function

Type

Output

I/O

Comments

A0 - A23

D0 - D15

CS4 - CS7

NCS0 - NCS3

NWR0

Address Bus

–

All valid after reset

Data Bus

–

Chip Select

Output

Input

High

Low

–

A23 - A20 after reset

Chip Select

Lower Byte 0 Write Signal

Lower Byte 1 Write Signal

Read Signal

Used in Byte Write option

Used in Byte Select option

NWR1

EBI

NRD

NWE

Write Enable

NOE

Output Enable

NUB

Upper Byte Select (16-bit SRAM)

Lower Byte Select (16-bit SRAM)

Wait Input

NLB

NWAIT

BMS

Boot Mode Select

Chip Select

Input

Sampled during reset

MPI_NCS

MPI_RNW

Input

Low

–

Read Not Write Signal

Input

Bus Request From External

Processor

MPI_BR

Input

High

MPI_BG

Bus Grant To External Processor

Output Enable

Output

Input

I/O

High

Low

–

MPI

MPI_NOE

MPI_NLB

Lower Byte Select

Upper Byte Select

Address Bus

MPI_NUB

MPI_A1 - MPI_A9

MPI_D0 - MPI_D15 Data Bus

–

IRQ0 - IRQ3

FIQ

External Interrupt Request

Input

I/O

–

PIO controlled after reset

Input after reset

AIC

Fast External Interrupt Request

Timer External Clock

Multipurpose Timer I/O Pin A

Multipurpose Timer I/O Pin B

External Serial Clock

Transmit Data Output

Receive Data Input

–

TCLK0 - TCLK5

TIOA0 - TIOA5

TIOB0 - TIOB5

SCK0 - SCK2

TXD0 - TXD2

RXD0 - RXD2

SPCK

–

Timer

–

I/O

–

I/O

–

USART

SPI

Output

Input

I/O

–

SPI Clock

–

MISO

Master In Slave Out

I/O

–

MOSI

Master Out Slave In

I/O

–

NSS

Slave Select

Input

Output

I/O

Low

–

NPCS0 - NPCS3

PA0 - PA29

PB0 - PB27

NWDOVF

MCKI

Peripheral Chip Select

Programmable I/O Port A

Programmable I/O Port B

Watchdog Timer Overflow

Master Clock Input

PIO

I/O

–

Input after reset

WD

Output

Input

Output

Input

Low

–

Open drain

Schmitt trigger

Clock

Reset

MCKO

Master Clock Output

Hardware Reset Input

–

NRST

Low

Schmitt trigger, internal pull-up

3

Table 2. AT91M63200 Pin Description (Continued)

Active

Level

Module

Name

Function

Type

Comments

JTAGSEL

Selects between JTAG and ICE Mode

Input

High enables IEEE 1149.1 JTAG

boundary scan.

Low enables ARM Standard ICE

debug.

TMS

Test Mode Select

Test Data In

Input

–

Schmitt trigger, internal pull-up

JTAG/ICE

TDI

TDO

Test Data Out

Test Clock

Output

Input

–

TCK

–

Schmitt trigger, internal pull-up

3V or 5V nominal supply

NTRST

VDDIO

VDDCORE

GND

Test Reset Input

I/O Power

Input

Low

–

Power

Ground

Input

Power

Core Power

–

2.0V or 3V nominal supply

Ground

–

Emulation

NTRI

Tristate Mode Enable

Low

Sampled during reset

Figure 1. Pin Configuration (Top View)

176

133

132

1

AT91M63X00

176-Lead TQFP

44

89

45

88

AT91M63200

4

AT91M63200

Block Diagram

Figure 2. AT91M63200

NRST

NTRST

TMS

TDO

TDI

Reset

Embedded

ICE

MPI_A1-MPI_A9

TCK

MPI_D0-MPI_D15

MPI_NCS

MPI_RNW

MPI_BR

ARM7TDMI Core

MPI_BG

ASB

MCKI

PB17/MCKO

PB3

P

I

O

PB0/MPI_NOE

PB1/MPI_NLB

PB2/MPI_NUB

PB4

PB5

D0-D15

Internal RAM

2/8K Bytes

PB6

A1-A19

A0/NLB

NRD/NOE

NWR0/NWE

NWR1/NUB

NWAIT

NCS0-NCS3

A20/CS7

A21/CS6

A22/CS5

A23/CS4

PB7

PB8

PB9

PB10

PB11

PB12

PB13

PB14

PB15

PB16

ASB

Controller

AMBA Bridge

PA9/IRQ0

PA10/IRQ1

PA11/IRQ2

PA12/IRQ3

PA13/FIQ

EBI User

Interface

AIC: Advanced

Interrupt Controller

P

I

O

PB18/BMS

TC: Timer

Counter

Block 0

PB19/TCLK0

PB22/TCLK1

PB25/TCLK2

PA14/SCK0

PA15/TXD0

PA16/RXD0

2 PDC

Channels

USART0

PB20/TIOA0

PB21/TIOB0

APB

TC0

TC1

TC2

PA17/SCK1

PA18/TXD1/NTRI

PA19/RXD1

2 PDC

Channels

USART1

USART2

PB23/TIOA1

PB24/TIOB1

P

I

O

PA20/SCK2

PA21/TXD2

PA22/RXD2

PB26/TIOA2

PB27/TIOB2

2 PDC

Channels

TC: Timer

Counter

Block 1

PA0/TCLK3

PA3/TCLK4

PA6/TCLK5

PA23/SPCK

PA24/MISO

PMC: Power

Management

Controller

SPI: Serial

Peripheral

Interface

PA25/MOSI

PA26/NPCS0/NSS

PA27/NPCS1

PA28/NPCS2

PA29/NPCS3

PA1/TIOA3

PA2/TIOB3

TC0

TC1

TC2

Chip ID

PA4/TIOA4

PA5/TIOB4

2 PDC

Channels

PA7/TIOA5

PA8/TIOB5

WD: Watchdog

Timer

PIOA: Parallel I/O

Controller A

PIOB: Parallel I/O

Controller B

NWDOVF

5

Architectural Overview

The AT91M63200 architecture consists of two main buses,

the Advanced System Bus (ASB) and the Advanced

Peripheral Bus (APB). The ASB is designed for maximum

performance. It interfaces the processor with the on-chip

32-bit memories and the external memories and devices by

means of the External Bus Interface (EBI). The APB is

designed for accesses to on-chip peripherals and is opti-

mized for low power consumption. The AMBA Bridge pro-

vides an interface between the ASB and the APB.

The ARM7TDMI processor operates in little-endian mode

in the AT91M63200 microcontroller. The processor’s inter-

nal architecture and the ARM and Thumb instruction sets

are described in the ARM7TDMI datasheet. The memory

map and the on-chip peripherals are described in detail in

the datasheet entitled “AT91M63200 Datasheet” (Literature

No. 1028). Electrical and mechanical characteristics are

documented in a datasheet entitled “AT91M63200 Electri-

cal and Mechanical Characteristics” (Literature No. 1090).

An on-chip Peripheral Data Controller (PDC) transfers data

between the on-chip USARTs/SPI and the on- and off-chip

memories without processor intervention. Most importantly,

the PDC removes the processor interrupt handling over-

head and significantly reduces the number of clock cycles

required for a data transfer. It can transfer up to 64K contig-

uous bytes without reprogramming the starting address. As

a result, the performance of the microcontroller is

increased and the power consumption reduced.

The ARM Standard In-Circuit-Emulation debug interface is

supported via the ICE port of the AT91M63200 via the

JTAG/ICE port when JTAGSEL is low. IEEE JTAG bound-

ary scan is supported via the JTAG/ICE port when JTAG-

SEL is high.

PDC: Peripheral Data Controller

The AT91M63200 has an 8-channel PDC dedicated to the

three on-chip USARTs and to the SPI. One PDC channel is

connected to the receiving channel and one to the transmit-

ting channel of each peripheral.

The AT91M63200 peripherals are designed to be easily

programmable with a minimum number of instructions.

Each peripheral has a 16K byte address space allocated in

the upper 3M bytes of the 4G byte address space. Except

for the interrupt controller, the peripheral base address is

the lowest address of its memory space. The peripheral

register set is composed of control, mode, data, status and

interrupt registers.

The user interface of a PDC channel is integrated in the

memory space of each USART channel and in the memory

space of the SPI. It contains a 32-bit address pointer regis-

ter and a 16-bit count register. When the programmed data

is transferred, an end-of-transfer interrupt is generated by

the corresponding peripheral. See the USART section and

the SPI section for more details on PDC operation and pro-

gramming.

To maximize the efficiency of bit manipulation, frequently

written registers are mapped into three memory locations.

The first address is used to set the individual register bits,

the second resets the bits and the third address reads the

value stored in the register. A bit can be set or reset by writ-

ing a one to the corresponding position at the appropriate

address. Writing a zero has no effect. Individual bits can

thus be modified without having to use costly read-modify-

write and complex bit manipulation instructions.

Power Supplies

The AT91M63200 has two kinds of power supply pins:

• VDDCORE pins, which power the chip core

• VDDIO pins, which power the I/O lines

This allows core power consumption to be reduced by sup-

plying it with a lower voltage than the I/O lines. The

VDDCORE pins must never be powered at a voltage

greater than the supply voltage applied to the VDDIO pins.

All of the external signals of the on-chip peripherals are

under the control of the parallel I/O controller. The PIO con-

troller can be programmed to insert an input filter on each

pin or generate an interrupt on a signal change. After reset,

the user must carefully program the PIO Controller in order

to define which peripheral signals are connected with off-

chip logic.

Typical supported voltage combinations are shown in the

following table:

Pins

VDDCORE

VDDIO

Typical Supply Voltages

3.0V or 3.3V 3.0V or 3.3V

5.0V 3.0V or 3.3V 3.0V or 3.3V

2.0V

AT91M63200

6

AT91M63200

Internal sources are programmed to be level sensitive or

edge triggered. External sources can be programmed to be

positive or negative edge triggered or high- or low-level

sensitive.

EBI: External Bus Interface

The EBI generates the signals that control the access to

the external memory or peripheral devices. The EBI is fully

programmable and can address up to 64M bytes. It has

eight chip selects and a 24-bit address bus, the upper four

bits of which are multiplexed with a chip select.

PIO: Parallel I/O Controller

The AT91M63200 features 58 programmable I/O lines. 14

pins on the AT91M63200 are dedicated as general pur-

pose I/O pins. Other I/O lines are multiplexed with on-chip

peripheral I/O signals in order to optimize the use of avail-

able package pins. The I/O lines are controlled by two sep-

arate and identical PIO controllers (PIOA and PIOB). Each

PIO controller also provides an internal interrupt signal to

the Advanced Interrupt Controller (AIC).

The 16-bit data bus can be configured to interface with 8-

or 16-bit external devices. Separate read and write control

signals allow for direct memory and peripheral interfacing.

The EBI supports different access protocols, allowing sin-

gle clock cycle memory accesses.

The main features are:

• External memory mapping

• Up to 8 chip select lines

• 8- or 16-bit data bus

USART: Universal

Synchronous/Asynchronous

Receiver/Transmitter

The AT91M63200 provides three identical, full-duplex, uni-

versal synchronous/asynchronous receiver/transmitters

that interface to the APB and are connected to the Periph-

eral Data Controller.

• Byte write or byte select lines

• Remap of boot memory

• Two different read protocols

• Programmable wait state generation

• External wait request

• Programmable data float time

The main features are:

• Programmable baud rate generator

• Parity, framing and overrun error detection

• Line break generation and detection

MPI: Multi-Processor Interface

The AT91M63200 features a second bus interface that is

dedicated to parallel data exchange with an external pro-

cessing device. The MPI features a 1K byte dual-port RAM

memory and memory access arbitration logic. The ARM

processor core and the external processor can both read

and write to the dual-port RAM memory.

• Automatic echo, local loopback and remote loopback

channel modes

• Multi-drop mode: address detection and generation

• Interrupt generation

• Two dedicated peripheral data controller channels

• 5-, 6-, 7-, 8- and 9-bit character length

AIC: Advanced Interrupt Controller

The AT91M63200 has an 8-level priority, individually

maskable, vectored interrupt controller. This feature sub-

stantially reduces the software and real-time overhead in

handling internal and external interrupts.

SPI: Serial Peripheral Interface

The AT91M63200 features an SPI, which provides commu-

nication with external devices in master or slave mode.

The interrupt controller is connected to the NFIQ (fast inter-

rupt request) and the NIRQ (standard interrupt request)

inputs of the ARM7TDMI processor. The processor’s NFIQ

line can only be asserted by the external fast interrupt

request input: FIQ. The NIRQ line can be asserted by the

interrupts generated by the on-chip peripherals and the

external interrupt request lines: IRQ0 to IRQ3.

The SPI has four external chip selects that can be con-

nected to up to 15 devices. The data length is programma-

ble, from 8- to 16-bit.

As for the USART, a 2-channel PDC is used to move data

directly between memory and the SPI without CPU inter-

vention for maximum real-time processing throughput.

An 8-level priority encoder allows the customer to define

the priority between the different NIRQ interrupt sources.

7

TC: Timer/Counter

PMC: Power Management Controller

The AT91M63200 features two identical Timer/Counter

blocks, each containing three identical 16-bit timer counter

channels. Each channel can be independently

programmed to perform a wide range of functions,

including frequency measurement, event counting, interval

measurement, pulse generation, delay timing and pulse

width modulation.

The Power Management Controller allows optimization of

power consumption. The PMC enables/disables the clock

inputs to most of the peripherals as well as to the ARM pro-

cessor core.

When the ARM core clock is disabled, the current instruc-

tion is processed before the clock is stopped. The clock

can be re-enabled by any enabled interrupt or by a hard-

ware reset.

Each Timer/Counter channel has 3 external clock inputs, 5

internal clock inputs, and 2 multi-purpose input/output sig-

nals that can be configured by the user. Each channel

drives an internal interrupt signal that can be programmed

to generate processor interrupts via the Advanced Interrupt

Controller (AIC).

When a peripheral clock is disabled, the clock is immedi-

ately stopped. When the clock is re-enabled, the peripheral

resumes action where it left off.

Due to the static nature of the design, the contents of the

on-chip RAM and registers for which the clocks are dis-

abled remain unchanged.

Each Timer Counter block features two global registers that

act upon all three TC channels. The Block Control Register

allows the three channels to be started simultaneously with

the same instruction. The Block Mode Register defines the

external clock inputs for each Timer/Counter channel,

allowing them to be chained.

SF: Special Function

The AT91M63200 provides registers that implement the

following special functions:

• Chip identification

• RESET status

WD: Watchdog Timer

The AT91M63200 features an internal watchdog timer,

which can be used to guard against system lock-up if the

software becomes trapped in a deadlock.

AT91M63200

8

AT91M63200

Ordering Information

Max Speed

(MHz)

Operating

Power Supply Range

RAM

(Bytes)

Operating

Temperature Range

Ordering Code

Package

25

2.7V to 3.6V (Core)

2.7V to 5.5V (I/Os)

AT91M63200-25AC

2K

TQFP 176

Commercial

(0°C to 70°C)

AT91M63200-25AI

Industrial

(-40°C to 85°C)

12

1.8V to 3.6V (Core)

2.7V to 3.6V (I/Os)

AT91M63200-12AC-1.8

AT91M63200-12AI-1.8

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

9

Package Outline TQFP 176

Table 3. Common Dimensions (mm)

Symbol

c

Min

0.09

0.45

Nom

Max

0.2

c1

L

0.16

0.75

0.6

L1

R2

R1

S

1.00 REF

0.08

0.2

0°

0.2

θ

3.5°

7°

θ1

θ2

θ3

A

0°

11°

12°

13°

1.6

A1

A2

0.05

1.35

0.15

1.45

1.4

Tolerances of form and position

aaa

bbb

0.2

Table 4. Lead Count Dimensions

b

b1

Nom

0.2

Count

D/E

BSC

D1/E1

BSC

e

BSC

Version

ccc

ddd

Min

Nom

0.22

Max

Min

Max

176

A

26.0

24.0

0.17

0.27

0.17

0.23

0.50

0.10

0.08

AT91M63200

10

AT91M63200

Figure 3. 176-lead TQFP Package

PIN 1

θ2

θ3

θ

θ1

11

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1028CS–01/00/5M


型号：	AT91M63200-12AL-1.8
厂家：	ATMEL
描述：	RISC Microcontroller, 32-Bit, 12MHz, CMOS, PQFP176, TQFP-176 微控制器
文件：	总12页 (文件大小：232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT91M63200-12AL-1.8 [ATMEL]

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