AT91RM9200_0509 [ATMEL]
ARM920T based Microcontroller; 基于ARM920T微处理器
| 型号： | AT91RM9200_0509 |
| 厂家： | 
ATMEL |
| 描述： | ARM920T based Microcontroller |
| 文件： | 总38页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM920T™ ARM® Thumb® Processor
– 200 MIPS at 180 MHz, Memory Management Unit
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– In-circuit Emulator including Debug Communication Channel
– Mid-level Implementation Embedded Trace Macrocell (256-ball BGA Package Only)
• Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode
• Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
• External Bus Interface (EBI)
ARM920T™-
based
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to
CompactFlash® and NAND Flash/SmartMedia™
• System Peripherals for Enhanced Performance:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power Optimization Capabilities
– Four Programmable External Clock Signals
Microcontroller
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored
Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change
Interrupt and Open-drain Capability on Each Line
AT91RM9200
Summary
– 20-channel Peripheral DMA Controller (PDC)
• Ethernet MAC 10/100 Base-T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package)
– Integrated FIFOs and Dedicated DMA Channels
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
• Multimedia Card Interface (MCI)
– Automatic Protocol Control and Fast Automatic Data Transfers
– MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards
• Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I2S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Support for ISO7816 T0/T1 Smart Card
– Hardware Handshaking
– RS485 Support, IrDA Up To 115 Kbps
– Full Modem Control Lines on USART1
• Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects
• Two 3-channel, 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two-wire Interface (TWI)
– Master Mode Support, All 2-wire Atmel EEPROMs Supported
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• Power Supplies
– 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL
– 3.0V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)Available
• in a 208-lead PQFP or 256-ball BGA Package
Rev. 1768IS-ATARM–30-Sep-05
1. Description
The AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb pro-
cessor. It incorporates a rich set of system and application peripherals and standard interfaces
in order to provide a single-chip solution for a wide range of compute-intensive applications that
require maximum functionality at minimum power consumption at lowest cost.
The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency
External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip mem-
ories and memory-mapped peripherals is required by the application. The EBI incorporates
controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features
specific circuitry facilitating the interface for NAND Flash/SmartMedia and Compact Flash.
The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the
ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing
the time taken to transfer to an interrupt handler.
The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals,
enabling them to transfer data to or from on- and off-chip memories without processor interven-
tion. This reduces the processor overhead when dealing with transfers of continuous data
streams.The AT91RM9200 benefits from a new generation of PDC which includes dual pointers
that simplify significantly buffer chaining.
The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with general-
purpose data I/Os for maximum flexibility in device configuration. An input change interrupt,
open drain capability and programmable pull-up resistor is included on each line.
The Power Management Controller (PMC) keeps system power consumption to a minimum by
selectively enabling/disabling the processor and various peripherals under software control. It
uses an enhanced clock generator to provide a selection of clock signals including a slow clock
(32 kHz) to optimize power consumption and performance at all times.
The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed
Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides
connection to a extensive range of external peripheral devices and a widely used networking
layer. In addition, it provides an extensive set of peripherals that operate in accordance with sev-
eral industry standards, such as those used in audio, telecom, Flash Card, infrared and Smart
Card applications.
To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug
features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real
time trace. This enables the development and debug of all applications, especially those with
real-time constraints.
2
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
2. Block Diagram
Bold arrows (
) indicate master-to-slave dependency.
Figure 2-1. AT91RM9200 Block Diagram
Reset
and
Test
TST0-TST1
NRST
TSYNC
ARM920T Core
TCLK
ICE
ETM
JTAGSEL
TDI
TPS0 - TPS2
JTAG
Scan
TDO
Instruction Cache
16K bytes
Data Cache
16K bytes
TPK0 - TPK15
MMU
TMS
TCK
NTRST
BMS
D0-D15
FIQ
A0/NBS0
Address
Decoder
A1/NBS2/NWR2
A2-A15/A18-A22
A16/BA0
AIC
Fast SRAM
16K bytes
IRQ0-IRQ6
EBI
PCK0-PCK3
A17/BA1
CompactFlash
NAND Flash
SmartMedia
Abort
Status
NCS0/BFCS
NCS1/SDCS
NCS2
PLLRCB
PLLRCA
XIN
PLLB
PLLA
Fast ROM
128K bytes
NCS3/SMCS
NRD/NOE/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
Misalignment
Detector
PMC
OSC
XOUT
Peripheral
Bridge
Bus
Arbiter
SDCKE
SDRAM
Controller
RAS-CAS
SDWE
System
Timer
SDA10
Peripheral
Data
Controller
BFRDY/SMOE
BFCK
BFAVD
BFBAA/SMWE
BFOE
BFWE
A23-A24
Memory
Controller
Burst
Flash
Controller
XIN32
OSC
RTC
XOUT32
A25/CFRNW
NWAIT
Static
Memory
Controller
DRXD
DTXD
NCS4/CFCS
DBGU
NCS5/CFCE1
NCS6/CFCE2
NCS7
PDC
D16-D31
PIOA/PIOB/PIOC/PIOD
Controller
HDMA
HDPA
DMA
FIFO
FIFO
USB Host
HDMB
HDPB
DDM
DDP
USB Device
DMA
FIFO
ETXCK-ERXCK-EREFCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
MCCK
MCCDA
MCDA0-MCDA3
MCCDB
MCDB0-MCDB3
MCI
Ethernet MAC 10/100
PDC
EMDIO
EF100
RXD0
TXD0
SCK0
RTS0
CTS0
APB
TF0
TK0
TD0
RD0
RK0
RF0
USART0
USART1
PDC
SSC0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
DCD1
RI1
PDC
TF1
TK1
TD1
RD1
RK1
RF1
SSC1
PDC
PDC
PDC
PDC
PDC
TF2
TK2
TD2
RD2
RK2
RF2
RXD2
TXD2
SCK2
RTS2
CTS2
USART2
USART3
SSC2
RXD3
TXD3
SCK3
RTS3
CTS3
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TC0
TC1
TC2
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
SPI
TCLK3
TCLK4
TCLK5
TIOA3
TIOB3
TIOA4
TIOB4
TIOA5
TIOB5
Timer Counter
PDC
TC3
TC4
TC5
TWD
TWI
TWCK
3
1768IS–ATARM–30-Sep-05
3. Key Features
This section presents the key features of each block.
3.1
ARM920T Processor
• ARM9TDMI™-based on ARM® Architecture v4T
• Two instruction sets
– ARM® High-performance 32-bit Instruction Set
– Thumb® High Code Density 16-bit Instruction Set
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 16-Kbyte Data Cache, 16-Kbyte Instruction Cache
– Virtually-addressed 64-way Associative Cache
– 8 words per line
– Write-though and write-back operation
– Pseudo-random or Round-robin replacement
– Low-power CAM RAM implementation
• Write Buffer
– 16-word Data Buffer
– 4-address Address Buffer
– Software Control Drain
• Standard ARMv4 Memory Management Unit (MMU)
– Access permission for sections
– Access permission for large pages and small pages can be specified separately for
each quarter of the pages
– 16 embedded domains
– 64 Entry Instruction TLB and 64 Entry Data TLB
• 8-, 16-, 32-bit Data Bus for Instructions and Data
3.2
Debug and Test
• Integrated Embedded In-Circuit-Emulator
• Debug Unit
– Two-pin UART
– Debug Communication Channel
– Chip ID Register
• Embedded Trace Macrocell: ETM9 Rev2a
– Medium Level Implementation
– Half-rate Clock Mode
4
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two Counters
– One Sequencer
– One 18-byte FIFO
• IEEE1149.1 JTAG Boundary Scan on all Digital Pins
3.3
Boot Program
• Default Boot Program stored in ROM-based products
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader supporting a wide range of non-volatile memories
– SPI DataFlash® connected on SPI NPCS0
– Two-wire EEPROM
– 8-bit parallel memories on NCS0
• Boot Uploader in case no valid program is detected in external NVM and supporting several
communication media
• Serial communication on a DBGU (XModem protocol)
• USB Device Port (DFU Protocol)
3.4
Embedded Software Services
• Compliant with ATPCS
• Compliant with AINSI/ISO Standard C
• Compiled in ARM/Thumb Interworking
• ROM Entry Service
• Tempo, Xmodem and DataFlash services
• CRC and Sine tables
3.5
Reset Controller
• Two reset input lines (NRST and NTRST) providing, respectively:
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
and:
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero.
• Initialization of the embedded ICE TAP controller.
3.6
Memory Controller
• Programmable Bus Arbiter handling four Masters
– Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC
Masters
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1768IS–ATARM–30-Sep-05
– Each Master can be assigned a priority between 0 and 7
• Address Decoder provides selection for
– Eight external 256-Mbyte memory areas
– Four internal 1-Mbyte memory areas
– One 256-Mbyte embedded peripheral area
• Boot Mode Select Option
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
• Abort Status Registers
– Source, Type and all parameters of the access leading to an abort are saved
• Misalignment Detector
– Alignment checking of all data accesses
– Abort generation in case of misalignment
• Remap command
– Provides remapping of an internal SRAM in place of the boot NVM
3.7
External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– Burst Flash Controller
• Additional logic for NAND Flash/SmartMedia and CompactFlash support
• Optimized External Bus:
– 16- or 32-bit Data Bus
– Up to 26-bit Address Bus, up to 64-Mbytes addressable
– Up to 8 Chip Selects, each reserved to one of the eight Memory Areas
– Optimized pin multiplexing to reduce latencies on External Memories
• Configurable Chip Select Assignment:
– Burst Flash Controller or Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support
– Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support
– Static Memory Controller on NCS7
3.8
Static Memory Controller
• External memory mapping, 512-Mbyte address space
• Up to 8 Chip Select Lines
• 8- or 16-bit Data Bus
• Remap of Boot Memory
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
6
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
– Two different Read Protocols for each Memory Bank
• Multiple device adaptability
– Compliant with LCD Module
– Programmable Setup Time Read/Write
– Programmable Hold Time Read/Write
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
3.9
SDRAM Controller
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh and Low-power Modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)
• Auto Precharge Command not used
3.10 Burst Flash Controller
• Multiple Access Modes supported
– Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses
– Asynchronous Mode Half-word Write Accesses
• Adaptability to different device speed grades
– Programmable Burst Flash Clock Rate
– Programmable Data Access Time
– Programmable Latency after Output Enable
• Adaptability to different device access protocols and bus interfaces
– Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled
Address Advance
– Multiplexed or separate address and data buses
7
1768IS–ATARM–30-Sep-05
– Continuous Burst and Page Mode Accesses supported
3.11 Peripheral DMA Controller (PDC)
• Generates transfers to/from peripherals such as DBGU, USART, SSC, SPI and MCI
• Twenty channels
• One Master Clock cycle needed for a transfer from memory to peripheral
• Two Master Clock cycles needed for a transfer from peripheral to memory
3.12 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM® Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…)
– Source 2 to Source 31 control thirty embedded peripheral interrupts or external
interrupts
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
External Sources
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations
• General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
3.13 Power Management Controller
• Optimizes the power consumption of the whole system
• Embeds and controls:
– One Main Oscillator and One Slow Clock Oscillator (32.768Hz)
– Two Phase Locked Loops (PLLs) and Dividers
– Clock Prescalers
• Provides:
– the Processor Clock PCK
– the Master Clock MCK
– the USB Clocks, UHPCK and UDPCK, respectively for the USB Host Port and the
USB Device Port
8
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
– Programmable automatic PLL switch-off in USB Device suspend conditions
– up to thirty peripheral clocks
– four programmable clock outputs PCK0 to PCK3
• Four operating modes:
– Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode
3.14 System Timer
• One Period Interval Timer, 16-bit programmable counter
• One Watchdog Timer, 16-bit programmable counter
• One Real-time Timer, 20-bit free-running counter
• Interrupt Generation on event
3.15 Real Time Clock
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
3.16 Debug Unit
• System peripheral to facilitate debug of Atmel’s ARM®-based systems
• Composed of the following functions
– Two-pin UART
– Debug Communication Channel (DCC) support
– Chip ID Registers
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Interrupt generation
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
– Interrupt generation
• Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of
peripherals
9
1768IS–ATARM–30-Sep-05
3.17 PIO Controller
• Up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
3.18 USB Host Port
• Compliance with Open HCI Rev 1.0 specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
• Root hub integrated with two downstream USB ports
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Memory Controller
3.19 USB Device Port
• USB V2.0 full-speed compliant, 12 Mbits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded dual-port RAM for endpoints
• Suspend/Resume logic
• Ping-pong mode (two memory banks) for isochronous and bulk endpoints
• Six general-purpose endpoints
– Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode
– Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode
– Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode
3.20 Ethernet MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 Mbits per second data throughput capability
• Full- and half-duplex operation
• MII or RMII interface to the physical layer
• Register interface to address, status and control registers
• DMA interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
10
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Supports promiscuous mode where all valid frames are copied to memory
• Supports physical layer management through MDIO interface
3.21 Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Connection to PDC channel optimizes data transfers
– One channel for the receiver, one channel for the transmitter
– Next buffer support
3.22 Two-wire Interface
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential Read/Write operations
3.23 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Optional hardware handshaking RTS-CTS
– Optional modem signal management DTR-DSR-DCD-RI
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
11
1768IS–ATARM–30-Sep-05
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
• Connection of two Peripheral DMA Controller (PDC) channels
– Offers buffer transfer without processor intervention
3.24 Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
• Contains an independent receiver and transmitter and a common clock divider
• Interfaced with two PDC channels to reduce processor overhead
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
3.25 Timer Counter
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Internal interrupt signal
• Two global registers that act on all three TC Channels
3.26 MultiMedia Card Interface
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
12
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
• Supports two slots
– One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card
• Support for stream, block and multi-block data read and write
• Connection to a Peripheral DMA Controller (PDC) channel
– Minimizes processor intervention for large buffer transfers
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1768IS–ATARM–30-Sep-05
4. AT91RM9200 Product Properties
4.1
Power Supplies
The AT91RM9200 has five types of power supply pins:
• VDDCORE pins. They power the core, including processor, memories and peripherals;
voltage ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDIOM pins. They power the External Bus Interface I/O lines; voltage ranges from 3.0V to
3.6V, 3V or 3.3V nominal.
• VDDIOP pins. They power the Peripheral I/O lines and the USB transceivers; voltage ranges
from 3.0V to 3.6V, 3V or 3.3V nominal.
• VDDPLL pins. They power the PLL cells; voltage ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDOSC pin. They power both oscillators; voltage ranges from 1.65V to 1.95V, 1.8V
nominal.
The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 15 and
Table 4-2 on page 17. These supplies enable the user to power the device differently for inter-
facing with memories and for interfacing with peripherals.
Ground pins are common to all power supplies, except VDDPLL and VDDOSC pins. For these
pins, GNDPLL and GNDOSC are provided, respectively.
4.2
Pinout
The AT91RM9200 is available in two packages:
• 208-lead PQFP, 31.2 x 31.2 mm, 0.5 mm lead pitch
• 256-ball BGA, 15 x 15 mm, 0.8 mm ball pitch
The product features of the 256-ball BGA package are extended compared to the 208-lead
PQFP package. The features that are available only with the 256-ball BGA package are:
• Parallel I/O Controller D
• ETM port with outputs multiplexed on the PIO Controller D
• a second USB Host transceiver, opening the Hub capabilities of the embedded USB Host.
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AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.2.1
208-lead PQFP Package Pinout
Table 4-1.
Pin
AT91RM9200 Pinout for 208-lead PQFP Package
Pin
Pin
Number Signal Name
Pin
Number Signal Name
Number Signal Name
Number Signal Name
1
PC24
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDDPLL
PLLRCB
GNDPLL
VDDIOP
GND
73
PA27
PA28
VDDIOP
GND
PA29
PA30
PA31/BMS
PB0
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
TMS
2
PC25
74
NTRST
VDDIOP
GND
3
PC26
75
4
PC27
76
5
PC28
77
TST0
TST1
NRST
VDDCORE
GND
6
PC29
PA0
78
7
VDDIOM
GND
PA1
79
8
PA2
80
9
PC30
PA3
81
PB1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PC31
PA4
82
PB2
PB23
PB24
PB25
PB26
PB27
PB28
PB29
HDMA
HDPA
DDM
PC10
PA5
83
PB3
PC11
PA6
84
PB4
PC12
PA7
85
PB5
PC13
PA8
86
PB6
PC14
PA9
87
PB7
PC15
PA10
PA11
PA12
PA13
VDDIOP
GND
88
PB8
PC0
89
PB9
PC1
90
PB10
PB11
PB12
VDDIOP
GND
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
JTAGSEL
TDI
VDDCORE
GND
91
92
DDP
PC2
93
VDDIOP
GND
PC3
PA14
PA15
PA16
PA17
VDDCORE
GND
94
PC4
95
VDDIOM
GND
PC5
96
PC6
97
A0/NBS0
A1/NBS2/NWR2
A2
VDDIOM
GND
98
99
VDDPLL
PLLRCA
GNDPLL
XOUT
XIN
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
100
101
102
103
104
105
106
107
108
A3
A4
A5
A6
A7
VDDOSC
GNDOSC
XOUT32
XIN32
A8
A9
TDO
A10
TCK
SDA10
15
1768IS–ATARM–30-Sep-05
Table 4-1.
AT91RM9200 Pinout for 208-lead PQFP Package (Continued)
Pin
Pin
Pin
Pin
Number Signal Name
Number Signal Name
Number Signal Name
Number Signal Name
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
A11
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
PC7
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
CAS
SDWE
D0
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
D10
VDDIOM
GND
PC8
D11
PC9
D12
A12
VDDIOM
D1
D13
A13
GND
D2
D14
A14
NCS0/BFCS
NCS1/SDCS
NCS2
D3
D15
A15
VDDIOM
GND
D4
VDDIOM
GND
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
VDDCORE
GND
NCS3/SMCS
NRD/NOE/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
A16/BA0
A17/BA1
A18
D5
D6
VDDCORE
GND
D7
A19
A20
A21
SDCKE
D8
160
A22
RAS
D9
Note:
1. Shaded cells define the pins powered by VDDIOM.
4.2.2
Mechanical Overview of the 208-lead PQFP Package
Figure 4-1 shows the orientation of the 208-lead PQFP package.
A detailed mechanical description is given in the section Mechanical Characteristics.
Figure 4-1. 208-lead PQFP Pinout (Top View)
156
105
157
104
208
53
1
52
16
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.2.3
256-ball BGA Package Pinout
Table 4-2.
Pin
A1
AT91RM9200 Pinout for 256-ball BGA Package
Signal Name
TDI
Pin
C3
Signal Name
PD14
PB22
PB19
PD10
PB13
PB12
PB6
Pin
E5
Signal Name
TCK
Pin
G14
G15
G16
G17
H1
Signal Name
PA1
A2
JTAGSEL
PB20
PB17
PD11
PD8
C4
E6
GND
PB15
GND
PB7
PA2
A3
C5
E7
PA3
A4
C6
E8
XIN32
PD23
A5
C7
E9
A6
C8
E10
E11
E12
E13
E14
E15
E16
E17
F1
PB3
H2
PD20
A7
VDDIOP
PB9
C9
PA29
PA26
PA25
PA9
H3
PD22
A8
C10
C11
C12
C13
C14
C15
C16
C17
D1
PB1
H4
PD21
A9
PB4
GND
H5
VDDIOP
VDDPLL
VDDIOP
GNDPLL
GND
A10
A11
A12
A13
A14
A15
A16
A17
B1
PA31/BMS
VDDIOP
PA23
PA20
H13
H14
H15
H16
H17
J1
PA18
PA6
VDDCORE
GND
PD3
PA19
PD0
GND
PA8
PD16
GND
PB23
PB25
PB24
VDDCORE
PB16
PB11
PA30
PA28
PA4
XOUT32
PD25
PA14
PD5
F2
VDDIOP
PA13
TST1
VDDIOP
VDDIOP
GND
F3
J2
PD27
D2
F4
J3
PD24
TDO
D3
F5
J4
PD26
B2
PD13
PB18
PB21
PD12
PD9
D4
F6
J5
PB28
B3
D5
VDDIOP
PD7
F7
J6
PB29
B4
D6
F9
J12
J13
J14
J15
J16
J17
K1
GND
B5
D7
PB14
VDDIOP
PB8
F11
F12
F13
F14
F15
F16
F17
G1
GNDOSC
VDDOSC
VDDPLL
GNDPLL
XIN
B6
D8
B7
GND
D9
B8
PB10
PB5
D10
D11
D12
D13
D14
D15
D16
D17
E1
PB2
PD2
B9
GND
PD1
B10
B11
B12
B13
B14
B15
B16
B17
C1
PB0
PA22
PA5
HDPA
DDM
VDDIOP
PA24
PA21
PLLRCB
PD19
PD17
GND
PB26
PD18
PB27
PA27
PA0
K2
PA16
K3
HDMA
VDDIOP
DDP
PA17
PA10
G2
K4
PA15
PD6
G3
K5
PA11
PD4
G4
K13
K14
K15
K16
K17
PC5
PA12
NRST
NTRST
GND
G5
PC4
PA7
E2
G6
PC6
TMS
E3
G12
G13
VDDIOM
XOUT
C2
PD15
E4
TST0
17
1768IS–ATARM–30-Sep-05
Table 4-2.
AT91RM9200 Pinout for 256-ball BGA Package (Continued)
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
NWR1/NBS1/
CFIOR
L1
GND
N2
A5
P13
D15
T7
L2
HDPB
HDMB
A6
N3
A9
P14
P15
P16
P17
R1
PC26
T8
SDWE
GND
L3
N4
A4
PC27
T9
L4
N5
A14
VDDIOM
GND
T10
T11
T12
T13
T14
T15
T16
T17
U1
VDDCORE
D9
L5
GND
N6
SDA10
L6
VDDIOP
PC10
N7
A8
GND
D12
L12
L13
L14
L15
L16
L17
N8
A21
R2
GND
GND
PC15
N9
NRD/NOE/CFOE
R3
A18
PC19
PC2
N10
N11
N12
N13
RAS
D2
R4
A20
PC21
PC3
R5
PC8
PC23
VDDCORE
PLLRCA
GND
PC28
R6
VDDIOM
NCS3/SMCS
PC25
R7
VDDCORE
NWR3/NBS3/
CFIOW
M1
VDDIOM
N14
PC31
R8
U2
GND
M2
GND
N15
N16
N17
P1
PC30
R9
D0
U3
A16/BA0
A19
M3
A3
PC11
R10
R11
R12
R13
R14
R15
R16
R17
T1
VDDIOM
D8
U4
M4
A1/NBS2/NWR2
A10
PC12
U5
GND
NCS0/BFCS
SDCK
CAS
M5
A7
D13
U6
M6
A2
P2
A13
PC17
U7
M7
GND
P3
A12
VDDIOM
PC24
U8
M9
NCS1/SDCS
D4
P4
VDDIOM
U9
D3
M11
M12
M13
M14
M15
M16
M17
N1
P5
A11
PC29
U10
U11
U12
U13
U14
U15
U16
U17
D6
GND
P6
A22
VDDIOM
A15
D7
PC13
PC1
P7
PC9
D11
P8
NWR0/NWE/CFWE
T2
VDDCORE
A17/BA1
PC7
D14
PC0
P9
SDCKE
D1
T3
PC16
PC18
PC20
PC22
GND
P10
P11
P12
T4
PC14
A0/NBS0
D5
T5
VDDIOM
NCS2
D10
T6
Note:
1. Shaded cells define the pins powered by VDDIOM.
4.2.4
Mechanical Overview of the 256-ball BGA Package
Figure 4-2 on page 19 shows the orientation of the 256-ball BGA Package.
A detailed mechanical description is given in the section Mechanical Characteristics.
18
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
Figure 4-2. 256-ball BGA Pinout (Top View)
4.3
Peripheral Multiplexing on PIO Lines
The AT91RM9200 features four PIO controllers:
• PIOA and PIOB, multiplexing I/O lines of the peripheral set.
• PIOC, multiplexing the data bus bits 16 to 31 and several External Bus Interface control
signals. Using PIOC pins increases the number of general-purpose I/O lines available but
prevents 32-bit memory access.
• PIOD, available in the 256-ball BGA package option only, multiplexing outputs of the
peripheral set and the ETM port.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The tables in the following paragraphs define how the I/O lines of the peripher-
als A and B are multiplexed on the PIO Controllers A, B, C and D. The two columns “Function”
and “Comments” have been inserted for the user’s own comments; they may be used to track
how pins are defined in an application.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If equal to “I/O”, the PIO line resets in input with the pull-up enabled so that the device is
maintained in a static state as soon as the NRST pin is asserted. As a result, the bit correspond-
ing to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is in the “Reset State” column, the PIO line is assigned to this function and the
corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, either
address lines or chip selects, and that require the pin to be driven as soon as NRST raises. Note
that the pull-up resistor is also enabled in this case.
See Table 4-3 on page 20, Table 4-4 on page 21, Table 4-5 on page 22 and Table 4-6 on page
23.
19
1768IS–ATARM–30-Sep-05
4.3.1
PIO Controller A Multiplexing
Table 4-3.
Multiplexing on PIO Controller A
PIO Controller A
Application Usage
Comments
Reset
State
I/O Line
PA0
Peripheral A
MISO
Peripheral B
Function
PCK3
PCK0
IRQ4
I/O
PA1
MOSI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PA2
SPCK
PA3
NPCS0
NPCS1
NPCS2
NPCS3
ETXCK/EREFCK
ETXEN
ETX0
IRQ5
PA4
PCK1
TXD3
PA5
PA6
RXD3
PCK2
MCCDB
MCDB0
MCDB1
MCDB2
MCDB3
TCLK0
TCLK1
TCLK2
IRQ6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
ETX1
ECRS/ECRSDV
ERX0
ERX1
ERXER
EMDC
EMDIO
TXD0
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
IRQ3
RXD0
SCK0
CTS0
RTS0
RXD2
TXD2
SCK2
PCK1
IRQ2
TWD
TWCK
MCCK
MCCDA
MCDA0
DRXD
IRQ1
TCLK3
TCLK4
TCLK5
CTS2
DTXD
RTS2
20
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.3.2
PIO Controller B Multiplexing
Table 4-4.
Multiplexing on PIO Controller B
PIO Controller B
Application Usage
Reset
State
I/O Line
PB0
Peripheral A
TF0
Peripheral B
Function
Comments
RTS3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PB1
TK0
CTS3
PB2
TD0
SCK3
PB3
RD0
MCDA1
MCDA2
MCDA3
TIOA3
TIOB3
TIOA4
TIOB4
TIOA5
TIOB5
ETX2
PB4
RK0
PB5
RF0
PB6
TF1
PB7
TK1
PB8
TD1
PB9
RD1
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
RK1
RF1
TF2
TK2
ETX3
TD2
ETXER
ERX2
RD2
RK2
ERX3
RF2
ERXDV
ECOL
ERXCK
RI1
DTR1
TXD1
RXD1
SCK1
DCD1
CTS1
DSR1
RTS1
PCK0
FIQ
EF100
IRQ0
21
1768IS–ATARM–30-Sep-05
4.3.3
PIO Controller C Multiplexing
The PIO Controller C has no multiplexing and only peripheral A lines are used. Selecting Peripheral B on the PIO Controller
C has no effect.
Table 4-5.
Multiplexing on PIO Controller C
PIO Controller C
Application Usage
Comments
Reset
State
I/O Line
PC0
Peripheral A
BFCK
Peripheral B
Function
I/O
PC1
BFRDY/SMOE
BFAVD
I/O
PC2
I/O
PC3
BFBAA/SMWE
BFOE
I/O
PC4
I/O
PC5
BFWE
I/O
PC6
NWAIT
I/O
PC7
A23
A23
A24
A25
NCS4
NCS5
NCS6
NCS7
I/O
PC8
A24
PC9
A25/CFRNW
NCS4/CFCS
NCS5/CFCE1
NCS6/CFCE2
NCS7
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
I/O
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
22
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.3.4
PIO Controller D Multiplexing
The PIO Controller D multiplexes pure output signals on peripheral A connections, in particular from the EMAC MII inter-
face and the ETM Port on the peripheral B connections.
The PIO Controller D is available only in the 256-ball BGA package option of the AT91RM9200.
Table 4-6.
Multiplexing on PIO Controller D
PIO Controller D
Application Usage
Comments
Reset
State
I/O Line
PD0
Peripheral A
ETX0
Peripheral B
Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD1
ETX1
PD2
ETX2
PD3
ETX3
PD4
ETXEN
ETXER
DTXD
PCK0
PD5
PD6
PD7
TSYNC
TCLK
TPS0
TPS1
TPS2
TPK0
TPK1
TPK2
TPK3
TPK4
TPK5
TPK6
TPK7
TPK8
TPK9
TPK10
TPK11
TPK12
TPK13
TPK14
TPK15
PD8
PCK1
PD9
PCK2
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PCK3
TD0
TD1
TD2
NPCS1
NPCS2
NPCS3
RTS0
RTS1
RTS2
RTS3
DTR1
23
1768IS–ATARM–30-Sep-05
4.3.5
Pin Name Description
Table 4-7 gives details on the pin name classified by peripheral.
Table 4-7.
Pin Name
Pin Description List
Active
Level
Function
Type
Comments
Power
VDDIOM
VDDIOP
VDDPLL
VDDCORE
VDDOSC
GND
Memory I/O Lines Power Supply
Power
Power
Power
Power
Power
Ground
Ground
Ground
3.0V to 3.6V
Peripheral I/O Lines Power Supply
Oscillator and PLL Power Supply
Core Chip Power Supply
Oscillator Power Supply
Ground
3.0V to 3.6V
1.65V to 1.95V
1.65V to 1.95V
1.65V to 1.95V
GNDPLL
GNDOSC
PLL Ground
Oscillator Ground
Clocks, Oscillators and PLLs
XIN
Main Crystal Input
Main Crystal Output
32KHz Crystal Input
32KHz Crystal Output
PLL A Filter
Input
Output
Input
XOUT
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
Output
Input
PLL B Filter
Input
Programmable Clock Output
Output
ICE and JTAG
TCK
Test Clock
Input
Input
Output
Input
Input
Input
Schmitt trigger
TDI
Test Data In
Internal Pull-up, Schmitt trigger
Tri-state
TDO
Test Data Out
Test Mode Select
Test Reset Signal
JTAG Selection
TMS
Internal Pull-up, Schmitt trigger
Internal Pull-up, Schmitt trigger
Schmitt trigger
NTRST
JTAGSEL
Low
ETM
TSYNC
Trace Synchronization Signal
Trace Clock
Output
Output
Output
Output
TCLK
TPS0 - TPS2
TPK0 - TPK15
Trace ARM Pipeline Status
Trace Packet Port
Reset/Test
NRST
Microcontroller Reset
Test Mode Select
Input
Input
Low
No on-chip pull-up, Schmitt trigger
Must be tied low for normal
operation, Schmitt trigger
TST0 - TST1
24
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
Table 4-7.
Pin Name
Pin Description List (Continued)
Active
Level
Function
Type
Comments
Memory Controller
Debug Unit
BMS
Boot Mode Select
Input
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Input
Debug Receive Data
Debug Transmit Data
Output
AIC
PIO
IRQ0 - IRQ6
FIQ
External Interrupt Inputs
Fast Interrupt Input
Input
Input
PA0 - PA31
PB0 - PB29
PC0 - PC31
PD0 - PD27
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
I/O
I/O
I/O
I/O
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
EBI
D0 - D31
A0 - A25
Data Bus
I/O
Pulled-up input at reset
0 at reset
Address Bus
Output
SMC
NCS0 - NCS7
NWR0 - NWR3
NOE
Chip Select Lines
Write Signal
Output
Output
Output
Output
Output
Output
Output
Input
Low
Low
Low
Low
Low
Low
Low
Low
Low
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
1 at reset
Output Enable
Read Signal
NRD
NUB
Upper Byte Select
Lower Byte Select
Write Enable
NLB
NWE
NWAIT
Wait Signal
NBS0 - NBS3
Byte Mask Signal
Output
1 at reset
EBI for CompactFlash Support
CFCE1 - CFCE2
CFOE
CompactFlash Chip Enable
Output
Output
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
CFWE
CFIOR
CFIOW
CompactFlash IO Write
CFRNW
CFCS
CompactFlash Read Not Write
CompactFlash Chip Select
Low
25
1768IS–ATARM–30-Sep-05
Table 4-7.
Pin Name
Pin Description List (Continued)
Active
Level
Function
Type
EBI for NAND Flash/SmartMedia Support
Comments
SMCS
SMOE
SMWE
NAND Flash/SmartMedia Chip Select
Output
Output
Output
Low
Low
Low
NAND Flash/SmartMedia Output Enable
NAND Flash/SmartMedia Write Enable
SDRAM Controller
SDCK
SDRAM Clock
Output
Output
Output
Output
Output
Output
Output
SDCKE
SDCS
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select
High
Low
BA0 - BA1
SDWE
SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Low
Low
RAS - CAS
SDA10
Burst Flash Controller
BFCK
Burst Flash Clock
Output
Output
Output
Output
Output
Input
BFCS
Burst Flash Chip Select
Burst Flash Address Valid
Burst Flash Address Advance
Burst Flash Output Enable
Burst Flash Ready
Low
Low
Low
Low
High
Low
BFAVD
BFBAA
BFOE
BFRDY
BFWE
Burst Flash Write Enable
Output
Multimedia Card Interface
MCCK
Multimedia Card Clock
Output
I/O
MCCDA
Multimedia Card A Command
Multimedia Card A Data
Multimedia Card B Command
Multimedia Card B Data
MCDA0 - MCDA3
MCCDB
I/O
I/O
MCDB0 - MCDB3
I/O
USART
SCK0 - SCK3
TXD0 - TXD3
RXD0 - RXD3
RTS0 - RTS3
CTS0 - CTS3
DSR1
Serial Clock
I/O
Transmit Data
Output
Input
Receive Data
Ready To Send
Clear To Send
Data Set Ready
Data Terminal Ready
Data Carrier Detect
Ring Indicator
Output
Input
Input
DTR1
Output
Input
DCD1
RI1
Input
26
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
Table 4-7.
Pin Name
Pin Description List (Continued)
Active
Level
Function
Type
Comments
USB Device Port
USB Host Port
DDM
DDP
USB Device Port Data -
USB Device Port Data +
Analog
Analog
HDMA
HDPA
HDMB
HDPB
USB Host Port A Data -
USB Host Port A Data +
USB Host Port B Data -
USB Host Port B Data +
Analog
Analog
Analog
Analog
Ethernet MAC
EREFCK
ETXCK
Reference Clock
Input
Input
Input
RMII only
MII only
MII only
Transmit Clock
ERXCK
ETXEN
Receive Clock
Transmit Enable
Output
Output
Output
Input
Input
ETX0 - ETX3
ETXER
Transmit Data
ETX0 - ETX1 only in RMII
MII only
Transmit Coding Error
Receive Data Valid
Carrier Sense and Data Valid
Receive Data
ERXDV
ECRSDV
ERX0 - ERX3
ERXER
ECRS
MII only
RMII only
Input
ERX0 - ERX1 only in RMII
Receive Error
Input
Input
Input
Carrier Sense
MII only
MII only
ECOL
Collision Detected
Management Data Clock
Management Data Input/Output
Force 100 Mbits/sec.
EMDC
Output
I/O
EMDIO
EF100
Output
High
RMII only
Synchronous Serial Controller
TD0 - TD2
RD0 - RD2
TK0 - TK2
RK0 - RK2
TF0 - TF2
RF0 - RF2
Transmit Data
Output
Receive Data
Input
Transmit Clock
I/O
Receive Clock
I/O
Transmit Frame Sync
Receive Frame Sync
I/O
I/O
Timer/Counter
TCLK0 - TCLK5
TIOA0 - TIOA5
TIOB0 - TIOB5
External Clock Input
I/O Line A
Input
I/O
I/O Line B
I/O
27
1768IS–ATARM–30-Sep-05
Table 4-7.
Pin Name
Pin Description List (Continued)
Active
Level
Function
Type
Comments
SPI
MISO
MOSI
SPCK
NPCS0
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
SPI Peripheral Chip Select 0
I/O
Low
Low
NPCS1 - NPCS3
SPI Peripheral Chip Select
Output
Two-Wire Interface
TWD
Two-wire Serial Data
Two-wire Serial Clock
I/O
I/O
TWCK
28
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.4
Peripheral Identifiers
The AT91RM9200 embeds a wide range of peripherals. Table 4-8 defines the peripheral identifi-
ers of the AT91RM9200. A peripheral identifier is required for the control of the peripheral
interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with
the Power Management Controller.
Table 4-8.
Peripheral Identifiers
Peripheral
ID
Peripheral
Mnemonic
Peripheral
Name
External
Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
1
SYSIRQ
PIOA
PIOB
PIOC
PIOD
US0
US1
US2
US3
MCI
2
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
Parallel I/O Controller D
USART 0
3
4
5
6
7
USART 1
8
USART 2
9
USART 3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Multimedia Card Interface
USB Device Port
UDP
TWI
Two-wire Interface
SPI
Serial Peripheral Interface
Synchronous Serial Controller 0
Synchronous Serial Controller 1
Synchronous Serial Controller 2
Timer/Counter 0
SSC0
SSC1
SSC2
TC0
TC1
TC2
TC3
TC4
TC5
UHP
EMAC
AIC
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
Timer/Counter 4
Timer/Counter 5
USB Host Port
Ethernet MAC
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
AIC
AIC
AIC
AIC
AIC
AIC
29
1768IS–ATARM–30-Sep-05
4.4.1
System Interrupt
The System Interrupt is the wired-OR of the interrupt signals coming from:
• the Memory Controller
• the Debug Unit
• the System Timer
• the Real-Time Clock
• the Power Management Controller
The clock of these peripherals cannot be controlled and the Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
4.4.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ6, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
30
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.5
Product Memory Mapping
A first level of address decoding is performed by the Memory Controller, i.e., by the implementa-
tion of the Advanced System Bus (ASB) with additional features.
Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are
directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The
area 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M bytes of internal memory area. The area 15 is reserved for the peripherals and pro-
vides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
4.5.1
External Memory Mapping
Figure 4-3. External Memory Mapping
0x0000 0000
256M Bytes
256M Bytes
256M Bytes
256M Bytes
Internal Memories
Chip Select 0
Chip Select 1
Chip Select 2
Chip Select 3
Chip Select 4
Chip Select 5
Chip Select 6
Chip Select 7
0x0FFF FFFF
0x1000 0000
SMC or BFC
SMC or SDRAMC
SMC
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000
SMC
SMC
SMC
SMC
SMC
NAND Flash/SmartMedia
256M Bytes
256M Bytes
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
256M Bytes
256M Bytes
256M Bytes
CompactFlash
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
Undefined
(Abort)
6 x 256M Bytes
1,536 bytes
0xEFFF FFFF
0xF000 0000
256M Bytes
Peripherals
0xFFFF FFFF
31
1768IS–ATARM–30-Sep-05
4.5.2
Internal Memory Mapping
4.5.2.1
Internal RAM
The AT91RM9200 integrates a high-speed, 16-Kbyte internal SRAM. After reset and until the
Remap Command is performed, the SRAM is only accessible at address 0x20 0000. After
Remap, the SRAM is also available at address 0x0.
4.5.2.2
4.5.2.3
Internal ROM
The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the ROM is mapped at
address 0x10 0000. It is also accessible at address 0x0 after reset and before the Remap Com-
mand if the BMS is tied high during reset.
USB Host Port
The AT91RM9200 integrates a USB Host Port Open Host Controller Interface (OHCI). The reg-
isters of this interface are directly accessible on the ASB Bus and are mapped like a standard
internal memory at address 0x30 0000.
Figure 4-4. Internal Memory Mapping
0x0000 0000
Internal Memory Area 0
1 MBytes
1 MBytes
1 MBytes
1 MBytes
0x000F FFFF
0x0010 0000
Internal Memory Area 1
Internal ROM
0x001F FFFF
0x0020 0000
Internal Memory Area 2
Internal SRAM
256Mbytes
0x002F FFFF
0x0030 0000
Internal Memory Area 3
USB Host Port
0x003F FFFF
0x0040 0000
Undefined Area
(Abort)
252M bytes
0x0FFF FFFF
32
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.5.3
Peripheral Mapping
4.5.3.1
System Peripherals Mapping
The System Peripherals are mapped to the top 4K bytes of the address space, between the
addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has 256 or 512 bytes.
Figure 4-5. System Peripherals Mapping
Peripheral Name
Size
0xFFFF F000
Advanced Interrupt Controller
512 bytes/128 registers
AIC
0xFFFF F1FF
0xFFFF F200
Debug Unit
512 bytes/128 registers
512 bytes/128 registers
512 bytes/128 registers
512 bytes/128 registers
512 bytes/128 registers
DBGU
PIOA
0xFFFF F3FF
0xFFFF F400
PIO Controller A
PIO Controller B
PIO Controller C
PIO Controller D
0xFFFF F5FF
0xFFFF F600
PIOB
PIOC
PIOD
0xFFFF F7FF
0xFFFF F800
0xFFFF F9FF
0xFFFF FA00
0xFFFF FBFF
0xFFFF FC00
PMC
ST
Power Management Controller
System Timer
256 bytes/64 registers
256 bytes/64 registers
256 bytes/64 registers
256 bytes/64 registers
0xFFFF FCFF
0xFFFF FD00
0xFFFF FDFF
0xFFFF FE00
RTC
MC
Real-time Clock
0xFFFF FEFF
0xFFFF FF00
Memory Controller
0xFFFF FFFF
33
1768IS–ATARM–30-Sep-05
4.5.3.2
User Peripherals Mapping
The User Peripherals are mapped in the upper 256M bytes of the address space, between the
addresses 0xFFFA 0000and 0xFFFE 3FFF. Each peripheral has a 16-Kbyte address space.
Figure 4-6. User Peripherals Mapping
Peripheral Name
Size
0xF000 0000
Reserved
0xFFF9 FFFF
0xFFFA 0000
TC0, TC1, TC2
TC3, TC4, TC5
Timer/Counter 0, 1 and 2
Timer/Counter 3, 4 and 5
16K Bytes
16K Bytes
0xFFFA 3FFF
0xFFFA 4000
0xFFFA 7FFF
0xFFFA 8000
Reserved
UDP
0xFFFA FFFF
0xFFFB 0000
USB Device Port
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
0xFFFB 3FFF
0xFFFB 4000
MCI
Multimedia Card Interface
Two-Wire Interface
Ethernet MAC
0xFFFB 7FFF
0xFFFB 8000
TWI
0xFFFB BFFF
0xFFFB C000
EMAC
USART0
USART1
USART2
USART3
SSC0
0xFFFB FFFF
0xFFFC 0000
Universal Synchronous Asynchronous
Receiver Transmitter 0
0xFFFC 3FFF
0xFFFC 4000
Universal Synchronous Asynchronous
Receiver Transmitter 1
0xFFFC 7FFF
0xFFFC 8000
Universal Synchronous Asynchronous
Receiver Transmitter 2
0xFFFC BFFF
0xFFFC C000
Universal Synchronous Asynchronous
Receiver Transmitter 3
0xFFFC FFFF
0xFFFD 0000
Serial Synchronous Controller 0
Serial Synchronous Controller 1
Serial Synchronous Controller 2
0xFFFD 3FFF
0xFFFD 4000
SSC1
0xFFFD 7FFF
0xFFFD 8000
SSC2
0xFFFD BFFF
0xFFFD C000
Reserved
SPI
0xFFFD FFFF
0xFFFE 0000
Serial Peripheral Interface
16K Bytes
0xFFFE 3FFF
0xFFFE 4000
Reserved
0xFFFE FFFF
34
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
4.6
Peripheral Implementation
4.6.1
USART
The USART describes features allowing management of the Modem Signals DTR, DSR, DCD
and RI.
In the AT91RM9200, only the USART1 implements these signals, named DTR1, DSR1, DCD1
and RI1.
The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and
CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in
these USARTs for other features.
Thus, programming the USART0, USART2 or the USART3 in Modem Mode may lead to unpre-
dictable results. In these USARTs, the commands relating to the Modem Mode have no effect
and the status bits relating the status of the modem signals are never activated.
4.6.2
Timer Counter
The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to
TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock
(MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock.
Table 4-9 gives the correspondence between the Timer Counter clock inputs and clocks in the
AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration.
Table 4-9.
TC Clock Input
TIMER_CLOCK1
Timer Counter Clocks Assignment
Clock
MCK/2
MCK/8
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
MCK/32
MCK/128
SLCK
35
1768IS–ATARM–30-Sep-05
5. Revision History
Doc. Rev
Lit°1768A
Lit°1768B
Lit°1768C
Lit°1768D
Lit°1768E
Lit°1768F
Doc. Rev
1768GS
Source
Comments
• Date Qualified: May 2001
• Date Qualified: September 2001
• Date Qualified: November 2001
• Date Qualified: 5 Mar-02
• Date Qualified: 12-Julr-02
• Date Qualified: 5 Feb-03
Source
Comments
Review
• Date Qualified: 04-Sep-03
• Page 2; Added Description.
• Page 3; Updated Figure 1, Block Diagram, remove reference to Multi-master Memory Controller.
• Page 4; Added section Key Features. Updated all descriptions of key blocks
• Page 17; Added text to section Peripheral Mulitplexing on PIO Lines.
• Page 18; Expanded Table 3, Multiplexing on PIO Controller A.
• Page 19: Expanded Table 4, Multiplexing on PIO Controller B.
• Page 20; Expanded Table 5, Multiplexing on PIO Controller C.
• Page 21; Expanded Table 6, Multiplexing on PIO Controller D.
• Page 27; Updated Table 8, Peripheral Identifiers, Peripheral ID 1 description.
• Page 28; Added section Product Memory Mapping.
• Page 30; Updated and corrected Figure 6, System Peripherals Mapping.
• Page 31; Updated and corrected Figure 7, User Peripherals Mapping.
Comments
Doc. Rev
Source
1768HS
CSRs/Review
• Date Qualified: Unqualified/Internal on Intranet 27-Jan-05
• Global; Reformat in Corporate Template.
• Global; Peripheral Data Controller (PDC) nenamed Peripheral DMA Controller.
• Page 1; Features: USART Hardware Handshaking. Software Handshaking removed.
• Page 3; Figure 1: NWAIT pin added to block diagram.
CSR 04-066
CSR 03-209
CSR 03-244
• Page 14; Table 1. AT91RM9200 Pinout for 208-lead PQFP package, pins 28, 30, 37 and 39
names changed
CSR 04-315
CSR 03-209
• Page 23; Table 7. Pin Description, ICE and JTAG description, “Internal Pullup” added to
comments for all signals, except TDO.
• Page 24; Table 7. Pin Description, NWAIT pin added.
36
AT91RM9200 Summary
1768IS–ATARM–30-Sep-05
AT91RM9200 Summary
Doc. Rev
Source
Comments
1768IS
Corrected power consumption values on page 1.
CSR 05-348
In Table 4-7, “Pin Description List,” on page 24 added mention of Schmitt trigger for pins
JTAGSEL, TDI, TCK, TMS, NTRST, TST0, TST1 and NRST.
37
1768IS–ATARM–30-Sep-05
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