AT91SAM7XC128 [ATMEL]
Thumb-based Microcontrollers; 拇指型微控制器
| 型号： | AT91SAM7XC128 |
| 厂家： | 
ATMEL |
| 描述： | Thumb-based Microcontrollers |
| 文件： | 总38页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
– 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes
– 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase,
Full Erase Time: 15 ms
AT91 ARM®
Thumb®-based
Microcontrollers
– 10,000 Write Cycles, 10-year Data Retention Capability,
Sector Lock Capabilities, Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (AT91SAM7XC256)
AT91SAM7XC256
AT91SAM7XC128
– 32 Kbytes (AT91SAM7XC128)
• Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
Summary
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
Preliminary
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
• Power Management Controller (PMC)
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
Idle Mode
– Four Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
• Two Parallel Input/Output Controllers (PIO)
– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
6209AS–ATARM–20-Oct-05
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
• Seventeen Peripheral DMA Controller (PDC) Channels
• One Advanced Encryption System (AES)
– 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
– Buffer Encryption/Decryption Capabilities with PDC
• One Triple Data Encryption System (TDES)
– Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications
– Optimized for Triple Data Encryption Capability
• One USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 1352-byte Configurable Integrated FIFOs
• One Ethernet MAC 10/100 base-T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive
• One Part 2.0A and Part 2.0B Compliant CAN Controller
– Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1
• Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit Power Width Modulation Controller (PWMC)
• One Two-wire Interface (TWI)
– Master Mode Support Only, All Two-wire Atmel EEPROMs Supported
• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA™ Boot Assistance
– Default Boot program
– Interface with SAM-BA Graphic User Interface
• IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
• 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each
• Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
– 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
– 1.8V VDDCORE Core Power Supply with Brownout Detector
• Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions
• Available in a 100-lead LQFP Green Package
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AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
1. Description
Atmel's AT91SAM7XC256/128 is a member of a series of highly integrated Flash microcontrol-
lers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and
64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN control-
ler, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of
system functions minimizes the number of external components.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to mounting. Built-in lock bits and a secu-
rity bit protect the firmware from accidental overwrite and preserve its confidentiality.
The AT91SAM7XC256/128 system controller includes a reset controller capable of managing
the power-on sequence of the microcontroller and the complete system. Correct device opera-
tion can be monitored by a built-in brownout detector and a watchdog running off an integrated
RC oscillator.
By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of
peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, AES 128 accelera-
tor, TDES, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the
AT91SAM7XC256/128 is a powerful device that provides a flexible, cost-effective solution to
many embedded control applications requiring secure communication over, for example, Ether-
net, CAN wired and Zigbee wireless networks.
2. Configuration Summary of the AT91SAM7XC256 and AT91SAM7XC128
The AT91SAM7XC256 and AT91SAM7XC128 differ only in memory sizes. Table 2-1 summa-
rizes the configurations of the two devices.
Table 2-1.
Configuration Summary
Device
Flash
SRAM
AT91SAM7XC256
AT91SAM7XC128
256K bytes
128K bytes
64K bytes
32K bytes
3
6209AS–ATARM–20-Oct-05
3. AT91SAM7XC256/128 Block Diagram
Figure 3-1. AT91SAM7XC256/128 Block Diagram
TDI
TDO
TMS
TCK
ICE
ARM7TDMI
Processor
JTAG
SCAN
JTAGSEL
1.8 V
Voltage
VDDIN
GND
System Controller
AIC
Regulator
VDDOUT
TST
FIQ
VDDCORE
VDDIO
IRQ0-IRQ1
Memory Controller
SRAM
Embedded
Address
Decoder
64/32 Kbytes
Flash
PDC
PDC
DRXD
DTXD
DBGU
Controller
Abort
Status
Misalignment
Detection
PCK0-PCK3
PLLRC
VDDFLASH
ERASE
PLL
Flash
256/128 Kbytes
XIN
XOUT
PMC
OSC
Peripheral Bridge
RCOSC
ROM
VDDCORE
VDDFLASH
Peripheral DMA
Controller
BOD
POR
PGMRDY
PGMNVALID
PGMNOE
Reset
Controller
17 Channels
Fast Flash
Programming
Interface
VDDCORE
NRST
PGMCK
PGMM0-PGMM3
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN1
PIT
WDT
RTT
APB
SAM-BA
DMA
FIFO
ETXCK-ERXCK-EREFCK
ETXEN-ETXER
ECRS-ECOL, ECRSDV
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
EMDIO
PIOA
PIOB
Ethernet MAC 10/100
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
USART0
USART1
EF100
PDC
PDC
VDDFLASH
FIFO
DDM
DDP
USB Device
PWM0
PWM1
PWM2
PWM3
TF
TK
TD
RD
RK
RF
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
PDC
PDC
PWMC
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
PDC
SPI0
SPI1
SSC
PDC
PDC
PDC
Timer Counter
TC0
TC1
TC2
TWI
PDC
PDC
ADTRG
AD0
AD1
AD2
AD3
TIOA2
TIOB2
TWD
TWCK
ADC
AD4
AD5
AD6
AD7
CANRX
CANTX
CAN
PDC
ADVREF
AES 128
PDC
PDC
TDES
PDC
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AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
4. Signal Description
Table 4-1.
Signal Description List
Active
Signal Name
Function
Type
Level
Comments
Power
Voltage Regulator and ADC Power
Supply Input
VDDIN
Power
3V to 3.6V
VDDOUT
VDDFLASH
VDDIO
Voltage Regulator Output
Flash and USB Power Supply
I/O Lines Power Supply
Core Power Supply
PLL
Power
Power
Power
Power
Power
Ground
1.85V
3V to 3.6V
3V to 3.6V
1.65V to 1.95V
1.65V to 1.95V
VDDCORE
VDDPLL
GND
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Main Oscillator Output
PLL Filter
Input
Output
Input
XOUT
PLLRC
PCK0 - PCK3
Programmable Clock Output
Output
ICE and JTAG
TCK
Test Clock
Input
Input
No pull-up resistor
No pull-up resistor.
TDI
Test Data In
TDO
Test Data Out
Test Mode Select
JTAG Selection
Output
Input
TMS
No pull-up resistor.
Pull-down resistor.
JTAGSEL
Input
Flash Memory
Flash and NVM Configuration Bits Erase
Command
ERASE
Input
High
Pull-down resistor
Reset/Test
Pull-Up resistor, Open Drain
Output
NRST
TST
Microcontroller Reset
Test Mode Select
I/O
Low
Input
High
Pull-down resistor
Debug Unit
AIC
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Input
Output
IRQ0 - IRQ1
FIQ
External Interrupt Inputs
Fast Interrupt Input
Input
Input
PIO
PA0 - PA30
PB0 - PB30
Parallel IO Controller A
Parallel IO Controller B
I/O
I/O
Pulled-up input at reset
Pulled-up input at reset
5
6209AS–ATARM–20-Oct-05
Table 4-1.
Signal Description List (Continued)
Active
Level
Signal Name
Function
Type
USB Device Port
Comments
DDM
DDP
USB Device Port Data -
USB Device Port Data +
Analog
Analog
USART
SCK0 - SCK1
TXD0 - TXD1
RXD0 - RXD1
RTS0 - RTS1
CTS0 - CTS1
DCD1
Serial Clock
I/O
I/O
Transmit Data
Receive Data
Input
Output
Input
Input
Output
Input
Input
Request To Send
Clear To Send
Data Carrier Detect
Data Terminal Ready
Data Set Ready
Ring Indicator
DTR1
DSR1
RI1
Synchronous Serial Controller
TD
RD
TK
RK
TF
RF
Transmit Data
Output
Receive Data
Input
Transmit Clock
I/O
Receive Clock
I/O
Transmit Frame Sync
Receive Frame Sync
I/O
I/O
Timer/Counter
TCLK0 - TCLK2
TIOA0 - TIOA2
TIOB0 - TIOB2
External Clock Inputs
I/O Line A
Input
I/O
I/O Line B
I/O
PWM Controller
PWM0 - PWM3
PWM Channels
Output
Serial Peripheral Interface - SPIx
SPIx_MISO
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
SPIx_MOSI
SPIx_SPCK
SPIx_NPCS0
SPIx_NPCS1-NPCS3
SPI Peripheral Chip Select 0
I/O
Low
Low
SPI Peripheral Chip Select 1 to 3
Output
Two-wire Interface
TWD
Two-wire Serial Data
Two-wire Serial Clock
I/O
I/O
TWCK
6
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
Table 4-1.
Signal Description List (Continued)
Active
Signal Name
Function
Type
Level
Comments
Analog-to-Digital Converter
AD0-AD3
AD4-AD7
ADTRG
Analog Inputs
Analog Inputs
ADC Trigger
Analog
Digital pulled-up inputs at reset
Analog Inputs
Analog
Input
ADVREF
ADC Reference
Analog
Fast Flash Programming Interface
PGMEN0-PGMEN1
PGMM0-PGMM3
PGMD0-PGMD15
PGMRDY
Programming Enabling
Programming Mode
Programming Data
Programming Ready
Data Direction
Input
Input
I/O
Output
Output
Input
Input
High
Low
Low
PGMNVALID
PGMNOE
Programming Read
Programming Clock
PGMCK
PGMNCMD
Programming Command
Input
CAN Controller
Low
CANRX
CANTX
CAN Input
Input
CAN Output
Output
Ethernet MAC 10/100
EREFCK
ETXCK
Reference Clock
Input
Input
RMII only
MII only
MII only
Transmit Clock
ERXCK
ETXEN
Receive Clock
Input
Transmit Enable
Output
Output
Output
Input
ETX0 - ETX3
ETXER
Transmit Data
ETX0 - ETX1 only in RMII
MII only
Transmit Coding Error
Receive Data Valid
Carrier Sense and Data Valid
Receive Data
ERXDV
ECRSDV
ERX0 - ERX3
ERXER
ECRS
MII only
Input
RMII only
Input
ERX0 - ERX1 only in RMII
Receive Error
Input
Carrier Sense
Input
MII only
MII only
ECOL
Collision Detected
Management Data Clock
Management Data Input/Output
Force 100 Mbits/sec.
Input
EMDC
Output
I/O
EMDIO
EF100
Output
High
RMII only
7
6209AS–ATARM–20-Oct-05
5. Package
The AT91SAM7XC256/128 is available in 100-lead LQFP package.
5.1
100-lead LQFP Mechanical Overview
Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip-
tion is given in the Mechanical Characteristics section of the full datasheet.
Figure 5-1. 100-lead LQFP Package Pinout (Top View)
51
75
76
50
26
100
25
1
5.2
AT91SAM7XC256/128 Pinout
Table 5-1.
Pinout in 100-lead TQFP Package
ADVREF PA18/PGMD6
1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
TDI
GND
PB16
PB4
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TDO
JTAGSEL
TMS
2
GND
AD4
PB9
PB8
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
3
4
AD5
PB14
TCK
5
AD6
PB13
PA23/PGMD11
PA24/PGMD12
NRST
PA30
6
AD7
PB6
PA0/PGMEN0
PA1/PGMEN1
GND
7
VDDOUT
VDDIN
GND
8
VDDIO
PB5
TST
9
PB27/AD0
PB28/AD1
PB29/AD2
PB30/AD3
PA8/PGMM0
PA9/PGMM1
VDDCORE
GND
PA25/PGMD13
PA26/PGMD14
VDDIO
VDDIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PB15
PA3
PB17
PA2
VDDCORE
PB7
VDDCORE
PB18
VDDCORE
PA4/PGMNCMD
PA5/PGMRDY
PA6/PGMNOE
PA7/PGMNVALID
ERASE
PB12
PB19
PB0
PB20
PB1
PB21
VDDIO
PB2
PB22
PA10/PGMM2
PA11/PGMM3
PA12/PGMD0
PA13/PGMD1
PA14/PGMD2
PA15/PGMD3
PA16/PGMD4
PA17/PGMD5
PB3
GND
DDM
PB10
PB23
DDP
PB11
PB24
VDDFLASH
GND
PA19/PGMD7
PA20/PGMD8
VDDIO
PA21/PGMD9
PA22/PGMD10
PB25
PB26
XIN/PGMCK
XOUT
PA27/PGMD15
PA28
PLLRC
PA29
VDDPLL
8
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
6. Power Considerations
6.1
Power Supplies
The AT91SAM7XC256/128 has six types of power supply pins and integrates a voltage regula-
tor, allowing the device to be supplied with only one voltage. The six power supply pin types are:
• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,
3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC
are not used, VDDIN, ADVREF, AD5, AD6 and AD7 should be connected to GND. In this
case, VDDOUT should be left unconnected.
• VDDOUT pin. It is the output of the 1.8V voltage regulator.
• VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for
the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,
1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE
is required for the device, including its embedded Flash, to operate correctly.
• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the
VDDOUT pin.
No separate ground pins are provided for the different power supplies. Only GND pins are pro-
vided and should be connected as shortly as possible to the system ground plane.
6.2
6.3
Power Consumption
The AT91SAM7XC256/128 has a static current of less than 60 µA on VDDCORE at 25°C,
including the RC oscillator, the voltage regulator and the power-on reset when the brownout
detector is deactivated. Activating the brownout detector adds 28 µA static current.
The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running
out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not
exceed 10 mA.
Voltage Regulator
The AT91SAM7XC256/128 embeds a voltage regulator that is managed by the System
Controller.
In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100
mA of output current.
The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA
static current and draws 1 mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil-
lations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or
1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as
possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT
and GND.
9
6209AS–ATARM–20-Oct-05
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop. The input decoupling capacitor should be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
6.4
Typical Powering Schematics
The AT91SAM7XC256/128 supports a 3.3V single supply mode. The internal regulator input
connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 6-1
shows the power schematics to be used for USB bus-powered systems.
Figure 6-1. 3.3V System Single Power Supply Schematic
VDDFLASH
Power Source
VDDIO
ranges
from 4.5V (USB)
to 18V
DC/DC Converter
VDDIN
Voltage
Regulator
3.3V
VDDOUT
VDDCORE
VDDPLL
10
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
7. I/O Lines Considerations
7.1
7.2
7.3
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not
integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations.
Test Pin
The TST pin is used for manufacturing test or fast programming mode of the
AT91SAM7XC256/128 when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-
ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
7.4
7.5
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing
time is 200 ms.
PIO Controller Lines
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma-
ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be
driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while
the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be
taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at
reset.
11
6209AS–ATARM–20-Oct-05
7.6
I/O Lines Current Drawing
The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to
16 mA permanently.
The remaining I/O lines can draw only 8 mA.
However, the total current drawn by all the I/O lines cannot exceed 200 mA.
12
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
8. Processor and Architecture
8.1
8.2
8.3
ARM7TDMI Processor
• RISC processor based on ARMv4T Von Neumann architecture
– Runs at up to 55 MHz, providing 0.9 MIPS/MHz
• Two instruction sets
– ARM® high-performance 32-bit instruction set
– Thumb® high code density 16-bit instruction set
• Three-stage pipeline architecture
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
Debug and Test Features
• Integrated embedded in-circuit emulator
– Two watchpoint units
– Test access port accessible through a JTAG protocol
– Debug communication channel
• Debug Unit
– Two-pin UART
– Debug communication channel interrupt handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on all digital pins
Memory Controller
• Programmable Bus Arbiter
– Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA
Controller
• Address decoder provides selection signals for
– Three internal 1 Mbyte memory areas
– One 256 Mbyte embedded peripheral area
• Abort Status Registers
– Source, Type and all parameters of the access leading to an abort are saved
– Facilitates debug by detection of bad pointers
• Misalignment Detector
– Alignment checking of all data accesses
– Abort generation in case of misalignment
• Remap Command
– Remaps the SRAM in place of the embedded non-volatile memory
– Allows handling of dynamic exception vectors
13
6209AS–ATARM–20-Oct-05
• Embedded Flash Controller
– Embedded Flash interface, up to three programmable wait states
– Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required
wait states
– Key-protected program, erase and lock/unlock sequencer
– Single command for erasing, programming and locking operations
– Interrupt generation in case of forbidden operation
8.4
Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Seventeen channels
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the Advanced Encryption Standard 128-bit accelerator
– Two for the Triple Data Encryption Standard 128-bit accelerator
– One for the Analog-to-digital Converter
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirements
14
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
9. Memory
9.1
AT91SAM7XC256
• 256 Kbytes of Flash Memory
– 1024 pages of 256 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming time: 6 ms, including page auto-erase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 write cycles, 10-year data retention capability
– 16 lock bits, each protecting 16 sectors of 64 pages
– Protection Mode to secure contents of the Flash
• 64 Kbytes of Fast SRAM
– Single-cycle access at full speed
9.2
AT91SAM7XC128
• 128 Kbytes of Flash Memory
– 512 pages of 256 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming time: 6 ms, including page auto-erase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 write cycles, 10-year data retention capability
– 8 lock bits, each protecting 8 sectors of 64 pages
– Protection Mode to secure contents of the Flash
• 32 Kbytes of Fast SRAM
– Single-cycle access at full speed
15
6209AS–ATARM–20-Oct-05
9.3
Memory Mapping
9.3.1
Internal RAM
• The AT91SAM7XC256 embeds a high-speed 64-Kbyte SRAM bank
• The AT91SAM7XC128 embeds a high-speed 32-Kbyte SRAM bank.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.
9.3.2
9.3.3
Internal ROM
Internal Flash
The AT91SAM7XC256/128 embeds an Internal ROM. At any time, the ROM is mapped at
address 0x30 0000. The ROM contains FFPI and SAM-BA program.
• The AT91SAM7XC256 features one bank of 256 Kbytes of Flash
• The AT91SAM7XC128 features one bank of 128 Kbytes of Flash.
At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0
after the reset and before the Remap Command.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the
Flash.
This GPNVM bit can be cleared or set respectively through the commands “Clear General-pur-
pose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.
Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM
Bit 2 and thus selects the boot from the ROM by default.
Figure 9-1. Internal Memory Mapping with GPNVM Bit 2 = 0 (default)
0x0000 0000
ROM Before Remap
1 M Bytes
SRAM After Remap
0x000F FFFF
0x0010 0000
Internal FLASH
1 M Bytes
0x001F FFFF
0x0020 0000
Internal SRAM
Internal ROM
256M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
0x002F FFFF
0x0030 0000
0x003F FFFF
0x0040 0000
Undefined Areas
(Abort)
0x0FFF FFFF
16
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
Figure 9-2. Internal Memory Mapping with GPNVM Bit 2 = 1
0x0000 0000
Flash Before Remap
SRAM After Remap
1 M Bytes
1 M Bytes
0x000F FFFF
0x0010 0000
Internal FLASH
0x001F FFFF
0x0020 0000
Internal SRAM
Internal ROM
256M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
0x002F FFFF
0x0030 0000
0x003F FFFF
0x0040 0000
Undefined Areas
(Abort)
0x0FFF FFFF
9.4
Embedded Flash
9.4.1
Flash Overview
• The Flash of the AT91SAM7XC256 is organized in 1024 pages of 256 bytes. It reads as
65,536 32-bit words.
• The Flash of the AT91SAM7XC128 is organized in 512 pages of 256 bytes. It reads as
32,768 32-bit words.
The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.
The Flash benefits from the integration of a power reset cell and from the brownout detector.
This prevents code corruption during power supply changes, even in the worst conditions.
When Flash is not used (read or write access), it is automatically placed into standby mode.
9.4.2
Embedded Flash Controller
The Embedded Flash Controller (EFC) manages accesses performed by the masters of the sys-
tem. It enables reading the Flash and writing the write buffer. It also contains a User Interface,
mapped within the Memory Controller on the APB. The User Interface allows:
• programming of the access parameters of the Flash (number of wait states, timings, etc.)
• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit
clear, etc.
• getting the end status of the last command
• getting error status
• programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit
access to the Flash. This is particularly efficient when the processor is running in Thumb mode.
17
6209AS–ATARM–20-Oct-05
9.4.3
Lock Regions
9.4.3.1
AT91SAM7XC256
The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against
inadvertent flash erasing or programming commands. The AT91SAM7XC256 contains 16 lock
regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16
Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the EFC
trigs an interrupt.
The 16 NVM bits are software programmable through the EFC User Interface. The command
“Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.4.3.2
AT91SAM7XC128
The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against
inadvertent flash erasing or programming commands. The AT91SAM7XC128 contains 8 lock
regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16
Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the EFC
trigs an interrupt.
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.4.4
Security Bit Feature
The AT91SAM7XC256/128 features a security bit, based on a specific NVM-Bit. When the secu-
rity is enabled, any access to the Flash, either through the ICE interface or through the Fast
Flash Programming Interface, is forbidden. This ensures the confidentiality of the code pro-
grammed in the Flash.
This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and
after a full flash erase is performed. When the security bit is deactivated, all accesses to the
flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
9.4.5
Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD),
so that even after a power loss, the brownout detector operations remain in their state.
These two GPNVM bits can be cleared or set respectively through the commands “Clear Gen-
eral-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.
18
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
• GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables
the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus
disables the brownout detector by default.
• The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting
the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the
GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by
default.
9.4.6
Calibration Bits
Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits
are factory configured and cannot be changed by the user. The ERASE pin has no effect on the
calibration bits.
9.5
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial
JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-program-
ming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when the TST pin and the PA0 and PA1 pins are all tied high.
9.6
SAM-BA Boot Assistant
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in-
situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device
Port.
• Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via
software auto-detection.
• Communication via the USB Device Port is limited to an 18.432 MHz crystal.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when the GPNVM Bit 2 is
set to 0.
19
6209AS–ATARM–20-Oct-05
10. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power,
time, debug and reset.
Figure 10-1. System Controller Block Diagram
jtag_nreset
Boundary Scan
TAP Controller
System Controller
nirq
nfiq
irq0-irq1
Advanced
Interrupt
Controller
fiq
proc_nreset
ARM7TDMI
periph_irq[2..19]
PCK
int
debug
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
efc_irq
ice_nreset
force_ntrst
MCK
periph_nreset
dbgu_irq
Debug
Unit
force_ntrst
dbgu_rxd
dbgu_txd
pit_irq
security_bit
MCK
debug
Periodic
Interval
Timer
periph_nreset
flash_poe
SLCK
Real-Time
Timer
Embedded
Flash
rtt_irq
flash_wrdis
periph_nreset
cal
SLCK
debug
Watchdog
Timer
wdt_irq
gpnvm[0..2]
idle
proc_nreset
cal
gpnvm[0]
wdt_fault
WDRPROC
gpnvm[1]
efc_irq
en
bod_rst_en
Memory
Controller
MCK
flash_wrdis
BOD
proc_nreset
ice_nreset
jtag_nreset
periph_nreset
proc_nreset
Reset
Controller
Voltage
Regulator
Mode
POR
flash_poe
standby
cal
Voltage
Regulator
Controller
rstc_irq
NRST
SLCK
SLCK
RCOSC
OSC
periph_clk[2..18]
pck[0-3]
UDPCK
periph_clk[11]
USB Device
Port
XIN
MAINCK
Power
Management
Controller
periph_nreset
periph_irq[11]
usb_suspend
PCK
XOUT
UDPCK
MCK
PLLRC
PLL
PLLCK
int
pmc_irq
idle
periph_nreset
periph_clk[4..19]
periph_nreset
usb_suspend
Embedded
Peripherals
periph_nreset
periph_clk[2-3]
dbgu_rxd
periph_irq{2-3]
irq0-irq1
fiq
periph_irq[4..19]
PIO
Controller
dbgu_txd
in
PA0-PA30
PB0-PB30
out
enable
20
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
10.1 System Controller Mapping
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space,
between addresses 0xFFFF F000 and 0xFFFF FFFF.
Figure 10-2 shows the mapping of the System Controller. Note that the Memory Controller con-
figuration user interface is also mapped within this address space.
Figure 10-2. System Controller Mapping
Address
Peripheral
Peripheral Name
Size
0xFFFF F000
AIC
Advanced Interrupt Controller
512 Bytes/128 registers
0xFFFF F1FF
0xFFFF F200
DBGU
PIOA
PIOB
Debug Unit
512 Bytes/128 registers
512 Bytes/128 registers
512 Bytes/128 registers
0xFFFF F3FF
0xFFFF F400
PIO Controller A
PIO Controller B
0xFFFF F5FF
0xFFFF F600
0xFFFF F7FF
0xFFFF F800
Reserved
PMC
0xFFFF FBFF
0xFFFF FC00
Power Management Controller
Reset Controller
256 Bytes/64 registers
16 Bytes/4 registers
0xFFFF FCFF
0xFFFF FD00
0xFFFF FD0F
RSTC
Reserved
RTT
0xFFFF FD20
0xFFFF FC2F
0xFFFF FD30
0xFFFF FC3F
0xFFFF FD40
0xFFFF FD4F
Real-time Timer
16 Bytes/4 registers
16 Bytes/4 registers
16 Bytes/4 registers
PIT
Periodic Interval Timer
Watchdog Timer
WDT
Reserved
VREG
0xFFFF FD60
0xFFFF FC6F
0xFFFF FD70
Voltage Regulator Mode Controller
4 Bytes/1 register
Reserved
0xFFFF FEFF
0xFFFF FF00
MC
Memory Controller
256 Bytes/64 registers
0xFFFF FFFF
21
6209AS–ATARM–20-Oct-05
10.2 Reset Controller
• Based on one power-on reset cell and one brownout detector
• Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog
Reset, Brownout Reset
• Controls the internal resets and the NRST pin output
• Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets
any requirement.
10.2.1
Brownout Detector and Power-on Reset
The AT91SAM7XC256/128 embeds one brownout detection circuit and a power-on reset cell.
The power-on reset is supplied with and monitors VDDCORE.
Both signals are provided to the Flash to prevent any code corruption during power-up or power-
down sequences or if brownouts occur on the power supplies.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low
during power-up until VDDCORE goes over this voltage level. This signal goes to the reset con-
troller and allows a full re-initialization of the device.
The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by
comparing them to a fixed trigger level. It secures system operations in the most difficult environ-
ments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger
level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated.
When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the
reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays
below the threshold voltage for longer than about 1µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brown-
out detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of
± 2% and is factory calibrated.
When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger
level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated.
When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the
reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays
below the threshold voltage for longer than about 1µs.
The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brown-
out detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of
± 3.5% and is factory calibrated.
The brownout detector is low-power, as it consumes less than 28 µA static current. However, it
can be deactivated to save its static current. In this case, it consumes less than 1µA. The deac-
tivation is configured through the GPNVM bit 0 of the Flash.
22
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
10.3 Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL
with the following characteristics:
• RC Oscillator ranges between 22 KHz and 42 KHz
• Main Oscillator frequency ranges between 3 and 20 MHz
• Main Oscillator can be bypassed
• PLL output ranges between 80 and 200 MHz
It provides SLCK, MAINCK and PLLCK.
Figure 10-3. Clock Generator Block Diagram
Clock Generator
Embedded
Slow Clock
RC
Oscillator
SLCK
XIN
Main
Oscillator
Main Clock
MAINCK
XOUT
PLL and
Divider
PLL Clock
PLLCK
PLLRC
Status
Power
Control
Management
Controller
23
6209AS–ATARM–20-Oct-05
10.4 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK
• all the peripheral clocks, independently controllable
• four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Figure 10-4. Power Management Controller Block Diagram
Processor
PCK
Clock
Controller
int
Master Clock Controller
Idle Mode
SLCK
Prescaler
MAINCK
MCK
/1,/2,/4,...,/64
PLLCK
Peripherals
Clock Controller
periph_clk[2..18]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
pck[0..3]
USB Clock Controller
ON/OFF
Divider
/1,/2,/4
PLLCK
UDPCK
10.5 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
sources
• 8-level Priority Controller
– Drives the normal interrupt nIRQ of the processor
– Handles priority of the interrupt sources
24
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes interrupt service routine branch and execution
– One 32-bit vector register per interrupt source
– Interrupt vector register reads the corresponding current interrupt vector
• Protect Mode
– Easy debugging by preventing automatic operations
• Fast Forcing
– Permits redirecting any interrupt source on the fast interrupt
• General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
10.6 Debug Unit
• Comprises:
– One two-pin UART
– One Interface for the Debug Communication Channel (DCC) support
– One set of Chip ID Registers
– One Interface providing ICE Access Prevention
• Two-pin UART
– USART-compatible User Interface
– Programmable Baud Rate Generator
– Parity, Framing and Overrun Error
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
• Debug Communication Channel Support
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
• Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of
peripherals
– Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7XC256
– Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7XC128
10.7 Period Interval Timer
• 20-bit programmable counter plus 12-bit interval counter
10.8 Watchdog Timer
10.9 Real-time Timer
6209AS–ATARM–20-Oct-05
• 12-bit key-protected Programmable Counter running on prescaled SLCK
• Provides reset or interrupt signals to the system
• Counter may be stopped while the processor is in debug state or in idle mode
• 32-bit free-running counter with alarm running on prescaled SLCK
• Programmable 16-bit prescaler for SLCK accuracy compensation
25
10.10 PIO Controllers
• Two PIO Controllers, each controlling 31 I/O lines
• Fully programmable through set/clear registers
• Multiplexing of two peripheral functions per I/O line
• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)
– Input change interrupt
– Half a clock period glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
10.11 Voltage Regulator Controller
The purpose of this controller is to select the Power Mode of the Voltage Regulator between
Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
26
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
11. Peripherals
11.1 Peripheral Mapping
Each peripheral is allocated 16 Kbytes of address space.
Figure 11-1. User Peripheral Mapping
Peripheral Name
0xF000 0000
Reserved
Size
0xFFF9 FFFF
0xFFFA 0000
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16 Kbytes
16 Kbytes
16 Kbytes
0xFFFA 3FFF
0xFFFA 4000
Advanced Encryption Standard
128-bit
AES 128
0xFFFA 7FFF
0xFFFA 8000
TDES
Triple Data Encryption Standard
0xFFFA BFFF
0xFFFA C000
Reserved
0xFFFA FFFF
0xFFFB 0000
UDP
USB Device Port
16 Kbytes
16 Kbytes
0xFFFB 3FFF
0xFFFB 4000
Reserved
0xFFFB 7FFF
0xFFFB 8000
TWI
Two-Wire Interface
0xFFFB BFFF
0xFFFB C000
Reserved
0xFFFB FFFF
0xFFFC 0000
Universal Synchronous Asynchronous
Receiver Transmitter 0
16 Kbytes
16 Kbytes
USART0
0xFFFC 3FFF
0xFFFC 4000
Universal Synchronous Asynchronous
Receiver Transmitter 1
USART1
0xFFFC 7FFF
0xFFFC 8000
Reserved
0xFFFC BFFF
0xFFFC C000
PWM Controller
PWMC
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0xFFFC FFFF
0xFFFD 0000
CAN Controller
CAN
0xFFFD 3FFF
0xFFFD 4000
SSC
Serial Synchronous Controller
Analog-to-Digital Converter
Ethernet MAC
0xFFFD 7FFF
0xFFFD 8000
ADC
0xFFFD BFFF
0xFFFD C000
EMAC
16 Kbytes
16 Kbytes
0xFFFD FFFF
0xFFFE 0000
SPI0
Serial Peripheral Interface 0
Serial Peripheral Interface 1
0xFFFE 3FFF
0xFFFE 4000
SPI1
16 Kbytes
0xFFFE 7FFF
0xFFFE 8000
Reserved
0xFFFE FFFF
27
6209AS–ATARM–20-Oct-05
11.2 Peripheral Multiplexing on PIO Lines
The AT91SAM7XC256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func-
tions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC
Controller.
Table 11-1 on page 29 and Table 11-2 on page 30 defines how the I/O lines of the peripherals A,
B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two
columns “Function” and “Comments” have been inserted for the user’s own comments; they may
be used to track how pins are defined in an application.
Note that some peripheral functions that are output only, may be duplicated in the table.
At reset, all I/O lines are automatically configured as input with the programmable pull-up
enabled, so that the device is maintained in a static state as soon as a reset is detected.
28
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
11.3 PIO Controller A Multiplexing
Table 11-1. Multiplexing on PIO Controller A
PIO Controller A
Application Usage
I/O Line
PA0
Peripheral A
RXD0
Peripheral B
Comments
High-Drive
High-Drive
High-Drive
High-Drive
Function
Comments
PA1
TXD0
PA2
SCK0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
PA3
RTS0
PA4
CTS0
PA5
RXD1
PA6
TXD1
PA7
SCK1
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
PA8
RTS1
PA9
CTS1
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
TWD
TWCK
SPI_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
CANRX
CANTX
TF
PCK1
IRQ1
TCLK2
SPI1_NPCS0
SPI1_SPCK
SPI1_MOSI
SPI1_MISO
SPI1_NPCS1
SPI1_NPCS2
PCK3
TK
TD
RD
RK
RF
DRXD
DTXD
FIQ
SPI1_NPCS3
PCK2
IRQ0
29
6209AS–ATARM–20-Oct-05
11.4 PIO Controller B Multiplexing
Table 11-2. Multiplexing on PIO Controller B
PIO Controller A
Application Usage
Function Comments
I/O Line
PB0
Peripheral A
ETXCK/EREFCK
ETXEN
ETX0
Peripheral B
Comments
PCK0
PB1
PB2
PB3
ETX1
PB4
ECRS
PB5
ERX0
PB6
ERX1
PB7
ERXER
EMDC
PB8
PB9
EMDIO
ETX2
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
SPI1_NPCS1
SPI1_NPCS2
TCLK0
ETX3
ETXER
ERX2
SPI0_NPCS1
SPI0_NPCS2
ERX3
ERXDV/ECRSDV
ECOL
SPI1_NPCS3
SPI0_NPCS3
ADTRG
TCLK1
PCK0
ERXCK
EF100
PWM0
PWM1
PWM2
PWM3
TIOA0
PCK1
PCK2
DCD1
TIOB0
DSR1
TIOA1
DTR1
TIOB1
RI1
TIOA2
PWM0
PWM1
PWM2
PWM3
AD0
AD1
AD2
AD3
TIOB2
PCK1
PCK2
30
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
11.5 Peripheral Identifiers
The AT91SAM7XC256/128 embeds a wide range of peripherals. Table 11-3 defines the Periph-
eral Identifiers of the AT91SAM7XC256/128. Unique peripheral identifiers are defined for both
the Advanced Interrupt Controller and the Power Management Controller.
Table 11-3. Peripheral Identifiers
External
Peripheral ID
Peripheral Mnemonic
AIC
Peripheral Name
Interrupt
0
Advanced Interrupt Controller
FIQ
1
SYSIRQ(1)
PIOA
2
Parallel I/O Controller A
Parallel I/O Controller B
Serial Peripheral Interface 0
Serial Peripheral Interface 1
USART 0
3
PIOB
4
SPI0
5
SPI1
6
US0
7
US1
USART 1
8
SSC
Synchronous Serial Controller
Two-wire Interface
9
TWI
10
11
12
13
14
15
16
17
18
19
20-29
30
31
PWMC
UDP
Pulse Width Modulation Controller
USB device Port
TC0
Timer/Counter 0
TC1
Timer/Counter 1
TC2
Timer/Counter 2
CAN
CAN Controller
EMAC
ADC(1)
AES
Ethernet MAC
Analog-to Digital Converter
Advanced Encryption Standard 128-bit
Triple Data Encryption Standard
TDES
Reserved
AIC
Advanced Interrupt Controller
Advanced Interrupt Controller
IRQ0
IRQ1
AIC
Note:
1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The
System Controller and ADC are continuously clocked.
31
6209AS–ATARM–20-Oct-05
11.6 Ethernet MAC
• DMA Master on Receive and Transmit Channels
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbit/s operation
• Full- and half-duplex operation
• Statistics Counter Registers
• MII/RMII interface to the physical layer
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit FIFO and 28-byte receive FIFO
• Automatic pad and CRC generation on transmitted frames
• Automatic discard of frames received with errors
• Address checking logic supports up to four specific 48-bit addresses
• Support Promiscuous Mode where all valid received frames are copied to memory
• Hash matching of unicast and multicast destination addresses
• Physical layer management through MDIO interface
• Half-duplex flow control by forcing collisions on incoming frames
• Full-duplex flow control with recognition of incoming pause frames
• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged
frames
• Multiple buffers per receive and transmit frame
• Jumbo frames up to 10240 bytes supported
11.7 Serial Peripheral Interface
• Supports communication with external serial devices
– Four chip selects with external decoder allow communication with up to 15
peripherals
– Serial memories, such as DataFlash® and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays per chip select, between consecutive transfers and
between clock and data
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Maximum frequency at up to Master Clock
11.8 Two-wire Interface
• Master Mode only
• Compatibility with standard two-wire serial memories
32
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
• One, two or three bytes for slave address
• Sequential read/write operations
11.9 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode
– 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB or LSB first
– Optional break generation and detection
– By 8 or by 16 over-sampling receiver frequency
– Hardware handshaking RTS - CTS
– Modem Signals Management DTR-DSR-DCD-RI on USART1
– Receiver time-out and transmitter timeguard
– Multi-drop Mode with address generation and detection
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
11.10 Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
11.11 Timer Counter
• Three 16-bit Timer Counter Channels
– Three output compare or two input capture
• Wide range of functions including:
– Frequency measurement
– Event counting
– Interval measurement
– Pulse generation
33
6209AS–ATARM–20-Oct-05
– Delay timing
– Pulse Width Modulation
– Up/down capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
• Five internal clock inputs, as defined in Table 11-4
Table 11-4. Timer Counter Clocks Assignment
TC Clock input
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
Clock
MCK/2
MCK/8
MCK/32
MCK/128
MCK/1024
– Two multi-purpose input/output signals
– Two global registers that act on all three TC channels
11.12 Pulse Width Modulation Controller
• Four channels, one 16-bit counter per channel
• Common clock generator, providing thirteen different clocks
– One Modulo n counter providing eleven clocks
– Two independent linear dividers working on modulo n counter outputs
• Independent channel programming
– Independent enable/disable commands
– Independent clock selection
– Independent period and duty cycle, with double buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
11.13 USB Device Port
• USB V2.0 full-speed compliant,12 Mbits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 1352-byte dual-port RAM for endpoints
• Six endpoints
– Endpoint 0: 8 bytes
– Endpoint 1 and 2: 64 bytes ping-pong
– Endpoint 3: 64 bytes
– Endpoint 4 and 5: 256 bytes ping-pong
– Ping-pong Mode (two memory banks) for bulk endpoints
• Suspend/resume logic
34
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
11.14 CAN Controller
•
•
•
Fully compliant with CAN 2.0A and 2.0B
Bit rates up to 1Mbit/s
Eight object oriented mailboxes each with the following properties:
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message
– Object configurable to receive (with overwrite or not) or transmit
– Local tag and mask filters up to 29-bit identifier/channel
– 32-bit access to data registers for each mailbox data object
– Uses a 16-bit time stamp on receive and transmit message
– Hardware concatenation of ID unmasked bitfields to speedup family ID processing
– 16-bit internal timer for time stamping and network synchronization
– Programmable reception buffer length up to 8 mailbox objects
– Priority management between transmission mailboxes
– Autobaud and listening mode
– Low power mode and programmable wake-up on bus activity or by the application
– Data, remote, error and overload frame handling
11.15 128-bit Advanced Encryption Standard
• Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
• 128-bit Cryptographic Key
• 12-clock Cycles Encryption/Decryption Processing Time
• Support of the Five Standard Modes of Operation specified in the NIST Special Publication
800-38A:
– Electronic Codebook (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– Counter (CTR)
• 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode
• Last Output Data Mode allowing Message Authentication Code (MAC) generation
• Hardware Countermeasures against Differential Power Analysis attacks
• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support AES 128-bit Key Algorithm Hardware Accelerator
11.16 Triple Data Encryption Standard
• Single Data Encryption Standard (DES) and Triple Data Encryption
• Algorithm (TDEA or TDES) supports
• Compliant with FIPS Publication 46-3, Data Encryption Standard (DES)
• 64-bit Cryptographic Key
• Two-key or Three-key Algorithms
35
6209AS–ATARM–20-Oct-05
• 18-clock Cycles Encryption/Decryption Processing Time for DES
• 50-clock Cycles Encryption/Decryption Processing Time for TDES
• Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES
• Modes of Operation:
– Electronic Codebook (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
• 8-, 16-, 32- and 64- Data Sizes Possible in CFB Mode
• Last Output Data Mode allowing Optimized Message (Data) Authentication Code (MAC)
generation
• Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes:
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
11.17 Analog-to-Digital Converter
• 8-channel ADC
• 10-bit 384 Ksamples/sec. Successive Approximation Register ADC
• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity
• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
• Four of eight analog inputs shared with digital signals
36
AT91SAM7XC256/128 Preliminary
6209AS–ATARM–20-Oct-05
AT91SAM7XC256/128 Preliminary
12. AT91SAM7XC256/128 Ordering Information
Table 12-1. Ordering Information
Temperature
Ordering Code
Package
Package Type
Operating Range
Industrial
(-40°C to 85°C)
AT91SAM7XC256-AU
LQFP 100
Green
Industrial
(-40°C to 85°C)
AT91SAM7XC128-AU
LQFP 100
Green
13. Export Regulations Statement
These commodities, technology or software will be exported from France and the applicable
Export Administration Regulations will apply. French, United States and other relevant laws, reg-
ulations and requirements regarding the export of products may restrict sale, export and re-
export of these products; please assure you conduct your activities in accordance with the appli-
cable relevant export regulations.
37
6209AS–ATARM–20-Oct-05
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