AT91SAM9261S [ATMEL]
AT91 ARM Thumb-based Microcontrollers; AT91 ARM的Thumb-基于微控制器
| 型号： | AT91SAM9261S |
| 厂家： | 
ATMEL |
| 描述： | AT91 ARM Thumb-based Microcontrollers |
| 文件： | 总39页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP Instruction Extensions
– ARM Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 210 MIPS at 190 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
– Mid-level implementation Embedded Trace Macrocell™
• Additional Embedded Memories
– 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed
– 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, NAND Flash and CompactFlash®
• LCD Controller
AT91 ARM
Thumb-based
Microcontrollers
– Supports Passive or Active Displays
AT91SAM9261S
Summary
– Up to 16-bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048
• USB
– USB 2.0 Full Speed (12 Mbits per second) Host Double Port
• Dual On-chip Transceivers
• Integrated FIFOs and Dedicated DMA Channels
– USB 2.0 Full Speed (12 Mbits per second) Device Port
• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
• Bus Matrix
– Handles Five Masters and Five Slaves
– Boot Mode Select Option
– Remap Command
• Fully Featured System Controller (SYSC) for Efficient System Management, including
– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a
Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Three 32-bit PIO Controllers
• Reset Controller (RSTC)
– Based on Power-on Reset Cells, Reset Source Identification and Reset Output
Control
• Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a
Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator and two PLLs
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Four Programmable External Clock Signals
6242DS–ATARM–06-Jan-09
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock
• Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Nineteen Peripheral DMA (PDC) Channels
• Multimedia Card Interface (MCI)
– SDCard and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant
• Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support
• Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel EEPROMs Supported
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and for VDDPLL
– 2.7V to 3.6V for VDDIOP (Peripheral I/Os)
– 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 217-ball LFBGA RoHS-compliant Package
2
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
1. Description
The AT91SAM9261S is a complete system-on-chip built around the ARM926EJ-S ARM Thumb
processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210
MIPS at 190 MHz.
The AT91SAM9261S is an optimized host processor for applications with an LCD display. Its
integrated LCD controller supports BW and up to 16M color, active and passive LCD displays.
The 16 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for
LCD refresh on the overall processor performance. The External Bus Interface incorporates con-
trollers for synchronous DRAM (SDRAM) and Static memories and features specific interface
circuitry for CompactFlash and NAND Flash.
The AT91SAM9261S integrates a ROM-based Boot Loader supporting code shadowing from,
for example, external DataFlash® into external SDRAM. The software controlled Power Manage-
ment Controller (PMC) keeps system power consumption to a minimum by selectively
enabling/disabling the processor and various peripherals and adjustment of the operating
frequency.
The AT91SAM9261S also benefits from the integration of a wide range of debug features includ-
ing JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace.
This enables the development and debug of all applications, especially those with real-time
constraints.
3
6242DS–ATARM–06-Jan-09
2. Block Diagram
Figure 2-1. AT91SAM9261S Block Diagram
JTAGSEL
TDI
ARM926EJ-S Core
JTAG
Boundary Scan
TDO
TMS
ICE
Instruction Cache
16K bytes
Data Cache
16K bytes
MMU
BIU
I
TCK
NTRST
RTCK
System Controller
AIC
BMS
D0-D15
A0/NBS0
TST
FIQ
D
A1/NBS2/NWR2
A2-A15/A18-A21
A22/REG
IRQ0-IRQ2
DRXD
DTXD
PCK0-PCK3
DBGU
PDC
EBI
A16/BA0
Fast SRAM
16K bytes
CompactFlash
NAND Flash
A17/BA1
NCS0
NCS1/SDCS
NCS2
PLLA
PLLRCA
PLLRCB
NCS3/NANDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
Fast ROM
32K bytes
PMC
PLLB
OSC
XIN
XOUT
5-layer
Matrix
SDCKE
SDRAM
Controller
RAS-CAS
SDWE
SDA10
WDT
PIT
NWAIT
A23-A24
Peripheral
Bridge
A25/CFRNW
NCS4/CFCS0
Static
Memory
Controller
GPBREG
RTT
NCS5/CFCS1
CFCE1
CFCE2
NCS6/NANDOE
NCS7/NANDWE
D16-D31
XIN32
XOUT32
OSC
Peripheral
DMA
Controller
SHDN
WKUP
SHDWC
HDMA
HDPA
VDDBU
GNDBU
POR
POR
DMA
FIFO
RSTC
USB Host
HDMB
HDPB
VDDCORE
NRST
FIFO
APB
DDM
DDP
PIOA
PIOB
PIOC
USB Device
DMA
FIFO
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
MCCK
MCCDA
MCDA0-MCDA3
MCI
LUT
LCD Controller
LCDCC
PDC
TF0
TK0
TD0
RD0
RK0
RF0
RXD0
TXD0
SCK0
RTS0
CTS0
SSC0
USART0
USART1
USART2
PDC
PDC
PDC
PDC
RXD1
TXD1
SCK1
RTS1
CTS1
TF1
TK1
TD1
RD1
RK1
RF1
SSC1
PDC
PDC
RXD2
TXD2
SCK2
RTS2
CTS2
TF2
TK2
TD2
RD2
RK2
RF2
SSC2
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
SPI0
SPI1
TC0
TC1
TC2
PDC
PDC
SPI1_NPCS10
SPI1_NPCS1
SPI1_NPCS12
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
TWD
TWI
TWCK
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AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
3. Signal Description
Table 3-1.
Signal Description by Peripheral
Signal Name
Function
Type
Active Level Comments
Power
VDDIOM
VDDIOP
VDDBU
EBI I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
PLL Power Supply
Power
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
1.65 V to 1.95V and 3.0V to 3.6V
2.7V to 3.6V
1.08V to 1.32V
VDDPLL
VDDOSC
VDDCORE
GND
3.0V to 3.6V
Oscillator Power Supply
Core Chip Power Supply
Ground
3.0V to 3.6V
1.08V to 1.32V
GNDPLL
GNDOSC
GNDBU
PLL Ground
Oscillator Ground
Backup Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
XOUT
Main Oscillator Output
Slow Clock Oscillator Input
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
Slow Clock Oscillator Output
PLL Filter
Output
Input
PLL Filter
Input
Programmable Clock Output
Output
Shutdown, Wakeup Logic
SHDN
WKUP
Shutdown Control
Wake-Up Input
Output
Input
Do not tie over VDDBU.
Accepts between 0V and VDDBU.
ICE and JTAG
Input
TCK
Test Clock
No pull-up resistor.
No pull-up resistor.
No pull-up resistor.
RTCK
TDI
Returned Test Clock
Test Data In
Output
Input
TDO
TMS
NTRST
Test Data Out
Output
Test Mode Select
Test Reset Signal
Input
No pull-up resistor.
Pull-up resistor.
Input
Low
Low
Pull-down resistor. Accepts
between 0V and VDDBU.
JTAGSEL
JTAG Selection
Input
Reset/Test
I/O
NRST
TST
Microcontroller Reset
Test Mode Select
Boot Mode Select
Pull-up resistor
Input
Pull-down resistor.
BMS
Input
Debug Unit
Input
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Output
5
6242DS–ATARM–06-Jan-09
Table 3-1.
Signal Description by Peripheral (Continued)
Signal Name
Function
Type
Active Level Comments
AIC
PIO
IRQ0 - IRQ2
FIQ
External Interrupt Inputs
Fast Interrupt Input
Input
Input
PA0 - PA31
PB0 - PB31
PC0 - PC31
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
I/O
I/O
I/O
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
EBI
D0 - D31
A0 - A25
NWAIT
Data Bus
I/O
Pulled-up input at reset
0 at reset
Address Bus
Output
Input
External Wait Signal
Low
SMC
NCS0 - NCS7
NWR0 - NWR3
NRD
Chip Select Lines
Write Signal
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
Read Signal
NWE
Write Enable
NBS0 - NBS3
Byte Mask Signal
CompactFlash Support
CFCE1 - CFCE2
CFOE
CompactFlash Chip Enable
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
CFWE
CFIOR
CFIOW
CompactFlash IO Write
CFRNW
CompactFlash Read Not Write
CompactFlash Chip Select Lines
Output
Output
CFCS0 - CFCS1
Low
NAND Flash Support
Output
NANDOE
NANDWE
NANDCS
NAND Flash Output Enable
NAND Flash Write Enable
NAND Flash Chip Select
Low
Low
Low
Output
Output
SDRAM Controller
Output
SDCK
SDRAM Clock
SDCKE
SDCS
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select
Output
High
Low
Output
BA0 - BA1
SDWE
Output
SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Output
Low
Low
RAS - CAS
SDA10
Output
Output
Multimedia Card Interface
MCCK
Multimedia Card Clock
Output
MCCDA
Multimedia Card A Command
Multimedia Card A Data
I/O
I/O
MCDA0 - MCDA3
6
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
Table 3-1.
Signal Description by Peripheral (Continued)
Signal Name
Function
Type
Active Level Comments
USART
SCK0 - SCK2
TXD0 - TXD2
RXD0 - RXD2
RTS0 - RTS2
CTS0 - CTS2
Serial Clock
I/O
Transmit Data
Receive Data
Request To Send
Clear To Send
Output
Input
Output
Input
Synchronous Serial Controller
TD0 - TD2
RD0 - RD2
TK0 - TK2
RK0 - RK2
TF0 - TF2
RF0 - RF2
Transmit Data
Output
Receive Data
Input
Transmit Clock
I/O
Receive Clock
I/O
Transmit Frame Sync
Receive Frame Sync
I/O
I/O
Timer/Counter
TCLK0 - TCLK2
TIOA0 - TIOA2
TIOB0 - TIOB2
External Clock Input
I/O Line A
Input
I/O
I/O
I/O Line B
SPI
SPI0_MISO -
SPI1_MISO
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
SPI0_MOSI -
SPI1_MOSI
SPI0_SPCK -
SPI1_SPCK
SPI0_NPCS0,
SPI1_NPCS0
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
I/O
Low
Low
SPI0_NPCS1 -
SPI0_NPCS3
Output
SPI1_NPCS1 -
SPI1_NPCS3
Two-Wire Interface
I/O
TWD
Two-wire Serial Data
Two-wire Serial Clock
TWCK
I/O
LCD Controller
Output
LCDD0 - LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCD Data Bus
LCD Vertical Synchronization
LCD Horizontal Synchronization
LCD Dot Clock
Output
Output
Output
LCD Data Enable
Output
LCDCC
LCD Contrast Control
Output
USB Device Port
Analog
DDM
DDP
USB Device Port Data -
USB Device Port Data +
Analog
7
6242DS–ATARM–06-Jan-09
Table 3-1.
Signal Description by Peripheral (Continued)
Signal Name
Function
Type
Active Level Comments
USB Host Port
HDMA
HDPA
HDMB
HDPB
USB Host Port A Data -
USB Host Port A Data +
USB Host Port B Data -
USB Host Port B Data +
Analog
Analog
Analog
Analog
8
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
4. Package and Pinout
The AT91SAM9261S is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm,
0.8 mm ball pitch
4.1
217-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 217-ball LFBGA Package.
A detailed mechanical description is given in the section “AT91SAM9261S Mechanical Charac-
teristics” of the product datasheet.
Figure 4-1. 217-ball LFBGA Package Outline (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B C D E F G H J K L M N P R T U
Ball A1
9
6242DS–ATARM–06-Jan-09
4.2
Pinout
Table 4-1.
AT91SAM9261S Pinout for 217-ball LFBGA Package (1)
Pin
Signal Name
Pin
Signal Name
VDDCORE
A10
Pin
J14
J15
J16
J17
K1
Signal Name
VDDIOP
PB9
Pin
P17
R1
Signal Name
PA20
PC19
PC21
GND
A1
A19
D5
A2
A16/BA0
A14
D6
A3
D7
A5
PB6
R2
A4
A12
D8
A0/NBS0
SHDN
NC
PB4
R3
A5
A9
D9
D6
R4
PC27
PC29
PC4
A6
A6
D10
D11
D12
D13
D14
D15
D16
D17
E1
K2
D8
R5
A7
A3
VDDIOP
PB29
K3
D10
R6
A8
A2
K4
D7
R7
PC8
A9
NC
PB28
K8
GND
R8
PC12
PC14
VDDPLL
PA0
A10
A11
A12
A13
A14
A15
A16
A17
B1
XOUT32
XIN32
DDP
PB23
K9
GND
R9
PB20
K10
K14
K15
K16
K17
L1
GND
R10
R11
R12
R13
R14
R15
R16
R17
T1
PB17
VDDCORE
PB3/BMS
PB1
HDPB
HDMB
PB27
GND
TCK
PA7
NWR1/NBS1/CFIOR
NWR0/NWE/CFWE
NRD/CFOE
SDA10
PB22
PA10
PA13
PA17
GND
E2
PB2
E3
D9
PB24
A20
E4
L2
D11
E14
E15
E16
E17
F1
L3
D12
PA18
PC20
PC23
PC26
PC2
B2
A18
PB18
L4
VDDIOM
PA30
B3
A15
PB15
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
T2
B4
A13
TDI
PA27
T3
B5
A11
SDCKE
RAS
PA31
T4
B6
A7
F2
PB0
T5
VDDIOP
PC5
B7
A4
F3
NWR3/NBS3/CFIOW
NCS0
D13
T6
B8
A1/NBS2/NWR2
VDDBU
JTAGSEL
WKUP
DDM
F4
D15
T7
PC9
B9
F14
F15
F16
F17
G1
PB16
PC18
VDDCORE
PA25
T8
PC10
PC15
VDDOSC
GNDOSC
PA1
B10
B11
B12
B13
B14
B15
B16
B17
C1
NRST
TDO
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
NTRST
D0
PA26
PB31
HDMA
PB26
PB25
PB19
A22
PA28
G2
D1
PA29
PA4
G3
SDWE
NCS3/NANDCS
PB14
D14
PA6
G4
N2
PC17
PC31
VDDIOM
PA22
PA8
G14
G15
G16
G17
H1
N3
PA11
PA14
PC25
PC0
PB12
N4
C2
A21
PB11
N14
N15
N16
N17
P1
C3
VDDIOM
A17/BA1
VDDIOM
A8
PB8
PA21
U2
C4
D2
PA23
U3
PC3
C5
H2
D3
PA24
U4
GND
C6
H3
VDDIOM
SDCK
GND
PC16
PC30
PC22
PC24
PC28
PC1
U5
PC6
C7
GND
H4
P2
U6
VDDIOP
GND
C8
VDDIOM
GNDBU
TST
H8
P3
U7
C9
H9
GND
P4
U8
PC13
PLLRCB
PLLRCA
XIN
C10
C11
C12
C13
C14
C15
C16
C17
D1
H10
H14
H15
H16
H17
J1
GND
P5
U9
GND
PB10
P6
U10
U11
U12
U13
U14
U15
U16
U17
HDPA
PB30
NC
PB13
P7
PC7
PB7
P8
PC11
GNDPLL
PA3
XOUT
PA2
PB5
P9
VDDIOP
PB21
TMS
D4
P10
P11
P12
P13
P14
P15
P16
PA5
J2
D5
VDDIOP
VDDCORE
PA15
PA12
PA9
J3
GND
NCS2
NCS1/SDCS
GND
J4
CAS
RTCK
D2
J8
GND
PA16
D3
J9
GND
VDDIOP
PA19
D4
VDDIOM
J10
GND
Note:
1. Shaded cells define the pins powered by VDDIOM.
10
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
5. Power Considerations
5.1
Power Supplies
The AT91SAM9261S has six types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the memories and the peripherals;
voltage ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to
1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal.
• VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
2.7V and 3.6V, 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
• VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These
supplies enable the user to power the device differently for interfacing with memories and for
interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Sep-
arated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are
GNDBU, GNDOSC and GNDPLL, respectively.
5.2
Power Consumption
The AT91SAM9261S consumes about 550 µA of static current on VDDCORE at 25°C. This
static current rises at up to 5.5 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C.
For dynamic power consumption, the AT91SAM9261S consumes a maximum of 50 mA on
VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-perfor-
mance algorithm.
6. I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied
to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩto GNDBU, so that it can
be left unconnected for normal operations.
The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low
level. It integrates a permanent pull-up resistor of about 15 kΩ to VDDIOP, so that it can be left
unconnected for normal operations.
11
6242DS–ATARM–06-Jan-09
6.2
6.3
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
Reset Pin
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can
be left unconnected in case no reset from the system needs to be applied to the product.
The NRST pin integrates a permanent pull-up resistor of 100 kΩ minimum to VDDIOP.
The NRST signal is inserted in the Boundary Scan.
6.4
6.5
PIO Controller A, B and C Lines
All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up
resistor of 100 kΩ. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
Shutdown Logic Pins
The SHDN pin is an output only, driven by Shutdown Controller.
The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
12
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
7. Processor and Architecture
7.1
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete AHB
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
13
6242DS–ATARM–06-Jan-09
7.2
Debug and Test Features
• Integrated Embedded In-circuit Emulator Real-Time
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
7.3
Bus Matrix
• Five Masters and Five Slaves handled
– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the
Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD
Controller and USB Host Port.
– Round-Robin Arbitration (three modes supported: no default master, last accessed
default master, fixed default master)
– Burst Breaking with Slot Cycle Limit
• One Address Decoder Provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap.
• Boot Mode Select Option
– Non-volatile Boot Memory can be Internal or External.
– Selection is made by BMS pin sampled at reset.
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
7.4
Peripheral DMA Controller
• Transfers from/to peripheral to/from any memory space without intervention of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Nineteen channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the Multimedia Card Interface
14
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
8. Memories
Figure 8-1. AT91SAM9261S Memory Mapping
Address Memory Space
Internal Memory Mapping
Notes :
(1) Can be ROM, EBI_NCS0 or SRAM
depending on BMS and REMAP
0x0000 0000
0x0000 0000
0x10 0000
0x20 0000
0x30 0000
0x40 0000
0x50 0000
0x60 0000
0x70 0000
0x0FFF FFFF
Boot Memory (1)
Reserved
Internal Memories 256M Bytes
0x0FFF FFFF
0x1000 0000
EBI
Chip Select 0
256M Bytes
256M Bytes
Reserved
0x1FFF FFFF
0x2000 0000
EBI
Chip Select 1/
SDRAMC
1M Bytes
1M Bytes
SRAM
0x2FFF FFFF
0x3000 0000
ROM
EBI
Chip Select 2
256M Bytes
256M Bytes
UHP User Interface
LCD User Interface
Reserved
1M Bytes
1M Bytes
0x3FFF FFFF
0x4000 0000
EBI
Chip Select 3/
NAND Flash
0x4FFF FFFF
0x5000 0000
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
256M Bytes
0x5FFF FFFF
0x6000 0000
EBI
Chip Select 5/
Compact Flash
Slot 1
0x6FFF FFFF
0x7000 0000
System Controller Mapping
0xFFFF C000
EBI
Chip Select 6
256M Bytes
256M Bytes
Reserved
Peripheral Mapping
Reserved
0x7FFF FFFF
0x8000 0000
0xF000 0000
EBI
Chip Select 7
0xFFFF EA00
0xFFFF EC00
SDRAMC
SMC
512 Bytes
512 Bytes
0xFFFA 0000
0xFFFA 4000
0x8FFF FFFF
0x9000 0000
16K Bytes
16K Bytes
TCO, TC1, TC2
UDP
0xFFFF EE00
0xFFFF F000
0xFFFA 8000
0xFFFA C000
0xFFFB 0000
MATRIX
512 Bytes
512 Bytes
16K Bytes
16K Bytes
MCI
TWI
AIC
0xFFFF F200
0xFFFF F400
0xFFFF F600
16K Bytes
16K Bytes
DBGU
PIOA
512 Bytes
512 Bytes
512 bytes
USART0
USART1
0xFFFB 4000
0xFFFB 8000
0xFFFB C000
1,518M Bytes
Undefined
(Abort)
16K Bytes
16K Bytes
USART2
SSC0
PIOB
PIOC
0xFFFF F800
0xFFFF FA00
0xFFFF FC00
0xFFFF FD00
512 bytes
0xFFFC 0000
16K Bytes
16K Bytes
SSC1
SSC2
Reserved
PMC
0xFFFC 4000
0xFFFC 8000
256 Bytes
16K Bytes
16K Bytes
RSTC
SHDWC
RTT
16 Bytes
16 Bytes
SPI0
SPI1
0xFFFC C000
0xFFFC D000
0xFFFF FD10
0xFFFF FD20
16 Bytes
16 Bytes
0xFFFF FD30
0xFFFF FD40
PIT
0xEFFF FFFF
0xF000 0000
Reserved
SYSC
WDT
16 Bytes
16 Bytes
0xFFFF FD50
0xFFFF FD60
GPBR
0xFFFF C000
0xFFFF FFFF
Internal Peripherals 256M Bytes
16K Bytes
Reserved
0xFFFF FFFF
0xFFFF FFFF
15
6242DS–ATARM–06-Jan-09
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to
8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7.
The area 0 is reserved for the addressing of the internal memories, and a second level of decod-
ing provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and
provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The Bus Matrix manages five Masters and five Slaves.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master.
Regarding Master 0 and Master 1 (ARM926™ Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to Table 8-3 for details.
Table 8-1.
Master 0
Master 1
Master 2
Master 3
Master 4
List of Bus Matrix Masters
ARM926 Instruction
ARM926 Data
PDC
LCD Controller
USB Host
Each Slave has its own arbiter, thus allowing a different arbitration per Slave.
Table 8-2.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
LCD Controller and USB Host Port Interfaces
External Bus Interface
Internal Peripherals
8.1
Embedded Memories
• 32 KB ROM
– Single Cycle Access at full bus speed
• 16 KB Fast SRAM
– Single Cycle Access at full bus speed
16
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
8.1.1
Internal Memory Mapping
Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
Table 8-3.
Address
Internal Memory Mapping
Master 0: ARM926 Instruction
REMAP(RCB0) = 0
Master 1: ARM926 Data
REMAP (RCB0) = 1
Int. RAM C
REMAP (RCB1) = 0
REMAP (RCB1) = 1
Int. RAM C
BMS = 1
Int. ROM
BMS = 0
EBI NCS0(1)
BMS = 1
Int. ROM
BMS = 0
0x0000 0000
EBI NCS0(1)
Note:
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
8.1.1.1
Internal SRAM
The AT91SAM9261S embeds a high-speed 16-Kbyte SRAM.
8.1.1.2
8.1.1.3
Internal ROM
The AT91SAM9261S integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is
also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.
USB Host Port
The AT91SAM9261S integrates a USB Host Port Open Host Controller Interface (OHCI). The
registers of this interface are directly accessible on the AHB Bus and are mapped like a standard
internal memory at address 0x0050 0000.
8.1.1.4
LCD Controller
The AT91SAM9261S integrates an LCD Controller. The interface is directly accessible on the
AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted for each Master of the Bus Matrix. Refer to the
Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 15.
The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the
BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
17
6242DS–ATARM–06-Jan-09
8.1.2.1
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• DataFlash Boot
– Downloads and runs an application from SPI DataFlash into internal SRAM
– Downloaded code size from SPI DataFlash depends on embedded SRAM size
– Automatic detection of valid application
– SPI DataFlash connected to SPI NPCS0
• NAND Flash boot
• Boot Uploader in case no valid program is detected in external SPI DataFlash
– Small monitor functionalities (read/write/run) interface with SAM-BA® application
– Automatic detection of the communication link
Serial communication on a DBGU (XModem protocol)
USB Device Port (CDC Protocol)
8.1.2.2
BMS = 0, Boot on External Memory
• Boot on slow clock (32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock
4. Switch the main clock to the new value.
8.2
External Memories
The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3).
Refer to the memory map in Figure 8-1 on page 15.
18
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power,
time, debug and reset.
The System Peripherals are all mapped within the highest 6 Kbytes of address space, between
addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or
512 Bytes, representing 64 or 128 registers.
Figure 9-1 on page 20 shows the System Controller block diagram.
Figure 8-1 on page 15 shows the mapping of the User Interfaces of the System Controller
peripherals.
19
6242DS–ATARM–06-Jan-09
9.1
Block Diagram
Figure 9-1. System Controller Block Diagram
System Controller
nirq
nfiq
irq0-irq2
fiq
Advanced
Interrupt
Controller
periph_irq[2..21]
int
pit_irq
rtt_irq
ice_nreset
force_ntrst
ntrst
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ARM926EJ-S
proc_nreset
MCK
dbgu_irq
force_ntrst
dbgu_txd
Debug
Unit
periph_nreset
PCK
dbgu_rxd
debug
MCK
Periodic
Interval
Timer
debug
pit_irq
periph_nreset
SLCK
debug
Watchdog
Timer
jtag_nreset
Boundary Scan
TAP Controller
wdt_irq
idle
proc_nreset
wdt_fault
WDRPROC
VDDCORE Powered
MCK
NRST
Bus Matrix
ice_nreset
periph_nreset
periph_nreset
proc_nreset
VDDCORE
jtag_nreset
POR
Reset
Controller
backup_nreset
rstc_irq
UDPCK
VDDBU
POR
periph_clk[10]
periph_nreset
periph_irq[10]
usb_suspend
USB Device
Port
SLCK
rtt_irq
SLCK
Real-Time
Timer
rtt_alarm
backup_nreset
SLCK
rtt_alarm
SHDN
Shutdown
Controller
UHPCK
WKUP
periph_clk[20]
periph_nreset
periph_irq[20]
backup_nreset
USB Host
Port
4 General-purpose
Backup Registers
VDDBU Powered
XIN32
SLOW
CLOCK
OSC
SLCK
XOUT32
LCDCK
periph_clk[2..21]
pck[0-3]
periph_clk[21]
XIN
LCD
Controller
MAINCK
MAIN
OSC
periph_nreset
periph_irq[21]
PCK
XOUT
UDPCK
UHPCK
LCDCK
MCK
Power
Management
Controller
PLLRCA
PLLRCB
PLLA
PLLB
PLLACK
PLLBCK
pmc_irq
idle
periph_clk[6..21]
periph_nreset
int
periph_nreset
usb_suspend
Embedded
Peripherals
periph_nreset
periph_clk[2..4]
dbgu_rxd
periph_irq{2..4]
irq0-irq2
fiq
periph_irq[6..21]
PIO
Controllers
PA0-PA31
dbgu_txd
in
PB0-PB31
PC0-PC31
out
enable
20
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
9.2
9.3
Reset Controller
• Based on two Power-on-Reset cells
• Status of the last reset
– Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset
• Controls the internal resets and the NRST pin output
Shutdown Controller
• Shutdown and Wake-up logic:
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
9.4
9.5
General-purpose Backup Registers
• Four 32-bit general-purpose backup registers
Clock Generator
• Embeds the Low-power 32768 Hz Slow Clock Oscillator
– Provides the permanent Slow Clock to the system
• Embeds the Main Oscillator
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
• Embeds Two PLLs
– Outputs 80 to 240 MHz clocks
– Integrates an input divider to increase output accuracy
– 1 MHz minimum input frequency
• Provides SLCK, MAINCK, PLLACK and PLLBCK.
Figure 9-2. Clock Generator Block Diagram
Clock Generator
XIN32
XOUT32
XIN
Slow Clock
Oscillator
Slow Clock
SLCK
Main
Oscillator
Main Clock
MAINCK
XOUT
PLL and
Divider A
PLLA Clock
PLLACK
PLLRCA
PLLRCB
PLL and
Divider B
PLLB Clock
PLLBCK
Status
Power
Control
Management
Controller
21
6242DS–ATARM–06-Jan-09
9.6
Power Management Controller
• The Power Management Controller provides:
– the Processor Clock PCK
– the Master Clock MCK
– the USB Clock USBCK (HCK0)
– the LCD Controller Clock LCDCK (HCK1)
– up to thirty peripheral clocks
– four programmable clock outputs: PCK0 to PCK3
Figure 9-3. Power Management Controller Block Diagram
Processor
Clock
Controller
PCK
int
Master Clock Controller
Idle Mode
SLCK
MAINCK
PLLACK
PLLBCK
Divider
/1,/2,/3,/4
Prescaler
/1,/2,/4,...,/64
MCK
APB Peripherals
Clock Controller
periph_clk[2..21]
ON/OFF
AHB Peripherals
Clock Controller
HCKx
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
pck[0..3]
USB Clock Controller
ON/OFF
usb_suspend
UDPCK
UHPCK
Divider
/1,/2,/4
PLLBCK
9.7
Periodic Interval Timer
• Includes a 20-bit Periodic Counter with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real time OS or Linux®/WindowsCE® compliant tick generator
9.8
9.9
Watchdog Timer
• 12-bit key-protected only-once programmable counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
Real-time Timer
• 32-bit Free-running backup counter
• Alarm Register capable to generate a wake-up of the system
22
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
9.10 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external
interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive
• Four External Sources
• 8-level Priority Controller
– Drives the normal interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect mode is enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
• General Interrupt Mask
– Provides processor synchronization on events without triggering an interrupt
9.11 Debug Unit
• Composed of four functions
– Two-pin UART
– Debug Communication Channel (DCC) support
– Chip ID Registers
– ICE Access Prevention
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
23
6242DS–ATARM–06-Jan-09
– Offers visibility of COMMRX and COMMTX signals from the ARM Processor
• Chip ID Registers
– Identification of the device revision, sizes of the embedded memories, set of
peripherals
• ICE Access prevention
– Enables software to prevent system access through the ARM Processor’s ICE
– Prevention is made by asserting the NTRST line of the ARM Processor’s ICE
9.12 PIO Controllers
• Three PIO Controllers, each controlling up to 32 programmable I/O Lines
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O)
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
24
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10. Peripherals
10.1 User Interface
The User Peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of
address space.
A complete memory map is presented in Figure 8-1 on page 15.
10.2 Peripheral Identifiers
Table 10-1 defines the Peripheral Identifiers of the AT91SAM9261S. A peripheral identifier is
required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for
the control of the peripheral clock with the Power Management Controller.
Table 10-1. Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
System Interrupt
FIQ
1
SYSIRQ
PIOA
PIOB
PIOC
-
2
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
Reserved
3
4
5
6
US0
US1
US2
MCI
USART 0
7
USART 1
8
USART 2
9
Multimedia Card Interface
USB Device Port
10
11
12
13
14
15
16
17
18
19
20
21
22 - 28
29
30
31
UDP
TWI
Two-Wire Interface
SPI0
SPI1
SSC0
SSC1
SSC2
TC0
TC1
TC2
UHP
LCDC
-
Serial Peripheral Interface 0
Serial Peripheral Interface 1
Synchronous Serial Controller 0
Synchronous Serial Controller 1
Synchronous Serial Controller 2
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
USB Host Port
LCD Controller
Reserved
AIC
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
IRQ0
IRQ1
IRQ2
AIC
AIC
Note:
Setting AIC, SYSIRQ, UHP, LCDC and IRQ0 to IRQ2 bits in the clock set/clear registers of the
PMC has no effect.
25
6242DS–ATARM–06-Jan-09
10.3 Peripheral Multiplexing on PIO Lines
The AT91SAM9261S features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the
I/O lines of the peripheral set.
Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two
peripheral functions, A or B. Table 10-2 on page 28, Table 10-3 on page 29 and Table 10-4 on
page 30 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-
lers. The two columns “Function” and “Comments” have been inserted for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some output only peripheral functions might be duplicated within the tables.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device
is maintained in a static state as soon as the reset is released. As a result, the bit corresponding
to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
10.3.1
Resource Multiplexing
10.3.1.1
LCD Controller
The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel
without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the
chip select line 0 of the SPI1.
16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output
on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on
LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and
the SPI1 lines.
10.3.1.2
10.3.1.3
EBI
If not required, the NWAIT function (external wait request) can be deactivated by software,
allowing this pin to be used as a PIO.
32-bit Data Bus
Using a 32-bit Data Bus prevents:
• using the three Timer Counter channels’ outputs and trigger inputs
• using the SSC2
10.3.1.4
10.3.1.5
NAND Flash Interface
Using the NAND Flash interface prevents:
• using NCS3, NCS6 and NCS7 to access other parallel devices
Compact Flash Interface
Using the CompactFlash interface prevents:
• using NCS4 and/or NCS5 to access other parallel devices
26
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10.3.1.6
SPI0 and the MultiMedia Card Interface
As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI.
Here, the SPI0 signal is multiplexed with the MCI.
10.3.1.7
10.3.1.8
USARTs
• Using USART0 with its control signals prevents using some clock outputs and interrupt lines.
Clock Outputs
Interrupt Lines
• Using the clock outputs multiplexed with the PIO A prevents using the Debug Unit and/or the
Two Wire Interface.
• Alternatively, using the second implementation of the clock outputs prevents using the LCD
Controller Interface and/or USART0.
10.3.1.9
• Using FIQ prevents using the USART0 control signals.
• Using IRQ0 prevents using the NWAIT EBI signal.
• Using the IRQ1 and/or IRQ2 prevents using the SPI1.
27
6242DS–ATARM–06-Jan-09
10.3.2
PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A
Application Usage
Function
Reset
State
I/O Line
PA0
Peripheral A
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
TWD
Peripheral B
MCDA0
Comments
Power Supply
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
Comments
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A23
A24
PA1
MCCDA
MCCK
PA2
PA3
PA4
MCDA1
MCDA2
MCDA3
PCK0
PA5
PA6
PA7
PA8
TWCK
PCK1
PA9
DRXD
PCK2
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
DTXD
PCK3
TSYNC
TCLK
SCK1
RTS1
TPS0
CTS1
TPS1
SCK2
TPS2
RTS2
TPK0
CTS2
TPK1
TF1
TPK2
TK1
TPK3
TD1
TPK4
RD1
TPK5
RK1
TPK6
RF1
TPK7
RTS0
TPK8
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
A23
TPK9
TPK10
TPK11
TPK12
TPK13
TPK14
TPK15
A24
28
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10.3.3
PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B
Application Usage
Reset
State
I/O Line
PB0
Peripheral A
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
LCDCC
Peripheral B
Comments
Power Supply
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
Function
Comments
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PB1
PB2
PCK0
PB3(1)
See footnote(1)
PB4
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
LCDD16
LCDD17
LCDD18
LCDD19
LCDD20
LCDD21
LCDD22
LCDD23
IRQ2
PB5
LCDD0
PB6
LCDD1
PB7
LCDD2
PB8
LCDD3
PB9
LCDD4
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
LCDD5
LCDD6
LCDD7
LCDD8
LCDD9
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
TF0
TK0
TD0
RD0
RK0
RF0
SPI1_NPCS1
SPI1_NPCS0
SPI1_SPCK
SPI1_MISO
SPI1_MOSI
IRQ1
PCK2
Note:
1. PB3 is multiplexed with BMS signal. Care should be taken during reset time.
29
6242DS–ATARM–06-Jan-09
10.3.4
PIO Controller C Multiplexing
Table 10-4. Multiplexing on PIO Controller C
PIO Controller C
Application Usage
Reset
State
I/O Line
PC0
Peripheral A
NANDOE
NANDWE
NWAIT
A25/CFRNW
NCS4/CFCS0
NCS5/CFCS1
CFCE1
CFCE2
TXD0
RXD0
RTS0
Peripheral B
NCS6
Comments
Power Supply
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOP
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
Function
Comments
I/O
I/O
I/O
A25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PC1
NCS7
PC2
IRQ0
PC3
PC4
PC5
PC6
PC7
PC8
PCK2
PCK3
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
SCK0
CTS0
TXD1
RXD1
TXD2
RXD2
D16
FIQ
NCS6
NCS7
SPI1_NPCS2
SPI1_NPCS3
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TF2
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
TK2
D27
TD2
D28
RD2
D29
RK2
D30
RF2
D31
PCK1
30
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10.3.5
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-Time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.3.6
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.4 External Bus Interface
• Integrates two External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
• Additional logic for NAND Flash and CompactFlash support
– NAND Flash support: 8-bit as well as 16-bit devices are supported
– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True
IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL
(True IDE mode) are not handled.
• Optimized External Bus
– 16- or 32-bit Data Bus
– Up to 26-bit Address Bus, up to 64 Mbytes addressable
– Eight Chip Selects, each reserved to one of the eight Memory Areas
– Optimized pin multiplexing to reduce latencies on External Memories
• Configurable Chip Select Assignment Managed by EBI_CSA Register located in the MATRIX
user interface
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash Support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support
– Static Memory Controller on NCS6 - NCS7
31
6242DS–ATARM–06-Jan-09
10.5 Static Memory Controller
• External memory mapping, 256 Mbyte address space per Chip Select Line
• Up to Eight Chip Select Lines
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signal programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock Mode Supported
10.6 SDRAM Controller
• Supported Devices
– Standard and Low Power SDRAM (Mobile SDRAM)
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming Facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving Capabilities
– Self-refresh, power down and deep power down modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
32
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10.7 Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to
fifteen peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.8 Two-wire Interface
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
10.9 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By-8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA modulation and demodulation
33
6242DS–ATARM–06-Jan-09
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.10 Synchronous Serial Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and
more).
• Contains an independent receiver and transmitter and a common clock divider.
• Offers a configurable frame sync and data length.
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal.
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal.
10.11 Timer Counter
• Three 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
10.12 Multimedia Card Interface
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• Each MCI has two slots, each supporting
– One slot for one MultiMedia Card bus (up to 30 cards) or
– One SD Memory Card
• Support for stream, block and multi-block data read and write
34
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
10.13 USB
• USB Host Port:
– Compliance with Open HCI Rev 1.0 specification
– Compliance with USB V2.0 Full-speed and Low-speed Specification
– Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices
– Root hub integrated with two downstream USB ports
– Two embedded USB transceivers
– No overcurrent detection
– Supports power management
– Operates as a master on the Bus Matrix
• USB Device Port:
– USB V2.0 full-speed compliant, 12 Mbits per second
– Embedded USB V2.0 full-speed transceiver
– Embedded dual-port RAM for endpoints
– Suspend/Resume logic
– Ping-pong mode (two memory banks) for isochronous and bulk endpoints
– Six general-purpose endpoints:
Endpoint 0: 8 bytes, no ping-pong mode
Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode
Endpoint 3: 64 bytes, no ping-pong mode
Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode
• Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user
interface
10.14 LCD Controller
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported.
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048 x 2048
35
6242DS–ATARM–06-Jan-09
11. Package Drawing
Figure 11-1. 217-ball LFBGA Package Drawing
36
AT91SAM9261S
6242DS–ATARM–06-Jan-09
AT91SAM9261S
12. AT91SAM9261S Ordering Information
Table 12-1. AT91SAM9261S Ordering Information
Ordering Code
Package
Package Type
Temperature Operating Range
Industrial
-40°C to 85°C
AT91SAM9261S-CJ
BGA217
RoHS-compliant
Industrial
-40°C to 85°C
AT91SAM9261SB-CU
BGA217
RoHS-compliant
37
6242DS–ATARM–06-Jan-09
13. Revision History
In the table below the most recent version of the datasheet appears first.
Change
Doc. Rev.
Comments
Request Ref.
“Features”
6242DS
Additional Embedded Memories, 16 Kbytes SRAM updated.
Debug Unit (DBGU) updated.
5848
5846
Section 12. “AT91SAM9261S Ordering Information”
Updated with Revision B Parts: AT91SAM9261SB-CU
Section 7.2 “Debug and Test Features”, removed ETM9 list.
5487
6242CS
5794
6242BS
6242AS
Section 12. “AT91SAM9261S Ordering Information” added to document.
First Issue
38
AT91SAM9261S
6242DS–ATARM–06-Jan-09
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6242DS–ATARM–06-Jan-09
相关型号：
AT91SAM9261S-CU
RISC Microcontroller, 32-Bit, MROM, 240MHz, CMOS, PBGA217, 15 X 15 MM, 0.80 MM PITCH, GREEN, MO-205, LFBGA-217
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