AT91SAM9XE512-QU [ATMEL]
AT91 ARM Thumb Microcontrollers; AT91 ARM的Thumb微控制器
| 型号： | AT91SAM9XE512-QU |
| 厂家： | 
ATMEL |
| 描述： | AT91 ARM Thumb Microcontrollers |
| 文件： | 总48页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration
– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
• Additional Embedded Memories
– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for
AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed
– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,
AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024
Pages of 512 Bytes Respectively.
AT91 ARM
Thumb
Microcontrollers
• 128-bit Wide Access
• Fast Read Time: 45 ns
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
Preliminary
• Page Programming Time: 4 ms, Including Page Auto-erase,
Full Erase Time: 10 ms
• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash
Security Bit
• Enhanced Embedded Flash Controller (EEFC)
– Interface of the Flash Block with the 32-bit Internal Bus
– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory
Interface
• External Bus Interface (EBI)
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™
• USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM
• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device
and Double Port in 217-ball LFBGA Device
Summary
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
• Bus Matrix
– Six 32-bit-layer Matrix
– Remap Command
• Fully-featured System Controller, including
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
6254BS–ATARM–29-Apr-09
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
• Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply,
Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer Plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-Time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog to Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• Peripheral DMA Controller Channels (PDC)
• Two-slot Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
• One Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
• One 2-wire UART
• Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
• Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
• Two Two-wire Interfaces (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
– Connection to PDC Channel to Optimize Data Transfers in Master Mode Only
2
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package
1. AT91SAM9XE128/256/512 Description
The AT91SAM9XE128/256/512 is based on the integration of an ARM926EJ-S processor with
fast ROM and RAM, 128, 256 or 512 Kbytes of Flash and a wide range of peripherals.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to mounting. Built-in lock bits a security bit
and MMU protect the firmware from accidental overwrite and preserve its confidentiality.
The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB
Host Controller. It also integrates several standard peripherals, like six UARTs, SPI, TWI, Timer
Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface.
The AT91SAM9XE128/256/512 system controller includes a reset controller capable of manag-
ing the power-on sequence of the microcontroller and the complete system. Correct device
operation can be monitored by a built-in brownout detector and a watchdog running off an inte-
grated RC oscillator.
The AT91SAM9XE128/256/512 is architectured on a 6-layer matrix, allowing a maximum inter-
nal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of
interfacing with a wide range of memory devices.
The pinout and ball-out are fully compatible with the AT91SAM9260 with the exception that the
pin BMS is replaced by the pin ERASE.
3
6254BS–ATARM–29-Apr-09
2. AT91SAM9XE128/256/512 Block Diagram
The block diagram shows all the features for the 217-LFBGA package. Some functions are not
accessible in the 208-PQFP package and the unavailable pins are highlighted in “Multiplexing
on PIO Controller A” on page 37, “Multiplexing on PIO Controller B” on page 38, “Multiplexing on
PIO Controller C” on page 39. The USB Host Port B is also not available. Table 2-1 on page 4
defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.
Table 2-1.
Unavailable Signals in 208-pin PQFP Device
PIO
Peripheral A
HDPB
HDMB
SCK2
Peripheral B
-
-
-
-
PA30
PA31
PB12
PB13
PC2
PC3
PC12
RXD4
SCK0
TXD4
TWD1
TWCK1
AD2
ISI_D10
ISI_D11
PCK1
AD3
SPI1_NPCS3
NCS7
IRQ0
4
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Figure 2-1. AT91SAM9XE128/256/512 Block Diagram
F i l t e r
5
6254BS–ATARM–29-Apr-09
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Active
Level
Reference
Voltage
Signal Name
Function
Type
Power Supplies
Power
Comments
VDDIOM
VDDIOP0
VDDIOP1
VDDBU
EBI I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Peripherals I/O Lines Power Supply
Backup I/O Lines Power Supply
Analog Power Supply
1.65V to 1.95V or 3.0V to 3.6V
3.0V to 3.6V
Power
Power
1.65V to 3.6V
Power
1.65V to 1.95V
VDDANA
VDDPLL
Power
3.0V to 3.6V
PLL Power Supply
Power
1.65V to 1.95V
Core Chip and Embedded Memories
Power Supply
VDDCORE
Power
1.65V to 1.95V
GND
Ground
Ground
Ground
Ground
Ground
GNDPLL
GNDANA
GNDBU
PLL Ground
Analog Ground
Backup Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
XOUT
XIN32
XOUT32
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Output
Accepts between 0V and
VDDBU.
OSCSEL
Slow Clock Oscillator Selection
Input
VDDBU
PLLRCA
PLL A Filter
Input
PCK0 - PCK1
Programmable Clock Output
Output
VDDIOP0
Shutdown, Wakeup Logic
SHDN
WKUP
Shutdown Control
Wake-Up Input
Output
Low
VDDBU
VDDBU
Driven at 0V only.
Accepts between 0V and
VDDBU.
Input
ICE and JTAG
NTRST
TCK
Test Reset Signal
Test Clock
Input
Low
VDDIOP0
VDDIOP0
Pull-Up resistor (100 kΩ)
No pull-up resistor, Schmitt
trigger
Input
No pull-up resistor, Schmitt
trigger
TDI
Test Data In
Input
Output
Input
VDDIOP0
VDDIOP0
VDDIOP0
VDDBU
TDO
Test Data Out
Test Mode Select
JTAG Selection
No pull-up resistor, Schmitt
trigger
TMS
JTAGSEL
Input
Pull-down resistor (15 kΩ).
6
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Table 3-1.
Signal Description List (Continued)
Active
Level
Reference
Voltage
Signal Name
Function
Type
Comments
RTCK
Return Test Clock
Output
VDDIOP0
Flash Memory
Flash and NVM Configuration Bits
Erase Command
ERASE
Input
High
Low
VDDIOP0
Pull-down resistor (15 kΩ)
Reset/Test
Open-drain output,
Pull-Up resistor (100 kΩ).
Inserted in the Boundary
Scan.
NRST
TST
Microcontroller Reset
Test Mode Select
I/O
VDDIOP0
VDDBU
Input
Pull-down resistor (15 kΩ)
Debug Unit - DBGU
Input
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
VDDIOP0
VDDIOP0
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ2
FIQ
External Interrupt Inputs
Fast Interrupt Input
Input
Input
VDDIOP0
VDDIOP0
PIO Controller - PIOA - PIOB - PIOC
Pulled-up input at reset
PA0 - PA31
PB0 - PB30
PC0 - PC31
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
(100kΩ)(1)
Pulled-up input at reset
(100kΩ)(1)
Pulled-up input at reset
(100kΩ)(1)
External Bus Interface - EBI
D0 - D31
A0 - A25
NWAIT
Data Bus
I/O
VDDIOM
VDDIOM
VDDIOM
Pulled-up input at reset
0 at reset
Address Bus
Output
External Wait Signal
Input
Low
Static Memory Controller - SMC
NCS0 - NCS7
Chip Select Lines
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
NWR0 - NWR3 Write Signal
NRD
Read Signal
NWE
Write Enable
NBS0 - NBS3
Byte Mask Signal
7
6254BS–ATARM–29-Apr-09
Table 3-1.
Signal Description List (Continued)
Active
Level
Reference
Voltage
Signal Name
Function
Type
Comments
CompactFlash Support
CFCE1 -
CFCE2
CompactFlash Chip Enable
Output
Low
VDDIOM
CFOE
CompactFlash Output Enable
CompactFlash Write Enable
CompactFlash IO Read
Output
Output
Output
Output
Output
Low
Low
Low
Low
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
CFWE
CFIOR
CFIOW
CFRNW
CompactFlash IO Write
CompactFlash Read Not Write
CFCS0 -
CFCS1
CompactFlash Chip Select Lines
Output
Low
VDDIOM
NAND Flash Support
NANDCS
NANDOE
NANDWE
NAND Flash Chip Select
NAND Flash Output Enable
NAND Flash Write Enable
Output
Output
Low
VDDIOM
VDDIOM
VDDIOM
Low
Low
Output
SDRAM Controller
Output
SDCK
SDRAM Clock
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
SDCKE
SDCS
SDRAM Clock Enable
SDRAM Controller Chip Select
Bank Select
Output
Output
Output
Output
Output
Output
High
Low
BA0 - BA1
SDWE
SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Low
Low
RAS - CAS
SDA10
Multimedia Card Interface MCI
MCCK
Multimedia Card Clock
Output
VDDIOP0
VDDIOP0
MCCDA
Multimedia Card Slot A Command
Multimedia Card Slot A Data
Multimedia Card Slot B Command
Multimedia Card Slot B Data
I/O
I/O
I/O
I/O
MCDA0 -
MCDA3
VDDIOP0
VDDIOP0
VDDIOP0
MCCDB
MCDB0 -
MCDB3
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
DTR0
DSR0
USARTx Serial Clock
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
USART0 Data Terminal Ready
USART0 Data Set Ready
Input
Output
Input
Output
Input
8
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Table 3-1.
Signal Description List (Continued)
Active
Level
Reference
Voltage
Signal Name
DCD0
Function
Type
Input
Input
Comments
USART0 Data Carrier Detect
USART0 Ring Indicator
VDDIOP0
VDDIOP0
RI0
Synchronous Serial Controller - SSC
TD
RD
TK
RK
TF
RF
SSC Transmit Data
Output
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
SSC Receive Data
Input
SSC Transmit Clock
SSC Receive Clock
I/O
I/O
SSC Transmit Frame Sync
SSC Receive Frame Sync
I/O
I/O
Timer/Counter - TCx
TCLKx
TIOAx
TIOBx
TC Channel x External Clock Input
TC Channel x I/O Line A
Input
I/O
VDDIOP0
VDDIOP0
VDDIOP0
TC Channel x I/O Line B
I/O
Serial Peripheral Interface - SPIx_
SPIx_MISO
SPIx_MOSI
SPIx_SPCK
SPIx_NPCS0
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
SPI Peripheral Chip Select 0
I/O
Low
Low
SPIx_NPCS1-
SPIx_NPCS3
SPI Peripheral Chip Select
Output
VDDIOP0
Two-Wire Interface
I/O
TWDx
Two-wire Serial Data
Two-wire Serial Clock
VDDIOP0
VDDIOP0
TWCKx
I/O
USB Host Port
Analog
HDPA
HDMA
HDPB
HDMB
USB Host Port A Data +
USB Host Port A Data -
USB Host Port B Data +
USB Host Port B Data +
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Analog
Analog
Analog
USB Device Port
Analog
DDM
DDP
USB Device Port Data -
USB Device Port Data +
VDDIOP0
VDDIOP0
Analog
9
6254BS–ATARM–29-Apr-09
Table 3-1.
Signal Description List (Continued)
Active
Level
Reference
Voltage
Signal Name
Function
Type
Ethernet 10/100
Input
Comments
ETXCK
ERXCK
ETXEN
ETX0-ETX3
ETXER
ERXDV
ERX0-ERX3
ERXER
ECRS
Transmit Clock or Reference Clock
Receive Clock
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
MII only, REFCK in RMII
MII only
Input
Transmit Enable
Output
Output
Output
Input
Transmit Data
ETX0-ETX1 only in RMII
MII only
Transmit Coding Error
Receive Data Valid
Receive Data
RXDV in MII, CRSDV in RMII
ERX0-ERX1 only in RMII
Input
Receive Error
Input
Carrier Sense and Data Valid
Collision Detect
Input
MII only
MII only
ECOL
Input
EMDC
Management Data Clock
Management Data Input/Output
Force 100Mbit/sec.
Output
I/O
EMDIO
EF100
Output
High
Image Sensor Interface
ISI_D0-
ISI_D11
Image Sensor Data
Input
VDDIOP1
ISI_MCK
Image sensor Reference clock
Image Sensor Horizontal Synchro
Image Sensor Vertical Synchro
Image Sensor Data clock
output
input
input
input
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
ISI_HSYNC
ISI_VSYNC
ISI_PCK
Analog to Digital Converter
AD0-AD3
ADVREF
ADTRG
Analog Inputs
Analog
VDDANA
VDDANA
VDDANA
Digital pulled-up inputs at reset
Analog Positive Reference
ADC Trigger
Analog
Input
Fast Flash Programming Interface
Input
PGMEN[2:0]
PGMNCMD
PGMRDY
Programming Enabling
Programming Command
Programming Ready
Programming Read
Data Direction
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Input
Output
Input
Output
Input
I/O
Low
High
Low
Low
PGMNOE
PGMNVALID
PGMM[3:0]
PGMD[15:0]
Programming Mode
Programming Data
Note:
1. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all
the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter-
face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the
peripheral multiplexing tables.
10
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
4. Package and Pinout
The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch) or
in a 217-ball LFBGA Green package (0.8 mm ball pitch).
4.1
208-pin PQFP Package Outline
Figure 4-1 shows the orientation of the 208-pin PQFP package.
A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character-
istics” of the product datasheet.
Figure 4-1. 208-pin PQFP Package Outline (Top View)
156
105
157
104
208
53
1
52
11
6254BS–ATARM–29-Apr-09
4.2
208-pin PQFP Package Pinout
Table 4-1.
Pinout for 208-pin PQFP Package
Pin
1
Signal Name
PA24
Pin
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Signal Name
GND
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
Signal Name
RAS
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
Signal Name
ADVREF
PC0
2
PA25
DDM
D0
3
PA26
DDP
D1
PC1
4
PA27
PC13
PC11
PC10
PC14
PC9
D2
VDDANA
PB10
PB11
PB20
PB21
PB22
PB23
PB24
PB25
VDDIOP1
GND
5
VDDIOP0
GND
D3
6
D4
7
PA28
D5
8
PA29
D6
9
PB0
PC8
GND
VDDIOM
SDCK
SDWE
SDCKE
D7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PB1
PC4
PB2
PC6
PB3
PC7
VDDIOP0
GND
VDDIOM
GND
PB4
PC5
D8
PB26
PB27
GND
PB5
NCS0
CFOE/NRD
CFWE/NWE/NWR0
NANDOE
NANDWE
A22
D9
PB6
D10
PB7
D11
VDDCORE
PB28
PB29
PB30
PB31
PA0
PB8
D12
PB9
D13
PB14
D14
PB15
A21
D15
PB16
A20
PC15
PC16
PC17
PC18
PC19
VDDIOM
GND
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
GND
VDDCORE
VDDPLL
XIN
VDDIOP0
GND
A19
PA1
VDDCORE
GND
PA2
PB17
PA3
PB18
A18
PA4
PB19
BA1/A17
BA0/A16
A15
PA5
TDO
PA6
TDI
PA7
TMS
A14
VDDIOP0
GND
VDDIOP0
GND
A13
A12
PA8
TCK
A11
PA9
NTRST
NRST
RTCK
VDDCORE
GND
A10
PA10
A9
PA11
A8
PA12
VDDIOM
GND
PA13
PA14
ERASE
OSCSEL
TST
A7
PA15
A6
PA16
A5
PA17
JTAGSEL
GNDBU
XOUT32
XIN32
VDDBU
WKUP
A4
VDDIOP0
GND
A3
A2
PA18
NWR2/NBS2/A1
NBS0/A0
SDA10
XOUT
GNDPLL
NC
PA19
VDDCORE
GND
12
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Table 4-1.
Pinout for 208-pin PQFP Package (Continued)
Pin
49
50
51
52
Signal Name
SHDN
Pin
101
102
103
104
Signal Name
CFIOW/NBS3/NWR3
CFIOR/NBS1/NWR1
SDCS/NCS1
Pin
153
154
155
156
Signal Name
GNDPLL
PLLRCA
Pin
205
206
207
208
Signal Name
PA20
HDMA
PA21
HDPA
VDDPLL
PA22
VDDIOP0
CAS
GNDANA
PA23
4.3
217-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 217-ball LFBGA package.
A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character-
istics” of the product datasheet.
Figure 4-2.
217-ball LFBGA Package Outline (Top View)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B C D E F G H J K L M N P R T U
Ball A1
13
6254BS–ATARM–29-Apr-09
4.4
217-ball LFBGA Package Pinout
Table 4-2.
Pinout for 217-ball LFBGA Package
Pin
Signal Name
Pin
Signal Name
Pin
J14
J15
J16
J17
K1
Signal Name
TDO
PB19
TDI
Pin
P17
R1
Signal Name
PB5
NC
GNDANA
PC29
VDDANA
PB12
PB23
GND
A1
A2
A3
CFIOW/NBS3/NWR3
NBS0/A0
NWR2/NBS2/A1
D5
D6
D7
A5
GND
A10
R2
A4
A6
D8
GND
PB16
PC24
PC20
D15
R3
A5
A8
D9
VDDCORE
GND
R4
A6
A11
D10
D11
D12
D13
D14
D15
D16
D17
E1
K2
R5
A7
A13
VDDIOM
GND
K3
R6
A8
BA0/A16
A18
K4
PC21
GND
R7
A9
DDM
K8
R8
PB26
PB28
PA0
A10
A11
A12
A13
A14
A15
A16
A17
B1
A21
HDPB
NC
K9
GND
R9
A22
K10
K14
K15
K16
K17
L1
GND
R10
R11
R12
R13
R14
R15
R16
R17
T1
CFWE/NWE/NWR0
CFOE/NRD
NCS0
PC5
VDDBU
XIN32
D10
PB4
PA4
PB17
GND
PA5
PA10
PA21
PA23
PA24
PA29
PLLRCA
GNDPLL
PC0
E2
D5
PB15
GND
PC6
E3
D3
PC4
E4
D4
L2
PC26
PC25
VDDIOP0
PA28
PB9
SDCK
CFIOR/NBS1/NWR1
SDCS/NCS1
SDA10
A3
E14
E15
E16
E17
F1
HDPA
HDMA
GNDBU
XOUT32
D13
L3
B2
L4
B3
L14
L15
L16
L17
M1
M2
M3
M4
M14
M15
M16
M17
N1
T2
B4
T3
B5
PB8
T4
PC1
B6
A7
F2
SDWE
D6
PB14
VDDCORE
PC31
GND
T5
PB10
PB22
GND
B7
A12
F3
T6
B8
A15
F4
GND
T7
B9
A20
F14
F15
F16
F17
G1
OSCSEL
ERASE
JTAGSEL
TST
T8
PB29
PA2
B10
B11
B12
B13
B14
B15
B16
B17
C1
NANDWE
PC7
PC22
PB1
T9
T10
T11
T12
T13
T14
T15
T16
T17
U1
PA6
PC10
PC13
PC11
PC14
PC8
PB2
PA8
PC15
D7
PB3
PA11
VDDCORE
PA20
GND
G2
PB7
G3
SDCKE
VDDIOM
GND
XIN
G4
N2
VDDPLL
PC23
PC27
PA31
PA30
PB0
WKUP
D8
G14
G15
G16
G17
H1
N3
PA22
PA27
GNDPLL
ADVREF
PC2
NRST
RTCK
TMS
N4
C2
D1
N14
N15
N16
N17
P1
C3
CAS
U2
C4
A2
PC18
D14
U3
C5
A4
H2
PB6
U4
PC3
C6
A9
H3
D12
XOUT
VDDPLL
PC30
PC28
PB11
PB13
PB24
VDDIOP1
PB30
PB31
PA1
U5
PB20
PB21
PB25
PB27
PA12
PA13
PA14
PA15
PA19
PA17
PA16
PA18
C7
A14
H4
D11
P2
U6
C8
BA1/A17
A19
H8
GND
P3
U7
C9
H9
GND
P4
U8
C10
C11
C12
C13
C14
C15
C16
C17
NANDOE
PC9
H10
H14
H15
H16
H17
J1
GND
P5
U9
VDDCORE
TCK
P6
U10
U11
U12
U13
U14
U15
U16
PC12
DDP
P7
NTRST
PB18
PC19
PC17
VDDIOM
P8
HDMB
NC
P9
P10
P11
P12
VDDIOP0
SHDN
J2
J3
PA3
14
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Table 4-2.
Pinout for 217-ball LFBGA Package (Continued)
Pin
D1
D2
D3
D4
Signal Name
Pin
Signal Name
Pin
Signal Name
PA7
Pin
Signal Name
D9
J4
PC16
P13
P14
P15
P16
U17
VDDIOP0
D2
J8
GND
PA9
RAS
D0
J9
GND
PA26
J10
GND
PA25
5. Power Considerations
5.1
Power Supplies
The AT91SAM9XE128/256/512 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and
1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is
selectable by software.
• VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
3.0V and 3.6V, 3V or 3.3V nominal.
• VDDIOP1 pin: Powers the Peripherals I/O lines involving the Image Sensor Interface; voltage
ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDPLL pins: Power the PLL cells and the main oscillator; voltage ranges from 1.65V and
1.95V, 1.8V nominal.
• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V,
3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and
their associated I/O lines in the multiplexing tables. These supplies enable the user to power the
device differently for interfacing with memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power
supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These
ground pins are respectively GNDBU, GNDPLL and GNDANA.
15
6254BS–ATARM–29-Apr-09
6. I/O Line Considerations
6.1
ERASE Pin
The pin ERASE is used to re-initialize the Flash content and the NVM bits. It integrates a perma-
nent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operations.
This pin is debounced on the RC oscillator or 32,768 Hz to improve the glitch tolerance. Mini-
mum debouncing time is 200 ms.
6.2
6.3
I/O Line Drive Levels
The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC3 are high-drive current capable.
Each of these I/O lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines.
Refer to the “DC Characteristics” section of the product datasheet.
Shutdown Logic Pins
The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is
no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1
MΩ. The resisitor value is calculated according to the regulator enable implementation and the
SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
7. Processor and Architecture
7.1
ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
• DSP Instruction Extensions
• 5-Stage Pipeline Architecture:
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
• 8 KB Data Cache, 16 KB Instruction Cache
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
16
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2
Bus Matrix
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal ROM boot, one for internal flash boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal ROM or internal Flash
– Selection is made by General purpose NVM bit sampled at reset
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
(ROM or Flash)
– Allows Handling of Dynamic Exception Vectors
7.2.1
Matrix Masters
The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can
perform an access concurrently with others, depending on whether the slave it accesses is
available.
17
6254BS–ATARM–29-Apr-09
Each Master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
List of Bus Matrix Masters
ARM926™ Instruction
ARM926 Data
Peripheral DMA Controller
USB Host Controller
Image Sensor Controller
Ethernet MAC
7.2.2
Matrix Slaves
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
Slave 0
List of Bus Matrix Slaves
Internal Flash
Slave 1
Internal SRAM
Internal ROM
Slave 2
USB Host User Interface
Slave 3
Slave 4
Slave 5
External Bus Interface
Reserved
Internal Peripherals
7.2.3
Masters to Slaves Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the internal peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.
AT91SAM9XE128/256/512 Masters to Slaves Access
Table 7-3.
Slave
Master
0 and 1
2
3
4
5
ARM926 Instruction Periphera DMA
ISI Controller
Ethernet MAC
USB Host
Controller
and Data
Controller
0
1
Internal Flash
X
X
X
X
X
–
–
X
X
–
–
X
–
–
X
–
–
X
X
–
–
X
–
–
Internal SRAM
Internal ROM
X
–
–
X
–
–
2
UHP User Interface
3
4
External Bus Interface
Reserved
X
–
Internal Peripherals
X
X
7.3
Peripheral DMA Controller
• Acting as one Matrix Master
18
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-four channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– Two for the Two Wire Interface
– One for Multimedia Card Interface
– One for Analog To Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
– TWI0 Transmit Channel
– TWI1 Transmit Channel
– DBGU Transmit Channel
– USART4 Transmit Channel
– USART3 Transmit Channel
– USART2 Transmit Channel
– USART1 Transmit Channel
– USART0 Transmit Channel
– SPI1 Transmit Channel
– SPI0 Transmit Channel
– SSC Transmit Channel
– TWI0 Receive Channel
– TWI1 Receive Channel
– DBGU Receive Channel
– USART4 Receive Channel
– USART3 Receive Channel
– USART2 Receive Channel
– USART1 Receive Channel
– USART0 Receive Channel
– ADC Receive Channel
– SPI1 Receive Channel
– SPI0 Receive Channel
– SSC Receive Channel
– MCI Transmit/Receive Channel
7.4
Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
19
6254BS–ATARM–29-Apr-09
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
20
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
8. Memories
Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping
Address Memory Space
Internal Memory Mapping
Notes : (1) Can be ROM or Flash
depending on GPNVM[3]
0x0000 0000
0x0000 0000
0x10 0000
0x10 8000
0x20 0000
0x28 0000
0x30 0000
0x30 8000
0x50 0000
0x50 4000
Boot Memory (1)
ROM
Internal Memories 256M Bytes
32K Bytes
0x0FFF FFFF
0x1000 0000
Reserved
EBI
Chip Select 0
256M Bytes
256M Bytes
Flash
128, 256 or 512K Bytes
32K Bytes
0x1FFF FFFF
0x2000 0000
Reserved
EBI
Chip Select 1/
SDRAMC
SRAM
0x2FFF FFFF
0x3000 0000
Reserved
UHP
EBI
Chip Select 2
16K Bytes
256M Bytes
256M Bytes
0x3FFF FFFF
0x4000 0000
Reserved
EBI
Chip Select 3/
NANDFlash
0x0FFF FFFF
0x4FFF FFFF
0x5000 0000
EBI
Chip Select 4/
Compact Flash
Slot 0
256M Bytes
256M Bytes
0x5FFF FFFF
0x6000 0000
EBI
Peripheral Mapping
Chip Select 5/
Compact Flash
Slot 1
0xF000 0000
0xFFFA 0000
System Controller Mapping
0x6FFF FFFF
0x7000 0000
Reserved
TCO, TC1, TC2
UDP
0xFFFF C000
EBI
Chip Select 6
16K Bytes
256M Bytes
256M Bytes
Reserved
ECC
0xFFFA 4000
0xFFFA 8000
0xFFFF E800
0xFFFF EA00
0xFFFF EC00
0xFFFF EE00
0x7FFF FFFF
0x8000 0000
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
512 Bytes
512 Bytes
512 Bytes
EBI
Chip Select 7
MCI
0xFFFA C000
SDRAMC
SMC
0x8FFF FFFF
0x9000 0000
TWI0
0xFFFB 0000
0xFFFB 4000
0xFFFB 8000
0xFFFB C000
0xFFFC 0000
0xFFFC 4000
0xFFFC 8000
USART0
USART1
USART2
SSC
MATRIX
CCFG
0xFFFF EF10
0xFFFF F000
512 Bytes
512 Bytes
AIC
0xFFFF F200
0xFFFF F400
0xFFFF F600
DBGU
PIOA
512 Bytes
512 Bytes
512 bytes
ISI
EMAC
1,518M Bytes
Undefined
(Abort)
SPI0
PIOB
PIOC
EEFC
0xFFFC C000
0xFFFF F800
0xFFFF FA00
0xFFFF FC00
0xFFFF FD00
SPI1
512 bytes
0xFFFD 0000
0xFFFD 4000
USART3
512 bytes
256 Bytes
USART4
PMC
0xFFFD 8000
0xFFFD C000
0xFFFE 0000
0xFFFE 4000
0xFFFF C000
TWI1
RSTC
16 Bytes
16 Bytes
0xFFFF FD10
0xFFFF FD20
SHDC
RTTC
PITC
TC3, TC4, TC5
16 Bytes
16 Bytes
0xFFFF FD30
0xFFFF FD40
ADC
0xEFFF FFFF
0xF000 0000
WDTC
GPBR
16 Bytes
16 Bytes
0xFFFF FD50
0xFFFF FD60
Reserved
SYSC
Internal Peripherals 256M Bytes
16K Bytes
Reserved
0xFFFF FFFF
0xFFFF FFFF
0xFFFF FFFF
21
6254BS–ATARM–29-Apr-09
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripher-
als and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap, refer to Table 8-3, “Internal Memory Mapping,” on page 26 for details.
A complete memory map is presented in Figure 8-1 on page 21.
8.1
Embedded Memories
8.1.1
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
ROM Topology
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 16 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 128 KB Embedded Flash
8.1.2
8.1.3
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 32 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 256 KB Embedded Flash
• 32 KB ROM
– Single Cycle Access at full matrix speed
• 32 KB Fast SRAM
– Single Cycle Access at full matrix speed
• 512 KB Embedded Flash
8.1.4
22
The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs.
Each of these two programs is stored at 16 KB Boundary and the program executed at address
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
zero depends on the combination of the TST pin and PA0 to PA2 pins. Figure 8-2 shows the con-
tents of the ROM and the program available at address zero.
Figure 8-2. ROM Boot Memory Map
0x0000 0000
0x0000 0000
0x0000 0000
SAM-BA
Program
SAM-BA
Program
FFPI
Program
FFPI
Program
0x0000 7FFF
0x0000 3FFF
0x0000 3FFF
ROM
TST=1
PA0=1
PA1=1
PA2=0
TST=0
8.1.4.1
Fast Flash Programming Interface
The Fast Flash Programming Interface programs the device through a serial JTAG interface or a
multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard
industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.
Table 8-1.
Signal Name
PGMEN0
Signal Description
PIO
PA0
Type
Input
Active Level
High
Comments
Must be connected to VDDIO
Must be connected to VDDIO
Must be connected to GND
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
PGMEN1
PA1
Input
High
PGMEN2
PA2
Input
Low
PGMNCMD
PGMRDY
PA4
Input
Low
PA5
Output
Input
High
PGMNOE
PA6
Low
PGMNVALID
PGMM[3:0]
PGMD[15:0]
PA7
Output
Input
Low
PA8..PA10
PA12..PA27
Input/Output
8.1.4.2
SAM-BA® Boot Assistant
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in
situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication through the DBGU or through the
USB Device Port.
23
6254BS–ATARM–29-Apr-09
• Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via
software auto-detection.
• Communication through the USB Device Port is depends on crystal selected:
– limited to an 18,432 Hz crystal if the internal RC oscillator is selected
– supports a wide range of crystals from 3 to 20 MHz if the 32,768 Hz crystal is
selected
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
8.1.5
Embedded Flash
The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes
directly connected to the 32-bit internal bus. Each page contains 128 words.
The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is
write-only as 128 32-bit words, and accessible all along the 1 MB address space, so that each
word can be written at its final address.
The Flash benefits from the integration of a power reset cell and from a brownout detector to
prevent code corruption during power supply changes, even in the worst conditions.
8.1.5.1
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked.
The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configu-
rable through its User Interface on the APB bus. It ensures the interface of the Flash block with
the 32-bit internal bus. Its 128-bit wide memory interface increases performance, four 32-bit data
are read during each access, this multiply the throughput by 4 in case of consecutive data.
It also manages the programming, erasing, locking and unlocking sequences of the Flash using
a full set of commands. One of the commands returns the embedded Flash descriptor definition
that informs the system about the Flash organization, thus making the software generic pro-
gramming of the access parameters of the Flash (number of wait states, timings, etc.)
8.1.5.2
Lock Regions
The memory plane of 128, 256 or 512 Kbytes is organized in 8, 16 or 32 locked regions of 32
pages each. Each lock region can be locked independently, so that the software protects the
first memory plane against erroneous programming:
If a locked-regions erase or program command occurs, the command is aborted and the EEFC
could trigger an interrupt.
The Lock bits are software programmable through the EEFC User Interface. The command “Set
Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
24
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Figure 8-3. Flash First Memory Plane Mapping
0x0020 0000
Locked Region 0
Page 0
Locked Regions Area
128, 256 or 512 Kbytes
256, 512 or
1024 Pages
Page 31
512 bytes
16 KBytes
Locked Region 7, 15 or 31
0x0021 FFFF
or 0x0023 FFFF
or 0x0027 FFFF
32 bits wide
8.1.5.3
GPNVM Bits
The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respec-
tively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User
Interface.
Table 8-2.
General-purpose Non volatile Memory Bits
Function
GPNVMBit[#]
0
1
2
3
Security Bit
Brownout Detector Enable
Brownout Detector Reset Enable
Boot Mode Select (BMS)
8.1.5.4
Security Bit
The AT91SAM9XE128/256/512 features a security bit, based on a specific GPNVM bit, GPN-
VMBit[0]. When the security is enabled, access to the Flash, either through the ICE interface or
through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of
the code programmed in the Flash.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full
Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are
permitted.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation.
25
6254BS–ATARM–29-Apr-09
8.1.5.5
Non-volatile Brownout Detector Control
Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a
power loss, the brownout detector operations remain in their state.
• GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the
BOD, clearing it disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables
the brownout detector by default.
• GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting
GPNVMBit[2] enables the brownout reset when a brownout is detected, clearing
GPNVMBit[2] disables the brownout reset. Asserting ERASE disables the brownout reset by
default.
8.1.6
Boot Strategies
Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the GPNVMBit[3] state at reset.
Table 8-3.
Internal Memory Mapping
REMAP = 0
REMAP = 1
SRAM
Address
GPNVMBit[3] clear
ROM
GPNVMBit[3] set
Flash
0x0000 0000
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. Refer to the section “AT91SAM9XE Bus
Matrix” in the product datasheet for more details.
When REMAP = 0, a non volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to
lay out to 0x0, at his convenience, the ROM or the Flash. Refer to the section “Enhanced
Embedded Flash Controller (EEFC)” in the product datasheet for more details.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in Figure 8-1 on page 21.
The AT91SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3]
at reset. The internal memory area mapped between address 0x0 and 0x0FFF FFFF is reserved
for this purpose.
If GPNVMBit[3] is set, the boot memory is the internal Flash memory
If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a
Flash erase, the boot memory is the internal ROM.
8.1.6.1
GPNVMBit[3] = 0, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device Port
26
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
8.1.6.2
GPNVMBit[3] = 1, Boot on Internal Flash
• Boot on slow clock (On-chip RC or 32,768 Hz)
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:
1. Program the PMC (main oscillator enable or bypass mode)
2. Program and start the PLL
3. Switch the main clock to the new value.
8.2
External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256 MB memory area assigned.
Refer to the memory map in Figure 8-1 on page 21.
8.2.1
External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– ECC Controller
• Additional logic for NANDFlash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64 MB linear)
• Up to 8 chip selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
8.2.2
Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
27
6254BS–ATARM–29-Apr-09
8.2.3
SDRAM Controller
• Supported devices:
– Standard and Low Power SDRAM (Mobile SDRAM)
• Numerous configurations supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
• Programming facilities
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
• Energy-saving capabilities
– Self-refresh, power down and deep power down modes supported
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
8.2.4
Error Corrected Code Controller
• Hardware error corrected code generation
– Detection and correction by software
• Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path
• Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes
specified by software
• Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data
path
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes
with 8-bit data path
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes
with 8-bit data path
Ω
28
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
9. System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a
set of registers for the chip configuration. The chip configuration registers configure the EBI chip
select assignment and voltage range for external memories.
The System Controller’s peripherals are all mapped within the highest 16 KB of address space,
between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All
the registers of the System Controller can be addressed from a single pointer by using the stan-
dard ARM instruction set, as the Load/Store instruction have an indexing mode of 4 KB.
Figure 9-1 on page 30 shows the System Controller block diagram.
Figure 8-1 on page 21 shows the mapping of the User Interfaces of the System Controller
peripherals.
29
6254BS–ATARM–29-Apr-09
9.1
System Controller Block Diagram
Figure 9-1. AT91SAM9XE128/256/512 System Controller Block Diagram
System Controller
VDDCORE Powered
irq0-irq2
fiq
nirq
nfiq
Advanced
Interrupt
periph_irq[2..24]
por_ntrst
Controller
efc2_irq
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
ntrst
ARM926EJ-S
int
proc_nreset
PCK
debug
MCK
Debug
Unit
dbgu_irq
dbgu_txd
periph_nreset
dbgu_rxd
MCK
debug
periph_nreset
Periodic
Interval
Timer
jtag_nreset
Boundary Scan
TAP Controller
pit_irq
SLCK
debug
Watchdog
Timer
wdt_irq
idle
MCK
proc_nreset
wdt_fault
WDRPROC
periph_nreset
gpnvm[3]
Bus Matrix
gpnvm[2]
bod_rst_en
cal
gpnvm[1]
rstc_irq
flash_wrdis
BOD
POR
VDDCORE
periph_nreset
proc_nreset
Reset
Controller
por_ntrst
jtag_nreset
security_bit(gpnvm0)
flash_poe
backup_nreset
VDDCORE
NRST
flash_poe
Embedded
Flash
flash_wrdis
cal
VDDBU
POR
VDDBU Powered
VDDBU
SLCK
SLCK
gpnvm[1..3]
rtt_irq
Real-Time
Timer
rtt_alarm
backup_nreset
SLCK
UHPCK
SHDN
WKUP
periph_clk[20]
Shutdown
Controller
USB Host
Port
RC
OSC
periph_nreset
periph_irq[20]
backup_nreset
rtt0_alarm
OSCSEL
SLOW
CLOCK
OSC
4 General-Purpose
Backup Registers
XIN32
XOUT32
SLCK
UDPCK
int
periph_clk[2..27]
pck[0-1]
XIN
periph_clk[10]
periph_nreset
periph_irq[10]
USB
Device
Port
MAINCK
MAIN
OSC
XOUT
PCK
Power
Management
Controller
UDPCK
PLLRCA
PLLA
PLLB
PLLACK
PLLBCK
UHPCK
MCK
pmc_irq
idle
periph_nreset
periph_clk[6..24]
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
periph_irq[2..4]
irq0-irq2
fiq
Embedded
Peripherals
PIO
Controllers
periph_irq[6..24]
PA0-PA31
PB0-PB31
PC0-PC31
dbgu_txd
in
out
enable
30
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
9.2
Reset Controller
• Based on two Power-on reset cells
– One on VDDBU and one on VDDCORE
• Status of the last reset
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
reset, user reset or watchdog reset
• Controls the internal resets and the NRST pin output
– Allows shaping a reset signal for the external devices
9.3
Brownout Detector and Power-on Reset
The AT91SAM9XE128/256/512 embeds one brownout detection circuit and power-on reset
cells. The power-on reset are supplied with and monitor VDDCORE and VDDBU.
Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption
during power-up or power-down sequences or if brownouts occur on the VDDCORE power
supply.
The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low
during power-up until VDDCORE goes over this voltage level. This signal goes to the reset con-
troller and allows a full re-initialization of the device.
The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed
trigger level. It secures system operations in the most difficult environments and prevents code
corruption in case of brownout on the VDDCORE.
When the brownout detector is enabled and VDDCORE decreases to a value below the trigger
level (Vbot-), the brownout output is immediately activated. For more details on Vbot, see the
table “Brownout Detector Characteristics” in the section “AT91SAM9XE128/256/512 Electrical
Characteristics” in the full datasheet.
When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + Vhyst), the reset
is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below
the threshold voltage for longer than about 1µs.
The VDDCORE threshold voltage has a hysteresis of about 50 mV typical, to ensure spike free
brownout detection. The typical value of the brownout detector threshold is 1.55V with an accu-
racy of 2% and is factory calibrated.
The brownout detector is low-power, as it consumes less than 12 µA static current. However, it
can be deactivated to save its static current. In this case, it consumes less than 1 µA. The deac-
tivation is configured through the GPNVMBit[1] of the Flash.
Additional information can be found in the “Electrical Characteristics” section of the product
datasheet.
9.4
Shutdown Controller
• Shutdown and Wake-Up logic
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
31
6254BS–ATARM–29-Apr-09
9.5
Clock Generator
• Embeds a low power 32,768 Hz slow clock oscillator and a low-power RC oscillator
selectable with OSCSEL signal
– Provides the permanent slow clock SLCK to the system
• Embeds the main oscillator
– Oscillator bypass feature
– Supports 3 to 20 MHz crystals
• Embeds 2 PLLs
– PLL A outputs 80 to 240 MHz clock
– PLL B outputs 70 MHz to 130 MHz clock
– Both integrate an input divider to increase output accuracy
– PLLB embeds its own filter
9.6
Power Management Controller
• Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– independent peripheral clocks, typically at the frequency of MCK
– 2 programmable clock outputs: PCK0, PCK1
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
9.7
Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Includes a 12-bit Interval Overlay Counter
• Real Time OS or Linux®/WindowsCE® compliant tick generator
9.8
9.9
Watchdog Timer
• 16-bit key-protected only-once-Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
Real-time Timer
• Real-time Timer with 32-bit free-running back-up counter
• Integrates a 16-bit programmable prescaler running on slow clock
• Alarm Register capable to generate a wake-up of the system through the Shutdown
Controller
32
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
9.10 General-purpose Back-up Registers
• Four 32-bit backup general-purpose registers
9.11 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• Three External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
• Protect Mode
– Easy debugging by preventing automatic operations when protect modeIs are
enabled
• Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.12 Debug Unit
• Composed of two functions
– Two-pin UART
– Debug Communication Channel (DCC) support
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
• Debug Communication Channel Support
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
33
6254BS–ATARM–29-Apr-09
9.13 Chip Identification
• Chip ID:
– 0x329AA3A0 for the SAM9XE512
– 0x329A93A0 for the SAM9XE256
– 0x329973A0 for the SAM9XE128
• JTAG ID: 05B1_C03F
• ARM926 TAP ID: 0x0792603F
34
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
10. Peripherals
10.1 User Interface
The Peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of
address space. A complete memory map is presented in Figure 8-1 on page 21.
10.2 Peripheral Identifier
The AT91SAM9XE128/256/512 embeds a wide range of peripherals. Table 10-1 defines the
Peripheral Identifiers of the AT91SAM9XE128/256/512. A peripheral identifier is required for the
control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the
peripheral clock with the Power Management Controller.
Table 10-1. AT91SAM9XE128/256/512 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
System Controller Interrupt
Parallel I/O Controller A
Parallel I/O Controller B
Parallel I/O Controller C
Analog-to-digital Converter
USART 0
FIQ
1
SYSC
PIOA
PIOB
PIOC
ADC
US0
US1
US2
MCI
UDP
TWI0
SPI0
SPI1
SSC
-
2
3
4
5
6
7
USART 1
8
USART 2
9
Multimedia Card Interface
USB Device Port
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Two Wire Interface 0
Serial Peripheral Interface 0
Serial Peripheral Interface1
Synchronous Serial Controller
Reserved
-
Reserved
TC0
TC1
TC2
UHP
EMAC
ISI
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
USB Host Port
Ethernet MAC
Image Sensor Interface
USART 3
US3
US4
TWI1
TC3
TC4
TC5
AIC
USART 4
Two Wire Interface 1
Timer/Counter 3
Timer/Counter 4
Timer/Counter 5
Advanced Interrupt Controller
Advanced Interrupt Controller
Advanced Interrupt Controller
IRQ0
IRQ1
IRQ2
AIC
AIC
35
6254BS–ATARM–29-Apr-09
Note:
Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no
effect. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC
clock is automatically stopped after each conversion.
10.2.1
Peripheral Interrupts and Clock Control
10.2.1.1
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
• Enhanced Embedded Flash Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.3 Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9XE128/256/512 features 3 PIO controllers, PIOA, PIOB, PIOC, which multiplex
the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and
“Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral function which are output only, might be duplicated within the both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corre-
sponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
36
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
10.3.1
PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A
Application Usage
Reset
State
Power
Supply
I/O Line
PA0
Peripheral A
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
RTS2
Peripheral B
MCDB0
Comments
Function
Comments
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
PA1
MCCDB
PA2
PA3
MCDB3
MCDB2
MCDB1
PA4
PA5
CTS2
PA6
MCDA0
MCCDA
MCCK
PA7
PA8
PA9
MCDA1
MCDA2
MCDA3
ETX0
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30(1)
PA31(1)
ETX2
ETX3
ETX1
ERX0
ERX1
ETXEN
ERXDV
ERXER
ETXCK
EMDC
EMDIO
ADTRG
TWD0
ETXER
ETX2
TWCK0
TCLK0
TIOA0
ETX3
ERX2
ERX3
ERXCK
ECRS
ECOL
RXD4
TXD4
TIOA1
TIOA2
SCK1
SCK2
SCK0
Note:
1. Not available in the 208-lead PQFP package.
37
6254BS–ATARM–29-Apr-09
10.3.2
PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B
Application Usage
Power Supply Function
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
I/O Line
PB0
Peripheral A
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
TXD0
Peripheral B Comments Reset State
Comments
TIOA3
TIOB3
TIOA4
TIOA5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PB1
PB2
PB3
PB4
PB5
RXD0
PB6
TXD1
TCLK1
TCLK2
PB7
RXD1
PB8
TXD2
PB9
RXD2
PB10
PB11
PB12(1)
PB13(1)
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
TXD3
ISI_D8
ISI_D9
ISI_D10
ISI_D11
RXD3
TWD1
TWCK1
DRXD
DTXD
TK0
TCLK3
TF0
TCLK4
TD0
TIOB4
RD0
TIOB5
RK0
ISI_D0
RF0
ISI_D1
DSR0
ISI_D2
DCD0
DTR0
ISI_D3
ISI_D4
RI0
ISI_D5
RTS0
ISI_D6
CTS0
ISI_D7
RTS1
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
CTS1
PCK0
PCK1
Note:
1. Not available in the 208-lead PQFP package.
38
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
10.3.3
PIO Controller C Multiplexing
Table 10-4. Multiplexing on PIO Controller C
PIO Controller C
Application Usage
I/O Line
PC0
Peripheral A
Peripheral B
SCK3
Comments
AD0
Reset State Power Supply Function
Comments
I/O
I/O
I/O
I/O
A23
A24
I/O
I/O
I/O
I/O
A25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
PC1
PCK0
AD1
PC2(1)
PC3(1)
PC4
PCK1
AD2
SPI1_NPCS3
SPI1_NPCS2
SPI1_NPCS1
CFCE1
AD3
A23
PC5
A24
PC6
TIOB2
TIOB1
NCS4/CFCS0
NCS5/CFCS1
A25/CFRNW
NCS2
IRQ0
PC7
CFCE2
PC8
RTS3
PC9
TIOB0
PC10
PC11
PC12(1)
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
CTS3
SPI0_NPCS1
NCS7
FIQ
NCS6
NCS3/NANDCS
NWAIT
D16
IRQ2
IRQ1
SPI0_NPCS2
SPI0_NPCS3
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
EF100
D17
D18
D19
D20
D21
D22
TCLK5
D23
D24
D25
D26
D27
D28
D29
D30
D31
Note:
1. Not available in the 208-lead PQFP package.
39
6254BS–ATARM–29-Apr-09
10.4 Embedded Peripherals
10.4.1
Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
10.4.2
10.4.3
Two-wire Interface
• Master, Multi-master and Slave modes supported
• General call supported in Slave mode
• Connection to PDC Channel
USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by 16 oversampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
40
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
10.4.4
Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
10.4.5
Timer Counter
• Six 16-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
10.4.6
Multimedia Card Interface
• One double-channel Multimedia Card Interface
• Compatibility with MultiMedia Card Specification Version 2.2
• Compatibility with SD Memory Card Specification Version 1.0
• Compatibility with SDIO Specification Version V1.0.
• Cards clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• MCI has two slot, each supporting
– One slot for one MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
• Support for stream, block and multi-block data read and write
41
6254BS–ATARM–29-Apr-09
10.4.7
USB Host Port
• Compliance with Open HCI Rev 1.0 Specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
• Root hub integrated with two downstream USB ports in the 217-LFBGA package
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Matrix
10.4.8
USB Device Port
• USB V2.0 full-speed compliant, 12 MBits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 2,688-byte dual-port RAM for endpoints
• Suspend/Resume logic
• Ping-pong mode (two memory banks) for isochronous and bulk endpoints
• Eight general-purpose endpoints
– Endpoint 0 and 3: 64 bytes, no ping-pong mode
– Endpoint 1, 2, 6, 7: 64 bytes, ping-pong mode
– Endpoint 4 and 5: 512 bytes, ping-pong mode
• Embedded pad pull-up
10.4.9
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 128-byte transmit and 128-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface control of alarm and update
time/calendar data in
10.4.10 Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats
42
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
• Preview scaler to generate smaller size image
10.4.11 Analog-to-digital Converter
• 4-channel ADC
• 10-bit 312K samples/sec. Successive Approximation Register ADC
• -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
• Individual enable and disable of each channel
• External voltage reference for better accuracy on low voltage inputs
• Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter
0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep
mode after conversions of all enabled channels
• Four analog inputs shared with digital signals
43
6254BS–ATARM–29-Apr-09
11. Package Drawings
Figure 11-1. 208-pin PQFP Package Drawing
44
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
Figure 11-2. 217-ball LFBGA Package Drawing
45
6254BS–ATARM–29-Apr-09
12. AT911SAM9XE128/256/512 Ordering Information
Table 12-1. AT91SAM9XE128/256/512 Ordering Information
Ordering Code
Package
PQFP208
BGA217
PQFP208
BGA217
PQFP208
BGA217
Package Type
Green
Temperature Operating Range
AT91SAM9XE128-QU
AT91SAM9XE128-CU
AT91SAM9XE256-QU
AT91SAM9XE256-CU
AT91SAM9XE512-QU
AT91SAM9XE512-CU
Industrial
-40°C to 85°C
Green
Green
Industrial
-40°C to 85°C
Green
Green
Industrial
-40°C to 85°C
Green
46
AT91SAM9XE128/256/512 Preliminary
6254BS–ATARM–29-Apr-09
AT91SAM9XE128/256/512 Preliminary
13. Revision History
Change
Request
Ref.
Doc.
Ref.
Comments
6254BS
Removed 6.8, Slow CLock Selection (is shown in 27.5 of the full datasheet)
Removed fomer Section 5.2 “Power Consumption”.
Removed Clock Generator block diagram from Section 9.5 “Clock Generator” (is shown in Figure 27.1 of
the full datasheet).
rfo
Removed PMC block diagram from Section 9.6 “Power Management Controller” (is shown in Figure 28.1
of the full datasheet).
“Features”,
5800
5846
5800
rfo
“Ethernet MAC 10/100 Base-T”, 128-byte FIFOs (typo corrected).
Debug Unit (DBGU), added, Mode for general purpose6-2-wire UART serial communication
Section 9.13 “Chip Identification”, SAM9XE512 chip ID is 0x329AA3A0.
Table 3-1, “Signal Description List,””, comment column updated in certain instances and “PIO Controller -
PIOA - PIOB - PIOC” , has a foot note added to its comments column. SHDWN is active Low.
Section 5.1 “Power Supplies”, added “Caution: VDDCORE and VDDIO constraints.......
Section 6. “I/O Line Considerations”, unneeded paragraphs removed.
“Features”, “Additional Embedded Memories”Fast Read Time: 45 ns
“Features”, “Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)”, added
Manchester Encoding/Decoding.
5930
rfo
Section 6.3 “Shutdown Logic Pins”, updated with external pull-up requirement.
First issue.
6254AS
47
6254BS–ATARM–29-Apr-09
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