AT93C66A-10SA-5.0C [ATMEL]
EEPROM, 256X16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8;
| 型号： | AT93C66A-10SA-5.0C |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 256X16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总13页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Medium-voltage and Standard-voltage Operation
– 5.0(VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• Three-wire Serial Interface
• Sequential Read Operation
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• 8-lead PDIP and 8-lead JEDEC SOIC Packages
Three-wire
Serial
Automotive
EEPROMs
Description
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable program-
mable read-only memory (EEPROM). The EEPROM is organized as 128/256 words of
16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits
each (when the ORG pin is tied to ground.) The device is optimized for use in many
automotive applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP and 8-lead JEDEC
SOIC packages.
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C56A
AT93C66A
The AT93C56A/66A is enabled through the Chip Select (CS) pin and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed, and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable state. When CS is brought high
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
Preliminary
The AT93C56A/66A is available in 4.5V to 5.5V and 2.7V to 5.5V versions.
Table 1. Pin Configurations
8-lead PDIP
Pin Name
CS
Function
Chip Select
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
DC
8-lead SOIC
Power Supply
Internal Organization
Don’t Connect
CS
1
2
3
4
8
7
6
5
VCC
SK
DI
DC
ORG
GND
DO
3403D–SEEPR–10/04
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
MEMORY ARRAY
ADDRESS
DECODER
256/512 x 8
OR
128/256 X 16
DATA
REGISTER
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Note:
When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground, the “x 8” organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the “x 16” organization is selected.
2
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
AT93C56A/66A [Preliminary]
Table 1. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 2. DC Characteristics
Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted)
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
5.5
2.0
2.0
10.0
30
Unit
V
Supply Voltage
Supply Voltage
VCC2
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
6.0
17
mA
mA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
3.0
3.0
IOL
Output Leakage
(1)
VIL1
Input Low Voltage
Input High Voltage
−0.6
0.8
CC + 1
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
V
(1)
VIH1
2.0
V
IOL = 2.1 mA
0.4
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
I
OH = −0.4 mA
2.4
Note:
1. VIL min and VIH max are reference only and are not tested.
3
3403D–SEEPR–10/04
Table 3. AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 125°C, VCC = As Specified, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
150
tDF
2.7V ≤ VCC ≤ 5.5V
0.1
1M
3
10
ms
tWP
Write Cycle Time
5.0V, 25°C
Endurance(1)
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
AT93C56A/66A [Preliminary]
Table 4. Instruction Set for the AT93C56A and AT93C66A
Address
Op
Data
Instruction
SB
Code
x 8
x 16
x 8
x 16
Comments
Reads data stored in memory, at
specified address
READ
1
10
A8 – A0
A7 − A0
Write enable must precede all
programming modes
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
1
11
01
A8 − A0
A8 − A0
A7 − A0
A7 − A0
Erases memory location An − A0
Writes memory location An − A0
WRITE
D7 − D0
D15 − D0
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
ERAL
1
00
10XXXXXXX
10XXXXXX
Writes all memory locations. Valid
only at VCC = 5.0V 10% and Disable
Register cleared.
WRAL
1
1
00
00
01XXXXXXX
00XXXXXXX
01XXXXXX
00XXXXXX
D7 − D0
D15 − D0
EWDS
Disables all programming instructions.
Note:
The Xs in the address field represent don’t care values and must be clocked.
Functional
Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instruction contains the Address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy sta-
tus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
5
3403D–SEEPR–10/04
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2. Synchronous Data Timing
1µs (1)
Note:
This is the minimum SK period.
Table 5. Organization Key for Timing Diagrams
AT93C56A (2K)
AT93C66A (4K)
I/O
AN
DN
x 8
x 16
x 8
x 16
A7
(1)
(2)
A8
D7
A7
A8
D7
D15
D15
Notes: 1. A8 is a don’t care value, but the extra clock is required.
2. A7 is a don’t care value, but the extra clock is required.
6
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
AT93C56A/66A [Preliminary]
Figure 3. READ Timing
tCS
High Impedance
Figure 4. EWEN Timing
tCS
CS
SK
...
DI
1
0
0
1
1
Figure 5. EWDS Timing
tCS
CS
SK
...
0
0
0
DI
1
0
7
3403D–SEEPR–10/04
Figure 6. WRITE Timing
tCS
CS
SK
...
...
DI
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
Figure 7. WRAL Timing
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
A0
DI
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
8
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
AT93C56A/66A [Preliminary]
Figure 9. ERAL Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
Valid only at VCC = 4.5V to 5.5V.
9
3403D–SEEPR–10/04
AT93C56A Ordering Information
Ordering Code
Package
Operation Range
AT93C56A-10PA-5.0C
AT93C56A-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT93C56A-10PA-2.7C
AT93C56A-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
10
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
AT93C56A/66A [Preliminary]
AT93C66A Ordering Information
Ordering Code
Package
Operation Range
AT93C66A-10PA-5.0C
AT93C66A-10SA-5.0C
8P3
8S1
Automotive
(−40°C to 125°C)
AT93C66A-10PA-2.7C
AT93C66A-10SA-2.7C
8P3
8S1
Automotive
(−40°C to 125°C)
Package Type
8P3
8S1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
−5.0
−2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
11
3403D–SEEPR–10/04
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
–
MAX
0.210
0.195
0.022
0.070
0.045
0.014
0.400
–
NOM
–
NOTE
SYMBOL
D1
A2 A
A
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
–
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.100 BSC
0.300 BSC
0.130
0.325
0.280
b
E1
e
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
AT93C56A/66A [Preliminary]
3403D–SEEPR–10/04
Atmel Corporation
Atmel Operations
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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Japan
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3403D–SEEPR–10/04
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