ATA5278 [ATMEL]
STAND-ALONE ANTENNA DRIVER; 独立的天线驱动器
| 型号： | ATA5278 |
| 厂家： | 
ATMEL |
| 描述： | STAND-ALONE ANTENNA DRIVER |
| 文件： | 总33页 (文件大小：487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• SPI for Microcontroller Connection with Up to 1 Mbit/s
• Internal Data Buffer for Timing-independent Data Transmission
• Programmable Driver Current Regulation
• One-chip Antenna Driver Stage for 1 A Peak Current
• LF Baud Rates Between 1 kbaud and 4 kbaud
• Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing
• Integrated Oscillator for Ceramic Resonators
• Power Supply Range from 7.5 V to 16 V Direct Battery Input
(Up to 28 V With Limited Function Range)
• Amplitude Shift Keying (ASK) Modulation
• Phase Shift Keying (PSK) Modulation
• Carrier Frequency Range from 100 kHz to 150 kHz
• Operational Temperature -40°C to +105°C
• EMI and ESD According to Automotive Requirements
Stand-alone
Antenna Driver
• Highly Integrated — Less External Components Required
ATA5278
Applications
• Hands-free Car Access (Passive Entry/Go)
• Tire Pressure Measurement
• Home Access Control
Preliminary
• Care Watch Systems
Benefits
• Diagnosis Function and Overtemperature Protection
• Load Dump Protection Up to 45 V for 12 V Boards
• Power-down Mode for Minimum Power Consumption
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a
transmitter for Passive Entry/Go (PEG) car applications and for other hands-free
access control applications.
It includes the full functionality of generating a magnetic LF field in conjunction with an
antenna coil to transmit data to a receiver in a key fob, card or transponder. A micro-
controller can access the chip via a bi-directional serial interface.
Rev. 4832A–RKE–10/04
Figure 1. Block Diagram
MODACTIVE
VL1 VL2 VL3
CINT
VBATT
VDD OSCI OSCO VIF NRES CLKO
Boost
converter
control
S_CS
S_CLK
S_DI
PGND1
PGND2
PGND3
5-V
regulator
Oscillator
Voltage
interface
S_DO
ATA5278
VDS
CBOOST
Control
and
status
register
HS driver
LS driver
DRV1
SPI
Driver control
logic
QSC
Current and
zero crossing
sensing
LF data buffer
VSHUNT
AGND
DGND SCANE TEST
Pin Configuration
Figure 2. Pinning QFN28
28 27 26 25 24 23 22
21 S_CLK
PGND1
PGND2
1
2
3
4
5
6
7
20
19
S_CS
OSCI
PGND3
VDS
ATA5278
18 OSCO
17
16
DRV1
VIF
CBOOST
QSC
CLKO
15 TEST
9 10 11 12 13 14
8
2
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Pin Description
Pin
Symbol
PGND1
PGND2
PGND3
VDS
Function
1
Boost transistor ground
2
Boost transistor ground
3
Boost transistor ground
4
Driver voltage supply input
5
DRV1
Antenna driver stage output
6
CBOOST
QSC
External bootstrap capacitor connection
QSC transistor-gate driver-stage output
Antenna current-shunt resistor connection
Analog ground (sensoric/antenna driver)
Digital ground (logic)
7
8
VSHUNT
AGND
DGND
CINT
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
External integrator-capacitor connection
Modulator status pin output
MODACTIVE
NRES
SCANE
TEST
Reset input (inverted)
For factory test purposes only (connect to ground)
For factory test purposes only (connect to ground)
Clock signal output
CLKO
VIF
Logic interface voltage supply
Oscillator output (for resonator/crystal connection)
OSCO
OSCI
Oscillator input (for external clock source or resonator/crystal connection)
Chip select for serial interface
S_CS
S_CLK
S_DI
Clock input for serial interface
Data input for serial interface
S_DO
VDD
Data output of serial interface
Internal 5 V stabilizing capacitor connection
Battery supply
VBATT
VL1
Coil connection for the boost converter low-side switch
Coil connection for the boost converter low-side switch
Coil connection for the boost converter low-side switch
VL2
VL3
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4832A–RKE–10/04
Functional Description
General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and
control logic with diagnosis circuitry. It is controllable by a serial programming interface
(SPI).
In combination with an LC antenna circuitry, the IC generates an electromagnetic LF
field. The carrier frequency for the antenna is generated by the oscillator and a pre-
scaler logic.
The LF field can be modulated to transmit data to a suitable receiver. Two modulation
modes are available: Amplitude Shift Keying (ASK) and 180° Phase Shift Keying (PSK).
The transmission data has to be stored in the internal data buffer.
The IC consists of two main functional blocks:
•
•
The SPI with the data buffer, the control registers and the oscillator
The driver stage with its control logic and the power supply stage
A boost converter is used to supply the driver half-bridge with a high voltage and a regu-
lated current even if the battery voltage is low. The antenna current is programmable in
16 steps to support a transmission with various field strengths.
The driver circuitry is protected against short-circuits and overload.
Operational States
After power-on-reset, the ATA5278 is in power-down mode. To achieve minimum power
consumption, only the internal 5-V supply and the control registers are active. The IC
can only be activated by the external control unit via the serial interface (i.e., the chip
select line is enabled).
Once activated, the chip keeps the oscillator active and waits for commands on the
serial bus. This state can be described as standby mode. Only upon an external reset or
on command followed by disabling the chip select line, the power-down mode is re-
invoked.
The modulator stage, together with the antenna driver and the power supply, is acti-
vated as soon as LF data is written into the buffer and remains in this state until all data
has been sent, a stop command has been given via the SPI or a fault occurred. The
data modulation is running independently of the SPI activity and can be monitored with
the MODACTIVE pin.
Power-down Mode
The ATA5278 should be kept in power-down mode as long as the LF channel is not
used, because not only is the current consumption minimal, but the internal logic is also
reset. The antenna driver stage is in high impedance mode. To power-up the chip, the
chip-select line (S_CS) has to be activated for an appropriate time. The SPI then starts
the internal oscillator which is necessary for proper operation. Only after a certain oscil-
lation build-up time, is full functionality available. The microcontroller can check out the
state of the IC with two state bits automatically returned by any SPI command.
4
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Figure 3. Power-up Timing
S_CS
OSCI/OSCO
QSC
Oscillation build-up
Steady oscillation
DRV1
Z
tstartup
tdeb
Legend: Z = high impedance
The startup time, tstartup, in Figure 3 depends on the clock source used in the application.
Typical oscillation build-up times are below 100 µs for ceramic and about 1 ms for crys-
tal resonators. When using an active clock source, the startup time can be neglected.
The internal logic debounces the first clock signals until it finally powers-up the IC for the
time tdeb. Note that during this time, the chip select signal S_CS has to be permanently
active.
The normal way to bring the chip back into power-down mode is to use an SPI com-
mand. Deactivating the chip-select line right after the power-down command, an internal
standby timer is started and will run for ttimeout = (2048/fOSCI). In this time, the antenna
driver stage is stopped to discharge any energies possibly remaining in the antenna
circuit. If the chip-select line is reactivated during this time, the sequence is interrupted
and the IC remains in standby mode. Otherwise, the power-down mode is engaged after
the timeout, the oscillator is stopped and the driver stages are switched to high imped-
ance. Figure 4 illustrates this behavior.
Figure 4. Power-down Timing
S_CS
S_CLK
S_DI
8 CLK
cmd 4
X
DRV1
OSC
Z
f = 8 MHz
ttimeout
Legend: X = do not care
Z = high impedance
Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278
stays operational (i.e., the oscillator keeps running, an eventually running LF data mod-
ulation is not interrupted). Here, only the SPI itself is disabled and the serial bus can be
used for other devices connected to it.
5
4832A–RKE–10/04
In case the microcontroller is not able to communicate properly with the ATA5278 or any
other disturbance has occurred, it can trigger a reset (like a power-on-reset, POR) in the
chip by pulling the NRES pin to ground, which will bring the logic back to the startup
state, i.e., all configurations are at default and the IC is in power-down mode.
Figure 5. External Reset
OSC
S_CS
f = 8 MHz
X
X
Int. state
NRES
POR
Power-down
tNRES
Oscillator
The ATA5278 is equipped with an internal oscillator circuitry that provides the system
clock signal needed for operation. It is intended to work with an externally applied pas-
sive reference device such as a ceramic resonator or a crystal. Active clock sources like
microcontrollers or crystal oscillators, however, can also be used. Figure 6 shows the
internal structure of the oscillator circuitry.
Figure 6. Internal Oscillator Circuitry
Enable signal
from SPI
S1
Pull-down
Clock signal
judging
To internal
logic
Cin = 12 pF typ.
Cout = 12 pF typ.
Rfb = 250 kΩ typ.
Rd = 420 Ω
OSCI
OSCO
6
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
The main element of this circuit is the parallel inverting stage which generates the clock
signal in conjunction with the external reference device. During power-down mode,
these inverters are shut down and the pull-down structure on the OSCI pin is active. As
soon as the SPI enables the oscillator, the pull-down is disabled and the inverters are
powered up. Now, the clock signal assessment stage monitors the signal on the OSCI
pin. As soon as the amplitude and the period reach acceptable values, one of the two
inverters (i.e., the drivers) is shut down in order to reduce power dissipation in the exter-
nal reference device. Figure 7 on page 7 illustrates the period assessment.
Figure 7. Oscillator Signal Assessment
Oscillator
enable signal
OSCO signal
Second inverter
enable signal
Clock signal for
internal logic
Clock signal for
internal logic
t > tLOW,max
t < tLOW,max
I/O Voltage Interface
All digital I/O pins, including the reset input pin NRES, are passed through the internal
voltage interface before they reach their concerning blocks. This interface prevents pos-
sible compensation currents, as the control logic of the ATA5278 is supplied by the
internal 5 V regulator. It is capable of handling I/O voltages between 3.15 V and 5.5 V,
determined by the voltage applied to the VIF pin.
The pins NRES and S_CS are additionally equipped with a pull-up and a pull-down
structure respectively in order to ensure a defined behavior of the ATA5278 in case of a
broken connection. If the NRES line is broken, the pull-up structure keeps the input in
passive state and normal operation is possible. A broken S_CS line will cause a perma-
nently disabled SPI and S_DO pin, so communication between the microcontroller and
other SPI bus members is still possible. For further details on the voltage interface,
please refer to the table “Electrical Characteristics” on page 26.
SPI
The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a
clock input (S_CLK) which supports frequencies up to 1 MHz, a chip select line (S_CS)
which enables the interface, a serial data input (S_DI) and a serial data output (S_DO).
The output pin is of a tristate type, which will be set to high-impedance state as soon as
the chip-select line is disabled. The interface is in slave mode configuration. This means
that an SPI master (e.g. a microcontroller) is required for communication with the
ATA5278, as the IC will neither start a communication by itself nor is it able to provide
the serial clock signal. Figure 8 on page 8 sketches the internal structure.
7
4832A–RKE–10/04
Figure 8. SPI Structure
Internal data bus
8
S_CLK
MSB
MSB
6
6
5
4
3
2
2
1
1
LSB
LSB
Output register
5
4
3
S_DI
Input register
tri
S_DO
S_CS
8
Control logic/internal data bus
Once enabled by the chip-select line, the data at the S_DI pin is shifted into the input
register with every rising edge of the input clock signal. At the pin S_DO, the actual data
of the LSB of the output register is available. The output register is shifted on every fall-
ing edge of the input clock signal. Two timing schemes for SPI data communication are
supported, which are shown in Figure 9.
8
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Figure 9. SPI Timing Diagram
tDO,enable
tS_CLK,per
tDO,disable
S_CS
S_CLK
S_DI
tDI,setup
tS_CLK,h
tS_CLK,l
tDO,delay
tDI,hold
X
X
Z
X
Z
LSB
Input bit 1
Input bit 2
MSB
MSB
X
S_DO
LSB
Output bit 1
Output bit 2
X
First Possible Serial Timing, S_CLK Polarity 0, Phase 0
tDO,enable
tS_CLK,per
tDO,disable
S_CS
S_CLK
S_DI
tDI,setup
tS_CLK,h
tS_CLK,l tDI,hold
tDO,delay
X
X
Z
X
Z
LSB
Input bit 1
Input bit 2
MSB
X
S_DO
X
LSB
Output bit 1
out
MSB
Second Possible Serial Timing, S_CLK Polarity 1, Phase 1
9
4832A–RKE–10/04
SPI Commands
The microcontroller can access the following functions of the ATA5278 via the SPI:
•
•
•
•
•
•
•
•
Read from/write to configuration register 1
Read from/write to configuration register 2
Read from the status register
Write LF transmission data to the buffer and start the transmission
Verify the state of the data buffer
Clear the fault memory
Stop the modulator
Enable the power-down mode
Table 1 lists all functions and their definitions.
Table 1. SPI Commands
No. I/O MSB
6
5
4
3
2
1
LSB Description
Check status of IC
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
I1
O1
0
SR
0
0
0
0
0
0
0
0
0
0
0
RTS
0
0
1
2
3
4
Reset fault memory
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
I1
O1
0
SR
0
0
0
0
1
0
0
0
0
0
0
RTS
1
0
Stop modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
I1
O1
0
SR
0
0
1
0
0
0
0
0
0
0
0
RTS
1
0
Enable power-down mode
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
0
SR
1
0
0
0
0
0
0
0
0
0
0
RTS
1
0
I1
Write configuration register 1
I1
O1
I2
0
SR
0
0
0
0
0
0
0
IC3
0
0
0
IC2
0
0
0
IC1
0
1
0
IC0
1
0
RTS
0
0
0
AP
0
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
5
6
7
8
O2
0
0
AP: 0 ASK modulation mode, 1 PSK modulation mode
Read configuration register 1
I1
O1
I2
0
SR
X
0
0
X
0
0
0
X
0
0
X
0
0
X
1
0
X
1
RTS
X
0
0
X
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC3..0: antenna coil current selector
O2
0
IC3
IC2
IC1
IC0
0
AP
AP: 0 ASK modulation mode, 1 PSK modulation mode
Write configuration register 2
I1
O1
I2
0
SR
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
BR1
0
0
0
0
PS
0
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
RTS
BR0
0
O2
0
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
Read configuration register 2
I1
O1
I2
0
SR
X
0
0
X
0
0
0
X
0
0
0
X
0
1
0
X
0
0
0
X
1
RTS
X
0
0
X
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
BR1..0: LF data baud rate selector
O2
0
BR1
BR0
PS
PS: 0 CLKO prescaler disabled, 1 prescaler enabled
10
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Table 1. SPI Commands (Continued)
No. I/O MSB
6
5
4
3
2
1
LSB Description
Read status register
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
IC: illegal command received
CH: overcurrent in antenna footpoint detected
OL: open load detected
SH: overcurrent to VBATT detected at driver output
SL: overcurrent to GND detected at driver output
OT: overtemperature detected
I1
O1
I2
0
SR
X
0
0
X
0
0
0
X
0
0
X
1
0
X
1
0
X
1
RTS
X
0
0
X
9
O2
0
IC
CH
OL
SH
SL
OT
I1
O1
I2
0
SR
X
0
0
X
0
0
X
0
0
X
0
0
X
0
0
X
1
RTS
X
0
0
X
Check free LF data buffer space
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
D6..0: free logical LF data bits in buffer
10
11
O2
0
D6
D5
D4
D3
D2
D1
D0
Write LF data to buffer and start modulator
SR: 0 system not ready, 1 system ready
RTS: 0 modulator not ready, 1 modulator ready
I1
O1
Ix
1
D6
0
HB6
B6
D5
0
HB5
B5
D4
0
HB4
B4
D3
0
HB3
B3
D2
0
HB2
B2
D1
RTS
HB1
B1
D0
0
SR
HB7
B7
HB0 D6..0: number of logical LF bits to be written into buffer
B0
Ox
HB7..0: LF half bits (2 for one logical bit)
B7..0: input bit from the previous controller data word
Command Description
Table 1 on page 10 summarizes the commands interpreted by the SPI control logic of
the ATA5278. Each command consists of one or more data words which the controller
has to transfer to the SPI of the ATA5278. An SPI data word is always eight bits in width
and has to be transferred starting with the least significant bit (LSB).
The following list contains detailed information on every command of the chip.
•
The main purpose of command 1 is to check the operational status of the chip. Only
if the System-Ready bit (SR) and the Ready-To-Send bit (RTS) have been received
as 1, the ATA5278 is fully functional. In special cases, only the SR bit will be
received as 1. This is when the LF data buffer is full or when the power stages have
been shut down due to a fault. This command can be used at any time to check the
status of the chip.
•
Command 2 is the first out of three special function commands. It is used to reset
the internal fault memory. Once a fault is detected by the internal diagnosis stage, it
is stored in the fault memory (i.e., the status register) and the power stages are shut
down to protect them from damage. In order to enable the chip again, this command
has to be sent to the IC.
•
•
Command 3 can be used to stop the LF data transmission immediately. Regularly,
the modulator stage works as long as new (i.e., unsent) LF data is in the data buffer.
When using this command, all data in the buffer will be deleted and the antenna
driver stage is switched to idle mode.
Command 4 has to be used to shut down the IC. In order to start the power-down
sequence properly, no further command must be transmitted to the chip and the
chip-select line (S_CS) has to be disabled afterwards.
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4832A–RKE–10/04
•
Command 5 is used to write configuration data into register 1, which is used for LF
data modulation control. All register access commands are of a 16-bit structure (i.e.,
two data words). The first data word defines the access itself (i.e., read or write, and
the register number). The second data word is the configuration data, which is to be
sent to the ATA5278. Note that in return for the second data word, the first input
data word is sent back to the controller. This can be used to validate the SPI
transmission. Register 1 contains the four-bit-wide antenna coil current selector
(IC3..IC0) and the modulation type selector bit (NASK_PSK). For further details,
please refer to the section “Current Adjustment” on page 19.
•
•
Command 6 can be used to validate a change in register 1 (i.e., a prior command 5
operation) or to check its actual state after a power-down period. Like all register
access commands, it consists of two data words. The return data in the second data
word has the same bit sequence as in command 5.
Command 7 writes configuration data to register 2, which handles timing relevant
setup information. Like all register access commands, it consists of two data words,
where the second one is the configuration data itself. Note that in return for the
second data word, the first input data word is sent back to the controller. This can be
used to validate the SPI transmission. Register 2 contains the two-bit-wide LF data
baud-rate selector (BR1..BR0) and the pin CLKO prescaler bit. For further details,
please refer to the sections “LF Data Modulation” on page 14 and “Clock Supply”.
•
•
Command 8 can be used to validate a change of register 2 (i.e., a prior command 7
operation) or to check its actual state after a power-down period. Like all register
access commands, it consists of two data words. The return data in the second data
word has the same bit sequence as in command 7.
The status register of the ATA5278 can be read out with command 9. As soon as
the internal diagnosis stage detects a fault, it is stored in the status register until a
fault reset command is given or a power-on-reset occurs. Note that the power
stages of the chip are disabled as long as a power stage fault (i.e., a short-circuit at
the driver stage output pin, open load, overcurrent at the current sense pin or over
temperature) is present in the status register. Like all register access commands, it
consists of two data words, where the return data in the second data word contains
the fault bits. For further details, please refer to the section “Fault Diagnosis” on
page 20.
•
•
Command 10 accesses a special register, where the actual amount of free logical
bits in the data buffer is stored. This value decreases with each logical bit that is
transferred to the buffer, and increases with each logical bit the modulator stage
fetches from the buffer in order to transmit it via the LF channel. It can be used to
determine the amount of data which can be transferred to the buffer or to determine
the actual modulation process. Like all register access commands, it consists of two
data words, where the second one contains the six-bit-wide value.
Command 11 is used to write LF data to the on-chip data buffer and to start the
modulator stage. This command is indicated by the most significant bit (MSB) of the
first data word from the controller, which is, in contrast to all other commands, 1. The
other seven bits of this word determine the amount of logical LF data to be written to
the buffer. This amount of data has then to be transferred from the controller to the
ATA5278. As one logical bit consists of two half bits, a maximum of four logical bits
can be transferred per one SPI data word. With the data buffer being able to store
up to 96 logical bits, command 11 may reach a maximum length of 25 SPI data
words (i.e., the first word with the amount of data, followed by up to 24 words with
the data itself). Note that the input data from the SPI input register is always read
out starting from the least significant bit (LSB), working towards the MSB. So if less
than four logical bits are transferred to the buffer, they have to be stored in the lower
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ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
area of the SPI data word (i.e., starting with the LSB). It is important that the number
of actually transferred LF data matches the amount given in the first word of this
command, because there are no consistency checks. This is even then the case if
the data buffer was already full at the beginning of the transmission, or got full
during the transmission of LF data, or if the driver stages are disabled due to a
present fault. Data which is transferred under such circumstances is not stored and
therefore lost.
The SPI control logic checks the incoming data for valid commands. If the first data word
transmitted by the microcontroller does not match any of the above listed functions, an
illegal command fault is detected and written into the fault register. It can be read out
with command 9, bit 5 (IC). Note that this fault does not cause a shut down of the power
stages.
LF Data Buffer
The ATA5278 features an 192-bit wide data storage intended to buffer LF data between
the microcontroller and the modulator stage. It can be filled with data via the SPI and
therefore at high speeds (i.e., up to 1 Mbit/s). The modulator stage then accesses this
buffer with the selected LF baud rate and controls the connected LF antenna accord-
ingly. Hence the controller can handle other tasks during the comparatively slow LF data
transmission.
The data buffer is structured as a First-In-First-Out (FIFO) system, as can be seen in
Figure 10.
Figure 10. Structure Of Internal Data Buffer
MSB
6
5
4
Upper
Lower
4-1
MUX
3
2
1
Bit 0
Bit 1
LSB
Bit 2
Bit 3
.
.
.
.
.
.
.
.
Data pointer
.
.
.
.
.
.
.
.
.
.
Bit 188
Bit 190
Bit 189
Bit 191
LF
modulator
stage
Upper
Lower
The buffer is structured into two parallel blocks with the same storage capacity. The rea-
son for this is that the LF data is handled as logical (e.g., Manchester coded) bits, where
each data is encoded by two so-called half bits. The minimum amount of data which can
be written to or read from the buffer is one logical bit, hence two half bits.
13
4832A–RKE–10/04
After activating the IC from power-down mode or any fault, the data pointer in Figure 10
on page 13 is at the lowest point of the buffer (i.e., bit 190/191). Any write operation will
store the data to the position the pointer is pointing at, and moves it upwards one posi-
tion. The data is always read from the lowest point of the buffer by the modulator stage.
Any read operation will cause the data in the buffer to drop down one position, including
the data pointer. Any further writes are ignored if the data pointer reaches the upper bor-
der of the buffer, and the LF modulator stage stops operation after the pointer has
reached the lower border.
LF Data Modulation
The LF modulator stage of the ATA5278 is fed with data from the LF data buffer. It is
started after a successfully received SPI command 11. Two half bits are loaded at a time
and brought sequentially to the driver control logic, starting with the half bit labeled lower
in Figure 10 on page 13. It is applied for half the period time selected by the LF baud
rate selector. Then the half bit labeled upper is applied for the same time. The driver
control stage generates a control signal for the power output stages according to the
input and the selected modulation mode. The IC has two modulation modes, ASK and
PSK. They are selected by the NASK_PSK bit (i.e., bit 0) in control register 1. In ASK
modulation mode (NASK_PSK = 0), the IC switches the carrier on and off depending on
the value of the half bit applied by the modulator stage, where 1 activates the carrier and
0 deactivates it. So if the carrier is to be activated for a certain time (i.e., continuous
wave), a corresponding amount of half bits have to be set to 1 in the LF data buffer. Fig-
ure 11 illustrates this behavior.
Figure 11. LF Data Modulation with ASK
Half bit
values
X
0
1
1
0
1
1
1
1
X
Driver control
input
Driver control
signal
Resulting
antenna
signal
MODACTIVE pin
tBitlength/2
tBitlength
Start of modulation
End of modulation
The LF data stream in Figure 11 has a length of four logical bits and therefore eight half
bits. To get this result, a hex value of 0F6h has to be written into the data buffer via the
SPI. The time value tBitrate is the period of one logical bit, which is defined by the
selected data baud rate in configuration register 2. Note that the MODACTIVE pin is
active even if the half bit at the modulator stage is '0'.
In PSK mode (NASK_PSK = 1), the phase of the carrier signal is shifted by 180° on any
change of the LF data in the buffer. Taking the same data sequence as in the previous
example, the diagram changes shown in Figure 12 on page 15.
14
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Figure 12. LF Data Modulation with PSK
Half bit
values
X
0
1
1
0
1
1
1
1
X
Driver control
input
Driver control
signal
Resulting
antenna
signal
MODACTIVE pin
tBitlength/2
tBitlength
Start of modulation
End of modulation
The carrier signal is now always on as long as the LF data is in the buffer. It is only at the
change of the LF data values that the phase of the antenna current is shifted by 180°.
For further details, please refer to the section “Driver Stage” on page 16.
An internal timer, derived from the system clock generates the modulation times for the
half bits applied to the driver stage. These times depend on the selected LF baud rate in
configuration register 2 (i.e., the bits BR0 and BR1). Table 2 lists the bit settings and
their corresponding timings.
Table 2. LF Baud Rate Time Values
Time for One
Half Bit
Time for One Logical
BR0 Bit
Setting
BR1 Bit
Setting
Selected
Baud Rate
Bit
tBitlength
t
Bitlength/2
512 µs
256 µs
160 µs
128 µs
0
1
0
1
0
0
1
1
1 kbaud
2 kbaud
3 kbaud
4 kbaud
1024 µs
512 µs
320 µs
256 µs
Note that due to synchronization issues, the time for which the LF field is really active in
ASK mode when transmitting one half bit might vary by ±8 µs. This is a non-accumulat-
ing effect, which means, the transmission time for the complete LF data stream may
also vary by ±8 µs, independent of the total amount of logical bits. The same is true for
the distance of two phase shifts when transmitting LF data in PSK mode.
If data rates above 2 kbauds are demanded or the PSK modulation mode is selected,
the use of an external antenna current loop switch is mandatory. This switch has to be
controlled in a defined way which is supported by the ATA5278. For further details on
this topic, please refer to the section “QSC Feature” on page 16.
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4832A–RKE–10/04
QSC Feature
The Quick Start Control (QSC) feature supports a short oscillation build up and decay
time during LF data modulation. An external high-voltage MOS transistor is used as a
switch to close and open the current loop of the antenna. By synchronizing this switch to
the zero-crossing events of the antenna current, very short build-up and decay times for
the LF field, and therefore high data rates can be achieved.
Figure 13. QSC Operation
Half-bit from
data buffer
Voltage at
QSC pin
Current
through
antenna
Modulation in ASK mode
Modulation in PSK mode
The gate of the external transistor is driven by the QSC pin of the ATA5278. The signal
provided here is suited to drive standard MOSFETs (i.e., no logic-level FETs). During
power-down mode or a fault shutdown, the external transistor is switched off. Otherwise,
this would lead to a conducting state as long as no data modulation takes place. For fur-
ther information on this pin, please refer to the table “Electrical Characteristics” on page
26.
Driver Stage
The driver stage of the ATA5278 consists of following blocks:
•
•
•
DMOS half-bridge antenna driver
Switched Mode Power Supply (SMPS) in boost configuration
Antenna current sensor for peak value and zero-crossing detection
All these blocks are controlled by the internal driver control logic. The antenna driver
stage itself is supplied by the boost converter output voltage, which is applied at the
VDS pin. It consists of two power NMOS transistors in half-bridge configuration. As the
high-side transistor requires a control voltage above the output voltage (i.e., a voltage
above the supply voltage VDS), a bootstrap configuration is implemented. This circuitry
requires an external capacitor of 10 nF to 22 nF, connected between the driver output
and the CBOOST pin. This capacitor is charged during the time when the low-side tran-
sistor is active. As soon as the low-side transistor is switched off and the high-side
transistor starts conducting, both the voltage at the DRV1 pin and the CBOOST pin
rises, but always with CBOOST being higher than DRV1 and hence being able to pro-
vide an appropriate control voltage for the transistor. Figure 14 on page 17 illustrates
this boot strapping configuration.
16
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Figure 14. Bootstrap Configuration Circuitry
CBOOST
Charge supply
voltage
VDS
HS transistor
High side driver
control signal
DRV1
LS transistor
Low side driver
control signal
AGND
The output signal of the antenna driver stage is of a square wave shape. The duty cycle
of this signal is dependant on the selected antenna current. For further details, please
refer to the section “Current Adjustment” on page 19.
The antenna driver stage and the boost converter are thermally monitored in order to
protect them from overheating, and the output pin DRV1 is short-circuit protected by
means of current limitation. For further details, please refer to the section “Fault Diagno-
sis” on page 20.
The current sensor system is equipped with a zero-crossing detector and a sample and
hold stage. The zero-crossing detector provides the synchronization signal for the driver
control logic, which then calculates the phase shift between the antenna driver output
signal and the current flowing through the antenna. Based on this phase information, the
sample and hold stage is controlled in order to sample the top point of the input signal,
hence the peak current value.
Current Regulation
A main feature of the ATA5278 is its ability to generate a stabilized magnetic field with a
connected LC antenna, mainly independent of the battery voltage and the frequency
mismatch between the driver output frequency and the antenna resonance frequency.
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4832A–RKE–10/04
Figure 15. Antenna Current Regulation Loop
VBAT
T
CINT
VSHUN
T
+
VDS
DRV1
Selected
current
Boost
converter
-
Integrator
LC-antenna
DMOS half
bridge
Current
sample
and
hold
The input signal for the regulation loop in Figure 15 is the selected antenna current,
which is defined in configuration register 1. An external shunt resistor of 1 Ω, which has
to be connected to the VSHUNT pin, is used to measure the current in the LC antenna.
As the peak voltage over this resistor is directly linked with the peak current in the
antenna and hence the magnetic field strength, this value can be seen as output. This
signal is sampled and held by an internal stage controlled by the control logic. The differ-
ence of the input signal and the sampled signal then controls an integrator. The
parameter of this stage can be influenced with an externally applied charging capacitor
connected to the CINT pin. The charging/discharging behavior of the integrator stage is
described in Figure 16.
Figure 16. Integrator Output Current on CINT Pin
30,0
20,0
10,0
0,0
-10,0
-20,0
-30,0
0,5
0,6
0,7
0,8
0,9
1,0
1,1
1,2
1,3
1,4
Voltage at VSHUNT pin (V)
As can be seen in Figure 17, a current is charged into, respectively discharged from the
external capacitor depending on the voltage at the VSHUNT pin. Note that the shown
values for VSHUNT are only valid if maximum antenna current (i.e., 1 Apeak when using
a shunt resistor of 1 Ω) is selected. When the input voltage reaches the desired value
(e.g., 1 V), no current is flowing through the CINT pin and the voltage over the capacitor
is not changing. This voltage influences the output voltage of the boost converter. Note
that the lower the voltage on the integration capacitor, the higher the output voltage of
the boost converter will be. The maximum output voltage is 40 V.
18
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Boost Converter
The ATA5278 provides the supply current for its driver stage by means of a Switch
Mode Power Supply (SMPS) in boost configuration. A low-side switch that charges the
inductor, and the therefore needed control circuitry is integrated. The other necessary
components such as the inductor, the free-wheeling diode and the charging capacitor
have to be applied externally. For further details, please refer to the section “Application
Hints” on page 22.
The SMPS control circuitry is in current-mode configuration. This means that the current
through the coil charging transistor (i.e., the current through the VL1..3 and the
PGND1..3 pins) is measured and compared to a reference current in each switching
period. Should the measured value exceed the reference value, the transistor is
switched off and the inductor then discharges its energy through the free-wheeling diode
to the charging capacitor. The reference current is generated from the voltage on the
CINT pin, hence the integrator output voltage.
Current Adjustment
The maximum reachable output current in the antenna circuit can be calculated as
follows:
VDRV
----------------------------
A
×
2
Iant,eff
=
π × Z
Here, VDRV is the maximum reachable driver voltage and Z the antenna’s impedance
(including the RDSon of the QSC MOSFET, the shunt resistor and the driver output resis-
tance). Note when calculating the amount of complex Z, that the antenna driver output
frequency (i.e., f = fOSC/64) has to be taken into account for the complex parts of the
impedance.
The antenna coil current can be adjusted in 16 steps by modifying the IC0..IC3 bits in
the configuration register 1. Dependent on the selected current, the duty cycle of the
antenna coil driver signal is adapted. This improves the possibility to use one and the
same antenna over the whole range of selectable output currents. Table 3 provides a list
of the current settings for all 16 steps.
Table 3. Current Settings
Step
1
Current [mA]
Imaximum/3.597
Imaximum/3.226
Imaximum/2.976
Imaximum/2.604
Imaximum/2.353
Imaximum/2.132
Imaximum/1.984
Imaximum/1.825
Imaximum/1.709
Imaximum/1.57
IC0
0
IC1
0
IC2
0
IC3
0
P/P ratio
1.25/6.75
1.25/6.75
1.25/6.75
1.25/6.75
1.75/6.25
1.750/6.25
1.75/6.25
1.75/6.25
2.5/5.5
2
1
0
0
0
3
0
1
0
0
4
1
1
0
0
5
0
0
1
0
6
1
0
1
0
7
0
1
1
0
8
1
1
1
0
9
0
0
0
1
10
11
12
13
1
0
0
1
2.5/5.5
Imaximum/1.456
Imaximum/1.361
Imaximum/1.256
0
1
0
1
2.5/5.5
1
1
0
1
2.5/5.5
0
0
1
1
4/4
Note:
1. Default
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4832A–RKE–10/04
Table 3. Current Settings (Continued)
Step
14
Current [mA]
Imaximum/1.163
Imaximum/1.081
Imaximum
IC0
1
IC1
0
IC2
1
IC3
1
P/P ratio
4/4
15
16(1)
0
1
1
1
4/4
1
1
1
1
4/4
Note:
1. Default
Fault Diagnosis
The IC contains several fault diagnosis systems to protect itself from destruction and to
provide diagnosis information. If a fault at the power stages is detected for a certain
debounce time, both the switch mode power supply and the antenna driver stage includ-
ing the external NMOS transistor (if present) are switched off and the corresponding
fault information is written into the status register. Also the LF data buffer is cleared. The
fault information can be read out with SPI command 9. In order to restart the operation
of the power stages, the status register has to be cleared by transmitting SPI command
2.
The following protection and diagnosis mechanisms are defined:
•
A temperature monitoring system detects critical junction temperatures. Once
detected, the debounce timer is started. If the temperature is still above the critical
limit after the debouncing time has passed, a fault shutdown is performed.
•
A short-circuit protection of the antenna driver output is realized by means of
internal shunt-voltage monitoring. Both the high-side and the low-side transistors
are equipped with a shunt resistor which provides information about the current
flowing through them. If the current through one of the transistors surpasses the
internally defined overcurrent level, a current limitation is invoked immediately and
the debounce timer is started. Should this condition persist for the whole
debouncing time, a fault shutdown is performed.
•
•
The current through the external high-voltage MOSFET is monitored in order to
detect short-circuits on the return line of the antenna. Like for the other faults, a
debounce timer is started as soon as an overcurrent situation is detected and a fault
shutdown is performed after this time has passed.
The signal at the VSHUNT pin is monitored while the driver stage is active in order
to detect a broken antenna connection (i.e., an open load failure). The monitor
searches for polarity changes in the signal and starts the fault debouncing timer if it
fails to find such changes. A fault shutdown is performed if this fault persists for the
whole debouncing time.
•
The input register of the SPI is scanned for illegal commands. Note that this kind of
fault will cause neither a shutdown of the power stages nor a clearing of the LF data
buffer. This diagnosis function is just to provide information about problems on the
SPI bus. Also, no debouncing time is applied for this fault.
Some faults, like open load or a short-circuit of the antenna output pin to ground, can
only be detected while the driver stage is active (i.e., in modulation mode). As the low-
side antenna driver transistor and the QSC transistor are also both active in standby
mode, faults concerning these devices are also monitored then. Only during power-
down, no fault monitoring is active.
Figure 17 on page 21 illustrates the fault shutdown timing sequence.
20
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Figure 17. Fault Shutdown Timing
t < tdeb,min
t > tdeb,min
Fault is latched in status
register afterwards
Internal fault
signal
1
X
1
1
1
Driver output
X
Z
0
0
0
stage
Boost converter
operation
QSC gate
signal
MODACTIVE pin
Note: Internal fault signal rises as soon as a fault (overtemperature, short-circuit or open load) is detected
Figure 17 shows the sequence of a fault shutdown during the antenna driver-stage
being active. If a critical condition persists for a time shorter than the debouncing time
(e.g., caused by interferences), no shutdown will occur.
The diagnosis bits are based in the status register and are encoded as shown in Table
4.
Table 4. Diagnosis Bits (Status Register)
Bit Position
Bit Name
Fault Type
0 (LSB)
OT
SL
SH
OL
CH
IC
-
Overtemperature detected
1
Antenna driver output pin has overload to Ground
Antenna driver output pin has overload to VDS (VBATT)
Open load detected (no oscillation at VSHUNT pin)
Overcurrent at antenna return line (QSC drain input) detected
Illegal command in the SPI input register found
Not defined
2
3
4
5
6
7 (MSB)
-
Not defined
CLKO Output Pin
The clock output pin CLKO of the ATA5278 can be used to supply an on-board micro-
controller with a clock signal (either 4 MHz or 8 MHz). This signal is not suited to supply
any device beyond the PCB boundaries.
The clock signal is directly derived from the clock source connected to the OSCI/OSCO
pins of the ATA5278 and is available as long as the ATA5278 is not in power-down
mode. The frequency can be selected with the prescaler (PS) bit in configuration
register 2, which is 0 for the full-clock rate (fCLKO = fOSCI) or 1 for the half clock-rate
(fCLKO = fOSCI/2).
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4832A–RKE–10/04
MODACTIVE Output Pin
Internal Supply Unit
The MODACTIVE pin of the ATA5278 can be used to directly control a timer/counter
stage of the microcontroller. The signal indicates LF data modulation activity. In con-
junction with suited timers and counting stages in the microcontroller, it enables the
software to precisely know the progress of the LF data transmission. For further details,
see Figure 11 on page 14 and Figure 12 on page 15 in the section “LF Data Modulation”
on page 14.
The ATA5278 is equipped with an internal supply unit that provides supply and refer-
ence voltages and currents. This unit is directly supplied by the VBATT pin. During
power-down mode, only the 5 V voltage regulator is active. This regulator requires an
external capacitor applied to the VDD pin because during operations high peak currents
may occur which must be buffered by the external device. For further details on this
issue, please refer to the section “Application Hints” on page 22.
The Power-On-Reset (POR) is also generated in the internal supply section. The VDD
voltage level is monitored permanently and compared with the regular output level. As
soon as the actual level is lower than the POR threshold, VPOR, a reset is triggered and
held for at least 30 µs.
Application Hints
The following Figure 18 sketches an application using the ATA5278.
Figure 18. Typical Application Circuit With ATA5278
C1
D1
VBATT
Microcontroller supply
(min. 7 V)
L1
VDD
X1
N_RES
P_IN1
P_IN2
C2
C3
MODACTIVE
CLKO
CINT
VBATT
VDD OSCI OSCO VIF NRES
D2
µC
S_CS
PGND1
PGND2
PGND3
Boost
converter
control
S_CS
S_CLK
S_DI
5-V
regulator
Oscillator
S_CLK
Voltage
interface
S_DI
S_DO
S_DO
VDS
ATA5278
C4
CBOOST
C5
Control
and
status
register
HS driver
LS driver
Ant
DRV1
SPI
Driver control
logic
LA
LF
receiver
QSC
Current and
zero crossing
sensing
LF data buffer
VSHUNT
Data
T1
HVNMOS
RShunt
AGND
DGND
TEST
GND
SCANE
The external components used in this schematic are listed in Table 5.
22
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Table 5. List of Used Components
Element
D1
Description
Standard diode
D2
Fast Shottky diode, VBR ≥ 50 V, ID ≥ 2.5 A
L1
Choke, ISAT ≥ 4 A, RESR ≤ 50 mΩ, L = 22 µH
Storage capacitor, C ≥ 220 µF, V ≥ 50 VDC
C1
C2
Ceramic (chip) capacitor, 33 nF ≤ C ≤ 100 nF
Ceramic (chip) capacitor, C ≥ 150 nF
C3
C4
Low ESR capacitor, 4,7 µF ≤ C ≤ 22 µF, V ≥ 50 VDC, RESR ≤ 0.8 Ω
Ceramic (chip) capacitor, C = 10 nF, V ≥ 50 VDC
Shunt resistor, R = 1 Ω (±1%), Pmax ≥ 0.6 W
C5
R1
XTAL
T1
Crystal or ceramic resonator, fRES = 8 MHz
High voltage N-channel MOSFET, VDS,max ≥ 600 VDC, CGS ≤ 2.5 nF
The following basic hints should be considered when designing an application with the
ATA5278.
•
Principally, the values for the external choke and the storage capacitor used in the
switched-mode power supply are not fixed, several performance factors, however,
are directly linked to these values. The parameters given in Table 5 on page 23 are
already optimized to the needs of the internal circuitry and the application.
•
The clock supply for the ATA5278 can be either an active clock source connected to
the OSCI pin, or a passive device like a crystal or a ceramic resonator. When using
a crystal, the prolonged oscillation build-up time (typically up to 1 ms) needs to be
considered. Full functionality of the chip will only be available after the oscillation
has reached a stable state.
•
The external HV-MOSFET for the QSC feature should have a low RDSon value, as
this value contributes to the quality factor of the LC antenna circuitry. Furthermore,
only standard gate input types may be used. TTL-compatible gate inputs might get
destroyed by the driving voltage of the QSC pin.
•
•
•
•
The VIF pin must be connected to the supply voltage with which the microcontroller
and possible other SPI bus members are driving the SPI bus.
The VDD pin is intended to be connected to a stabilizing capacitor only. It is not
suited for driving any loads.
The bootstrap capacitor C5 should not exceed values of 22 nF, as the internal
charging and clamping circuitry can handle only limited currents.
The value of the integrator capacitor C2 influences the current regulation speed.
The higher the capacitor, the slower the supply voltage for the antenna driver stage
and thus the current in the antenna is changed. For more details, please refer to the
section “Current Regulation” on page 17.
•
•
The power dissipation of the ATA5278 mainly depends on the supply voltage and
the selected antenna current. It is strongly recommended to solder the exposed die
pad to the PCB and to provide vias from the top layer (chip soldering side) to the
bottom layer, on which a copper plate, as big in size as possible, can dissipate the
heat. This plate can be connected to ground.
The ground pin of RSHUNT, C2, C4 and the AGND pin should be connected together
as closely as possible. The same is true for the connection between L1, D2 and
VL1..3 and the connection between D2, the positive pin of C4 and the VDS pin.
23
4832A–RKE–10/04
Note that in any case, the test pins SCANE and TEST must be connected to ground.
These pins are for factory test purposes only. For safety reasons, these pins are
equipped with a pull-down structure, so that the signals are still defined in case of bro-
ken connections. Connecting them to any signal other than ground will result in
malfunctions which can lead to the destruction of the chip or the external components.
The power dissipation of ATA5278 is, as already noted, dependant of the supply voltage
and the selected antenna current. Assuming an antenna with maximum allowable
impedance (i.e., the boost converter will generate 40 V output voltage) and the maxi-
mum available output current selected (i.e., step 16), the power dissipation of ATA5278
results as shown in Figure 19 on page 24
Figure 19. Power Dissipation versus Supply Voltage
8
7
6
Ta = 105°C
5
4
Ta = 85°C
3
2
1
7.5
8.5
9.5
10.5
11.5
12.5
13.5
14.5
15.5
16.5
Voltage at VBATT Pin [V]
The static thermal resistance of the chip, soldered onto a PCB can hardly be lowered
beneath 30 K/W. Hence, a static operation of ATA5278 is not possible in all cases. But
as most applications require only a temporary LF field, the dynamic thermal effects (i.e.,
the thermal capacitances) are important parameters that must be taken into account.
Figure 20 shows the maximum reachable LF carrier duration for an example PCB
design.
Figure 20. Operation Cycle Duration versus Power Dissipation
0.6
0.5
0.4
Ta = 85°C
0.3
0.2
Ta = 105°C
0.1
0.0
1.5
2.5
3.5
4.5
5.5
6.5
7.5
Power Dissipation [W]
24
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Note that the upper limit of this diagram (0.6 s) is not a design parameter but just for rep-
resentation reasons. The graphs continue to increase beyond the top line.
For this diagram, following parameters have been taken:
•
•
•
The total thermal resistance is 35 K/W, composed of 10 K/W for the junction-to-case
resistance Rth,jc, 5 K/W for the case-to-copper resistance Rth,cpcb and 20 K/W for the
copper-to-ambient resistance Rth,pcba
For the thermal capacitances, the package with an equivalent capacitance of
approximately 15 mJ/K and one PCB copper layer with dimensions of
50 mm × 50 mm × 0.05 mm, resulting in 0.426 J/K have been taken
The thermal shutdown of the chip triggers at 150°C junction temperature
The thermal resistance Rth,jc and the thermal capacitance of the package are fixed val-
ues, but everything behind (i.e., the thermal resistance between the solder pad and
ambient and the thermal capacitance of the copper layer(s)) depend only on the PCB
design.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VBATT
VINP
Value(1)
Unit
V
Supply voltage
-0.3 to +44
Input voltage (power pins)
Input voltage (interface pins)
Static power dissipation (Tamb = 85°C)
Emission
VSS -0.3 ≤ VIN ≤ 46,5
VSS -0.3 ≤ VIN ≤ 5.5
2
V
VIND
V
Ptot
W
EMI
250
V/M
1.5 (pins 7, 17, 26-28 versus other pins)
2 (all other pins versus each other)
2 (all pins versus GND)
Minimum ESD protection
(HBM, 100 pF through 1.5 kΩ)
ESD
kV
4 (pins 5, 6, 7, 8 vs. GND)
Junction temperature
TJ
150
°C
°C
Storage temperature range
Tstg
-55 to +150
Note:
1. Voltages are given relative to VSS.
Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance junction-case
RthJC
10
K/W
Thermal resistance junction-ambient
(QFN28)(1)
RthJA
32
K/W
Note:
1. To reach this value, special measures on the PCB have to be taken
Operating Range
Parameters
Symbol
VBATT
Value
Unit
V
Power supply range
Operating temperature range(1)
7.5 to 16.5
-40 to +105
Tamb
°C
Note:
1. For details, please refer to the section “Application Hints” on page 22 on maximum allowed operation temperature.
25
4832A–RKE–10/04
Electrical Characteristics
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Power Supply
VVBATT = 12 V
-40°C ≤ Tamb
105°C
Supply current in power-
down mode
1.1
≤
25
ISUP,0
30
40
µA
A
Supply current in
standby mode
1.2
1.3
1.4
VVBATT = 12 V
25
24
25
ISUP,1
7
9
mA
V
A
A
A
Internal 5 V supply
VVBATT = 12 V
VVBATT = 28 V
VVDD
IDISC1
IDISC2
4.7
5.5
Supply cap discharging
current
0.1
3.5
1.5
8
mA
mA
VVBATT = 40 V
Power-down mode
driver stage supply
current
V
VBATT = 12 V
1.5
4
4
IVDS,0
0.5
µA
A
A
VVDS = 40 V
V
V
VBATT = 12 V
VDS = 12 V
Standby mode driver
stage supply current
1.6
1.7
IVDS,1
1.2
2.2
0.5
mA
Pin 7 open
Voltage interface supply
current
VVIF = 5.5 V
All outputs open
17
24
IVIF
µA
V
A
A
VVDD
0.35
-
1.8
2
Power-on-reset level
VPOR
VVDD - 0.8
I/O Voltage Interface
Interface operation
voltage
2.1
17
VVIF
VINH
3.15
5.5
V
V
D
A
A
A
A
A
-40°C ≤ Tamb
+105°C
≤
≤
≤
13,
20-22
2.2
2.3
2.4
2.5
2.6
Input high level
0.6 × VVIF
-40°C ≤ Tamb
+105°C
13,
20-22
Input low level
VINL
0.3 × VVIF
V
-40°C ≤ Tamb
+105°C
13,
20-22
0,03 ×
VVIF
0,09 ×
VVIF
Input hysteresis
VIN,hyst
IIN,pd
IIN,pu
V
14,15,
20
Input pull-down current
Input pull-up current
V
IN = 5 V
15
60
-4
µA
µA
VVIF = 5 V
VIN = 0 V
13
-16
VVIF = 5 V
2.7
Input leakage current
VIN = 5 V
21, 22
IIN,leak
-300
+300
nA
A
VIN = 0 V
12,16,
23
2.8
2.9
Output source capability
Output sink capability
IOUT = -1 mA
VOUTH
VOUTL
0.8 × VVIF
V
V
A
A
12,16,
23
I
OUT = 1 mA
0.2 × VVIF
VS_CS = 0 V
VS_DO = 2.5 V
VVIF = 5 V
Output off-state leakage
current
2.10
23
IODIS
-300
135
+300
500
nA
ns
A
A
2.11 Reset prolonging time
13, 20
tRESHLD
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
26
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
Parameters
Test Conditions
NRES ≤ 0.3 × VVIF
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
2.12 Reset hold time
V
13
tNRES
10
ns
D
3
Antenna Driver Stage
VVDS = 12 V
CBOOST = 18 V
IDRV1 = -200 mA
Tamb = 105°C
High-side driver on
resistance
V
3.1
4, 5
RDS,HS
1.1
Ω
A
V
I
T
VDS = 12 V
Load = 200 mA
amb ≤ 105°C
Low-side driver on
resistance
3.2
3.3
3.4
5, 9
5
RDS,LS
1.1
150
400
Ω
ns
ns
A
A
A
Switching delay from LS
to HS
Trans. between
20% and 80%
tdLH
75
Trans. between
80% and 20%
VVDS
Switching delay from HS
to LS
5
tdHL
220
VVDS = 26 V
RLoad = 8.2 Ω
3.5
3.6
HS current limitation
LS current limitation
5
5
6
ILIM,HS
ILIM,LS
1.1
2.0
8
1.8
2.8
11
A
A
V
A
A
A
VVDS = 26 V
RLoad = 8.2 Ω
Bootstrap capacitor
clamping voltage
VVDS = 0 V
ICBOOST = 5 mA
VBSOUT,
max
3.7
4
Current Sensing
Zero crossing detection
threshold
Rising signal on
VSHUNT pin
4.1
8
8
VZC
8
55
mV
ns
A
A
Voltage jump on
VSHUNT pin from
-100 mV to
Zero crossing detection
delay
4.2
tdZC
300
+100 mV
Shunt resistor over-
current detection level
4.3
4.4
RSHUNT = 1 Ω
8
IQSCSC
IINTSRC
2.3
16
2.7
24
A
A
A
Nominal operation
integrator source current
VCINT = 1.9 V
11
µA
V
VSHUNT = 750 mV
VCINT = 1.9 V
VVSHUNT
1250 mV
Nominal operation
integrator sink current
4.5
=
11
IINTSINK
-24
-16
µA
A
Integrator upper voltage
limiting current (sink)
4.6
4.7
V
CINT = 2.8 V
11
11
ILIMUP
ILIMLOW
40
140
-30
µA
µA
A
A
Integrator lower voltage
limiting current (source)
VCINT = 1 V
-70
Integrator current de-
pendency from antenna
current
Current step 16,
4.8
4.9
VVSHUNT,p
1010 mV
=
11
11
dICINT
350
550
1000
nA
µA
A
A
Current step 1,
Integrator current for
antenna current step 1
VVSHUNT,p
278 mV
=
ISMPL1
-0.834
+0.834
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
27
4832A–RKE–10/04
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current step 2,
Integrator current for
antenna current step 2
4.10
VVSHUNT,p
310 mV
=
11
ISMPL2
-0.93
+0.93
µA
A
Current step 3,
Integrator current for
antenna current step 3
4.11
4.12
4.13
4.14
4.15
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
VVSHUNT,p
336 mV
=
11
11
11
11
11
11
11
11
11
11
11
11
11
11
ISMPL3
ISMPL4
ISMPL5
ISMPL6
ISMPL7
ISMPL8
ISMPL9
ISMPL10
ISMPL11
ISMPL12
ISMPL13
ISMPL14
ISMPL15
ISMPL16
-1.038
-1.152
-1.275
-1.407
-1.512
-1.644
-1.755
-1.911
-2.061
-2.205
-2.388
-2.58
+1.038
+1.152
+1.275
+1.407
+1.512
+1.644
+1.755
+1.911
+2.061
+2.205
+2.388
+2.58
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Current step 4,
Integrator current for
antenna current step 4
VVSHUNT,p
384 mV
=
Current step 5,
Integrator current for
antenna current step 5
VVSHUNT,p
425 mV
=
Current step 6,
Integrator current for
antenna current step 6
VVSHUNT,p
469 mV
=
Current step 7,
Integrator current for
antenna current step 7
VVSHUNT,p
504 mV
=
Current step 8,
Integrator current for
antenna current step 8
VVSHUNT,p
548 mV
=
Current step 9,
Integrator current for
antenna current step 9
VVSHUNT,p
585 mV
=
Current step 10,
Integrator current for
antenna current step 10
VVSHUNT,p
637 mV
=
Current step 11,
Integrator current for
antenna current step 11
VVSHUNT,p
687 mV
=
Current step 12,
Integrator current for
antenna current step 12
VVSHUNT,p
735 mV
=
Current step 13,
Integrator current for
antenna current step 13
VVSHUNT,p
796 mV
=
Current step 14,
Integrator current for
antenna current step 14
VVSHUNT,p
860 mV
=
Current step 15,
Integrator current for
antenna current step 15
VVSHUNT,p
925 mV
=
-2.775
-3
+2.775
+3
Current step 16,
Integrator current for
antenna current step 16
VVSHUNT,p
1000 mV
=
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
28
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
4.25
5
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Antenna current
regulation precision
-6
+6
%
C
Boost Converter
VVL1-3 = 18 V
-40°C ≤ Tamb
+105°C
Boost switch transistor
leakage current
5.1
≤
26-28
IVL,Leak
500
nA
A
Boost switch transistor
on resistance
IVL1..3 = 1 A
26-28,
1-3
5.2
5.3
5.4
RDSon
fBoost
tDCL
270
fOSCI/32
100
mΩ
Hz
ns
A
D
A
Tamb ≤ 105°C
Switching frequency
26-28
Minimum switch-on time
per period
fBoost = 250 kHz
fBoost = 250 kHz
26-28
0
3750
20
Maximum switch-on time
per period
5.5
5.6
5.7
5.8
5.9
5.10
26-28
26-28
26-28
11
tDCH
tf,Boost
3910
80
ns
ns
ns
V
A
A
A
A
A
A
Switching-on signal fall
time
I
VL1..3 = 0.4 A
Switching-off signal rise
time
IVL1.3 = 0.4 A
IVL = 1.25A
tr,Boost
20
80
Switch-off current
threshold
VCINT1
dICUT/dt
VVDSLIM
2.2
2.8
Switch-off current slope
compensation
VCINT = VCINT from
meas. 5.8
26-28
4
0.85
A/µs
V
Overvoltage shut-down
level
41
46.5
170
Overtemperature shut-
5.11 down level (junction
temperature)
Tamb = 105°C
26-28
TOTBoost
150
°C
B
6
QSC Transistor Driver
VVDS = 40 V
no DC load on pin
6.1
Maximum output voltage QSC,
-40°C ≤ Tamb
7
VQ,max
11
16
V
A
≤
+105°C
VVDS = 12 V
High-side output voltage
under load
IQSC = -40 mA
6.2
6.3
6.4
7
7
7
VQ,min
VQ,off
tr,QSC
8.5
0.2
100
12
0.5
200
V
V
A
A
A
-40°C ≤ Tamb
≤
+105°C
VVDS = 40 V
IQSC = 40 mA
-40°C ≤ Tamb
+105°C
Low-side output voltage
under load
≤
VVDS = 8 V
CLoad = 2 nF
10% to 90%
transition
Switch-on signal rise
time
ns
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
29
4832A–RKE–10/04
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
Parameters
Test Conditions
VDS = 8 V
Load = 2 nF
90% to 10%
transition
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
V
C
6.5
Switch-off signal fall time
7
tf,QSC
40
90
ns
A
V
VDS = 12 V
Bootstrap capacitor
charging voltage
VBSOUT,
min
6.6
ICBOOST
-10 mA
=
6
5.5
10
V
A
7
SPI
7.1
7.2
7.3
7.4
7.5
Clock frequency
21
21
21
22
22
fS_CLK
tS_CLK,h
tS_CLK,l
tDI,setup
tDI,hold
fOSCI/8
Hz
s
D
D
D
D
D
Clock signal high time
Clock signal low time
Input signal setup time
Input signal hold time
4/fOSCI
4/fOSCI
s
100
100
ns
ns
Output signal enable
time
7.6
7.7
23
tDO,enable
100
ns
D
Output signal disable
time
23
23
tDO,disable
tDO,delay
100
100
ns
ns
D
D
7.8
Output signal delay time
8
Oscillator
Ceramic
resonator, crystal
or external clock
source
8.1
Input frequency range
19
fOSCI
8
MHz
D
-40°C ≤ Tamb
+105°C
≤
8.2
8.3
8.4
8.5
8.6
Feedback resistance
Startup sink current
Operation sink current
Startup source current
18, 19
18
RFB,OSC
IL1
140
2.0
400
3.7
kΩ
mA
mA
mA
mA
A
A
A
A
A
VOSCI = 5 V
VOSCO = 4 V
VOSCI = 5 V
VOSCO = 3 V
18
IL2
1.2
1.8
VOSCI = 0 V
18
IH1
-3.7
-2.0
-2.0
-1.2
V
OSCO = 1.45 V
VOSCI = 0 V
VOSCO = 0.8 V
Operation source
current
18
IH2
Maximum OSCI low-
time for clock driver to
stay in operation mode
V
VVDD
OSCI < 0.5 ×
8.7
8.8
8.9
19
19
tLOW,max
IOSCI,PD
tdeb
660
250
ns
µA
s
D
A
D
Power-down
mode,
VOSCI = 5 V
Oscillator input pull-
down current
100
VOSCO = 5 V
Switch-on debounce
time after clock signal is
stable
192/fOSC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
30
ATA5278 [Preliminary]
4832A–RKE–10/04
ATA5278 [Preliminary]
Electrical Characteristics (Continued)
6.5 V < VBATT < 16.5 V, Tamb = 25°C unless otherwise specified. All values refer to GND pins. 6 V possible with approximately 30%
decrease of maximum output power, 28-V operation possible (jump start), but output current stability is not guaranteed in that case.
No.
9
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Fault Diagnosis
Debounce time for driver
stage faults
DRV1 short-circuit
to VBATT or GND
9.1
9.2
9.3
5
8
tdeb,min
tdeb,min
tdeb,min
120
µs
µs
µs
D
D
D
QSC input short-
circuit to VBATT
open load
Debounce time for
antenna return line faults
120
160
Debounce time for
overtemperature fault
20
32
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Soldering Recommendations
Parameters
Symbol
TD
Value
1 to 3
Unit
Maximum heating rate
Peak temperature in preheat zone
°C/s
°C
ZPH
100 to 140
Minimum 10
Maximum 75
Duration of time above melting point of solder
tMP
s
Peak reflow temperature
Maximum cooling rate
TPeak
220 to 225
2 to 4
°C
T
°C/s
rPeak
31
4832A–RKE–10/04
Ordering Information
Extended Type Number
Package
Remarks
ATA5278-PKQ
QFN28
7 mm × 7 mm, taped and reeled
Package Information
32
ATA5278 [Preliminary]
4832A–RKE–10/04
Atmel Corporation
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4832A–RKE–10/04
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