ATA5423-PLQW [ATMEL]
UHF ASK/FSK Transceiver; 超高频ASK / FSK收发器型号: | ATA5423-PLQW |
厂家: | ATMEL |
描述: | UHF ASK/FSK Transceiver |
文件: | 总100页 (文件大小:1501K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• Multi Channel Half-duplex Transceiver with Approximately ±2.5 MHz Programmable
Tuning Range
• High FSK Sensitivity: –106 dBm at 20 Kbit/s/–109.5 dBm at 2.4 Kbit/s (433.92 MHz)
• High ASK Sensitivity: –112.5 dBm at 10 Kbit/s/–116.5 dBm at 2.4 Kbit/s (433.92 MHz)
• Low Supply Current: 10.5 mA in RX and TX Mode (3V/TX with 5 dBm)
• Data Rate: 1 to 20 Kbit/s Manchester FSK, 1 to 10 Kbit/s Manchester ASK
• ASK/FSK Receiver Uses a Low-IF Architecture with High Selectivity, Blocking, and Low
Intermodulation (Typical Blocking 55 dB at ±750 kHz/61 dB at ±1.5 MHz and
70 dB at ±10 MHz, System I1dBCP = –30 dBm/System IIP3 = –20 dBm)
• 226 kHz/237 kHz IF Frequency with 30 dB Image Rejection and 170 kHz Usable IF
Bandwidth
UHF ASK/FSK
Transceiver
• Transmitter Uses Closed Loop Fractional-N Synthesizer for FSK Modulation with a
High PLL Bandwidth and an Excellent Isolation between PLL/VCO and PA
• Tolerances of XTAL Compensated by Fractional-N Synthesizer with 800 Hz RF
Resolution
ATA5423
ATA5425
ATA5428
ATA5429
• Integrated RX/TX-Switch, Single-ended RF Input and Output
• RSSI (Received Signal Strength Indicator)
• Communication to Microcontroller with SPI Interface Working at Maximum 500 kBit/s
• Configurable Self Polling and RX/TX Protocol Handling with FIFO-RAM Buffering of
Received and Transmitted Data
• 5 Push Button Inputs and One Wake-up Input are Active in Power-down Mode
• Integrated XTAL Capacitors
• PA Efficiency: up to 38% (433.92 MHz/10 dBm/3V)
• Low In-band Sensitivity Change of Typically ±1.8 dB within ±58 kHz Center Frequency
Change in the Complete Temperature and Supply Voltage Range
• Supply Voltage Switch, Supply Voltage Regulator, Reset Generation, Clock/Interrupt
Generation and Low Battery Indicator for Microcontroller
• Fully Integrated PLL with Low Phase Noise VCO, PLL Loop Filter and Full Support of
Multi-channel Operation with Arbitrary Channel Distance Due to Fractional-N
Synthesizer
• Sophisticated Threshold Control and Quasi-peak Detector Circuit in the Data Slicer
• Power Management via Different Operation Modes
• 315 MHz, 345 MHz, 433.92 MHz, 868.3 MHz and 915 MHz without External VCO and PLL
Components
• Inductive Supply with Voltage Regulator if Battery is Empty (AUX Mode)
• Efficient XTO Start-up Circuit (> –1.5 kΩ Worst Case Real Start-up Impedance)
• Changing of Modulation Type ASK/FSK and Data Rate without Component Changes
• Minimal External Circuitry Requirements for Complete System Solution
• Adjustable Output Power: 0 to 10 dBm Adjusted and Stabilized with External Resistor
• ESD Protection at all Pins (1.5 kV HBM, 200V MM, 1 kV FCDM)
• Supply Voltage Range: 2.4V to 3.6V or 4.4V to 6.6V
• Temperature Range: –40°C to +85°C
• Small 7 × 7 mm QFN48 Package
4841D–WIRE–10/07
Applications
Benefits
• Consumer Industrial Segment
• Access Control Systems
• Remote Control Systems
• Alarm and Telemetry Systems
• Energy Metering
• Home Automation
• Low System Cost Due to Very High System Integration Level
• Only One Crystal Needed in System
• Less Demanding Specification for the Microcontroller Due to Handling of Power-down Mode,
Delivering of Clock, Reset, Low Battery Indication and Complete Handling of Receive/Transmit
Protocol and Polling
• Single-ended Design with High Isolation of PLL/VCO from PA and the Power Supply Allows a
Loop Antenna in the Remote Control Unit to Surround the Whole Application
2
ATA5423/ATA5425/ATA5428/ATA5429
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
1. General Description
The ATA5423/25/28/29 is a highly integrated UHF ASK/FSK multi-channel half-duplex trans-
ceiver with low power consumption supplied in a small 7 x 7 mm QFN48 package. The receive
part is built as a fully integrated low-IF receiver, whereas direct PLL modulation with the frac-
tional-N synthesizer is used for FSK transmission and switching of the power amplifier for ASK
transmission.
The device supports data rates of 1 Kbit/s to 20 Kbit/s (FSK) and 1 Kbit/s to 10 Kbit/s (ASK) in
Manchester, Bi-phase and other codes in transparent mode. The ATA5428 can be used in the
431.5 MHz to 436.5 MHz and in the 862 MHz to 872 MHz bands, the ATA5423 in the 312.5 MHz
to 317.5 MHz band, the ATA5425 in the 342.5 MHz to 347.5 MHz band and the ATA5429 in the
912.5 MHz to 917.5 MHz band. The very high system integration level results in a small number
of external components needed.
Due to its blocking and selectivity performance, together with the additional 15 dB to 20 dB loss
and the narrow bandwidth of a typical loop antenna in a remote control unit, a bulky blocking
SAW is not needed in the remote control unit. Additionally, the building blocks needed for a typi-
cal remote control and access control system on both sides (the base and the mobile stations)
are fully integrated.
Its digital control logic with self-polling and protocol generation enables a fast challenge-
response system without using a high-performance microcontroller. Therefore, the
ATA5423/ATA5425/ATA5428/ATA5429 contains a FIFO buffer RAM and can compose and
receive the physical messages themselves. This provides more time for the microcontroller to
carry out other functions such as calculating crypto algorithms, composing the logical messages,
and controlling other devices. Therefore, a standard 4-/8-bit microcontroller without special
periphery and clocked with the CLK output of about 4.5 MHz is sufficient to control the communi-
cation link. This is especially valid for passive entry and access control systems, where within
less than 100 ms several challenge-response communications with arbitration of the communi-
cation partner have to be handled.
It is hence possible to design bi-directional remote control and access control systems with a
fast challenge-response crypto function, with the same PCB board size and with the same cur-
rent consumption as uni-directional remote control systems.
3
4841D–WIRE–10/07
Figure 1-1. System Block Diagram
ATA5423/ATA5425/ATA5428/ATA5429
RF Transceiver
Digital Control
Logic
Power
Supply
Antenna
ATmega
44/88/168
4 to 8
Matching/
RF Switch
Microcontroller
interface
XTO
Figure 1-2. Pinning QFN48
48 47 46 45 44 43 42 41 40 39 38 37
NC
NC
NC
1
2
3
4
5
6
7
8
9
36 RSSI
35 CS
34 DEM_OUT
33 SCK
RF_IN
NC
32 SDI_TMDI
433_N868
NC
31 SDO_TMDO
30 CLK
ATA5423/ATA5425
ATA5428/ATA5429
R_PWR
PWR_H
29 IRQ
28 N_RESET
27 VSINT
26 NC
RF_OUT 10
NC 11
NC 12
25 XTAL2
13 14 15 16 17 18 19 20 21 22 23 24
4
ATA5423/ATA5425/ATA5428/ATA5429
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Table 1-1.
Pin
1
Pin Description
Symbol
NC
Function
Not connected
2
NC
Not connected
3
NC
Not connected
4
RF_IN
NC
RF input
5
Not connected
6
433_N868
NC
Selects RF input/output frequency range
Not connected
7
8
R_PWR
PWR_H
RF_OUT
NC
Resistor to adjust output power
Pin to select output power
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
RF output
Not connected
NC
Not connected
NC
Not connected
NC
Not connected
NC
Not connected
AVCC
VS2
Blocking of the analog voltage supply
Power supply input for voltage range 4.4V to 6.6V
Power supply input for voltage range 2.4V to 3.6V
Auxiliary supply voltage input
Test input, at GND during operation
Blocking of the digital voltage supply
Output voltage power supply for external devices
Test input, at GND during operation
Reference crystal
VS1
VAUX
TEST1
DVCC
VSOUT
TEST2
XTAL1
XTAL2
NC
Reference crystal
Not connected
VSINT
N_RESET
IRQ
Microcontroller interface supply voltage
Output pin to reset a connected microcontroller
Interrupt request
CLK
Clock output to connect a microcontroller
Serial data out/transparent mode data out
Serial data in/transparent mode data in
Serial clock
SDO_TMDO
SDI_TMDI
SCK
DEM_OUT
CS
Demodulator open drain output signal
Chip select for serial interface
Output of the RSSI amplifier
Capacitor to adjust the lower cut-off frequency data filter
GND pin to decouple LNA in TX mode
Switch pin to decouple LNA in TX mode
Input to switch on the system (active high)
Key input 5 (can also be used to switch on the system (active low))
RSSI
CDEM
RX_TX2
RX_TX1
PWR_ON
T5
5
4841D–WIRE–10/07
Table 1-1.
Pin Description (Continued)
Pin
42
43
44
45
46
47
48
Symbol
Function
T4
Key input 4 (can also be used to switch on the system (active low))
Key input 3 (can also be used to switch on the system (active low))
Key input 2 (can also be used to switch on the system (active low))
Key input 1 (can also be used to switch on the system (active low))
Indicates RX operation mode
T3
T2
T1
RX_ACTIVE
NC
Not connected
NC
Not connected
GND
Ground/backplane
Figure 1-3. Block Diagram
AVCC
RX_ACTIVE
DVCC
433_N868
R_PWR
VS2
RF transceiver
Digital Control Logic
Power
Supply
Frontend Enable
PA_Enable (ASK)
TX_DATA (FSK)
VS1
VAUX
VSOUT
RF_OUT
PWR_H
PA
Switches
Regulators
Wake-up
Reset
RX/TX
Fractional-N
frequency
synthesizer
13
FREQ
PWR_ON
RX/TX
switch
FREF
RX_TX1
RX_TX2
T1
T2
T3
T4
T5
TX/RX - Data buffer
Control register
Status register
Polling circuit
Signal
Processing
(Mixer
IF-filter
Demod_Out
Bit-check logic
IF-amplifier
FSK/ASK
Demodulator,
Data filter
Data Slicer)
LNA
RF_IN
CDEM
RSSI
Reset
XTAL1
XTO
XTAL2
DEM_OUT
CLK
TEST1
TEST2
N_RESET
IRQ
Microcontroller
interface
CS
SCK
SPI
SDI_TMDI
SDO_TMDO
VSINT
GND
6
ATA5423/ATA5425/ATA5428/ATA5429
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2. Application Circuits
2.1
Typical Remote Control Unit Application with 1 Li Battery (3V)
Figure 2-1 shows a typical 433.92 MHz Remote Control Unit application with one battery. The
external components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 to C4 are 68 nF
voltage supply blocking capacitors. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed
capacitor used for the internal quasi-peak detector and for the high-pass frequency of the data
filter. C7 to C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching induc-
tor of about 5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor of 9 pF for
the crystal is integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm. The
loop antenna’s quality factor is somewhat reduced by this application due to the quality factor of
L2 and the RX/TX switch. On the other hand, this lower quality factor is necessary to have a
robust design with a bandwidth that is broad enough for production tolerances. Due to the sin-
gle-ended and ground-referenced design, the loop antenna can be a free-form wire around the
application as it is usually employed in remote control uni-directional systems. The
ATA5423/ATA5425/ATA5428/ATA5429 provides sufficient isolation and robust pulling behavior
of internal circuits from the supply voltage as well as an integrated VCO inductor to allow this.
Since the efficiency of a loop antenna is proportional to the square of the surrounded area it is
beneficial to have a large loop around the application board with a lower quality factor in order to
relax the tolerance specification of the RF components and to get a high antenna efficiency in
spite of their lower quality factor.
Figure 2-1. Typical Remote Control Unit Application, 433.92 MHz, 1 Li Battery (3V)
C11
L1
C7
C6
Sensor
CDEM
RSSI
CS
NC
NC
DEM_OUT
NC
RF_IN
NC
SCK
SDI_TMDI
SDO_TMDO
CLK
ATmega
48/88/168
C5
AVCC
433_N868
NC
ATA5423/ATA5425
ATA5428/ATA5429
R1
L2
R_PWR
PWR_H
RF_OUT
IRQ
N_RESET
VCC
VSINT
NC
VSS
NC
NC
C8
C9
C10
XTAL2
Loop antenna
C1
C4
13.25311 MHz
C3
C2
+ Lithium cell
7
4841D–WIRE–10/07
2.2
Typical Base-station Application (5V)
Figure 2.2 shows a typical 433.92 MHz VCC = 4.75V to 5.25V Base-station Application (5V). The
external components are 12 capacitors, 1 resistor, 4 inductors, a SAW filter, and a crystal. C1
and C3 to C4 are 68 nF voltage supply blocking capacitors. C2 and C12 are 2.2 µF supply block-
ing capacitors for the internal voltage regulators. C5 is a 10 nF supply blocking capacitor. C6 is a
15 nF fixed capacitor used for the internal quasi-peak detector and for the high-pass frequency
of the data filter. C7 to C11 are RF matching capacitors in the range of 1 pF to 33 pF. L2 to L4 are
matching inductors of about 5.6 nH to 56 nH. A load capacitor for the crystal of 9 pF is inte-
grated. R1 is typically 22 kΩ and sets the output power at RF_OUT to about 10 dBm. Since a
quarter wave or PCB antenna, which has high efficiency and wide band operation, is typically
used here, it is recommended to use a SAW filter to achieve high sensitivity in case of powerful
out-of-band blockers. L1, C9 and C10 together form a low-pass filter, which is needed to filter out
the harmonics in the transmitted signal to meet regulations. An internally regulated voltage at pin
VSOUT can be used in case the microcontroller only supports 3.3V operation, a blocking capac-
itor with a value of C12 = 2.2 µF has to be connected to VSOUT in any case.
Figure 2-2. Typical Base-station Application (5V), 433.92 MHz
C11
L4
L3
C7
C6
SAW-Filter
Sensor
CDEM
RSSI
CS
NC
NC
DEM_OUT
NC
RF_IN
NC
SCK
SDI_TMDI
SDO_TMDO
CLK
ATmega
48/88/168
C5
AVCC
433_N868
NC
ATA5423/ATA5425
ATA5428/ATA5429
R1
L2
R_PWR
PWR_H
RF_OUT
IRQ
N_RESET
VCC
VSINT
NC
VSS
50Ω
connector
NC
NC
C8
C9
L1
C10
XTAL2
RFOUT
C12
13.25311 MHz
C1 C2
C4
C3
V
= 4.75V to 5.25V
CC
8
ATA5423/ATA5425/ATA5428/ATA5429
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
2.3
Typical Remote Control Unit Application, 2 Li Batteries (6V)
Figure 2-3 shows a typical 433.92 MHz 2 Li battery Remote Control Unit application. The exter-
nal components are 11 capacitors, 1 resistor, 2 inductors and a crystal. C1 and C4 are 68 nF
voltage supply blocking capacitors. C2 and C3 are 2.2 µF supply blocking capacitors for the inter-
nal voltage regulators. C5 is a 10 nF supply blocking capacitor. C6 is a 15 nF fixed capacitor
used for the internal quasi-peak detector and for the high-pass frequency of the data filter. C7 to
C11 are RF matching capacitors in the range of 1 pF to 33 pF. L1 is a matching inductor of about
5.6 nH to 56 nH. L2 is a feed inductor of about 120 nH. A load capacitor for the crystal of 9 pF is
integrated. R1 is typically 22 kΩ and sets the output power to about 5.5 dBm.
Figure 2-3. Typical Remote Control Unit Application, 433.92 MHz, 2 Li Batteries (6V)
C11
L1
C7
C6
Sensor
CDEM
RSSI
CS
NC
NC
DEM_OUT
NC
RF_IN
NC
SCK
SDI_TMDI
SDO_TMDO
CLK
ATmega
48/88/168
C5
AVCC
433_N868
NC
ATA5423/ATA5425
ATA5428/ATA5429
R1
L2
R_PWR
PWR_H
RF_OUT
IRQ
N_RESET
VCC
VSINT
NC
VSS
NC
NC
C8
C9
C10
XTAL2
Loop antenna
C1
C2
C4
13.25311 MHz
C3
+ Lithium cell
+ Lithium cell
9
4841D–WIRE–10/07
3. RF Transceiver
As seen in Figure 1-3 on page 6, the RF transceiver consists of an LNA (Low-noise Amplifier),
PA (Power Amplifier), RX/TX switch, fractional-N frequency synthesizer and the signal process-
ing part with mixer, IF filter, IF amplifier with analog RSSI, FSK/ASK demodulator, data filter, and
data slicer.
In receive mode the LNA pre-amplifies the received signal which is converted down to 226 kHz
(ATA5423/ATA5428) and 235 kHz (ATA5425/ATA5429), filtered and amplified before it is fed
into an FSK/ASK demodulator, data filter, and data slicer. The RSSI (Received Signal Strength
Indicator) signal and the raw digital output signal of the demodulator are available at the pins
RSSI and DEM_OUT. The demodulated data signal Demod_Out is fed to the digital control logic
where it is evaluated and buffered as described in the section “Digital Control Logic” .
In transmit mode, the fractional-N frequency synthesizer generates the TX frequency which is
fed to the PA. In ASK mode the PA is modulated by the signal PA_Enable. In FSK mode the PA
is enabled and the signal TX_DATA (FSK) modulates the fractional-N frequency synthesizer.
The frequency deviation is digitally controlled and internally fixed to about ±16 kHz (see Table
4-1 on page 28 for exact values). The transmit data can also be buffered as described in the
section “Digital Control Logic” . A lock detector within the synthesizer ensures that the transmis-
sion will start only if the synthesizer is locked.
The RX/TX switch can be used to combine the LNA input and the PA output to a single antenna
with a minimum of losses.
Transparent modes without buffering of RX and TX data are also available to allow protocols
and coding schemes other than the internally supported Manchester encoding.
3.1
Low-IF Receiver
The receive path consists of a fully integrated low-IF receiver. It fulfills the sensitivity, blocking,
selectivity, supply voltage and supply current specification needed to manufacture, for example,
an automotive remote control unit without the use of SAW blocking filter (see Figure 2-1 on page
7). In a Base-station Application (5V) the receiver can be used with an additional blocking SAW
front-end filter as shown in Figure 2.2 on page 8.
At 433.92 MHz the receiver has a typical system noise figure of 7.0 dB, a system I1dBCP of
-30 dBm and a system IIP3 of –20 dBm. There is no AGC or switching of the LNA needed; thus,
a better blocking performance is achieved. This receiver uses an IF (Intermediate Frequency) of
226 kHz, the typical image rejection is 30 dB and the typical 3 dB IF filter bandwidth is 185 kHz
(fIF = 226 kHz ±92.5 kHz, flo_IF = 133.5 kHz and fhi_IF = 318.5 kHz). The demodulator needs a
signal to Gaussian noise ratio of 8 dB for 20 Kbit/s Manchester with ±16 kHz frequency deviation
in FSK mode; thus, the resulting sensitivity at 433.92 MHz is typically –106 dBm at 20 Kbit/s
Manchester.
Due to the low phase noise and spurious emissions of the synthesizer in receive mode(1)
together with the eighth order integrated IF filter, the receiver has a better selectivity and block-
ing performance than more complex double superhet receivers but without external components
and without numerous spurious receiving frequencies.
10
ATA5423/ATA5425/ATA5428/ATA5429
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A low-IF architecture is also less sensitive to second-order intermodulation (IIP2) than direct
conversion receivers, where every pulse or AM-modulated signal (especially the signals from
TDMA systems like GSM) demodulates to the receiving signal band at second-order
non-linearities.
Note:
–120 dBC/Hz at ±1 MHz and –75 dBC at ±FREF at 433.92 MHz
3.2
Input Matching at RF_IN
The measured input impedances as well as the values of a parallel equivalent circuit of these
impedances can be seen in Table 3-1. The highest sensitivity is achieved with power matching
of these impedances to the source impedance of 50Ω
Table 3-1.
Measured Input Impedances of the RF_IN Pin
fRF/MHz
Z(RF_IN)
(44-j233)Ω
(40-j211)Ω
(32-j169)Ω
(21-j78)Ω
(18-j70)Ω
Rp//Cp
315
345
1278Ω//2.1 pF
1153Ω//2.1 pF
925Ω//2.1 pF
311Ω//2.2 pF
290Ω//2.3 pF
433.92
868.3
915
The matching of the LNA Input to 50Ωwas done with the circuit shown in Figure 3-1 and with the
values given in Table 3-2 on page 12. The reflection coefficients were always ≤10 dB. Note that
value changes of C1 and L1 may be necessary to compensate for individual board layouts. The
measured typical FSK and ASK Manchester code sensitivities with a Bit Error Rate (BER) of 10-3
are shown in Table 3-3 and Table 3-4 on page 12. These measurements were done with induc-
tors having a quality factor according to Table 3-2, resulting in estimated matching losses of
0.8 dB at 315 MHz, 0.8 dB at 345 MHz, 0.7 dB at 433.92 MHz, 0.7 dB at 868.3 MHz and 0.7 at
915 MHz. These losses can be estimated when calculating the parallel equivalent resistance of
the inductor with Rloss = 2 × π × f × L × QL and the matching loss with 10 log(1 + Rp/Rloss).
With an ideal inductor, for example, the sensitivity at 433.92 MHz/FSK/20 Kbit/s/
±16 kHz/Manchester can be improved from –106 dBm to –106.7 dBm. The sensitivity depends
on the control logic which examines the incoming data stream. The examination limits must be
programmed in control registers 5 and 6. The measurements in Table 3-3 and Table 3-4 on
page 12 are based on the values of registers 5 and 6 according to Table 9-3 on page 61.
Figure 3-1. Input Matching to 50Ω
ATA5423/ATA5425
C1
ATA5428/ATA5429
4
RF_IN
L1
11
4841D–WIRE–10/07
Table 3-2.
Input Matching to 50Ω
C1/pF
fRF/MHz
L1/nH
47
QL1
66
67
70
50
52
315
345
2.4
1.8
1.8
1.2
1.3
43
433.92
868.3
915
27
6.8
5.6
Table 3-3.
Measured Sensitivity FSK, ±16 kHz, Manchester, dBm, BER = 10–3
RF
Frequency
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.4 Kbit/s
BR_Range_1
5.0 Kbit/s
BR_Range_2
10 Kbit/s
BR_Range_3
20 Kbit/s
315 MHz
345 MHz
–110.0 dBm
–109.5 dBm
–109.0 dBm
–106.0 dBm
–105.5 dBm
–110.5 dBm
–110.5 dBm
–109.5 dBm
–106.5 dBm
–106.0 dBm
–109.0 dBm
–109.0 dBm
–108.0 dBm
–105.5 dBm
–105.0 dBm
–108.0 dBm
–107.5 dBm
–107.0 dBm
–104.0 dBm
–103.5 dBm
–107.0 dBm
–107.0 dBm
–106.0 dBm
–103.5 dBm
–103.0 dBm
433.92 MHz
868.3 MHz
915 MHz
Table 3-4.
Measured Sensitivity 100% ASK, Manchester, dBm, BER = 10–3
BR_Range_0
1.0 Kbit/s
BR_Range_0
2.4 Kbit/s
BR_Range_1
5.0 Kbit/s
BR_Range_2
10 Kbit/s
RF Frequency
315 MHz
–117.0 dBm
–117.0 dBm
–116.0 dBm
–112.5 dBm
–112.5 dBm
–117.5 dBm
–117.5 dBm
–116.5 dBm
–113.0 dBm
–113.0 dBm
–115.0 dBm
–115.0 dBm
–114.0 dBm
–111.5 dBm
–111.0 dBm
–113.5 dBm
–113.0 dBm
–112.5 dBm
–109.5 dBm
–109.0 dBm
345 MHz
433.92 MHz
868.3 MHz
915 MHz
3.3
Sensitivity versus Supply Voltage, Temperature and Frequency Offset
To calculate the behavior of a transmission system it is important to know the reduction of the
sensitivity due to several influences. The most important are frequency offset due to crystal
oscillator (XTO) and crystal frequency (XTAL) errors, temperature and supply voltage depen-
dency of the noise figure and IF filter bandwidth of the receiver. Figure 3-2 shows the typical
sensitivity at 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus the frequency offset
between transmitter and receiver with Tamb = –40°C, +25°C and +105°C and supply voltage
VS1 = VS2 = 2.4V, 3.0V and 3.6V.
12
ATA5423/ATA5425/ATA5428/ATA5429
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ATA5423/ATA5425/ATA5428/ATA5429
Figure 3-2. Measured Sensitivity 433.92 MHz/FSK/20 Kbit/s/±16 kHz/Manchester versus
Frequency Offset, Temperature and Supply Voltage
-110
-109
-108
-107
-106
-105
-104
-103
-102
-101
-100
-99
V
V
V
V
V
V
V
V
V
= 2.4V T
= 3.0V T
= 3.6V T
= 2.4V T
= 3.0V T
= 3.6V T
= 2.4V T
= 3.0V T
= 3.6V T
= -40°C
S
S
S
S
S
S
S
S
S
amb
amb
amb
amb
amb
amb
amb
amb
amb
= -40°C
= -40°C
= +25°C
= +25°C
= +25°C
= +105°C
= +105°C
= +105°C
-98
-97
-96
-95
-100
-80
-60
-40
-20
0
20
40
60
80
100
Frequency Offset (kHz)
As can be seen in Figure 3-2 on page 13 the supply voltage has almost no influence. The tem-
perature has an influence of about +1.5/–0.7 dB, and a frequency offset of ±65 kHz also
influences by about ±1 dB. All these influences, combined with the sensitivity of a typical IC, are
then within a range of –103.7 dBm and –107.3 dBm over temperature, supply voltage and fre-
quency offset which is –105.5 dBm ±1.8dB. The integrated IF filter has an additional production
tolerance of only ±7 kHz, hence, a frequency offset between the receiver and the transmitter of
±58 kHz can be accepted for XTAL and XTO tolerances.
Note:
For the demodulator used in the ATA5423/ATA5425, the tolerable frequency offset does not
change with the data frequency, hence, the value of ±58 kHz is valid for up to 1 Kbit/s.
This small sensitivity spread over supply voltage, frequency offset and temperature is very
unusual in such a receiver. It is achieved by an internal, very fast and automatic frequency cor-
rection in the FSK demodulator after the IF filter, which leads to a higher system margin. This
frequency correction tracks the input frequency very quickly; if, however, the input frequency
makes a larger step (for example, if the system changes between different communication part-
ners), the receiver has to be restarted. This can be done by switching back to IDLE mode and
then again to RX mode. For that purpose, an automatic mode is also available. This automatic
mode switches to IDLE mode and back into RX mode every time a bit error occurs. (See “Digital
Control Logic” on page 36.)
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3.4
Frequency Accuracy of the Crystals
The XTO is an amplitude regulated Pierce oscillator with integrated load capacitors. The initial
tolerances (due to the frequency tolerance of the XTAL, the integrated capacitors on XTAL1,
XTAL2 and the XTO’s initial transconductance gm) can be compensated to a value within
±0.5 ppm by measuring the CLK output frequency and programming the control registers 2 and
3 (see Table 7-7 on page 39 and Table 7-10 on page 40). The XTO then has a remaining influ-
ence of less than ±2 ppm over temperature and supply voltage due to the band gap controlled
gm of the XTO.
The needed frequency stability of the used crystals over temperature and aging is hence
±58 kHz/315 MHz – 2 × ±2.5 ppm = ±179.2 ppm for 315 MHz,
±58 kHz/345 MHz – 2 × ±2.5 ppm = ±163.2 ppm for 345 MHz,
±58 kHz/433.92 MHz – 2 × ±2.5 ppm = ±128.6 ppm for 433.92 MHz,
±58 kHz/868.3 MHz – 2 × ±2.5 ppm = ±61.8 ppm for 868.3 MHz and
±58 kHz/915 MHz – 2 × ±2.5 ppm = ±58.4 ppm for 915 MHz.
Thus, the used crystals in receiver and transmitter each need to be better than ±89.6 ppm for
315 MHz, ±81.6 ppm for 345 MHz, ±64.3 ppm for 433.92 MHz, ±30.9 ppm for 868.3 MHz and
±29.2 ppm for 915 MHz. In access control systems it may be advantageous to have a more tight
tolerance at the Base-station in order to relax the requirement for the remote control unit.
3.5
RX Supply Current versus Temperature and Supply Voltage
Table 3-5 shows the typical supply current at 433.92 MHz of the transceiver in RX mode versus
supply voltage and temperature with VS = VS1 = VS2. As can be seen, the supply current at
2.4 V and –40°C is less than the typical supply current; this is useful because this is also the
operation point where a lithium cell has the worst performance. The typical supply current at
315 MHz, 345 MHz, 868.3 MHz or 915 MHz in RX mode is about the same as for 433.92 MHz.
Table 3-5.
Measured 433.92 MHz Receive Supply Current in FSK Mode
VS = VS1 = VS2
2.4V
3.0V
3.6V
Tamb = –40°C
Tamb = 25°C
Tamb = 85°C
8.4 mA
9.9 mA
10.9 mA
8.8 mA
10.3 mA
11.3 mA
9.2 mA
10.8 mA
11.8 mA
3.6
Blocking, Selectivity
As can be seen in Figure 3-3 and Figure 3-4 on page 15, the receiver can receive signals 3 dB
higher than the sensitivity level in the presence of very large blockers of –47 dBm/–34 dBm with
small frequency offsets of ±1/ ±10 MHz.
Figure 3-3 shows narrow band blocking and Figure 3-4 wide band blocking characteristics. The
measurements were done with a signal of 433.92 MHz/FSK/20 Kbit/s/±16 kHz/ Manchester, and
with a level of –106 dBm + 3 dB = –103 dBm which is 3 dB above the sensitivity level. The fig-
ures show how much larger than –103dBm a continuous wave signal can be before the BER is
higher than 10–3. The measurements were done at the 50Ω input according to Figure 3-1 on
page 11. At 1 MHz, for example, the blocker can be 56 dB higher than –103 dBm which is
-103 dBm + 56 dB = –47 dBm. These values, together with the good intermodulation perfor-
mance, avoid the need for a SAW filter in the remote control unit application.
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Figure 3-3. Narrow Band 3 dB Blocking Characteristic at 433.92 MHz
70
60
50
40
30
20
10
0
-10
-5
-4
-3
-2
-1
0
1
2
3
4
5
Distance of Interfering to Receiving Signal (MHz)
Figure 3-4. Wide Band 3 dB Blocking Characteristic at 433.92 MHz
80
70
60
50
40
30
20
10
0
-10
-50
-40
-30
-20
-10
0
10
20
30
40
50
Distance of Interfering to Receiving Signal (MHz)
Figure 3-5 on page 16 shows the blocking measurement close to the received frequency to illus-
trate the selectivity and image rejection. This measurement was done 6 dB above the sensitivity
level with a useful signal of 433.92 MHz/FSK/20 Kbit/s/±16 kHz/ Manchester with a level of
–106 dBm + 6 dB = –100 dBm. The figure shows to which extent a continuous wave signal can
surpass –100 dBm until the BER is higher than 10-3. For example, at 1 MHz the blocker can then
be 59 dB higher than –100 dBm which is –100 dBm + 59 dB = –41 dBm.
Table 3-6 on page 16 shows the blocking performance measured relative to –100 dBm for some
other frequencies. Note that sometimes the blocking is measured relative to the sensitivity level
(dBS) instead of the carrier (dBC).
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Table 3-6.
Frequency Offset
Blocking 6 dB Above Sensitivity Level with BER < 10–3
Blocker Level
–45 dBm
–45 dBm
–38 dBm
–38 dBm
–30 dBm
–30 dBm
Blocking
+0.75 MHz
–0.75 MHz
+1.5 MHz
–1.5 MHz
+10 MHz
–10 MHz
55 dBC/61 dBS
55 dBC/61 dBS
62 dBC/68 dBS
62 dBC/68 dBS
70 dBC/76 dBS
70 dBC/76 dBS
The ATA5423/ATA5425/ATA5428/ATA5429 can also receive FSK and ASK modulated signals if
they are much higher than the I1dBCP. It can typically receive useful signals at 10 dBm. This is
often referred to as the nonlinear dynamic range which is the maximum to minimum receiving
signal and is 116 dB for 20 Kbit/s Manchester. This value is useful if two transceivers have to
communicate and are very close to each other.
Figure 3-5. Close In 6 dB Blocking Characteristic and Image Response at 433.92 MHz
70
60
50
40
30
20
10
0
-10
-1.0 -0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
1.0
Distance of Interfering to Receiving Signal (MHz)
This high blocking performance even makes it possible for some applications using quarter
wave whip antennas to use a simple LC band-pass filter instead of a SAW filter in the receiver.
When designing such an LC filter take into account that the 3 dB blocking at
433.92 MHz/2 = 216.96 MHz is 43 dBC and at 433.92 MHz/3 = 144.64 MHz is 48 dBC and at
2 × (433.92 MHz + 226 kHz) + –226 kHz = 868.066 MHz/868.518 MHz is 56 dBC. And espe-
cially that at 3 × (433.92 MHz + 226 kHz) + 226 kHz = 1302.664 MHz the receiver has its
second LO harmonic receiving frequency with only 12 dBC blocking.
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3.7
In-band Disturbers, Data Filter, Quasi-peak Detector, Data Slicer
If a disturbing signal falls into the received band or a blocker is not continuous wave, the perfor-
mance of a receiver strongly depends on the circuits after the IF filter. The demodulator, data
filter and data slicer are important, in that case.
The data filter of the ATA5423/ATA5425/ATA5428/ATA5429 implies a quasi-peak detector. This
results in a good suppression of the above mentioned disturbers and exhibits a good carrier to
Gaussian noise performance. The required useful signal to disturbing signal ratio to be received
with a BER of 10–3 is less than 12 dB in ASK mode and less than 3 dB (BR_Range_0 to
BR_Range_2)/6 dB (BR_Range_3) in FSK mode. Due to the many different waveforms possible
these numbers are measured for signal as well as for disturbers with peak amplitude values.
Note that these values are worst case values and are valid for any type of modulation and mod-
ulating frequency of the disturbing signal as well as the receiving signal. For many combinations,
lower carrier to disturbing signal ratios are needed.
3.8
3.9
DEM_OUT Output
The internal raw output signal of the demodulator Demod_Out is available at pin DEM_OUT.
DEM_OUT is an open drain output and must be connected to a pull-up resistor if it is used (typi-
cally 100 kΩ) otherwise no signal is present at that pin.
RSSI Output
The output voltage of the pin RSSI is an analog voltage, proportional to the input power level.
Using the RSSI output signal, the signal strength of different transmitters can be distinguished.
The usable dynamic range of the RSSI amplifier is 70 dB, the input power range P(RFIN) is
–115 dBm to –45 dBm and the gain is 8 mV/dB. Figure 3-6 shows the RSSI characteristic of a
typical device at 433.92 MHz with VS1 = VS2 = 2.4 to 3.6 V and Tamb = –40°C to +85°C with a
matched input according to Table 3-2 on page 12 and Figure 3-1 on page 11. At 915 MHz about
3.3 dB and at 868.3 MHz about 2.7 dB more signal level, at 345 MHz about 0.8 dB and at
315 MHz about 1 dB less signal level is needed for the same RSSI results.
Figure 3-6. Typical RSSI Characteristic versus Temperature and Supply Voltage
1100
1000
900
800
max.
700
typ.
min.
600
500
400
-120
-110
-100
-90
-80
-70
-60
-50
-40
PRF_IN (dBm)
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3.10 Frequency Synthesizer
The synthesizer is a fully integrated fractional-N design with internal loop filters for receive and
transmit mode. The XTO frequency fXTO is the reference frequency FREF for the synthesizer.
The bits FR0 to FR12 in control registers 2 and 3 (see Table 7-7 on page 39 and Table 7-10 on
page 40) are used to adjust the deviation of fXTO. In transmit mode, at 433.92 MHz, the carrier
has a phase noise of –111 dBC/Hz at 1 MHz and spurious emissions at FREF of –66 dBC with a
high PLL loop bandwidth allowing the direct modulation of the carrier with 20 Kbit/s Manchester
data. Due to the closed loop modulation any spurious emissions caused by this modulation are
effectively filtered out as can be seen in Figure 3-9 on page 20. In RX mode the synthesizer has
a phase noise of –120 dBC/Hz at 1 MHz and spurious emissions of –75 dBC.
The initial tolerances of the crystal oscillator due to crystal tolerances, internal capacitor toler-
ances and the parasitics of the board have to be compensated at manufacturing setup with
control registers 2 and 3 as can be seen in Table 4-1 on page 28. The other control words for the
synthesizer needed for ASK, FSK and receive/transmit switching are calculated internally. The
RF (Radio Frequency) resolution is equal to the XTO frequency divided by 16384 which is
777.1 Hz at 315.0 MHz, 851.1 Hz at 345.0 MHz, 808.9 Hz at 433.92 MHz, 818.6 Hz at
868.3 MHz and 862.6 Hz at 915.0 MHz.
For the multi-channel system the frequency control word FREQ in control registers 2 and 3 can
be programmed in the range of 1000 to 6900, this is equivalent to a programmable tuning range
of ±2.5 MHz hence every frequency within the 315 MHz, 345 MHz, 433 MHz, 868 MHz and
915 MHz ISM bands can be programmed as receive and as transmit frequency, and the position
of channels within these ISM bands can be chosen arbitrarily (see Table 4-1).
Care must be taken as to the harmonics of the CLK output signal as well as to the harmonics
produced by a microprocessor clocked with it, since these harmonics can disturb the reception
of signals. In a single-channel system, using FREQ = 3803 to 4053 ensures that harmonics of
this signal do not disturb the receive mode.
3.11 FSK/ASK Transmission
Due to the fast modulation capability of the synthesizer and the high resolution, the carrier can
be internally FSK modulated, which simplifies the application of the transceiver. The deviation of
the transmitted signal is ±20 digital frequency steps of the synthesizer which is equal to
±15.54 kHz for 315 MHz, ±17.02 kHz for 345 MHz, ±16.17 kHz for 433.92 MHz, ±16.37 kHz for
868.3 MHz and ±17.25 kHz for 915 MHz.
Due to closed loop modulation with PLL filtering the modulated spectrum is very clean, meeting
ETSI and CEPT regulations when using a simple LC filter for the power amplifier harmonics as it
is shown in Figure 2.2 on page 8. In ASK mode the frequency is internally connected to the cen-
ter of the FSK transmission and the power amplifier is switched on and off to perform the
modulation. Figure 3-7 on page 19 to Figure 3-9 on page 20 show the spectrum of the FSK mod-
ulation with pseudo-random data with 20 Kbit/s/±16.17 kHz/Manchester and 5 dBm output
power.
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Figure 3-7. FSK-modulated TX Spectrum (433.92MHz/20 Kbit/s/±16.17 kHz/Manchester Code)
Atten 20 dB
Ref 10 dB
Samp
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 100 kHz
Span 30 MHz
VBW 100 kHz
Sweep 7.5 ms (401 pts)
Figure 3-8. Unmodulated TX Spectrum 433.92 MHz – 16.17 kHz (fFSK_L
)
Atten 20 dB
Ref 10 dB
Samp
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Span 1 MHz
Res BW 10 kHz
VBW 10 kHz
Sweep 27.5 ms (401 pts)
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Figure 3-9. FSK-modulated TX Spectrum (433.92 MHz/20 Kbit/s/±16.17 kHz/Manchester Code)
Atten 20 dB
Ref 10 dB
Samp
Log
10
dB/
VAvg
50
W1 S2
S3 FC
Center 433.92 MHz
Res BW 10 kHz
Span 1 MHz
VBW 10 kHz
Sweep 27.5 ms (401 pts)
3.12 Output Power Setting and PA Matching at RF_OUT
The Power Amplifier (PA) is a single-ended open collector stage which delivers a current pulse
which is nearly independent of supply voltage, temperature and tolerances due to band gap sta-
bilization. Resistor R1, see Figure 3-10 on page 21, sets a reference current which controls the
current in the PA. A higher resistor value results in a lower reference current, a lower output
power and a lower current consumption of the PA. The usable range of R1 is 15 kΩ to 56 kΩ. Pin
PWR_H switches the output power range between about 0 dBm to 5 dBm (PWR_H = GND) and
5 dBm to 10 dBm (PWR_H = AVCC) by multiplying this reference current by a factor 1
(PWR_H = GND) and 2.5 (PWR_H = AVCC), which corresponds to about 5 dB more output
power.
If the PA is switched off in TX mode, the current consumption without output stage with
VS1 = VS2 = 3 V, Tamb = 25°C is typically 6.5 mA for 868.3 MHz and 6.95 mA for 315 MHz and
433.92 MHz.
The maximum output power is achieved with optimum load resistances RLopt according to Table
3-7 on page 22 with compensation of the 1.0 pF output capacitance of the RF_OUT pin by
absorbing it into the matching network consisting of L1, C1, C3 as shown in Figure 3-10 on page
21. There must also be a low resistive DC path to AVCC to deliver the DC current of the power
amplifier's last stage. The matching of the PA output was done with the circuit shown in Figure
3-10 on page 21 with the values in Table 3-7 on page 22. Note that value changes of these ele-
ments may be necessary to compensate for individual board layouts.
20
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Example:
According to Table 3-7 on page 22, with a frequency of 433.92 MHz and output power of
11 dBm the overall current consumption is typically 17.8 mA; hence, the PA needs
17.8 mA - 6.95 mA = 10.85 mA in this mode, which corresponds to an overall power amplifier
efficiency of the PA of (10(11dBm/10) × 1 mW)/(3 V × 10.85 mA) × 100% = 38.6% in this case.
Using a higher resistor in this example of R1 = 1.091 × 22 kΩ = 24 kΩ results in 9.1% less cur-
rent in the PA of 10.85 mA/1.091 = 9.95 mA and 10 × log(1.091) = 0.38 dB less output power if
using a new load resistance of 300Ω × 1.091 = 327Ω. The resulting output power is then
11 dBm – 0.38 dB = 10.6 dBm and the overall current consumption is
6.95 mA + 9.95 mA = 16.9 mA.
The values of Table 3-7 on page 22 were measured with standard multi-layer chip inductors with
quality factors Q according to Table 3-7 on page 22. Looking to the 433.92 MHz/11 dBm case
with the quality factor of QL1 = 43 the loss in this inductor is estimated with the parallel equivalent
resistance of the inductor Rloss = 2 × π × f × L × QL1 and the matching loss with
10 log (1 + RLopt/Rloss) which is equal to 0.32 dB losses in this inductor. Taking this into account,
the PA efficiency is then 42% instead of 38.6%.
Be aware that the high power mode (PWR_H = AVCC) can only be used with a supply voltage
higher than 2.7V, whereas the low power mode (PWR_H = GND) can be used down to 2.4V as
can be seen in the “Electrical Characteristics: General” on page 67.
The supply blocking capacitor C2 (10 nF) has to be placed close to the matching network
because of the RF current flowing through it.
Figure 3-10. Power Setting and Output Matching
AVCC
C2
L1
ATA5423/ATA5425/
RFOUT
ATA5428/ATA5429
C1
10
8
RF_OUT
C3
R_PWR
PWR_H
R1
9
VPWR_H
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4841D–WIRE–10/07
Table 3-7.
Measured Output Power and Current Consumption with VS1 = VS2 = 3V, Tamb = 25°C
RLopt (Ω) L1 (nH)
Frequency (MHz) TX Current (mA) Output Power (dBm) R1 (kΩ) VPWR_H
QL1
28
32
35
75
74
65
40
38
43
58
54
57
62
62
60
C1 (pF) C3 (pF)
315
315
8.5
10.5
16.7
8.8
0.4
5.7
10.5
1.6
5.9
10.7
0.1
6.2
11
56
27
27
56
27
27
56
22
22
33
15
22
33
15
15
GND
GND
AVCC
GND
GND
AVCC
GND
GND
AVCC
GND
GND
AVCC
GND
GND
AVCC
2500
920
82
68
56
82
68
43
56
47
33
12
15
10
12
12
10
1.5
2.2
3.9
1.2
1.8
3.9
0.75
1.5
2.7
1.0
1.0
1.5
0.7
1.5
1.5
0
0
315
350
0
345
2400
900
0
345
10.4
16.9
8.6
0
345
320
0
433.92
433.92
433.92
868.3
868.3
868.3
915
2300
890
0
11.2
17.8
9.3
0
300
0
-0.3
5.4
9.5
0.1
4.9
10.2
1170
471
3.3
0
11.5
16.3
9.6
245
0
1100
465
0
915
11.8
20.3
0
915
230
0
3.13 Output Power and TX Supply Current versus Supply Voltage and Temperature
Table 3-8 on page 22 shows the measurement of the output power for a typical device with
VS = VS1 = VS2 in the 433.92 MHz and 6.2 dBm case versus temperature and supply voltage
measured according to Figure 3-10 on page 21 with components according to Table 3-7. As
opposed to the receiver sensitivity, the supply voltage has here the major impact on output
power variations because of the large signal behavior of a power amplifier. Thus, a two battery
system with voltage regulator or a 5V system shows much less variation than a 2.4V to 3.6V one
battery system because the supply voltage is then well within 3.0V and 3.6V.
The reason is that the amplitude at the output RF_OUT with optimum load resistance is
AVCC – 0.4V and the power is proportional to (AVCC – 0.4V)2 if the load impedance is not
changed. This means that the theoretical output power reduction if reducing the supply voltage
from 3.0V to 2.4V is 10 log ((3 V – 0.4 V)2/(2.4 V – 0.4 V)2) = 2.2 dB. Table 3-8 shows that prin-
ciple behavior in the measurement. This is not the same case for higher voltages, since here
increasing the supply voltage from 3V to 3.6V should theoretical increase the power by 1.8 dB;
but a gain of only 0.8 dB in the measurement shows that the amplitude does not increase with
the supply voltage because the load impedance is optimized for 3V and the output amplitude
stays more constant.
Table 3-8.
VS =
Measured Output Power and Supply Current at 433.92 MHz, PWR_H = GND
2.4 V
3.0 V
3.6 V
10.19 mA
3.8 dBm
10.19 mA
5.5 dBm
10.78 mA
6.2 dBm
T
amb = –40°C
amb = +25°C
Tamb = +85°C
10.62 mA
4.6 dBm
11.19 mA
6.2 dBm
11.79 mA
7.1 dBm
T
11.4 mA
3.9 dBm
12.02 mA
5.5 dBm
12.73 mA
6.6 dBm
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Table 3-9 shows the relative changes of the output power of a typical device compared to
3.0V/25°C. As can be seen, a temperature change to –40°C as well as to +85°C reduces the
power by less than 1 dB due to the band gap regulated output current. Measurements of all the
cases in Table 3-7 on page 22 over temperature and supply voltage have shown about the same
relative behavior as shown in Table 3-9.
Table 3-9.
VS =
Measurements of Typical Output Power Relative to 3V/25°C
2.4V
3.0V
–0.7 dB
0 dB
3.6V
0 dB
Tamb = –40°C
Tamb = +25°C
Tamb = +85°C
–2.4 dB
–1.6 dB
–2.3 dB
+0.9 dB
+0.4 dB
–0.7 dB
3.14 RX/TX Switch
The RX/TX switch decouples the LNA from the PA in TX mode, and directs the received power
to the LNA in RX mode. To do this, it has a low impedance to GND in TX mode and a high
impedance to GND in RX mode. To design a proper RX/TX decoupling, a linear simulation tool
for radio frequency design together with the measured device impedances of Table 3-1 on page
11, Table 3-7 on page 22, Table 3-10 and Table 3-11 on page 24 should be used, but the exact
element values have to be found on-board. Figure 3-11 shows an approximate equivalent circuit
of the switch. The principal switching operation is described here according to the application of
Figure 2-1 on page 7. The application of Figure 2.2 on page 8 works similarly.
Table 3-10. Impedance of the RX/TX Switch RX_TX2 Shorted to GND
Frequency
315 MHz
Z(RX_TX1) TX Mode
(4.8 + j3.2)Ω
(4.7 + j3.4)Ω
(4.5 + j4.3)Ω
(5 + j9)Ω
Z(RX_TX1) RX Mode
(11.3 – j214)Ω
(11.1 – j181)Ω
(10.3 – j153)Ω
(8.9 – j73)Ω
345 MHz
433.92 MHz
868.3 MHz
915 MHz
(5 + j9.2)Ω
(9 – j65)Ω
Figure 3-11. Equivalent Circuit of the Switch
RX_TX1
1.6 nH
2.5 pF
TX
11Ω
5Ω
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4841D–WIRE–10/07
3.15 Matching Network in TX Mode
In TX mode the 20 mm long and 0.4 mm wide transmission line which is much shorter than λ/4 is
approximately switched in parallel to the capacitor C9 to GND. The antenna connection between
C8 and C9 has an impedance of about 50Ω locking from the transmission line into the loop
antenna with pin RF_OUT, L2, C10, C8 and C9 connected (using a C9 without the added 7.6 pF
as discussed later). The transmission line can be approximated with a 16 nH inductor in series
with a 1.5Ω resistor, the closed switch can be approximated according to Table 3-10 on page 23
with the series connection of 1.6 nH and 5Ω in this mode. To have a parallel resonant high
impedance circuit with little RF power going into it looking from the loop antenna into the trans-
mission line a capacitor of about 7.6 pF to GND is needed at the beginning of the transmission
line (this capacitor is later absorbed into C9 which is then higher, as needed for 50Ω transforma-
tion). To keep the 50Ωimpedance in RX mode at the end of this transmission line, C7 also has to
be about 7.6 pF. This reduces the TX power by about 0.5 dB at 433.92 MHz compared to the
case the where the LNA path is completely disconnected.
3.16 Matching Network in RX Mode
In RX mode the RF_OUT pin has a high impedance of about 7 kΩ in parallel with 1.0 pF at
433.92 MHz as can be seen in Table 3-11. This, together with the losses of the inductor L2 with
120 nH and QL2 = 25, gives about 3.7 kΩ loss impedance at RF_OUT. Since the optimum load
impedance in TX mode for the power amplifier at RF_OUT is 890 Ω the loss associated with the
inductor L2 and the RF_OUT pin can be estimated to be 10 × log(1 + 890/3700) = 0.95 dB com-
pared to the optimum matched loop antenna without L2 and RF_OUT. The switch represents, in
this mode at 433.92 MHz, approximately an inductor of 1.6 nH in series with the parallel connec-
tion of 2.5 pF and 2.0 kΩ. Since the impedance level at pin RX_TX1 in RX mode is about 50Ω
this only negligibly dampens the received signal (by about 0.1 dB). When matching the LNA to
the loop antenna, the transmission line and the 7.6 pF part of C9 have to be taken into account
when choosing the values of C11 and L1 so that the impedance seen from the loop antenna into
the transmission line with the 7.6 pF capacitor connected is 50Ω. Since the loop antenna in RX
mode is loaded by the LNA input impedance, the loaded Q of the loop antenna is lowered by
about a factor of 2 in RX mode; hence the antenna bandwidth is higher than in TX mode.
Table 3-11. Impedance RF_OUT Pin in RX Mode
Frequency
315 MHz
Z(RF_OUT)RX
36Ω – j 502Ω
33Ω – j 480Ω
19Ω – j 366Ω
2.8Ω – j 141Ω
2.6Ω – j 135Ω
RP//CP
7 kΩ//1.0 pF
7 kΩ//1.0 pF
7 kΩ//1.0 pF
7 kΩ//1.3 pF
7 kΩ//1.3 pF
345 MHz
433.92 MHz
868.3 MHz
915 MHz
Note that if matching to 50Ω, like in Figure 2.2 on page 8, a high Q wire-wound inductor with a
Q > 70 should be used for L2 to minimize its contribution to RX losses that will otherwise be
dominant. The RX and TX losses will be in the range of 1.0 dB there.
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4. XTO
The XTO is an amplitude-regulated Pierce oscillator type with integrated load capacitances
(2 × 18 pF with a tolerance of ±17%) hence CLmin = 7.4 pF and CLmax = 10.6 pF. The XTO oscil-
lation frequency fXTO is the reference frequency FREF for the fractional-N synthesizer. When
designing the system in terms of receiving and transmitting frequency offset, the accuracy of the
crystal and XTO have to be considered.
The synthesizer can adjust the local oscillator frequency for the initial frequency error in fXTO
.
This is done at nominal supply voltage and temperature with the control registers 2 and 3 (see
Table 7-7 and Table 7-10). The remaining local oscillator tolerance at nominal supply voltage
and temperature is then < ±0.5 ppm. The XTO’s gm has very low influence of less than ±2 ppm
on the frequency at nominal supply voltage and temperature.
In a single channel system less than ±150 ppm should be corrected to avoid that harmonics of
the CLK output disturb the receive mode. If the CLK is not used or if it is carefully laid out on the
application PCB (as needed for multi channel systems), more than ±150 ppm can be
compensated.
Over temperature and supply voltage, the XTO's additional pulling is only ±2 ppm. The XTAL
versus temperature and its aging is then the main source of frequency error in the local
oscillator.
The XTO frequency depends on XTAL properties and the load capacitances CL1, 2 at pin XTAL1
and XTAL2. The pulling of fXTO from the nominal fXTAL is calculated using the following formula:
Cm
------- -------------------------------------------------------------
× 10 ppm.
C
LN – CL
6
P =
×
2
(C0 + CLN) × (C0 + CL)
Cm is the crystal's motional, C0 the shunt and CLN the nominal load capacitance of the XTAL
found in its data sheet. CL is the total actual load capacitance of the crystal in the circuit and con-
sists of CL1 and CL2 in series connection.
Figure 4-1. XTAL with Load Capacitance
Crystal equivalent circuit
C0
XTAL
Lm
Rm
Cm
CL1
CL2
CL = CL1 × CL2/ (CL1 + CL2
)
With Cm ≤14 fF, C0 ≥ 1.5 pF, CLN = 9 pF and CL = 7.4 pF to 10.6 pF, the pulling amounts to
P ≤±100 ppm and with Cm ≤7 fF, C0 ≥ 1.5 pF, CLN = 9 pF and CL = 7.4 pF to 10.6 pF, the pulling
is P ≤ ±50 ppm.
Since typical crystals have less than ±50 ppm tolerance at 25°C, the compensation is not criti-
cal, and can in both cases be done with the ±150 ppm.
25
4841D–WIRE–10/07
C0 of the XTAL has to be lower than CLmin/2 = 3.7 pF for a Pierce oscillator type in order to not
enter the steep region of pulling versus load capacitance where there is a risk of an unstable
oscillation.
To ensure proper start-up behavior the small signal gain, and thus the negative resistance, pro-
vided by this XTO at start is very large; for example, oscillation starts up even in worst case with
a crystal series resistance of 1.5 kΩ at C0 ≤2.2 pF with this XTO. The negative resistance is
approximately given by
Z1 × Z3 + Z2 × Z3 + Z1 × Z2 × Z3 × gm
-----------------------------------------------------------------------------------------------------
Re{ZXTOcore} = Re
Z1 + Z2 + Z3 + Z1 × Z2 × gm
with Z1, Z2 as complex impedances at pin XTAL1 and XTAL2, hence
Z1 = –j/(2 × π × fXTO × CL1) + 5Ω and Z2 = –j/(2 × π × fXTO × CL2) + 5Ω.
Z3 consists of crystals C0 in parallel with an internal 110 kΩ resistor hence
Z3 = –j/(2 × π × fXTO × C0) /110 kΩ, gm is the internal transconductance between XTAL1 and
XTAL2 with typically 19 mS at 25°C.
With fXTO = 13.5 MHz, gm = 19 mS, CL = 9 pF, and C0 = 2.2 pF, this results in a negative resis-
tance of about 2 kΩ. The worst case for technological, temperature and supply voltage variations
is then for C0 ≤2.2 pF always higher than 1.5 kΩ.
Due to the large gain at startup, the XTO is able to meet a very low start-up time. The oscillation
start-up time can be estimated with the time constant τ .
2
τ = -----------------------------------------------------------------------------------------------------------
4 × π2 × fm2 × Cm × (Re(ZXTOcore) + Rm)
After 10 τ to 20 τ an amplitude detector detects the oscillation amplitude and sets XTO_OK to
High if the amplitude is large enough. This sets N_RESET to High and activates the CLK output
if CLK_ON in control register 3 is High (see Table 7-7). Note that the necessary conditions of the
VSOUT and DVCC voltage also have to be fulfilled (see Figure 4-2 and Figure 5-1).
To save current in IDLE and Sleep modes, the load capacitors are partially switched off in these
modes with S1 and S2, as seen in Figure 4-2.
It is recommended to use a crystal with Cm = 3.0 fF to 7.0 fF, CLN = 9 pF, Rm < 120Ω and
C0 = 1.0 pF to 2.2 pF.
Lower values of Cm can be used, this increases the start-up time slightly. Lower values of C0 or
higher values of Cm (up to 15 fF) can also be used, this has only little influence on pulling.
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Figure 4-2. XTO Block Diagram
XTAL1
XTAL2
CLK
&
fXTO
DVCC_OK
(from power supply)
Divider
/3
CLK_ON
VSOUT_OK
(control
(from power supply)
register 3)
8 pF
S1
10 pF
10 pF
8 pF
S2
Amplitude
detector
CL1
CL2
XTO_OK
(to reset logic)
Divider
/16
fDCLK
In IDLE mode and during Sleep mode (RX_Polling)
the switches S1 and S2 are open.
Divider
/1
/2
/4
fXDCLK
/8
/16
Baud1
Baud0
XLim
To find the right values used in control registers 2 and 3 (see Table 7-7 and Table 7-10), the
relationship between fXTO and the fRF is shown in Table 4-1 on page 28. To determine the right
content, the frequency at pin CLK as well as the output frequency at RF_OUT in ASK mode can
be measured, then the FREQ value can be calculated according to Table 4-1 on page 28 so that
fRF is exactly the desired radio frequency.
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4841D–WIRE–10/07
Table 4-1.
Calculation of fRF
CREG1
Frequency
(MHz)
Pin 6
433_N868
Bit(4)
FS
Frequency
Resolution
f
XTO (MHz)
fRF = fTX_ASK = fRX
fTX_FSK_L
fTX_FSK_H
fRF
15.54 kHz
+
FREQ + 20.5
315
345
AVCC
AVCC
AVCC
GND
1
0
0
0
0
12.73193
13.94447
13.25311
13.41191
14.13324
f
f
f
f
f
XTO × 24.5 + ----------------------------------
fRF –15.54 kHz
777.1 Hz
851.1 Hz
808.9 Hz
818.6 Hz
862.6 Hz
16384
fRF
17.02 kHz
+
FREQ + 20.5
XTO × 24.5 + ----------------------------------
fRF –17.02 kHz
fRF –16.17 kHz
fRF –16.37 kHz
fRF –17.25 kHz
16384
fRF
16.17 kHz
+
FREQ + 20.5
433.92
868.3
915
XTO × 32.5 + ----------------------------------
16384
fRF
16.37 kHz
+
FREQ + 20.5
XTO × 64.5 + ----------------------------------
16384
fRF
17.25 kHz
+
FREQ + 20.5
GND
XTO × 64.5 + ----------------------------------
16384
The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR12
in control register 2 and 3, and is calculated as follows:
FREQ = FREQ2 + FREQ3
Care must be taken to the harmonics of the CLK output signal fCLK as well as to the harmonics
produced by an microprocessor clocked with it, since these harmonics can disturb the reception
of signals if they get to the RF input. In a single channel system, using FREQ = 3803 to 4053
ensures that the harmonics of this signal do not disturb the receive mode. In a multichannel sys-
tem, the CLK signal can either be not used or carefully laid out on the application PCB. The
supply voltage of the microcontroller must also be carefully blocked in a multichannel system.
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4.1
Pin CLK
Pin CLK is an output to clock a connected microcontroller. The clock frequency fCLK is calculated
as follows:
fXTO
fCLK = ----------
3
Because the enabling of pin CLK is asynchronous, the first clock cycle may be incomplete. The
signal at CLK output has a nominal 50% duty cycle.
Figure 4-3. Clock Timing
VThres_2 = 2.38V (typically)
VSOUT
V
Thres_1 = 2.3V (typically)
CLK
N_RESET
CLK_ON
(Control register 3)
4.2
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry is derived from one clock. As shown in Figure 4-2
on page 27, this clock cycle TDCLK is derived from the crystal oscillator (XTO) in combination with
a divider.
fXTO
fDCLK = ----------
16
TDCLK controls the following application relevant parameters:
• Timing of the polling circuit including bit check
• TX bit rate
The clock cycle of the bit check and the TX bit rate depends on the selected bit-rate range
(BR_Range) which is defined in control register 6 (see Table 7-20 on page 42) and XLim which
is defined in control register 4 (see Table 7-13 on page 40). This clock cycle TXDCLK is defined by
the following formulas for further reference:
BR_Range
BR_Range 0: TXDCLK = 8 × TDCLK × XLim
BR_Range 1: TXDCLK = 4 × TDCLK × XLim
BR_Range 2: TXDCLK = 2 × TDCLK × XLim
BR_Range 3: TXDCLK = 1 × TDCLK × XLim
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5. Power Supply
Figure 5-1. Power Supply
VS1
SW_AVCC
IN
OUT
V_REG1
3.25V typ.
VS2
AVCC
VSINT
EN
(Control register 1)
AVCC_EN
PWR_ON
≥ 1
FF1
T1
to
S
R
Q
T5
SW_VSOUT
DVCC
DVCC_OK
OFFCMD
≥ 1
S
0
0
1
1
R Q
0
1
0
1
no change
(Command via SPI)
SW_DVCC
0
1
1
DVCC_OK
(to XTO and
Reset Logic)
V_Monitor
(1.5V typ.)
and
VS1+
0.55V
typ.
VSOUT_OK
(to XTO and
Reset Logic)
-
P_On_Aux
+
(Status register)
V_Monitor
(2.3V/
2.38V typ.)
Low_Batt
(Status Register
and Reset Logic)
IN
OUT
V_REG2
3.25V typ.
VAUX
VSOUT
EN
VSOUT_EN
(Control register 3)
The supply voltage range of the ATA5423/ATA5425/ATA5428/ATA5429 is 2.4V to 3.6V or 4.4V
to 6.6V.
Pin VS1 is the supply voltage input for the range 2.4V to 3.6V and is used in 1 Li battery applica-
tions (3V) using a single lithium 3V cell. Pin VS2 is the voltage input for the range 4.4V to 6.6V
(2 Li battery application (6V) and Base-station Application (5V); in this case, the voltage regula-
tor V_REG1 regulates VS1 to typically 3.25V. If the voltage regulator is active, a blocking
capacitor of 2.2 µF has to be connected to VS1.
Pin VAUX is an input for an additional auxiliary voltage supply and can be connected, for exam-
ple, to an inductive supply (see Figure 5-6 on page 36). This input can only be used together
with a rectifier or as in the application shown in Figure 2.2 on page 8 and must otherwise be left
open.
Pin VSINT is the voltage input for the Microcontoller_Interface and must be connected to the
power supply of the microcontroller. The voltage range of VVSINT is 2.4V to 5.25V (see Figure 5-5
on page 35 and Figure 5-6 on page 36).
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AVCC is the internal operation voltage of the RF transceiver and is fed by VS1 via the switch
SW_AVCC. AVCC must be blocked with a 68 nF capacitor (see Figure 2-1 on page 7, Figure 2.2
on page 8 and Figure 2-3 on page 9).
DVCC is the internal operation voltage of the digital control logic and is fed by VS1 or VSOUT
via the switch SW_DVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 2-1 on
page 7, Figure 2.2 on page 8 and Figure 2-3 on page 9).
Pin VSOUT is a power supply output voltage for external devices (for example, microcontrollers)
and is fed by VS1 via the switch SW_VSOUT, or by the auxiliary voltage supply VAUX via
V_REG2. The voltage regulator V_REG2 regulates VSOUT to typically 3.25V. If the voltage reg-
ulator is active, a blocking capacitor of 2.2 µF has to be connected to VSOUT. VSOUT can be
switched off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions
found in Figure 5-2 on page 32.
Pin N_RESET is set to low if the voltage VVSOUT at pin VSOUT drops below 2.3V (typically) and
can be used as a reset signal for a connected microcontroller (see Figure 5-3 on page 34 and
Figure 5-4 on page 35).
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set T1 to T5 to GND, or PWR_ON to
VCC only temporarily. Otherwise, an additional current flows because of a 50 kΩpull-up resistor.
There are two voltage monitors generating the following signals (see Figure 5-1 on page 30):
• DVCC_OK if DVCC > 1.5V typically
• VSOUT_OK if VSOUT > VThres1 (2.3V typically)
• Low_Batt if VSOUT < VThres2 (2.38V typically)
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Figure 5-2. Operation Modes Flow Chart
Bit AVCC_EN = 0 and OFF Command and
Pin PWR_ON = 0 and
OFF Mode
V
VAUX < 3.5V (typ)
Pin T1, T2, T3, T4 and T5 = 1
AVCC = OFF
DVCC = OFF
VSOUT = OFF
Pin PWR_ON = 1 or
Pin T1, T2, T3, T4 or
Pin T5
VVAUX > 3.5V (typ)
Pin PWR_ON = 1 or
Pin T1, T2, T3, T4 or
Pin T5 or
V
VAUX < VS1 + 0.5V
Bit AVCC_EN = 1
IDLE Mode
IDLE Mode
AUX Mode
AVCC = VS1
DVCC = VS1
VSOUT = VS1
AVCC = VS1
DVCC = VS1
VSOUT = V_REG2
AVCC = OFF
DVCC = V_REG2
VSOUT = V_REG2
VVAUX > VS1 + 0.5V
Bit AVCC_EN = 0 and
OFF Command and
Pin PWR_ON = 0 and
Pin T1, T2, T3, T4 and
T5 = 1
OPM1 OPM0
0
1
1
1
0
1
TX Mode
RX Polling Mode
RX Mode
VSOUT_EN = 0
IDLE Mode
AVCC = VS1
DVCC = VS1
VSOUT = OFF
Statusbit Power_On = 1
or
Event on Pin T1, T2, T3, T4 or T5
OPM1 = 0 and OPM0 = 1
TX Mode
RX Polling Mode
RX Mode
OPM1 = 0 and OPM0 = 1
OPM1 = 1 and OPM0 = 0
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
AVCC = VS1
DVCC = VS1
VSOUT = VS1
or V_REG2
OPM1 = 1 and OPM0 = 0
OPM1 = 1 and OPM0 = 1
or Bit check ok
OPM1 = 1 and OPM0 = 1
Status bit Power_On = 1
or
Event on Pin T1, T2, T3, T4 or T5
VSOUT_EN = 0
RX Polling Mode
Bit check ok
AVCC = VS1
DVCC = VS1
VSOUT = OFF
5.1
OFF Mode
If the power supply (battery) is connected to pin VS1 and/or VS2, and if the voltage on pin VAUX
VAUX < 3.5V (typically), then the transceiver is in OFF mode. In OFF mode AVCC, DVCC and
V
VSOUT are disabled, resulting in very low power consumption (IS_OFF is typically 10 nA). In OFF
mode the transceiver is not programmable via the 4-wire serial interface.
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5.2
5.3
AUX Mode
The transceiver changes from OFF mode to AUX mode if the voltage at pin VAUX VVAUX > 3.5V
(typically). In AUX mode DVCC and VSOUT are connected to the auxiliary power supply input
(VAUX) via the voltage regulator V_REG2. In AUX mode the transceiver is programmable via
the 4-wire serial interface, but no RX or TX operations are possible because AVCC = OFF.
The state transition OFF mode to AUX mode is indicated by an interrupt at pin IRQ and the sta-
tus bit P_On_Aux = 1.
IDLE Mode
In IDLE mode AVCC and DVCC are connected to the battery voltage (VS1).
From OFF mode the transceiver changes to IDLE mode if pin PWR_ON is set to 1 or pin T1, T2,
T3, T4 or T5 is set to “0”. This state transition is indicated by an interrupt at pin IRQ and the sta-
tus bits Power_On = 1 or ST1, ST2, ST3, ST4 or ST5 = 1.
From AUX mode the transceiver changes to IDLE mode by setting AVCC_EN = 1 in control
register 1 via the 4-wire serial interface or if pin PWR_ON is set to “1” or pin T1, T2, T3, T4 or T5
is set to “0”.
VSOUT is either connected to VS1 or to the auxiliary power supply (V_REG2).
If VVAUX < VS1 + 0.5V, VSOUT is connected to VS1. If VVAUX > VS1 + 0.5V, VSOUT is connected
to V_REG2 and the status bit P_On_Aux is set to “1”.
In IDLE mode, the RF transceiver is disabled and the power consumption IS_IDLE is about 230 µA
(VSOUT OFF and CLK output OFF and VS = VS1 = VS2 = 3V). The exact value of this current
is strongly dependent on the application and the exact operation mode, therefore check the sec-
tion “Electrical Characteristics: General” on page 67 for the appropriate application case.
Via the 4-wire serial interface a connected microcontroller can program the required parameter
and enable the TX, RX polling or RX mode.
The transceiver can be set back to OFF mode by an OFF command via the 4-wire serial inter-
face (the bit AVCC_EN must be set to “0”, the input level of pin PWR_ON must be “0” and pin
T1, T2, T3, T4 and T5 = 1 before writing the OFF command).
Table 5-1.
Control Register 1
OPM1
OPM0
Function
0
0
IDLE mode
5.4
Reset Timing and Reset Logic
If the transceiver is switched on (OFF mode to IDLE mode, OFF mode to AUX mode) DVCC and
VSOUT ramp up as illustrated in Figure 5-3 on page 34 (AVCC only ramps up if the transceiver
is set to the IDLE mode). The internal signal DVCC_RESET resets the digital control logic and
sets the control register to default values.
A voltage monitor generates a low level at pin N_RESET until the voltage at pin VSOUT
exceeds 2.38V (typically) and the start-up time of the XTO has elapsed (amplitude detector, see
Figure 4-2 on page 27). After the voltage at pin VSOUT exceeds 2.3V (typically) and the start-up
time of the XTO has elapsed, the output clock at pin CLK is available. Because the enabling of
pin CLK is asynchronous, the first clock cycle may be incomplete.
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4841D–WIRE–10/07
The status bit Low_Batt is set to “1” if the voltage at pin VSOUT VVSOUT drops below VThres_2
(typically 2.38V). Low_Batt is set to “0” if VVSOUT exceeds VThres_2 and the status register is read
via the 4-wire serial interface or N_RESET is set to low.
If VVSOUT drops below VThres_1 (typically 2.3V), N_RESET is set to low. If bit VSOUT_EN in con-
trol register 3 is “1”, a DVCC_RESET is also generated. If VVSOUT was already disabled by the
connected microcontroller by setting bit VSOUT_EN = 0, no DVCC_RESET is generated.
Note:
If VSOUT < VThres_1 (typically 2.3 V) the output of the pin CLK is low, the Microcontroller_Interface
is disabled and the transceiver is not programmable via the 4-wire serial interface.
Figure 5-3. Reset Timing
VThres_2 = 2.38V (typ)
VThres_1 = 2.3V (typ)
VSOUT
1.5V (typically)
DVCC
(AVCC)
DVCC_RESET
N_RESET
V
SOUT > 2.38V and the XTO is running
LOW_Batt
(Status Register)
VSOUT_EN
(Control Register 3)
VSOUT > 2.3V and the XTO is running
VSOUT
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Figure 5-4. Reset Logic, SR Latch Generates the Hysteresis in the NRESET Signal
DVCC_OK
and
DVCC_RESET
XTO_OK
≥ 1
VSOUT_EN
and
N_RESET
and
S
R
Q
Q
VSOUT_OK
LOW_BATT
S
R
Q
0
0
1
1
0
1
0
1
no change
0
1
no change
5.5
1 Li Battery Application (3V)
The supply voltage range is 2.4V to 3.6V and VAUX is not used.
Figure 5-5. 1 Li Battery Application (3V)
ATA5423/ATA5425/
ATA5428/ATA5429
ATmega
48/88/168
VS1
VS2
2.4V to 3.6V
VAUX
RF Transceiver
AVCC
Digital Control
Logic
DVCC
VSOUT
VSINT
VS
CS
OUT
OUT
OUT
IN
SCK
SDI_TMDI
SDO_TMDO
IRQ
IN
CLK
IN
NRESET
DEM_OUT
IN
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5.6
2 Li Battery Application (6V)
The supply voltage range is 4.4V to 6.6V and VAUX is connected to an inductive supply.
Figure 5-6. 2 Li Battery Application (6V) with Inductive Emergency Supply
ATmega
48/88/168
ATA5423/ATA5425/
ATA5428/ATA5429
VS1
VS2
4.4V to 6.6V
VAUX
RF Transceiver
AVCC
DVCC
Digital Control
Logic
VSOUT
VSINT
VS
CS
OUT
OUT
OUT
IN
SCK
SDI_TMDI
SDO_TMDO
IRQ
IN
CLK
IN
NRESET
DEM_OUT
IN
6. Microcontroller Interface
The microcontroller interface is a level converter which converts all internal digital signals that
are referred to the DVCC voltage into the voltage used by the microcontroller. Therefore, the pin
VSINT has to be connected to the supply voltage of the microcontroller.
This makes it possible to use the internal voltage regulator/switch at pin VSOUT as in Figure 2-1
on page 7 and Figure 2-3 on page 9 or to connect the microcontroller and the pin VSINT directly
to the supply voltage of the microcontroller as in Figure 2.2 on page 8.
7. Digital Control Logic
7.1
Register Structure
The configuration of the transceiver is stored in RAM cells. The RAM contains a 16 × 8-bit
TX/RX data buffer and a 6 × 8-bit control register and is writable and readable via a 4-wire serial
interface (CS, SCK, SDI_TMDI, SDO_TMDO).
The 1 × 8-bit status register is not part of the RAM and is readable via the 4-wire serial interface.
The RAM and the status information are stored as long as the transceiver is in any active mode
(DVCC = VS1 or DVCC = V_REG2) and are lost when the transceiver switches to OFF mode
(DVCC =OFF).
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After the transceiver is turned on via pin PWR_ON = High, T1 = Low, T2 = Low, T3 = Low,
T4 = Low or T5 = Low or the voltage at pin VAUX VVAUX > 3.5V (typically), the control registers
are in the default state.
Figure 7-1. Register Structure
MSB
LSB
TX/RX Data Buffer:
16 × 8 Bit
AVCC
_EN
T_
MODE
IR1
IR0
FS
-
OPM1 OPM0
Control Register 1 (ADR 0)
Control Register 2 (ADR 1)
Control Register 3 (ADR 2)
Control Register 4 (ADR 3)
Control Register 5 (ADR 4)
Control Register 6 (ADR 5)
P_
MODE
FR6
FR5
FR4
FR3
FR9
FR2
FR8
FR1
FR7
FR0
VSOUT CLK_
_EN ON
FR12 FR11 FR10
ASK/ Sleep Sleep Sleep Sleep Sleep
XSleep XLim
NFSK
4
3
2
1
0
BitChk BitChk Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
1
0
Baud Baud Lim_
Lim_
Lim_
Lim_
Lim_
Lim_
1
0
max5 max4 max3 max2 max1 max0
Power_ Low_ P_On
ST5
ST4
ST3
ST2
ST1
Status Register (ADR 8)
On
Batt
_Aux
7.2
TX/RX Data Buffer
The TX/RX data buffer is used to handle the data transfer during RX and TX operations.
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7.3
Control Register
To use the transceiver in different applications, it can be configured by a connected microcon-
troller via the 4-wire serial interface.
7.3.1
Control Register 1 (ADR 0)
Table 7-1.
Control Register 1 (Function of Bit 7 and Bit 6 in RX Mode)
IR1
IR0 Function (RX Mode)
Pin IRQ is set to “1” if 4 received bytes are in the TX/RX data buffer or a receiving error
occurred
0
0
1
Pin IRQ is set to “1” if 8 received bytes are in the TX/RX data buffer or a receiving error
occurred
0
Pin IRQ is set to “1” if 12 received bytes are in the TX/RX data buffer or a receiving error
occurred (default)
1
1
0
1
Pin IRQ is set to “1” if a receiving error occurred
Table 7-2.
Control Register 1 (Function of Bit 7 and Bit 6 in TX Mode)
IR1
0
IR0 Function (TX Mode)
0
1
Pin IRQ is set to “1” if 4 bytes remain in the TX/RX data buffer or the TX data buffer is empty
Pin IRQ is set to “1” if 8 bytes remain in the TX/RX data buffer or the TX data buffer is empty
0
Pin IRQ is set to “1” if 12 bytes remain in the TX/RX data buffer or the TX data buffer is
empty (default)
1
1
0
1
Pin IRQ is set to “1” if the TX data buffer is empty
Table 7-3.
Control Register 1 (Function of Bit 5)
AVCC_EN
Function
0
1
(default)
Enables AVCC, if the ATA5423/ATA5425 is in AUX mode
Table 7-4.
Control Register 1 (Function of Bit 4)
Function (RX Mode, TX Mode)
FS
0
Selected frequency 345/433/868/915 MHz (default)
Selected frequency 315 MHz
1
Table 7-5.
Control Register 1 (Function of Bit 2 and Bit 1)
OPM1
OPM0 Function
0
0
1
1
0
1
0
1
IDLE mode (default)
TX mode
RX polling mode
RX mode
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Table 7-6.
T_MODE
0
Control Register 1 (Function of Bit 0)
Function
TX and RX function via TX/RX data buffer (default)
Transparent mode, TX/RX data buffer disabled, TX modulation data stream via pin
SDI_TMDI, RX modulation data stream via pin SDO_TMDO
1
Control Register 2 (ADR 1)
Table 7-7.
7.3.2
Control Register 2 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2 and Bit 1)
FR6
26
FR5
FR4
24
FR3
23
FR2
22
FR1
21
FR0
20
25
0
0
.
Function
0
0
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
FREQ2 = 0
FREQ2 = 1
1
.
0
.
1
.
1
.
0
.
0
.
0
.
FREQ2 = 88 (default)
1
1
1
1
1
1
1
FREQ2 = 127
Note:
Tuning of fRF LSBs (total 13 bits), frequency trimming resolution of fRF is fXTO/16384, which is
approximately 800 Hz (see section “XTO”, Table 4-1 on page 28)
Table 7-8.
Control Register 2 (Function of Bit 0 in RX Mode)
Function (RX Mode)
P_MODE
0
1
Pin IRQ is set to “1” if the bit check is successful (default)
No effect on pin IRQ if the bit check is successful
Table 7-9.
Control Register 2 (Function of Bit 0 in TX Mode)
Function (TX Mode)
P_MODE
0
1
Manchester modulator on (default)
Manchester modulator off (NRZ mode)
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7.3.3
Control Register 3 (ADR 2)
Table 7-10. Control Register 3 (Function of Bit 7, Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)
FR12
212
FR11
211
FR10
210
FR9
29
FR8
28
FR7
27
Function
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
FREQ3 = 0
FREQ3 = 128
FREQ3 = 256
.
0
.
1
.
1
.
1
.
1
.
0
.
FREQ3 = 3840 (default)
.
1
1
1
1
1
1
1
1
1
1
0
1
FREQ3 = 7936
FREQ3 = 8064
Note:
Tuning of fRF MSBs
Table 7-11. Control Register 3 (Function of Bit 1)
VSOUT_EN Function
0
1
Output voltage power supply for external devices off (pin VSOUT)
Output voltage power supply for external devices on (default)
Note:
This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or
T5 occurs or the bit Power_On in the status register is “1”.
Setting VSOUT_EN = 0 in AUX mode is not allowed
Table 7-12. Control Register 3 (Function of Bit 0)
CLK_ON
Function
0
1
Clock output off (pin CLK)
Clock output on (default)
Note:
This bit is set to “1” if the bit check is OK (RX_Polling, RX mode), an event at pin T1, T2, T3, T4 or
T5 occurs or the bit Power_On in the status register is “1”.
7.3.4
Control Register 4 (ADR 3)
Table 7-13. Control Register 4 (Function of Bit 7)
ASK_NFSK Function (TX Mode, RX Mode)
0
1
FSK mode (default)
ASK mode
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Table 7-14. Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2)
Function (RX Mode)
Sleep4 Sleep3 Sleep2 Sleep1 Sleep0
Sleep
24
0
0
.
23
0
0
.
22
0
0
.
21
0
0
.
20
0
1
.
(TSleep = Sleep × 1024 × TDCLK × XSleep)
0
1
10
0
1
0
1
0
(TSleep = 10 × 1024 × TDCLK × XSleep)
(default)
.
.
.
.
.
1
1
1
1
1
31
Table 7-15. Control Register 4 (Function of Bit 1)
XSleep
Function
0
1
XSleep = 1; extended TSleep off (default)
XSleep = 8; extended TSleep on
Table 7-16. Control Register 4 (Function of Bit 0)
XLim
Function
0
1
XLim = 1; extended TLim_min, TLim_max off (default)
XLim = 2; extended TLim_min, TLim_max on
7.3.5
Control Register 5 (ADR 4)
Table 7-17. Control Register 5 (Function of Bit 7 and Bit 6)
BitChk1
BitChk0
Function
0
0
1
1
0
1
0
1
NBit-check = 0 (0 bits checked during bit check)
NBit-check = 3 (3 bits checked during bit check) (default)
NBit-check = 6 (6 bits checked during bit check)
NBit-check = 9 (9 bits checked during bit check)
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Table 7-18. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in RX Mode)
Function (RX Mode)
Lim_min
(Lim_min < 10 are not applicable)
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min × TXDCLK)
0
0
.
0
0
.
1
1
.
0
0
.
1
1
.
0
1
.
10
11
16
0
1
0
0
0
0
(TLim_min = 16 × TXDCLK)
(default)
.
.
.
.
.
.
1
1
1
1
1
1
63
Table 7-19. Control Register 5 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0 in TX Mode)
Function (TX Mode) Lim_min
(Lim_min < 10 are not applicable)
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TX_Bitrate = 1/((Lim_min + 1) × TXDCLK × 2)
0
0
.
0
0
.
1
1
.
0
0
.
1
1
.
0
1
.
10
11
16
(TX_Bitrate = 1/((16 + 1) × TXDCLK × 2)
(default)
0
1
0
0
0
0
.
.
.
.
.
.
1
1
1
1
1
1
63
7.3.6
Control Register 6 (ADR 5)
Table 7-20. Control Register 6 (Function of Bit 7 and Bit 6)
Baud1
Baud0
Function
Bit-rate range 0 (B0) 1.0 Kbit/s to 2.5 Kbit/s;
TXDCLK = 8 × TDCLK × XLim
0
0
Bit-rate range 1 (B1) 2.0 Kbit/s to 5.0 Kbit/s;
0
1
1
0
T
XDCLK = 4 × TDCLK × XLim
Bit-rate range 2 (B2) 4.0 Kbit/s to 10.0 Kbit/s;
TXDCLK = 2 × TDCLK × XLim; (default)
Bit-rate range 3 (B3) 8.0 Kbit/s to 20.0 Kbit/s;
TXDCLK = 1 × TDCLK × XLim
1
1
Note that the receiver does not work with >10 Kbit/s in ASK mode
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Table 7-21. Control Register 6 (Function of Bit 5, Bit 4, Bit 3, Bit 2, Bit 1 and Bit 0)
Function Lim_max
(Lim_max < 12 is not Applicable)
(TLim_max = (Lim_max – 1) × TXDCLK)
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
0
0
.
0
0
.
1
1
.
1
1
.
0
0
.
0
1
.
12
13
28
0
1
1
1
0
0
(TLim_max = (28 – 1) × TXDCLK)
(default)
.
.
.
.
.
.
1
1
1
1
1
1
63
7.4
Status Register
The status register indicates the current status of the transceiver and is readable via the 4-wire
serial interface. Setting Power_On or P_On_Aux or an event on ST1, ST2, ST3, ST4 or ST5 is
indicated by an IRQ.
Reading the status register resets the bits Power_On, Low_Batt, P_On_Aux and the IRQ.
7.4.1
Status Register (ADR 8)
Table 7-22. Status Register
Status Bit
Function
Status of pin T5
Pin T5 = 0 → ST5 = 1
Pin T5 = 1 → ST5 = 0
(see Figure 7-3 on page 45)
ST5
Status of pin T4
Pin T4 = 0 → ST4 = 1
Pin T4 = 1 → ST4 = 0
(see Figure 7-3 on page 45)
ST4
ST3
ST2
ST1
Status of pin T3
Pin T3 = 0 → ST3 = 1
Pin T3 = 1 → ST3 = 0
(see Figure 7-3 on page 45)
Status of pin T2
Pin T2 = 0 → ST2 = 1
Pin T2 = 1 → ST2 = 0
(see Figure 7-3 on page 45)
Status of pin T1
Pin T1 = 0 → ST1 = 1
Pin T1 = 1 → ST1 = 0
(see Figure 7-3 on page 45)
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Table 7-22. Status Register (Continued)
Status Bit
Function
Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin
PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3
are set to “1”.
Power_On
(see Figure 7-4 on page 46)
Indicates that output voltage on pin VSOUT is too low
(VVSOUT < 2.38V typically)
Low_Batt
(see Figure 7-5 on page 47)
Indicates that the auxiliary supply voltage on pin VAUX is high enough to operate.
State transition:
P_On_Aux
a) OFF mode → AUX mode (see Figure 5-2 on page 32)
b) IDLE mode (VSOUT = VS1) → IDLE mode (VSOUT = V_REG2)
(see Figure 7-6 on page 48)
7.5
Pin Tn
To switch the transceiver from OFF to IDLE mode, pin Tn must be set to “0” (maximum
0.2 × VVS2) for at least TTn_IRQ (see Figure 7-2). The transceiver recognizes the negative edge,
sets pin N_RESET to low and switches on DVCC, AVCC and the power supply for external
devices VSOUT.
If VDVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit STn to “1” and an interrupt is issued (TTn_IRQ).
After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is
elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-
nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V
(typically) and the XTO is settled.
Figure 7-2. Timing Pin Tn, Status Bit STn
Tn
VThres_2 = 2.38V (typ)
VSOUT
VThres_1 = 2.3V (typ)
1.5V (typ)
DVCC, AVCC
N_RESET
CLK
TTn_IRQ
STn
(Status register)
IRQ
OFF
IDLE
Mode
Mode
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If the transceiver is in any active mode (IDLE, AUX, TX, RX, RX_Polling), an integrated
debounce logic is active. If there is an event on pin Tn a debounce counter is set to 0 (T = 0) and
started. The status is updated, an interrupt is issued and the debounce counter is stopped after
reaching the counter value T = 8195 × TDCLK
.
An event on the same key input before reaching T = 8195 × TDCLK stops the debounce counter.
An event on an other key input before reaching T = 8195 × TDCLK resets and restarts the
debounce counter.
While the debounce counter is running, the bits VSOUT_EN and CLK_ON in control register 3
are set to “1”.
The interrupt is deleted after reading the status register or executing the command Delete_IRQ.
If pin Tn is not used, it can be left open because of an internal pull-up resistor (typically 50 kΩ).
Figure 7-3. Timing Flow Pin Tn, Status Bit STn
IDLE Mode or
AUX Mode or
TX Mode or
RX Polling Mode or
RX Mode
Event on Pin Tn ?
N
Y
T = 0
Start debounce counter
Event on Pin Tn ?
N
Y
T = 8195 × T ?
N
Y
Tn = STn ?
Y
Pin Tn = 0 ?
Y
N
N
Stop debounce counter
STn = 1
Stop debounce counter
STn = 0
Stop debounce counter
IRQ = 1
IRQ = 1
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7.6
Pin PWR_ON
To switch the transceiver from OFF to IDLE mode, pin PWR_ON must be set to “1” (minimum
0.8 × VVS2) for at least TPWR_ON (see Figure 7-4). The transceiver recognizes the positive edge,
sets pin N_RESET to low, and switches on DVCC, AVCC and the power supply for external
devices VSOUT.
If VDVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and
sets the status bit Power_On to “1” and an interrupt is issued (TPWR_ON_IRQ_1).
After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is
elapsed the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-
nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V
(typically) and the XTO is settled.
If the transceiver is in any active mode (IDLE, AUX, RX, RX_Polling, TX), a positive edge on pin
PWR_ON sets Power_On to “1” (after TPWR_ON_IRQ_2). The state transition Power_On 0 →1 gen-
erates an interrupt. If Power_On is still “1” during the positive edge on pin PWR_ON no interrupt
is issued. Power_On and the interrupt are deleted after reading the status register.
During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3 are set to “1”.
Note:
It is not possible to set the transceiver to OFF mode by setting pin PWR_ON to “0”. If pin
PWR_ON is not used, it must be connected to GND.
Figure 7-4. Timing Pin PWR_ON, Status Bit Power_On
TPWR_ON > TPWR_ON_IRQ_1
TPWR_ON > TPWR_ON_IRQ_2
PWR_ON
VThres_2 = 2.38V (typ)
VSOUT
V
Thres_1 = 2.V
(typ)
1.5V (typ)
DVCC, AVCC
N_RESET
CLK
TPWR_ON_IRQ_1
TPWR_ON_IRQ_2
Power_ON
(Status register)
IRQ
OFF
Mode
IDLE
Mode
IDLE, AUX, RX, RX Polling, TX
Mode
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7.7
Low Battery Indicator
The status bit Low_Batt is set to “1” if the voltage VVSOUT on pin VSOUT drops below 2.38V
(typically).
Low_Batt is set to “0” if VVSOUT exceeds VThres_2 and the status register is read via the 4-wire
serial interface (see Figure 5-3 on page 34).
Figure 7-5. Timing Status Bit Low_Batt
IDLE, AUX, TX, RX
or
RX Polling Mode
VVSOUT < 2.38V (typ)
N
?
Y
Low_Batt = 1
Read Status Register
7.8
Pin VAUX
To switch the transceiver from OFF to AUX mode, the voltage VVAUX on pin VAUX must exceed
3.5V (typically) (see Figure 7-6 on page 48). If VVAUX exceeds 2V (typically) pin N_RESET is set
to low, and DVCC and the power supply for external devices VSOUT are switched on.
If VVAUX exceeds 3.5V (typically) the status bit P_On_Aux is set to “1” and an interrupt is issued.
After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is
elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-
nous, the first clock cycle may be incomplete. N_RESET is set to high if VVSOUT exceeds 2.38V
(typically) and the XTO is settled.
If the transceiver is in any active mode (IDLE, TX, RX, RX_Polling), a positive edge on pin VAUX
and VVAUX > VS1 + 0.5V sets P_On_Aux to “1”. The state transition P_On_Aux 0 →1 generates
an interrupt. If P_On_Aux is still “1” during the positive edge on pin VAUX no interrupt is issued.
P_On_Aux and the interrupt are deleted after reading the status register.
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Figure 7-6. Timing Pin VAUX, Status Bit P_On_Aux
VVAUX > VS1 + 0.5V (typ)
VVAUX > VS1 + 0.5V (typ)
3.5V (typ)
VAUX
2.0V (typ)
VThres_2 = 2.38V (typ)
V
Thres_1 = 2.3V (typ)
VSOUT
DVCC
N_RESET
CLK
P_ON_AUX
(Status register)
IRQ
AUX
Mode
OFF
Mode
IDLE, TX, RX, RX polling
Mode
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8. Transceiver Configuration
The configuration of the transceiver takes place via a 4-wire serial interface (CS, SCK,
SDI_TMDI, SDO_TMDO) and is organized in 8-bit units. The configuration is initiated with an
8-bit command. While shifting the command into pin SDI_TMDI, the number of bytes in the
TX/RX data buffer are available on pin SDO_TMDO. The read and write commands are followed
by one or more 8-bit data units. Each 8-bit data transmission begins with the MSB. The serial
interface is in the reset state if the level on pin CS = Low.
8.1
Command: Read TX/RX Data Buffer
During a RX operation, the user can read the received bytes in the TX/RX data buffer
successively.
Figure 8-1. Read TX/RX Data Buffer
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI Command: Read TX/RX Data Buffer
X
X
No. Bytes in the TX/RX Data Buffer
RX Data Byte 1
RX Data Byte 1
SDO_TMDO
SCK
CS
8.2
Command: Write TX/RX Data Buffer
During a TX operation the user can write the bytes in the TX/RX data buffer successively. An
echo of the command and the TX data bytes are provided for the microcontroller on pin
SDO_TMDO.
Figure 8-2. Write TX/RX Data Buffer
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI Command: Write TX/RX Data Buffer
TX Data Byte 1
Write TX/RX Data Buffer
TX Data Byte 2
TX Data Byte 1
No. Bytes in the TX/RX Data Buffer
SDO_TMDO
SCK
CS
8.3
Command: Read Control/Status Register
The control and status registers can be read individually or successively.
Figure 8-3. Read Control/Status Register
MSB
LSB
MSB
LSB
MSB
LSB
SDI_TMDI
SDO_TMDO
SCK
Command: Read C/S Register X
No. Bytes in the TX/RX Data Buffer
Command: Read C/S Register Y
Data C/S Register X
Command: Read C/S Register Z
Data C/S Register Y
CS
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8.4
Command: Write Control Register
The control registers can be written individually or successively. An echo of the command and
the data bytes are provided for the microcontroller on pin SDO_TMDO.
Figure 8-4. Write Control Register
MSB
LSB
MSB
Data Control Register X
LSB
MSB
LSB
SDI_TMDI Command: Write Control Register X
Command: Write Control Register Y
Data Control Register X
No. Bytes in the TX/RX Data Buffer
Write Control Register X
SDO_TMDO
SCK
CS
8.5
Command: OFF Command
If AVCC_EN in control register 1 is “0”, the input level on pin PWR_ON is low and on the key
inputs Tn is high, then the OFF command sets the transceiver in the OFF mode.
Figure 8-5. OFF Command
MSB
LSB
SDI_TMDI
SDO_TMDO
SCK
Command: OFF Command
No. Bytes in the TX/RX Data Buffer
CS
8.6
Command: Delete IRQ
The delete IRQ command sets pin IRQ to low.
Figure 8-6. Delete IRQ
MSB
LSB
SDI_TMDI
Command: Delete IRQ
No. Bytes in the TX/RX Data Buffer
SDO_TMDO
SCK
CS
8.7
Command Structure
The three most significant bits of the command (bit 5 to bit 7) indicate the command type. Bit 0 to
bit 4 describe the target address when reading or writing a control or status register. In all other
commands bit 0 to bit 4 have no effect and should be set to “0” for compatibility with future
products.
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Table 8-1.
Command Structure
MSB
LSB
Bit 0
x
Command
Bit 7
Bit 6
Bit 5
Bit 4
x
Bit 3
x
Bit 2
x
Bit 1
x
Read TX/RX data buffer
Write TX/RX data buffer
Read control/status register
Write control register
OFF command
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x
x
x
x
x
A4
A4
X
A3
A3
X
A2
A2
X
A1
A1
X
A0
A0
X
Delete IRQ
X
X
X
X
X
Not used
X
X
X
X
X
Not used
X
X
X
X
X
8.8
4-wire Serial Interface
The 4-wire serial interface consists of the Chip Select (CS), the Serial Clock (SCK), the Serial
Data Input (SDI_TMDI) and the Serial Data Output (SDO_TMDO). Data is transmitted/received
bit by bit in synchronization with the serial clock.
Note:
If the output level on pin N_RESET is low, no data communication with the microcontroller is
possible.
When CS is low and the transparent mode is inactive (T_MODE = 0), SDO_TMDO is in a high
impedance state. When CS is low and the transparent mode is active (T_MODE = 1), the RX
data stream is available on pin SDO_TMDO.
Figure 8-7. Serial Timing
TCS_disable
CS
TCS_setup
TSCK_setup2
TCycle
TSCK_setup1
TSCK_hold
X
SCK
X
THold
TSetup
SDI_TMDI
X
MSB
X
MSB-1
X
X
TOut_enable
TOut_delay
TOut_disable
SDO_TMDO
MSB
X can be either ViL or ViH
MSB-1
LSB
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9. Operation Modes
9.1
RX Operation
The transceiver is set to RX operation with the bits OPM0 and OPM1 in control register 1.
Table 9-1.
Control Register 1
OPM1
OPM0
Function
RX polling mode
RX mode
1
1
0
1
The transceiver is designed to consume less than 1 mA in RX operation while remaining sensi-
tive to signals from a corresponding transmitter. This is achieved via the polling circuit. This
circuit enables the signal path periodically for a short time. During this time the bit-check logic
verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the
transceiver remain active and transfer the data to the connected microcontroller. This transfer
takes place either via the TX/RX data buffer or via the pin SDO_TMDO. When there is no valid
signal present, the transceiver is in sleep mode most of the time, resulting in low current con-
sumption. This condition is called RX polling mode. A connected microcontroller can be disabled
during this time.
All relevant parameters of the polling logic can be configured by the connected microcontroller.
This flexibility enables the user to meet the specifications in terms of current consumption, sys-
tem response time, data rate, etc.
In RX mode the RF transceiver is enabled permanently and the bit-check logic verifies the pres-
ence of a valid transmitter signal. When a valid signal is detected the transceiver transfers the
data to the connected microcontroller. This transfer take place either via the TX/RX data buffer
or via the pin SDO_TMDO.
9.1.1
RX Polling Mode
When the transceiver is in RX polling mode it stays in a continuous cycle of three different
modes. In sleep mode the RF transceiver is disabled for the time period TSleep while consuming
low current of IS = IIDLE_X. During the start-up period, TStartup_PLL and TStartup_Sig_Proc, all signal pro-
cessing circuits are enabled and settled. In the following bit-check mode, the incoming data
stream is analyzed bit by bit to see if it is a valid transmitter signal. If no valid signal is present,
the transceiver is set back to sleep mode after the period TBit-check. This period varies check by
check as it is a statistical process. An average value for TBit-check is given in the electrical charac-
teristics. During TStartup_PLL the current consumption is IS = IStartup_PLL_X. During TStartup_Sig_Proc
and TBit-check the current consumption is IS = IRX_X. The condition of the transceiver is indicated
on pin RX_ACTIVE (see Figure 9-1 on page 54 and Figure 9-2 on page 55). The average cur-
rent consumption in RX polling mode IP is different in 1 Li battery application (3V), 2 Li battery
application (6V) or Base-station Application (5V). To calculate IP the index X must be replaced
by VS1,VS2 in 1 Li battery application (3V), VS2 in 2 Li battery application (6V) or VS2,VAUX in
Base-station Application (5V) (see section “Electrical Characteristics: General” on page 67).
I
IDLE_X × TSleep + IStartup_PLL_X × TStartup_PLL + IRX_X × (TStartup_Sig_Proc + TBitcheck
IP = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sleep + TStartup_PLL + TStartup_Sig_Proc + TBit_check
)
T
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To save current it is recommended that CLK and VVSOUT be disabled during RX polling mode. IP
does not include the current of the Microcontroller_Interface, IVSINT, or the current of an external
device connected to pin VSOUT (for example, microcontroller). If CLK and/or VSOUT is enabled
during RX polling mode the current consumption is calculated as follows:
IS_Poll = IP + IVSINT + IEXT
During TSleep, TStartup_PLL and TStartup_Sig_Proc, the transceiver is not sensitive to a transmitter sig-
nal. To guarantee the reception of a transmitted command, the transmitter must start the
telegram with an adequate preburst. The required length of the preburst, TPreburst, depends on
the polling parameters TSleep, TStartup_PLL, TStartup_Sig_Proc and TBit-check. Thus, TBit-check depends on
the actual bit rate and the number of bits (NBit-check) to be tested.
T
Preburst ≥ TSleep + TStartup_PLL + TStartup_Sig_Proc + TBit_check
9.1.2
Sleep Mode
The length of period TSleep is defined by the 5-bit word sleep in control register 4, the extension
factor XSleep defined by the bit XSleep in control register 4, and the basic clock cycle TDCLK. It is
calculated to be:
TSleep = Sleep × 1024 × TDCLK × XSleep
In US and European applications, the maximum value of TSleep is about 38 ms if XSleep is set to 1
(which is done by setting the bit XSleep in control register 4 to “0”). The time resolution is about
1.2 ms in that case. The sleep time can be extended to about 300 ms by setting XSleep to 8
(which is done by setting XSleep in control register 4 to “1”), the time resolution is then about
9.6 ms.
9.1.3
Start-up Mode
During TStartup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing
circuit starts up (TStartup_Sig_Proc). After the start-up time all circuits are in stable condition and
ready to receive.
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Figure 9-1. Flow Chart Polling Mode/RX Mode (T_MODE = 0, Transparent Mode Inactive)
Start RX Polling Mode
Sleep:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE
TSleep = Sleep × 1024 × TDCLK × XSleep
Low; IS = IIDLE_X
XSleep
TDCLK
:
:
Defined by bit XSleep in Control register 4
Basic clock cycle
Start RX Mode
Start-up mode:
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE
TStartup_PLL
:
798.5 × TDCLK (typ)
High; IS = IStartup_PLL_X; IStartup_PLL
TStartup_Sig_Proc
:
882 × TDCLK
498 × TDCLK
306 × TDCLK
210 × TDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE
High; IS = IRX_X; TStartup_Sig_proc
Is defined by the selected baud rate range and
TDCLK .The baud-rate range is defined by bit
Baud 0 and Baud 1 in Control Register 6.
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise it is set to Sleep mode or to Start_up mode.
Output level on pin RX_ACTIVE
IS = IRX_X; TBit-check
High
TBit-check
:
Depends on the result of the bit check.
NO
Bit check
OK ?
If the bit check is ok, TBit-check depends on the
number of bits to be checked (NBit-check) and
on the utilized data rate.
YES
Set VSOUT_EN = 1
Set CLK_ON = 1
Set OPM0 = 1
If the bit check fails, the average time period for
that check despends on the selected bit-rate
range and on TXDCLK. The bit-rate range is
defined by bit Baud 0 and Baud 1 in Control
Register 6.
NO
OPM0 = 1
?
YES
NO
P_MODE = 0
?
NO
YES
TSLEEP = 0
?
Set IRQ
YES
Receiving mode:
The incomming data stream is passed via the TX/RX Data Buffer to the connected
microcontroller. If an bit error occurs the transceiver is set back to Start-up mode.
If the transceiver detects a bit errror after a
successful bit check and before the start bit is
detected pin IRQ will be set to high (only if
P_MODE = 0) and the transceiver is set back to
start-up mode.
Output level on pin RX_ACTIVE
IS = IRX_X
High
NO
Start bit
detected ?
YES
RX data stream is
written into the TX/RX
Data Buffer
NO
Bit error ?
YES
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Figure 9-2. Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)
Start RX Polling Mode
Sleep:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE Low; IS = IIDLE_X
XSleep
:
Defined by bit XSleep in Control register 4
Basic clock cycle
TSleep = Sleep × 1024 × TDCLK × XSleep
TDCLK
:
Start RX Mode
Start-up mode:
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE
TStartup_PLL
:
798.5 × TDCLK (typ)
High; IS = IStartup_PLL_X; IStartup_PLL
TStartup_Sig_Proc
:
882 × TDCLK
498 × TDCLK
306 × TDCLK
210 × TDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE
High; IS = IRX_X; TStartup_Sig_proc
Is defined by the selected baud rate range and
TDCLK .The baud-rate range is defined by bit
Baud 0 and Baud 1 in Control Register 6.
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise the transceiver is set to Sleep mode
(if OPM0 = 0 and TSleep > 0) or stays in Bit-check mode.
Output level on pin RX_ACTIVE
IS = IRX_X; TBit-check
High
TBit-check
:
Depends on the result of the bit check.
NO
Bit check
OK ?
If the bit check is ok, TBit-check depends on the
number of bits to be checked (NBit-check) and
on the utilized data rate.
YES
NO
OPM0 = 1
?
If the bit check fails, the average time period for
that check despends on the selected bit-rate
range and on TXDCLK. The bit-rate range is
defined by bit Baud 0 and Baud 1 in Control
Register 6.
YES
Set VSOUT_EN = 1
Set CLK_ON = 1
Set OPM0 = 1
NO
TSLEEP = 0
?
YES
Receiving mode:
The incomming data stream is passed via PIN SDO_TMDO to the connected
microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.
Output level on pin RX_ACTIVE
High
If in FSK mode the datastream is interrupted the
FSK-Demodulator-PLL tends to lock out and is
further not able to lock in, even there is a valid
data stream available.
IS = IRX_X
In this case the transceiver must be set back to
IDLE mode.
NO
Level on pin
CS = Low ?
YES
RX data stream
available on pin
SDO_TMDO
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9.1.4
9.1.5
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distance between 2 signal edges are continuously compared to a pro-
grammable time window. The maximum count of this edge-to-edge test before the transceiver
switches to receiving mode is also programmable.
Configuration of the Bit Check
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one
bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum
count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in control
register 5. This implies 0, 6, 12 and 18 edge-to-edge checks, respectively. If NBit-check is set to a
higher value, the transceiver is less likely to switch to receiving mode due to noise. In the pres-
ence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value.
In RX polling mode, the bit-check time is not dependent on NBit-check if no valid signal is present.
Figure 9-3 shows an example where 3 bits are tested successfully.
Figure 9-3. Timing Diagram for Complete Successful Bit Check (Number of Checked Bits: 3)
RX_ACTIVE
Bit check ok
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Demod_Out
TStartup_Sig_Proc
Start-up mode
TBit-check
Bit check mode
Receiving mode
As seen in Figure 9-4, the time window for the bit check is defined by two separate time limits. If
the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check
limit TLim_max, the check will be continued. If tee is smaller than limit TLim_min or exceeds TLim_max
,
the bit check will be terminated and the transceiver switches to sleep mode.
Figure 9-4. Valid Time Window for Bit Check
1/fSig
Demod_Out
tee
TLim_min
TLim_max
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For the best noise immunity, use of a low span between TLim_min and TLim_max is recommended.
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst: a
“11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice. A good compro-
mise between sensitivity and susceptibility to noise regarding the expected edge-to-edge time,
tee, is a time window of ±38%; to get the maximum sensitivity the time window should be ±50%
and then NBit-check ≥ 6. Using preburst patterns that contain various edge-to-edge time periods,
the bit-check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below:
T
Lim_min = Lim_min × TXDCLK
TLim_max = (Lim_max -1) × TXDCLK
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
Lim_min, TLim_max and TXDCLK. The time resolution defining TLim_min and TLim_max is TXDCLK. The
minimum edge-to-edge time tee is defined in the section “Receiving Mode” on page 59. The
lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is
Lim_max = 63.
Figure 9-5, Figure 9-6, and Figure 9-7 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during TStartup_PLL
and TStartup_Sig_Proc. The output of the ASK/FSK demodulator (Demod_Out) is undefined during
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
TXDCLK
.
Figure 9-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 9-6 on
page 58 the bit check fails because the value CV_Lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 9-7 on page 58.
Figure 9-5. Timing Diagram During Bit Check
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check ok
Bit check ok
Bit check
1/2 Bit
1/2 Bit
1/2 Bit
Demod_Out
0
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 1112131415 1 2 3 4 5 6 7
Bit-check counter
TXDCLK
TStartup_Sig_Proc
Start-up mode
TBit-check
Bit check mode
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Figure 9-6. Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check failed (CV_Lim < Lim_min)
Bit check
1/2 Bit
Demod_Out
0
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7
8
9 101112
0
Bit-check counter
TStartup_Sig_Proc
Start-up mode
TBit_check
Bit check mode
TSleep
Sleep mode
Figure 9-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Bit check failed (CV_Lim < Lim_min)
Bit check
Demod_Out
1/2 Bit
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 101112131415161718192021222324
0
Bit-check counter
TStartup_Sig_Proc
Start-up mode
TBit_check
Bit check mode
TSleep
Sleep mode
9.1.6
Duration of the Bit Check
If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers
random signals. The bit check is a statistical process and TBit-check varies for each check. There-
fore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on
the selected bit-rate range and on TXDCLK. A higher bit-rate range causes a lower value for
TBit-check, resulting in a lower current consumption in RX polling mode.
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In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that sig-
nal, fSignal, and the count of the bits, NBit-check. A higher value for NBit-check therefore results in a
longer period for TBit-check, requiring a higher value for the transmitter pre-burst, TPreburst
.
9.1.7
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the transceiver switches to
receiving mode. To activate a connected microcontroller, the bits VSOUT_EN and CLK_ON in
control register 3 are set to “1”. An interrupt is issued at pin IRQ if the control bits T_MODE = 0
and P_MODE = 0.
If the transparent mode is active (T_MODE = 1) and the level on pin CS is low (no data transfer
via the serial interface), the RX data stream is available on pin SDO_TMDO (Figure 9-8).
Figure 9-8. Receiving Mode (TMODE = 1)
Preburst
Byte 1
Byte 2
Byte 3
Start
bit
Bit check ok
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
SDO_TMDO
Bit-check mode
Receiving mode
If the transparent mode is inactive (T_MODE = 0), the received data stream is buffered in the
TX/RX data buffer (see Figure 9-9 on page 60). The TX/RX data buffer is only usable for
Manchester and Bi-phase coded signals. It is always possible to transfer the data from the data
buffer via the 4-wire serial interface to a microcontroller (see Figure 8-1 on page 49).
Buffering of the data stream:
After a successful bit check, the transceiver switches from bit-check mode to receiving mode. In
receiving mode the TX/RX data buffer control logic is active and examines the incoming data
stream. This is done, as in the bit check, by subsequent time frame checks where the distance
between two edges is continuously compared to a programmable time window as illustrated in
Figure 9-9 on page 60. Only two time differences between two edges in Manchester and
Bi-phase coded signals are valid (T and 2T).
The limits for T are the same as used for the bit check. They can be programmed in control
register 5 and 6 (Lim_min, Lim_max).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
TLim_min_2T = Lim_min_2T × TXDCLK
Upper limit of 2T:
Lim_max_2T = (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
TLim_max_2T = (Lim_max_2T - 1) × TXDCLK
If the result of Lim_min_2T or Lim_max_2T is not an integer value, it will be rounded up.
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If the TX/RX data buffer control logic detects the start bit, the data stream is written in the TX/RX
data buffer byte by byte. The start bit is part of the first data byte and must be different from the
bits of the preburst. If the preburst consists of a sequence of “00000...”, the start bit must be a
“1”. If the preburst consists of a sequence of “11111...”, the start bit must be a “0”.
If the data stream consists of more than 16 bytes, a buffer overflow occurs and the TX/RX data
buffer control logic overwrites the bytes already stored in the TX/RX data buffer. Therefore, it is
very important to ensure that the data is read in time so that no buffer overflow occurs (see Fig-
ure 8-1 on page 49). There is a counter that indicates the number of received bytes in the TX/RX
data buffer (see section “Transceiver Configuration” on page 49). If a byte is transferred to the
microcontroller, the counter is decremented; if a byte is received, the counter is incremented.
The counter value is available via the 4-wire serial interface.
An interrupt is issued if the counter (while counting up) reaches the value defined by the control
bits IR0 and IR1 in control register 1.
Figure 9-9. Receiving Mode (TMODE = 0)
Preburst
Byte 1
Byte 2
Byte 3
Start
bit
T
2T
Bit check ok
Demod_Out
'0' '0' '0' '0' '0' '0' '0' '0' '0' '1' '0' '1' '0' '0' '0' '0' '0' '1' '1' '1' '1' '0' '0' '1' '1' '0' '1' '0' '1' '1' '0' '0'
Bit-check mode
Receiving mode
TX/RX Data Buff
er
Byte 16, Byte 32, ...
Byte 15, Byte 31, ...
Byte 14, Byte 30, ...
Byte 13, Byte 29, ...
Byte 12, Byte 28, ...
Byte 11, Byte 27, ...
Byte 10, Byte 26, ...
Byte 9, Byte 25, ...
Byte 8, Byte 24, ...
Byte 7, Byte 23, ...
Byte 6, Byte 22, ...
Byte 5, Byte 21, ...
Byte 4, Byte 20, ...
Byte 3, Byte 19, ...
Byte 2, Byte 18, ...
Byte 1, Byte 17, ...
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
MSB
LSB
Readable via 4-wire ser
ial interface
If the TX/RX data buffer control logic detects a bit error, an interrupt is issued and the transceiver
is set back to the start-up mode (see Figure 9-1 on page 54, Figure 9-2 on page 55 and
Figure 9-10 on page 61).
Bit error:
a) tee < TLim_min or TLim_max < tee < TLim_min_2T or tee > TLim_max_2T
b) Logical error (no edge detected in the bit center)
Note:
The byte consisting of the bit error will not be stored in the TX/RX data buffer. Thus, it is not avail-
able via the 4-wire serial interface.
Writing the control register 1, 4, 5 or 6 during receiving mode resets the TX/RX data buffer con-
trol logic and the counter which indicates the number of received bytes. If the bits OPM0 and
OPM1 are still “1” after writing to a control register, the transceiver changes to the start-up mode
(start-up signal processing).
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Figure 9-10. Bit Error (TMODE = 0)
Bit error
Bit check ok
Byte n-1
Byte n
Byte n+1
Preburst
Byte 1
Demod_Out
Receiving mode
Start-up mode Bit-check mode
Receiving mode
Table 9-2.
Mode
RX Modulation Scheme
Bit in TX/RX Data
Buffer
Level on Pin
SD0_TMDO
ASK/_NFSK
T_MODE
RFIN
0
0
1
1
0
0
1
1
f
FSK_L → fFSK_H
1
0
–
–
1
0
–
–
X
X
1
0
X
X
1
0
f
FSK_H → fFSK_L
0
1
fFSK_H
fFSK_L
RX
fASK off → fASK on
fASK on → fASK off
fASK on
fASK off
9.1.8
Recommended Lim_min and Lim_max for Maximum Sensitivity
The sensitivity measurements in the section “Low-IF Receiver” in Table 3-3 on page 12 and
Table 3-4 on page 12 have been done with the Lim_min and Lim_max values according to Table
9-3. These values are optimized for maximum sensitivity. Note that since these limits are opti-
mized for sensitivity, the number of checked bits, NBit-check, has to be at least 6 to prevent the
circuit from waking up to often in polling mode due to noise.
Table 9-3.
Recommended Lim_min and Lim_max Values for Different Bit Rates
1.0 Kbit/s
BR_Range_0
XLim = 1
2.4 Kbit/s
BR_Range_0
XLim = 0
5 Kbit/s
BR_Range_1
XLim = 0
10 Kbit/s
BR_Range_2
XLim = 0
20 Kbit/s
BR_Range_3
XLim = 0
fRF (fXTAL)/
MHz
315
Lim_min = 13 (261 µs) Lim_min = 12 (121 µs) Lim_min = 11 (55 µs) Lim_min = 11 (28 µs)
Lim_min = 11 (14 µs)
(12.73193) Lim_max = 38 (744 µs) Lim_max = 34 (332 µs) Lim_max = 32 (156 µs) Lim_max = 32 (78 µs) Lim_max = 31 (38 µs)
345 Lim_min = 13 (239 µs) Lim_min = 12 (110 µs) Lim_min = 11 (50 µs) Lim_min = 11 (25 µs) Lim_min = 11 (13 µs)
(13.94447) Lim_max = 38 (679 µs) Lim_max = 34 (303 µs) Lim_max = 32 (142 µs) Lim_max = 32 (71 µs) Lim_max = 31 (34 µs)
433.92 Lim_min = 13 (251 µs) Lim_min = 12 (116 µs) Lim_min = 11 (53 µs) Lim_min = 11 (27 µs) Lim_min = 11 (13 µs)
(13.25311) Lim_max = 38 (715 µs) Lim_max = 34 (319 µs) Lim_max = 32 (150 µs) Lim_max = 32 (75 µs) Lim_max = 32 (37 µs)
868.3 Lim_min = 13 (248 µs) Lim_min = 12 (115 µs) Lim_min = 11 (52 µs) Lim_min = 11 (26 µs) Lim_min = 11 (13 µs)
(13.41191) Lim_max = 38 (706 µs) Lim_max = 34 (315 µs) Lim_max = 32 (148 µs) Lim_max = 32 (74 µs) Lim_max = 32 (37 µs)
915 Lim_min = 13 (235 µs) Lim_min = 12 (109 µs) Lim_min = 11 (50 µs) Lim_min = 11 (25 µs) Lim_min = 11 (12 µs)
(14.13324) Lim_max = 38 (670 µs) Lim_max = 34 (299 µs) Lim_max = 32 (140 µs) Lim_max = 32 (70 µs) Lim_max = 32 (35 µs)
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9.2
TX Operation
The transceiver is set to TX operation by using the bits OPM0 and OPM1 in the control
register 1.
Table 9-4.
Control Register 1
OPM1
OPM0
Function
0
1
TX mode
Before activating TX mode, the TX parameters (bit rate, modulation scheme, etc.) must be
selected as illustrated in Figure 9-11 on page 63. The bit rate depends on Baud 0 and Baud 1 in
control register 6, Lim_min0 to Lim_min5 in control register 5 and XLIM in control register 4 (see
section “Control Register” on page 38). The modulation is selected with ASK/_NFSK in control
register 4. The FSK frequency deviation is fixed to about ±16 kHz. If P_Mode is set to “1”, the
Manchester modulator is disabled and pattern mode is active (NRZ, see Table 9-5 on page 65).
After the transceiver is set to TX mode, the start-up mode is active and the PLL is enabled. If the
PLL is locked, the TX mode is active.
If the transceiver is in start-up or TX mode, the TX/RX data buffer can be loaded via the 4-wire
serial interface. After the first byte is in the buffer and the TX mode is active, the transceiver
starts transmitting automatically (beginning with the MSB). While transmitting it is always possi-
ble to load new data in the TX/RX data buffer. To prevent a buffer overflow or interruptions
during transmitting, the user must ensure that data is loaded at the same speed as it is
transmitted.
There is a counter that indicates the number of bytes to be transmitted (see section “Transceiver
Configuration” on page 49). If a byte is loaded, the counter is incremented, if a byte is transmit-
ted, the counter is decremented. The counter value is available via the 4-wire serial interface. An
IRQ is issued if the counter (while counting down) reaches the value defined by the control bits
IR0 and IR1 in control register 1.
Note:
Writing to the control register 1, 4, 5 or 6 during TX mode resets the TX/RX data buffer and the
counter which indicates the number of bytes to be transmitted.
If T_Mode in control register 1 is set to “1”, the transceiver is in TX transparent mode. In this
mode the TX/RX data buffer is disabled and the TX data stream must be applied on pin
SDI_TMDI. Figure 9-11 on page 63 illustrates the flow chart of the TX transparent mode.
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Figure 9-11. TX Operation (T_MODE = 0)
Write Control Register 6
Baud1, BAUD0:
Lim_max0 to Lim_max5:
Select baud rate range
Don't care
Write Control Register 5
Lim_min0 to Lim_min5:
Bit_ck0, Bit_ck1:
Select the baud rate
Don't care
Write Control Register 4
XLim:
Select the bit rate
Select modulation
Don't care
ASK/_NFSK:
Sleep0 to Sleep4:
XSleep:
Don't care
Write Control Register 3
FR7, FR8:
VSOUT_EN:
CLK_ON:
Adjust fRF
Set VSOUT_EN = 1
Don't care
Idle Mode
Write Control Register 2
FR0 to FR6:
P_mode:
Adjust fRF
Enable or disable the
Manchester modulator
Write Control Register 1
IR1, IR0:
Select an event which activates
an interrupt
AVCC_EN:
FS:
OPM1, OPM0:
T_mode:
Don't care
Select operation frequency
Set OPM1 = 0 and OPM0 = 1
Set T_mode = 0
Start-up
Mode (TX)
Write TX/RX Data Buffer (max. 16 byte)
TStartup = 331.5 × TDCLK
N
N
Pin IRQ = 1 ?
Y
TX more Data
Bytes ?
Y
TX Mode
Write TX/RX Data Buffer (max. 16 - number of bytes still
in the TX/RX Data Buffer)
Command: Delete_IRQ
N
Pin IRQ = 1 ?
Y
Write Control Register 1
OPM1, OPM0:
Set IDLE
Idle Mode
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4841D–WIRE–10/07
Figure 9-12. TX Transparent Mode (T_MODE = 1)
Write Control Register 4
XLim:
Don't care
ASK/_NFSK:
Sleep0 to Sleep4:
XSleep:
Select modulation
Don't care
Don't care
Write Control Register 3
FR7, FR8:
VSOUT_EN:
CLK_ON:
Adjust fRF
Set VSOUT_EN = 1
Don't care
Idle Mode
Write Control Register 2
FR0 to FR6:
P_mode:
Adjust fRF
Don't care
Write Control Register 1
IR1, IR0:
AVCC_EN:
FS:
OPM1, OPM0:
T_mode:
Don't care
Don't care
Select operation frequency
Set OPM1 = 0 and OPM0 = 1
Set T_mode = 1
Start-up
Mode (TX)
TStartup = 331.5 × TDCLK
Apply TX Data on Pin SDI_TMDI
TX Mode
Write Control Register 1
OPM1, OPM0:
Set IDLE (OPM1 = 0, OPM0 = 1
Idle Mode
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Table 9-5.
Mode
TX Modulation Schemes
Bit in TX/RX
Data Buffer
Level on Pin
SDI_TMDI
ASK/_NFSK
P_Mode
T_Mode
RFOUT
0
0
1
1
X
X
0
0
1
1
X
X
0
0
0
0
1
1
0
0
0
0
1
1
1
0
1
0
X
X
1
0
1
0
X
X
X
X
X
X
1
f
FSK_L → fFSK_H
f
FSK_H → fFSK_L
fFSK_H
0
fFSK_L
fFSK_H
0
fFSK_L
TX
X
X
X
X
1
fASK off → fASK on
fASK on → fASK off
fASK on
1
fASK off
f
ASK on
0
fASK off
9.3
Interrupts
Via pin IRQ, the transceiver signals different operating conditions to a connected microcontrol-
ler. If a specific operating condition occurs, pin IRQ is set to high.
If an interrupt occurs, it is recommended to delete the interrupt immediately by reading the sta-
tus register, so that a further potential interrupt doesn’t get lost. If the Interrupt pin doesn’t switch
to low by reading the status register, the interrupt was triggered by the RX/TX data buffer. In this
case read or write the RX/TX data buffer according to Table 9-6.
Table 9-6.
Interrupt Handling
Operating Conditions Which Set Pin IRQ to High
Level
Operations Which Set Pin IRQ to Low Level
Events in Status Register
State transition of status bit STn
(0 → 1; 1 → 0)
Appearance of status bit Power_On
(0 → 1)
Read status register or
Command Delete IRQ
Appearance of status bit P_On_Aux
(0 → 1)
Events During TX Operation (T_MODE = 0)
Write TX data buffer or
Write control register 1 or
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
4, 8 or 12 Bytes are in the TX data buffer or the TX
data buffer is empty (depends on IR0 and IR1 in
control register 1).
Events During RX Operation (T_MODE = 0)
4, 8 or 12 received bytes are in the RX data buffer or a Read RX data buffer(1) or
receiving error is occurred (depends on IR0 and IR1 Write control register 1 or
in control register 1).
Write control register 4 or
Write control register 5 or
Write control register 6 or
Command delete IRQ
Successful bit check (P_MODE = 0)
Note:
1. During reading of the RX/TX buffer, no IRQ is issued, due to the received bytes or a receiving
error.
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4841D–WIRE–10/07
10. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Tj
Min.
Max.
150
Unit
°C
°C
°C
V
Junction temperature
Storage temperature
Ambient temperature
Supply voltage VS2
Supply voltage VS1
Supply voltage VAUX
Supply voltage VSINT
Tstg
–55
–40
+125
+85
+7.2
+4
Tamb
VMaxVS2
VMaxVS1
VMaxVAUX
VMaxVSINT
–0.3
–0.3
–0.3
–0.3
V
+7.2
+5.5
V
V
ESD (Human Body Model ESD S 5.1)
every pin
HBM
MM
–1.5
–200
+ 1.5
+200
kV
V
ESD (Machine Model JEDEC A115A)
every pin
ESD (Field Induced Charge Device Model ESD
STM 5.3.1–1999)
every pin
FCDM
Pin_max
–1
+1
10
kV
Maximum input level, input matched to 50 Ω
dBm
11. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
25
K/W
66
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ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
1
RX_TX_IDLE Mode
ATA5423
V433_N868 = AVCC
4, 10
4, 10
4, 10
4, 10
4, 10
fRF
fRF
fRF
fRF
fRF
312.5
342.5
431.5
862
317.5
347.5
436.5
872
MHz
MHz
MHz
MHz
MHz
A
A
A
A
A
ATA5425
V433_N868 = AVCC
RF operating frequency ATA5428
1.1
range
V433_N868 = AVCC
ATA5428
V433_N868 = GND
ATA5429
V433_N868 = GND
912.5
917.5
VVS1 = VVS2 = 3V,
VVSINT = 0V
(1 battery) and
VVS2 = 6V (2 battery)
OFF mode is not
available if
VVS2 = VVAUX = 5V
VVSINT = 0V (base
station)
Supply current
OFF mode
1.2
IS_OFF
< 10
220
nA
A
VVSOUT disabled,
XTO running
VVS1 = VVS2 = 3V
(1 battery)
IS_IDLE
µA
B
Supply current
IDLE mode
1.3
VVS2 = 6V (2 battery)
IS_IDLE
IS_IDLE
310
310
µA
µA
B
B
VVS2 = VVAUX = 5V
(base station)
From OFF mode to
IDLE mode including
reset and XTO start-up
(see Figure 7-4 on page
46)
1.4 System start-up time
TPWR_ON_IRQ_1
0.3
ms
C
XTAL: Cm = 5 fF,
C0 = 1.8 pF, Rm =15Ω
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
67
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
From IDLE mode to
receiving mode
N
Bit-check = 3
Bit rate = 20 Kbit/s,
TStartup_PLL +
1.5 RX start-up time
BR_Range_3
TStartup_Sig_Proc
+ TBit-chek
1.39
ms
A
(see Figure 9-1 on page
54, Figure 9-2 on page
55 and Figure 9-3 on
page 56)
From IDLE mode to TX
mode (see Figure 9-11
on page 63)
1.6 TX start-up time
TStartup
0.4
ms
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
68
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ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
2
Receiver/RX Mode
f
RF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
17, 18
17, 18
IS_RX
10.5
10.3
mA
mA
A
A
2.1 Supply current RX mode
fRF = 868 MHz
IS_RX
f
RF = 915 MHz
T
Sleep = 49.45 ms
Supply current
2.2
XSLEEP = 8, Sleep = 5
Bit rate = 20 Kbit/s FSK,
17, 18
IP
444
µA
B
RX polling mode
VVSOUT disabled
FSK deviation
fDEV = ±16 kHz
limits according to
Table 9-3 on page 61,
BER = 10-3
Input sensitivity FSK
2.3
fRF = 433.92 MHz
Tamb = 25°C
Bit rate 20 Kbit/s
Bit rate 2.4 Kbit/s
(4)
(4)
PREF_FSK
PREF_FSK
–104.0
–107.5
–106.0
–109.5
–107.5
–111.0
dBm
dBm
B
B
ASK 100%, level of
carrier limits according
to Table 9-3 on page
61, BER = 10-3
Input sensitivity ASK
2.4
fRF = 433.92 MHz
Tamb = 25°C
Bit rate 10 Kbit/s
Bit rate 2.4 Kbit/s
(4)
(4)
PREF_ASK
PREF_ASK
–110.5
–114.5
–112.5
–116.5
–114.0
–118.0
dBm
dBm
B
B
fRF = 433.92 MHz
to fRF = 315 MHz
–1.0
–0.8
+2.7
+3.3
fRF = 433.92 MHz
to fRF = 345 MHz
Sensitivity change at
fRF = 315 MHz
fRF = 433.92 MHz
to fRF = 868.3 MHz
f
RF = 345 MHz
2.5 fRF = 868.3 MHz
fRF = 915 MHz
(4)
∆PREF1
dB
B
fRF = 433.92 MHz
to fRF = 915 MHz
compared to
fRF = 433.92 MHz
P = PREF_ASK + ∆PREF1
∆PREF2
+
P = PREF_FSK + ∆PREF1
∆PREF2
+
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
69
4841D–WIRE–10/07
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
Maximum frequency
difference of fRF
between receiver and
transmitter in FSK
mode (fRF is the center
frequency of the FSK
signal with
Maximum frequency
offset in FSK mode
2.6
(4)
∆fOFFSET
–58
+58
kHz
B
fDEV = ±16 kHz)
With up to 2 dB
loss of sensitivity.
Note that the tolerable
frequency offset is for
fDEV = ±22 kHz, 6 kHz
lower than for
SupportedFSK frequency
deviation
2.7
(4)
fDEV
±14
±16
±22
kHz
B
fDEV = ±16 kHz hence
∆fOFFSET ≤ ±52 kHz
fRF = 315 MHz
(4)
(4)
(4)
(4)
(4)
NF
NF
NF
NF
NF
fIF
6.0
6.2
dB
dB
B
B
B
B
B
A
A
A
A
A
fRF = 345 MHz
2.8 System noise figure
fRF = 433.92 MHz
7.0
dB
f
RF = 868.3 MHz
9.7
dB
fRF = 915 MHz
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
10.3
227
235
223
226
238
dB
kHz
kHz
kHz
kHz
kHz
fIF
2.9 Intermediate frequency
fIF
fIF
fIF
This value is for
information only!
Note that for crystal and
system frequency offset
calculations, ∆fOFFSET
must be used.
2.10 System bandwidth
System outband
(4)
(4)
SBW
IIP2
185
+50
kHz
A
C
∆fmeas1 = 1,800 MHz
2.11 2nd-order input intercept ∆fmeas2 = 2,026 MHz
point with respect to fIF fIF = ∆fmeas2 – ∆fmeas1
dBm
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
70
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ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
∆fmeas1 = 1.8 MHz
∆fmeas2 = 3.6 MHz
fRF = 315 MHz
(4)
IIP3
C
–22
–22
–21
–17
–16
dBm
dBm
dBm
dBm
dBm
System outband
2.12 3rd-order input intercept
point
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
∆fmeas1 = 1 MHz
(4)
(4)
(4)
(4)
IIP3
IIP3
IIP3
IIP3
C
C
C
C
(4)
I1dBCP
–31
dBm
C
f
RF = 315 MHz
f
RF = 345 MHz
(4)
(4)
(4)
(4)
4
I1dBCP
I1dBCP
I1dBCP
I1dBCP
Zin_LNA
Zin_LNA
Zin_LNA
Zin_LNA
Zin_LNA
PIN_max
PIN_max
–31
–30
dBm
dBm
dBm
dBm
Ω
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
System outband input
2.13
1 dB compression point fRF = 433.92 MHz
fRF = 868.3 MHz
–27
fRF = 915 MHz
–26
fRF = 315 MHz
(44 – j233)
(40 – j211)
(32 – j169)
(21 – j78)
(18 – j70)
+10
fRF = 345 MHz
4
Ω
2.14 LNA input impedance
fRF = 433.92 MHz
RF = 868.3 MHz
4
Ω
f
4
Ω
fRF = 915 MHz
BER < 10-3, ASK: 100%
FSK: fDEV = ±16 kHz
f < 1 GHz
4
Ω
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
–10
–10
–57
–47
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Allowable peak RF input
2.15
level, ASK and FSK
+10
f >1 GHz
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
–100
–100
–97
LO spurious emission at
LNA_IN
2.16
–84
–84
Within the complete
image band
2.17 Image rejection
(4)
20
30
dB
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
71
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
Peak level of useful
signal to peak level of
interferer for BER < 10-3
with any modulation
scheme of interferer
Useful signal to interfering
signal ratio
2.18
FSK BR_Ranges 0, 1, 2
FSK BR_Range_3
(4)
(4)
SNRFSK0-2
SNRFSK3
SNRASK
DRSSI
2
4
3
6
dB
dB
dB
dB
B
B
B
A
ASK (PRF < PRFIN_High
)
(4)
10
70
12
Dynamic range
(4), 36
Lower level of range
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
–116
–115
–115
–112
–111
dBm
dBm
dBm
dBm
dBm
(4), 36
(4), 36
PRFIN_Low
A
A
2.19 RSSI output
Upper level of range
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
–46
–45
–45
–42
–41
dBm
dBm
dBm
dBm
dBm
PRFIN_High
Gain
(4), 36
(4), 36
5.5
8.0
10.5
mV/dB
mV
A
A
Output voltage range
OVRSSI
RRSSI
400
1100
Output resistance RSSI RX mode
8
32
10
40
12.5
50
2.20
36
kΩ
C
pin
TX mode
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
72
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
Sensitivity (BER = 10–3)
is reduced by 6 dB if a
continuous wave
blocking signal at ±∆f is
∆PBlock higher than the
useful signal level
(bit rate = 20 Kbit/s,
FSK, fDEV ±16kHz,
Manchester code)
fRF = 315 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
56
60
63
69
71
(4)
(4)
(4)
(4)
∆PBlock
∆PBlock
∆PBlock
∆PBlock
∆PBlock
dBC
dBC
dBC
dBC
C
C
C
C
∆f ±10 MHz
fRF = 345 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
56
60
63
69
71
2.21 Blocking
∆f ±10 MHz
fRF = 433.92 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
55
59
62
68
70
∆f ±10 MHz
fRF = 868.3 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
50
53
57
67
69
∆f ±10 MHz
fRF = 915 MHz
∆f ±0.75 MHz
∆f ±1.0 MHz
∆f ±1.5 MHz
∆f ±5 MHz
50
53
57
67
69
(4)
37
dBC
nF
C
D
∆f ±10 MHz
Capacitor connected to
pin 37 (CDEM)
2.22 CDEM
–5%
15
+5%
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
73
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
3
Power Amplifier/TX Mode
f
RF = 868.3 MHz
IS_TX_PAOFF
6.50
6.95
mA
mA
A
A
fRF = 915 MHz
Supply current TX mode
power amplifier OFF
3.1
fRF = 315 MHz
f
f
RF = 345 MHz
RF = 433.92 MHz
IS_TX_PAOFF
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = 0V
fRF = 315 MHz
RR_PWR = 56 kΩ
RLopt = 2.5 kΩ
fRF = 345 MHz
RR_PWR = 56 kΩ
RLopt = 2.4 kΩ
fRF = 433.92 MHz
RR_PWR = 56 kΩ
RLopt = 2.3 kΩ
3.2 Output power 1
(10)
PREF1
–2.5
0
+2.5
dBm
B
fRF = 868.3 MHz
RR_PWR = 30 kΩ
RLopt = 1.3 kΩ
fRF = 915 MHz
RR_PWR = 33 kΩ
RLopt = 1.1 kΩ
RF_OUT matched to
RLopt //
j/(2 × π × fRF × 1.0 pF)
PA on/0 dBm
fRF = 315 MHz
17, 18
IS_TX_PAON1
8.5
mA
B
f
RF = 345 MHz
17, 18
17, 18
17, 18
17, 18
IS_TX_PAON1
IS_TX_PAON1
IS_TX_PAON1
IS_TX_PAON1
8.6
8.6
9.6
9.6
mA
mA
mA
mA
B
B
B
B
Supply current TX mode
power amplifier ON 1
3.3
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
74
ATA5423/ATA5425/ATA5428/ATA5429
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ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = 0V
fRF = 315 MHz
R
R
R_PWR = 30 kΩ
Lopt = 1.0 kΩ
fRF = 345 MHz
R_PWR = 33 kΩ
R
RLopt = 1.1 kΩ
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 1.1 kΩ
3.4 Output power 2
(10)
PREF2
3.5
5.0
6.5
dBm
B
fRF = 868.3 MHz
RR_PWR = 16 kΩ
RLopt = 0.5 kΩ
fRF = 915 MHz
RR_PWR = 15 kΩ
RLopt = 0.25 kΩ
RF_OUT matched to
RLopt//
j/(2 × π × fRF × 1.0 pF)
PA on/5 dBm
fRF = 315 MHz
17, 18
IS_TX_PAON2
10.3
mA
B
f
RF = 345 MHz
17, 18
17, 18
17, 18
17, 18
IS_TX_PAON2
IS_TX_PAON2
IS_TX_PAON2
IS_TX_PAON2
10.4
10.5
11.2
11.8
mA
mA
mA
mA
B
B
B
B
Supply current TX mode
power amplifier ON 2
3.5
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
75
4841D–WIRE–10/07
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
VVS1 = VVS2 = 3V
Tamb = 25°C
VPWR_H = AVCC
fRF = 315 MHz
R
R
R_PWR = 30 kΩ
Lopt = 0.38 kΩ
fRF = 345 MHz
R_PWR = 31 kΩ
R
RLopt = 0.38 kΩ
fRF = 433.92 MHz
RR_PWR = 27 kΩ
RLopt = 0.36 kΩ
3.6 Output power 3
(10)
PREF3
8.5
10
11.5
dBm
B
fRF = 868.3 MHz
RR_PWR = 20 kΩ
RLopt = 0.22 kΩ
fRF = 915 MHz
RR_PWR = 16 kΩ
RLopt = 0.24 kΩ
RF_OUT matched to
RLopt//
j/(2 × π × fRF × 1.0 pF)
PA on/10dBm
fRF = 315 MHz
17, 18
IS_TX_PAON3
15.7
mA
B
f
RF = 345 MHz
17, 18
17, 18
17, 18
17, 18
IS_TX_PAON3
IS_TX_PAON3
IS_TX_PAON3
IS_TX_PAON3
15.8
15.8
17.3
19.3
mA
mA
mA
mA
B
B
B
B
Supply current TX mode
power amplifier ON 3
3.7
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
Tamb = –40°C to +85°C
Pout = PREFX + ∆PREFX
X = 1, 2 or 3
(10)
∆PREF
–0.8
–1.5
dB
B
Output power variation for
3.8 full temperature and
supply voltage range
VVS1 = VVS2 = 3.0V
VVS1 = VVS2 = 2.7V
VVS1 = VVS2 = 2.4V
(10)
(10)
∆PREF
∆PREF
–2.5
–3.5
dB
dB
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
76
ATA5423/ATA5425/ATA5428/ATA5429
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
RF = 315 MHz
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Ω
Type*
f
10
ZRF_OUT_RX
ZRF_OUT_RX
ZRF_OUT_RX
ZRF_OUT_RX
ZRF_OUT_RX
(36 – j502)
(33 – j480)
(19 – j366)
(2.8 – j141)
(2.6 – j135)
C
C
C
C
C
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
10
Ω
Impedance RF_OUT in
3.9
10
Ω
RX mode
10
Ω
10
Ω
at ±10 MHz/at 5 dBm
fRF = 315 MHz
(10)
LTX10M
–127
dBC/Hz
C
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
(10)
(10)
(10)
(10)
LTX10M
LTX10M
LTX10M
LTX10M
–126
–126
–125
–125
dBC/Hz
dBC/Hz
dBC/Hz
dBC/Hz
C
C
C
C
Noise floor power
amplifier
3.10
This corresponds to
10 Kbit/s Manchester
coding and 20 Kbit/s
NRZ coding
3.11 ASK modulation rate
fData_ASK
1
10
kHz
C
4
XTO
Pulling at nominal
temperature and supply
voltage
fXTAL = resonant
frequency of the XTAL
C0 ≥ 1.0 pF
Pulling XTO due to XTO,
CL1 and CL2 tolerances
4.1
24, 25
24, 25
A
Rm ≤ 120Ω
C
C
m ≤ 7.0 fF
m ≤ 14 fF
–50
–100
+50
+100
∆fXTO1
fXTAL
ppm
ms
At start-up; after
start-up the amplitude
is regulated to VPPXTAL
Transconductance XTO at
start
4.2
gm, XTO
19
B
A
C0 ≤ 2.2 pF
Cm < 14fF
4.3 XTO start-up time
24, 25 TPWR_ON_IRQ_1
300
800
µs
Rm ≤ 120Ω
Required for stable
operation with internal
load capacitors
4.4 Maximum C0 of XTAL
4.5 Internal capacitors
24, 25
24, 25
C0max
3.8
pF
pF
D
B
CL1 and CL2
CL1, CL2
14.8
18 pF
21.2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
77
4841D–WIRE–10/07
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
1.0 pF ≤ C0 ≤ 2.2 pF
C
R
m ≤ 14.0 fF
m ≤120Ω
Pulling of radio frequency
fRF due to XTO, CL1 and
CL2 versus temperature
and supply changes
4.6
PLL adjusted with
FREQ at nominal
temperature and supply
voltage
4, 10
∆fXTO2
–2
+2
ppm
C
Cm = 5 fF, C0 = 1.8 pF
Rm =15Ω
Amplitude XTAL after
start-up
V(XTAL1, XTAL2)
peak-to-peak value
4.7
4.8
24, 25
24, 25
VPPXTAL
VPPXTAL
700
350
mVpp
mVpp
C
C
V(XTAL1)
peak-to-peak value
C0 ≤ 2.2 pF, small signal
start impedance, this
value is important for
crystal oscillator startup
Real part of XTO
impedance at start-up
24, 25
24, 25
ReXTO
–2,000
15
–1,500
120
Ω
B
B
Maximum series
4.9 resistance Rm of XTAL
after start-up
C0 ≤ 2.2 pF
Rm_max
Ω
Cm ≤ 14 fFΩ
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
12.73193
13.94447
13.25311
13.41191
14.13324
MHz
MHz
MHz
MHz
MHz
Nominal XTAL load
4.10
24, 25
fXTAL
D
resonant frequency
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
78
ATA5423/ATA5425/ATA5428/ATA5429
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
fRF = 315 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
fCLK
4.244
MHz
D
f
RF = 345 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
30
fCLK
4.648
4.418
4.471
4.711
–30
MHz
MHz
MHz
MHz
mV
D
D
D
D
C
f
RF = 433.92 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
4.11 External CLK frequency
fCLK
f
RF = 868.3 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
fCLK
fRF = 915 MHz
CLK division ratio = 3
CLK has nominal 50%
duty cycle
30
fCLK
VDC(XTAL1, XTAL2)
XTO running
(IDLE mode, RX mode
and TX mode)
4.12 DC voltage after start-up
24, 25
VDCXTO
–150
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
79
4841D–WIRE–10/07
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Synthesizer
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
5
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 345 MHz
–72
–74
–68
–70
–69
SPTX
dBC
C
f
RF = 433.92 MHz
fRF = 868.3 MHz
RF = 915 MHz
f
5.1 Spurious TX mode
At ±fXTO
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
–70
–68
–66
–60
–60
SPTX
SPRX
SPRX
dBC
dBC
dBC
C
C
C
At ±fCLK, CLK enabled
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
< –75
< –75
< –75
< –75
< –75
5.2 Spurious RX mode
At ±fXTO
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
–75
–73
–75
–68
–67
Measured at 20 kHz
distance to carrier
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
–85
–85
–80
–75
–75
In loop phase noise
TX mode
5.3
LTX20k
dBC/Hz
A
f
RF = 915 MHz
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
–121
–120
–120
–113
–113
Phase noise at 1M
RX mode
5.4
LRX1M
dBC/Hz
dBC/Hz
C
C
f
RF = 868.3 MHz
fRF = 915 MHz
f
RF = 315 MHz
fRF = 345 MHz
RF = 433.92 MHz
–113
–113
–111
–107
–107
Phase noise at 1M
TX mode
5.5
f
LTX1M
fRF = 868.3 MHz
fRF = 915 MHz
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
80
ATA5423/ATA5425/ATA5428/ATA5429
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
Phase noise at 10M
RX mode
5.6
Noise floor PLL
LRX10M
–135
dBC/Hz
C
Frequency where the
absolute value loop
gain is equal to 1
Loop bandwidth PLL
TX mode
5.7
fLoop_PLL
70
kHz
kHz
B
D
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
±15.54
±17.02
±16.17
±16.37
±17.25
Frequency deviation
TX mode
5.8
fDEV_TX
f
RF = 868.3 MHz
fRF = 915 MHz
f
RF = 315 MHz
777.1
851.1
808.9
818.6
862.6
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
5.9 Frequency resolution
4, 10
∆fStep_PLL
Hz
D
B
This correspond to
20 Kbit/s Manchester
coding and 40 Kbit/s
NRZ coding
5.10 FSK modulation rate
fData_FSK
1
20
kHz
6
RX/TX Switch
RX mode, pin 38 with
short connection to
GND, fRF = 0 Hz (DC)
39
39
39
39
ZSwitch_RX
ZSwitch_RX
ZSwitch_TX
ZSwitch_RX
23000
Ω
Ω
Ω
Ω
A
C
A
C
fRF = 315 MHz
fRF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
fRF = 915 MHz
(11.3 – j214)
(11.1 – j181)
(10.3 – j153)
(8.9 – j73)
6.1 Impedance RX mode
(9 – j65)
TX mode, pin 38 with
short connection to
GND, fRF = 0 Hz (DC)
5
fRF = 315 MHz
(4.8 + j3.2)
(4.7 + j3.4)
(4.5 + j4.3)
(5 + j9)
6.2 Impedance TX mode
f
RF = 345 MHz
fRF = 433.92 MHz
fRF = 868.3 MHz
f
RF = 915 MHz
(5 + j9.2)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
7
Microcontroller Interface
IVSINT < 10 µA if CLK is 27, 28,
disabled and all
interface pins are in
stable condition and
unloaded
29, 30,
31, 32,
33, 34,
35
Voltage range for
microcontroller interface
7.1
2.4
5.25
V
A
fCLK < 4.5 MHz
CL = 10 pF
CL = Load capacitance
on pin CLK
trise
tfall
20
20
30
30
ns
ns
CLK output rise and fall
time
7.2
30
B
2.4V ≤ VVSINT ≤ 5.25V
20% to 80% VVSINT
CLK enabled
VVSOUT enabled
(C
+ CL) × VVSINT × fXTO
IVSINT = --------C---L---K-------------------------------------------------------------
3
CLK disabled
VVSOUT enabled
< 10 µA
< 10 µA
Current consumption of
7.4 the microcontroller
interface
VVSOUT disabled
27
IVSINT
CL = Load capacitance
on pin CLK
(All interface pins,
except pin CLK, are in
stable condition and
unloaded)
Internal equivalent
capacitance
Used for current
calculation
7.5
30, 27
CCLK
8
pF
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
8
Power Supply General Definitions and AUX Mode
IVSINT
VSINT
IEXT = IVSOUT – IVSINT
VSOUT
IVSOUT IEXT
Current consumption of
8.1 an external device
connected to pin VSOUT
IEXT
IEXT = IVSOUT
IVSINT
VSINT
VSOUT
IEXT = IVSOUT
VAUX
IAUX_VAUX
8.2 AUX mode
AUX mode
VVAUX ≥ 4V
Power supply output
voltage
IVSOUT ≤ 13.5 mA
(3.25V regulator mode,
V_REG2, see
8.3
22
VVSOUT
2.7
3.5
V
A
Figure 5-1 on page 30)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
83
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12. Electrical Characteristics: General (Continued)
This device is manufactured with an industrial (not automotive) grade process and process controls. Although this device may
meet certain automotive grade criteria in performance, Atmel can not recommend that this device be used in any automotive
application.
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V (1-battery application), VVS2 = 6.0V (2-battery application)
and VVS2 = VVAUX = 5.0V (Base-station Application). Typical values are given at fRF = 433.92 MHz unless otherwise specified. Details
about current consumption, timing and digital pin properties can be found in the specific sections of the “Electrical Characteristics”.
No. Parameters
Test Conditions
Pin(1)
Symbol
Min.
Typ.
Max.
Unit
Type*
IVSOUT = 0
VVAUX = 6V
VVAUX = 4V to 7V
Current in AUX mode on
pin VAUX
8.4
19
IAUX_VAUX
380
500
500
µA
µA
B
CLK enabled
VVSOUT enabled
IS_AUX = IAUX_VAUX + IVSINT + IEXT
IS_AUX = IAUX_VAUX + IEXT
Supply current
AUX mode
19, 22,
27
8.5
8.6
IS_AUX
CLK disabled
VVSOUT enabled
Supported voltage range
VAUX
19
VVAUX
4
6
7
V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Pin numbers in brackets mean they were measured with RF_IN matched to 50Ω according to Figure 3-1 on page 11 with
component values according to Table 3-2 on page 12 and RF_OUT matched to 50Ω according to Figure 3-10 on page 21
with component values according to Table 3-7 on page 22.
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13. Electrical Characteristics: 1 Li Battery Application (3V)
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V. Application according to Figure 2-1 on page 7.
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS1
VS2
IIDLE_VS1,2 or
9
1 Li Battery Application (3V)
I
RX_VS1,2 or
IStartup_PLL_VS1,2 or
ITX_VS1,2
Supported voltage
range (every mode
except high power TX
mode)
1 Li battery application
(3V)
PWR_H = GND
9.1
9.2
17, 18
17, 18
V
VS1, VVS2
2.4
2.7
3.6
3.6
V
V
A
A
Supported voltage
range (high power TX (3V)
1 Li battery application
VVS1, VVS2
mode)
PWR_H = AVCC
1 Li battery application
(3V)
VVS1 = VVS2 ≥ 2.6V
VAUX open(1)
I
VSOUT ≤ 13.5 mA
(no voltage regulator to
stabilize VVSOUT
Power supply output
voltage
9.3
22
VVSOUT
2.4
VVS1
V
B
)
VVS1 = VVS2 ≥ 2.425V
VAUX open(1)
I
VSOUT ≤ 1.5 mA
(no voltage regulator to
stabilize VVSOUT
)
Supply voltage for
microcontroller
interface
9.4
9.5
9.6
27
22
22
VVSINT
∆VThres
VThres_1
2.4
5.25
100
V
mV
V
A
B
A
Threshold hysteresis
VThres_2 – VThres_1
60
80
2.3
Reset threshold voltage
at pin VSOUT
2.18
2.42
(N_RESET)
Reset threshold voltage
at pin VSOUT
(Low_Batt)
9.7
9.8
22
VThres_2
2.26
2.38
2
2.5
V
A
A
Supply current
OFF mode
VVS1 = VVS2 ≤ 3.6V
VVSINT = 0V
17, 18,
22, 27
IS_OFF
350
nA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.
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13. Electrical Characteristics: 1 Li Battery Application (3V) (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS1 = VVS2 = 3.0V. Application according to Figure 2-1 on page 7.
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
CLK enabled
Current in IDLE mode VVSOUT enabled
on pin VS1 and VS2
312
260
225
430
370
320
µA
µA
µA
A
B
B
9.9
17, 18
IIDLE_VS1, 2
CLK disabled
VVSOUT enabled
VVSOUT disabled
Supply current
IDLE mode
17, 18,
22, 27
9.10
9.11
9.12
IS_IDLE
IRX_VS1, 2
IS_RX
IS_IDLE = IIDLE_VS1, 2 + IVSINT + IEXT
10.5 14 mA
IS_RX = IRX_VS1, 2 + IVSINT + IEXT
Current in RX mode on VVS1 = VVS2 ≤ 3V
pin VS1and VS2
17, 18
A
IVSOUT = 0
Supply current
RX mode
CLK enabled
VVSOUT enabled
17, 18,
22, 27
Current during
9.13 TStartup_PLL on pin VS1
and VS2
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
17, 18 IStartup_PLL_VS1, 2
8.8
11.5
mA
C
Current in
9.14 RX polling mode on pin
VS1 and VS2
I
IDLE_VS1,2 × TSLEEP + IStartup_PLL_VS1,2 × TStartup_PLL + IRX_VS1,2 × (TStartup_Sig_Proc + TBitcheck
)
IP = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T
Sleep + TStartup_PLL + TStartup_Sig_Proc + TBitcheck
CLK enabled
VVSOUT enabled
IS_Poll = IP + IVSINT + IEXT
Supply current
9.15
17, 18,
22, 27
CLK disabled
VVSOUT enabled
IS_Poll
RX polling mode
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
VVS1 = VVS2 ≤ 3V
IVSOUT = 0
Pout = 5 dBm/10 dBm
315 MHz/5 dBm
315 MHz/10 dBm
10.3
15.7
13.4
20.5
345 MHz/5 dBm
345 MHz/10 dBm
10.4
15.8
13.5
20.6
Current in TX mode on
9.16
17, 18
ITX_VS1_VS2
mA
B
pin VS1 and VS2
433.92 MHz/5 dBm
433.92 MHz/10 dBm
10.5
15.8
13.5
20.5
868.3 MHz/5 dBm
868.3 MHz/10 dBm
11.2
17.3
14.5
22.5
915 MHz/5 dBm
915 MHz/10 dBm
11.8
19.3
15.3
25.1
CLK enabled
VVSOUT enabled
IS_TX = ITX_VS1, 2 + IVSINT + IEXT
IS_TX = ITX_VS1, 2 + IEXT
Supply current
9.17
17, 18,
22, 27
IS_TX
TX mode
CLK disabled
VVSOUT enabled
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The voltage of VAUX may rise up to 2V. The current IVAUX may not exceed 100 µA.
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14. Electrical Characteristics: 2 Li Battery Application (6V)
All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 6.0V. Application according to Figure 2-3 on page 9
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
I
IDLE_VS2 or
VS2
10
2 Li Battery Application (6V)
IRX_VS2 or
IStartup_PLL_VS2 or
ITX_VS2
Supported voltage
range
2 Li battery
application (6V)
10.1
10.2
17
22
VVS2
4.4
3.0
6.6
3.5
V
V
A
A
2 Li battery
application (6V)
V
VS2 ≥ 4.4V
VAUX open(1)
VSOUT ≤ 13.5 mA
Power supply output
voltage
VVSOUT
I
(3.3V regulator mode,
V_REG1, see Figure
5-1 on page 30)
Supply voltage for
microcontroller
interface
10.3
10.4
10.5
27
22
22
VVSINT
∆VThres
VThres_1
2.4
60
5.25
100
V
mV
V
A
B
A
Threshold hysteresis
VThres_2 – VThres_1
80
Reset threshold
voltage at pin VSOUT
(N_RESET)
2.18
2.3
2.42
Reset threshold
voltage at pin VSOUT
(Low_Batt)
10.6
10.7
22
VThres_2
2.26
2.38
10
2.5
V
A
A
Supply current
OFF mode
V
VS2 ≤ 6.6V
17,
22, 27
IS_OFF
350
nA
VVSINT = 0V
VVS2 ≤ 6V
IVSOUT = 0
CLK enabled
Current in IDLE mode
on pin VS2
VVSOUT enabled
410
560
µA
A
10.8
17
IIDLE_VS2
CLK disabled
VVSOUT enabled
348
309
490
430
µA
µA
B
B
VVSOUT disabled
Supply current IDLE
mode
17,
22, 27
10.9
10.10
10.11
IS_IDLE
IRX_VS2
IS_RX
IS_IDLE = IIDLE_VS2 + IVSINT + IEXT
10.8 14.5 mA
IS_RX = IRX_VS2 + IVSINT + IEXT
Current in RX mode
on pin VS2
IVSOUT = 0
17
B
Supply current
RX mode
CLK enabled
VVSOUT enabled
17,
22, 27
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.
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14. Electrical Characteristics: 2 Li Battery Application (6V) (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 6.0V. Application according to Figure 2-3 on page 9
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current during
TStartup_PLL on pin VS2
10.12
I
VSOUT = 0
17
IStartup_PLL_VS2
9.1
12
mA
C
Current in
10.13 RX polling mode on
on pin VS2
IIDLE_VS2 × TSLEEP + IStartup_PLL_VS2 × TStartup_PLL + IRX_VS2 × (TStartup_Sig_Proc + TBitcheck)
IP = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T
Sleep + TStartup_PLL + TStartup_Sig_Proc + TBitcheck
CLK enabled
VVSOUT enabled
IS_Poll = IP + IVSINT + IEXT
Supply current
10.14
17,
22, 27
CLK disabled
VVSOUT enabled
IS_Poll
RX polling mode
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
I
VSOUT = 0
Pout = 5 dBm/10 dBm
315 MHz/5 dBm
315 MHz/10 dBm
10.7
16.2
13.9
21.0
345 MHz/5 dBm
345 MHz/10 dBm
10.8
16.3
14.0
21.2
Current in TX mode
on pin VS2
10.15
17, 19
ITX_VS2
mA
B
433.92 MHz/5 dBm
433.92 MHz/10 dBm
10.9
16.3
14.0
21.0
868.3 MHz/5 dBm
868.3 MHz/10 dBm
11.6
17.8
15.0
23.0
915 MHz/5 dBm
915 MHz/10 dBm
12.3
20.0
16.0
26.0
CLK enabled
VVSOUT enabled
IS_TX = ITX_VS2 + IVSINT + IEXT
IS_TX = ITX_VS2 + IEXT
Supply current
10.16
17,
22, 27
IS_TX
TX mode
CLK disabled
VVSOUT enabled
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. The voltage of VAUX may rise up to 2 V. The current IVAUX may not exceed 100 µA.
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15. Electrical Characteristics: Base-station Application (5V)
All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 5.0V. Application according to Figure 2.2 on page 8
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VAUX
VS2
IIDLE_VS2,VAUX
or IRX_VS2,VAUX
or IStartup_PLL_VS2,VAUX
or ITX_VS2,VAUX
11
Base-station Application (5V)
Supported voltage
range
Base-station
application (5V)
17,
19, 27
11.1
11.2
VVS2, VAUX
4.75
5.25
V
V
A
A
Base-station
application (5V)
VVS2 = VVAUX
Power supply output
voltage
IVSOUT ≤ 13.5 mA
22
VVSOUT
3.0
3.5
(3.25V regulator
mode, V_REG2, see
Figure 5-1 on page
30)
Supply voltage for
microcontroller-
interface
11.3
11.4
11.5
27
22
22
VVSINT
∆VThres
VThres_1
2.4
60
5.25
100
V
mV
V
A
B
A
Threshold hysteresis
VThres_2 – VThres_1
80
Reset threshold
voltage at pin VSOUT
(N_RESET)
2.18
2.3
2.42
Reset threshold
voltage at pin VSOUT
(Low_Batt)
11.6
22
VThres_2
2.26
2.38
444
2.5
V
A
IVSOUT = 0
CLK enabled
VVSOUT enabled
580
Current in IDLE mode
on pin VS2 and VAUX CLK disabled
VVSOUT enabled
11.7
17, 19
IIDLE_VS2_VAUX
µA
B
380
310
500
400
VVSOUT disabled
17,
19,
22, 27
Supply current in
IDLE mode
11.8
11.9
IS_IDLE
IRX_VS2_VAUX
IS_RX
IS_IDLE = IIDLE_VS2_VAUX + IVSINT + IEXT
Current in RX mode
IVSOUT = 0
17, 19
10.8
14.5
mA
B
C
on pin VS2 and VAUX
17,
19,
22, 27
Supply current in RX
mode
CLK enabled VVSOUT
enabled
11.10
IS_RX = IRX_VS2_VAUX + IVSINT + IEXT
Current during
11.11 TStartup_PLL on pin VS2
and VAUX
IStartup_PLL_VS2,
IVSOUT = 0
17, 19
9.1
12
mA
VAUX
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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15. Electrical Characteristics: Base-station Application (5V) (Continued)
All parameters refer to GND and are valid for Tamb = 25°C, VVS2 = 5.0V. Application according to Figure 2.2 on page 8
fRF = 315 MHz/345 MHz/433.92 MHz/868.3 MHz/915 MHz unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Current in RX_Polling_Mode on pin VS2 and VAUX
11.12
I
IDLE_VS2,VAUX × TSLEEP + IStartup_PLL_VS2,VAUX × TStartup_PLL + IRX_VS2,VAUX × (TStartup_Sig_Proc + TBitcheck
IP = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Sleep + TStartup_PLL + TStartup_Sig_Proc + TBitcheck
)
T
CLK enabled
VVSOUT enabled
IS_Poll = IP + IVSINT + IEXT
17,
19,
22, 27
Supply current in RX
polling mode
11.13
CLK disabled
VVSOUT enabled
IS_Poll
IS_Poll = IP + IEXT
IS_Poll = IP
VVSOUT disabled
IVSOUT = 0
Pout = 5dBm/10dBm
315 MHz/5dBm
315 MHz/10dBm
10.7
16.2
13.9
21.0
345 MHz/5dBm
345 MHz/10dBm
10.8
16.3
14.0
21.2
Current in TX mode
11.14
17, 19
ITX_VS2_VAUX
mA
B
on pin VS2 and VAUX 433.92 MHz/5dBm
433.92 MHz/10dBm
10.9
16.3
14.0
21.0
868.3 MHz/10dBm
868.3 MHz/10dBm
11.6
17.8
15.0
23.0
915 MHz/5dBm
915 MHz/10dBm
12.3
20.0
16.0
26.0
CLK enabled
VVSOUT enabled
17,
19,
22, 27
IS_TX = ITX_VS2_VAUX + IVSINT + IEXT
IS_TX = ITX_VS2_VAUX + IEXT
Supply current in
TX mode
11.15
IS_TX
CLK disabled
VVSOUT enabled
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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16. Digital Timing Characteristics
All parameters refer to GND and are valid for Tamb = 25°C. VVS1 = VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery
application (6V)) and VVS2 = 5.0V (Base-station Application(5V)) unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
12 Basic Clock Cycle of the Digital Circuitry
12.1 Basic clock cycle
TDCLK
16/fXTO
16/fXTO
µs
A
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
8
4
2
1
8
4
2
1
Extended basic clock
cycle
× TDCLK
× TDCLK
12.2
TXDCLK
µs
A
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
16
8
4
2
16
8
4
2
× TDCLK
× TDCLK
13
RX Mode/RX Polling Mode
Sleep ×
Sleep ×
XSleep ×
1024 ×
TDCLK
Sleep and XSleep are
defined in control
register 4
XSleep
×
13.1 Sleep time
TSleep
ms
µs
A
A
1024 ×
TDCLK
798.5 × 798.5 ×
13.2 Start-up PLL RX mode from IDLE mode
BR_Range_0
TStartup_PLL
TDCLK
TDCLK
882
498
306
210
× TDCLK
882
498
306
210
× TDCLK
Start-up signal
processing
BR_Range_1
BR_Range_2
BR_Range_3
13.3
TStartup_Sig_Proc
A
Average time during
polling. No RF signal
applied.
fSignal = 1/(2 × tee)
Signal data rate
Manchester
(Lim_min and Lim_max
up to ±50% of tee, see
Figure 9-4 on page 56)
13.4 Time for bit check
Bit-check time for a valid
input signal fSignal
NBit-check = 0
N
Bit-check = 3
3/fSignal
6/fSignal
9/fSignal
3.5/fSignal
1/fSignal 6.5/fSignal
9.5/fSignal
NBit-check = 6
NBit-check = 9
TBit_check
ms
C
A
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
2.0
4.0
8.0
2.5
5.0
10.0
20.0
13.5 Bit-rate range
BR_Range
Kbit/s
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = 25°C. VVS1 = VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery
application (6V)) and VVS2 = 5.0V (Base-station Application(5V)) unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
10 ×
TXDCLK
13.6
31
TDATA_min
µs
A
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
Edge-to-edge time
period of the data signal BR_Range_1
for full sensitivity in RX BR_Range_2
BR_Range_0
200
100
50
500
250
125
62.5
13.7
TDATA
µs
µs
B
A
mode
BR_Range_3
25
14
TX Mode
331.5
× TDCLK × TDCLK
331.5
14.1 Start-up time
From IDLE mode
TStartup
15
Configuration of the Transceiver with 4-wire Serial Interface
CS set-up time to rising
edge of SCK
1.5 ×
TDCLK
15.1
33, 35
33
TCS_setup
TCycle
TSetup
µs
µs
ns
A
A
C
15.2 SCK cycle time
2
SDI_TMDI set-up time
to rising edge of SCK
15.3
15.4
32, 33
250
SDI_TMDI hold time
from rising edge of SCK
32, 33
31, 35
THold
250
ns
ns
C
C
SDO_TMDO enable
15.5 time from rising edge of
CS
TOut_enable
250
250
250
SDO_TMDO output
15.6 delay from falling edge CL = 10 pF
of SCK
31, 35
31, 33
TOut_delay
ns
ns
C
C
SDO_TMDO disable
15.7 time from falling edge of
CS
TOut_disable
1.5 ×
TDCLK
15.8 CS disable time period
35
TCS_disable
TSCK_setup1
TSCK_setup2
TSCK_hold
µs
ns
ns
ns
A
C
C
C
Time period SCK low to
CS high
15.9
33, 35
33, 35
33, 35
250
250
250
Time period SCK low to
CS low
15.10
Time period CS low to
SCK high
15.11
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
92
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16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = 25°C. VVS1 = VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery
application (6V)) and VVS2 = 5.0V (Base-station Application(5V)) unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Start Time Push Button Tn and PWR_ON
Timing of Wake-up via PWR_ON or Tn
16
From OFF mode to IDLE
mode, applications
according to Figure 2-1
on page 7, Figure 2.2 on
page 8 and Figure 2-3
on page 9
XTAL:
Cm < 14 fF (typ. 5 fF)
C0 < 2.2 pF (typ. 1.8 pF)
Rm ≤120Ω (typ. 15Ω)
1 Li battery application
(3V)
PWR_ON high to
positive edge on pin
IRQ (see Figure 7-4 on C3 = C4 = 68 nF
page 46)
C1 = C2 = 68 nF
0.3
0.8
1.3
1.3
ms
ms
ms
16.1
29, 40 TPWR_ON_IRQ_1
B
C5 = 10 nF
2 Li battery application
(6V)
C1 = C4 = 68 nF
C2 = C3 = 2.2 µF
C5 = 10 nF
0.45
Base-station Application
(5V)
C1 = C3 = C4 = 68 nF
C2 = C12 = 2.2 µF
C5 = 10 nF
0.45
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
93
4841D–WIRE–10/07
16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = 25°C. VVS1 = VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery
application (6V)) and VVS2 = 5.0V (Base-station Application(5V)) unless otherwise specified.
No. Parameters
PWR_ON high to
positive edge on pin
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Every mode except OFF
2 ×
TDCLK
16.2
29, 40 TPWR_ON_IRQ_2
µs
A
IRQ (see Figure 7-4 on mode
page 46)
From OFF mode to IDLE
mode, applications
according to Figure 2-1
on page 7, Figure 2.2 on
page 8 and Figure 2-3
on page 9
XTAL:
Cm < 14 fF (typ 5 fF)
C0 < 2.2 pF (typ 1.8 pF)
Rm ≤ 120Ω (typ 15Ω)
1 Li battery application
(3V)
C1 = C2 = 68 nF
C3 = C4 = 68 nF
C5 = 10 nF
Tn low to positive edge
16.3 on pin IRQ (see Figure
7-2 on page 44)
29, 41,
42, 43,
44, 45
0.3
0.8
1.3
1.3
ms
ms
TTn_IRQ
B
2 Li battery application
(6V)
C1 = C4 = 68 nF
C2 = C3 = 2.2 µF
C5 = 10 nF
0.45
0.45
Base-station Application
(5V)
C1 = C3 = C4 = 68 nF
C2 = C12 = 2.2 µF
C5 = 10 nF
ms
µs
29, 41,
42, 43,
44, 45
Push button debounce Every mode except OFF
time mode
8195
× TDCLK
8195
× TDCLK
16.4
TDebounce
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
94
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17. Digital Port Characteristics
All parameters refer to GND and are valid for Tamb = –40°C to +85 °C, VVS1 = VS2 = 2.4V to 3.6V (1 Li battery application (3V)) and
VVS2 = 4.4V to 6.6 V (2 Li battery application (6V)) and VVS2 = 4.75V to 5.25V (Base-station Application (5V)). Typical values at
VVS1 = VVS2 = 3V and Tamb = 25°C unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
17
Digital Ports
CS input
Low level input voltage
0.2 ×
VVSINT
VVSINT = 2.4V to 5.25V
35
35
33
33
32
32
VIl
VIh
VIl
V
V
V
V
V
V
A
A
A
A
A
A
17.1
0.8 ×
VVSINT
High level input voltage VVSINT = 2.4V to 5.25V
VVSINT
SCK input
0.2 ×
VVSINT
VVSINT = 2.4V to 5.25V
Low level input voltage
17.2
17.3
0.8 ×
VVSINT
High level input voltage VVSINT = 2.4V to 5.25V
VIh
VIl
VVSINT
SDI_TMDI input
0.2 ×
VVSINT
VVSINT = 2.4V to 5.25V
Low level input voltage
0.8 ×
VVSINT
High level input voltage VVSINT = 2.4V to 5.25V
VIh
VVSINT
TEST1 input must
17.4 TEST1 input
17.5 TEST2 input
PWR_ON input
always be directly
connected to GND
20
23
0
0
0
V
V
TEST2 input must
always be direct
connected to GND
0
Internal pull-down with
series connection of
40
40
VIl
0.4
V
A
Low level input voltage 40 kΩ ±20% resistor
and diode
17.6
Internal pull-down with
High level input
voltage(1)
series connection of
40 kΩ ±20% resistor
and diode
0.8
× VVS2
VIh
VIl
V
V
A
A
41, 42,
43, 44,
45
Tn input
Internal pull-up resistor
0.2
× VVS2
Low level input voltage of 50 kΩ ±20%
17.7
17.8
41, 42,
43, 44,
45
High level input
voltage(1)
Internal pull-up resistor
of 50 kΩ ±20%
× VVS2
–0.5V
VIh
VIl
V
V
A
A
433_N868 input
Low level input voltage
6
0.25
Input current low
6
6
6
IIl
VIh
IIh
–5
AVCC
1
µA
V
A
A
A
High level input voltage
Input current high
1.7
µA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ωmust be ensured for proper operation over full
temperature range.
95
4841D–WIRE–10/07
17. Digital Port Characteristics (Continued)
All parameters refer to GND and are valid for Tamb = –40°C to +85 °C, VVS1 = VS2 = 2.4V to 3.6V (1 Li battery application (3V)) and
VVS2 = 4.4V to 6.6 V (2 Li battery application (6V)) and VVS2 = 4.75V to 5.25V (Base-station Application (5V)). Typical values at
VVS1 = VVS2 = 3V and Tamb = 25°C unless otherwise specified.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
PWR_H input
Low level input voltage
9
VIl
0.25
V
A
Input current low
9
9
9
IIl
VIh
IIh
–5
AVCC
1
µA
V
A
A
A
17.9
High level input voltage
Input current high
SDO_TMDO output
1.7
µA
VVSINT = 2.4V to 5.25V
31
31
29
29
Vol
Voh
Vol
0.15
0.4
V
V
V
V
B
B
B
B
Saturation voltage low ISDO_TMDO = 250 µA
17.10
17.11
VVSINT = 2.4V to 5.25V
Saturation voltage high
VVSINT
0.4
–
–
VVSINT
0.15
–
–
ISDO_TMDO = –250 µA
IRQ output
Saturation voltage low IIRQ = 250 µA
VVSINT = 2.4V to 5.25V
0.15
0.4
VVSINT = 2.4V to 5.25V
VVSINT
0.4
VVSINT
0.15
Saturation voltage high
CLK output
Voh
IIRQ = –250 µA
VVSINT = 2.4V to 5.25V
ICLK = 100 µA
internal series resistor
30
30
Vol
0.15
0.4
V
V
B
B
Saturation voltage low of 1 kΩ for spurious
emission reduction in
PLL
17.12
VVSINT = 2.4V to 5.25V
ICLK = –100 µA
internal series resistor
of 1 kΩ for spurious
emission reduction in
PLL
VVSINT
0.4
–
–
VVSINT
0.15
–
–
Saturation voltage high
Voh
N_RESET output
Saturation voltage low IN_RESET = 250 µA
VVSINT = 2.4V to 5.25V
28
28
46
46
34
Vol
Voh
Vol
0.15
0.4
0.4
0.4
V
V
V
V
V
B
B
B
B
B
17.13
VVSINT = 2.4V to 5.25V
Saturation voltage high
VVSINT
0.4
VVSINT
0.15
IN_RESET = –250 µA
RX_ACTIVE output
Saturation voltage low IRX_ACTIVE = 25 µA
VVSINT = 2.4V to 5.25V
0.25
17.14
17.15
VVSINT = 2.4V to 5.25V
VAVCC
–0.5
VAVCC
–0.15
Saturation voltage high
DEM_OUT output
Voh
Vol
IRX_ACTIVE = –1500 µA
Open drain output
0.15
Saturation voltage low IDEM_OUT = 250 µA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. If a logic high level is applied to this pin, a minimum serial impedance of 100Ωmust be ensured for proper operation over full
temperature range.
96
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18. Ordering Information
Extended Type Number
ATA5423-PLQW
ATA5425-PLQW
ATA5428-PLQW
ATA5429-PLQW
ATA5423-PLSW
ATA5425-PLSW
ATA5428-PLSW
ATA5429-PLSW
Package
QFN48
QFN48
QFN48
QFN48
QFN48
QFN48
QFN48
QFN48
Remarks
Delivery
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
7 mm × 7 mm
Taped and reeled + Dry pack
Taped and reeled + Dry pack
Taped and reeled + Dry pack
Taped and reeled + Dry pack
Tubes + Dry pack
Tubes + Dry pack
Tubes + Dry pack
Tubes + Dry pack
Note:
W = RoHS compliant
19. Package Information
Package: QFN 48 - 7 x 7
Exposed pad 5.1 x 5.1
Dimensions in mm
Not indicated tolerances ± 0.05
7
1 max.
5.5
5.1
+0
0.05-0.05
37
48
48
1
36
25
1
technical drawings
according to DIN
specifications
12
12
24
13
0.5 nom.
Drawing-No.: 6.543-5089.02-4
Issue: 1; 14.01.03
97
4841D–WIRE–10/07
20. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
4841D-WIRE-10/07
• Put datasheet in a new template
• Put datasheet in a new template
• kBaud replaced through Kbit/s
4841C-WIRE-05/06
• Baud replaced through bit
• Table 9-6 “Interrupt Handling” on page 65 changed
98
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21. Table of Contents
Features..................................................................................................... 1
Applications .............................................................................................. 2
Benefits...................................................................................................... 2
General Description ................................................................................. 3
Application Circuits ................................................................................. 7
RF Transceiver ....................................................................................... 10
XTO .......................................................................................................... 25
Power Supply ......................................................................................... 30
Microcontroller Interface ....................................................................... 36
Digital Control Logic .............................................................................. 36
Transceiver Configuration .................................................................... 49
Operation Modes .................................................................................... 52
1
2
3
4
5
6
7
8
9
10 Absolute Maximum Ratings .................................................................. 66
11 Thermal Resistance ............................................................................... 66
12 Electrical Characteristics: General ...................................................... 67
13 Electrical Characteristics: 1 Li Battery Application (3V) .................... 85
14 Electrical Characteristics: 2 Li Battery Application (6V) .................... 87
15 Electrical Characteristics: Base-station Application (5V) .................. 89
16 Digital Timing Characteristics .............................................................. 91
17 Digital Port Characteristics ................................................................... 95
18 Ordering Information ............................................................................. 97
19 Package Information ............................................................................. 97
20 Revision History ..................................................................................... 98
99
4841D–WIRE–10/07
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4841D–WIRE–10/07
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