ATA5723P3C-TKQW [ATMEL]
Telecom Circuit, 1-Func, PDSO20, 4.40 MM, SSOP-20;
| 型号： | ATA5723P3C-TKQW |
| 厂家： | 
ATMEL |
| 描述： | Telecom Circuit, 1-Func, PDSO20, 4.40 MM, SSOP-20 电信 光电二极管 电信集成电路 |
| 文件： | 总44页 (文件大小：1716K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATA5723C/ATA5724C/ATA5728C
UHF ASK/FSK Receiver
DATASHEET
Features
● Frequency receiving range of (3 versions)
● f0 = 312.5MHz to 317.5MHz or
● f0 = 431.5MHz to 436.5MHz or
● f0 = 868MHz to 870MHz
● 30dB image rejection
● Receiving bandwidth
● BIF = 300kHz for 315MHz/433MHz version
● BIF = 600kHz for 868MHz version
● Fully integrated LC-VCO and PLL loop filter
● Very high sensitivity with power matched LNA
● Atmel® ATA5723C/ATA5724C:
● –107dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
● –113dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
● Atmel ATA5728C:
● –105dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
● –111dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3
● High system IIP3
● –18dBm at 868MHz
● –23dBm at 433MHz
● –24dBm at 315MHz
● System 1-dB compression point
● –27.7dBm at 868MHz
● –32.7dBm at 433MHz
● –33.7dBm at 315MHz
● High large-signal capability at GSM band (blocking –33dBm at +10MHz,
IIP3 = –24dBm at +20MHz)
● Logarithmic RSSI output
● XTO start-up with negative resistor of 1.5kΩ
● 5V to 20V automotive compatible data interface
● Data clock available for Manchester and bi-phase-coded signals
● Programmable digital noise suppression
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● Low power consumption due to configurable polling
● Temperature range –40°C to +105°C
● ESD protection 2kV HBM, all pins
● Communication to microcontroller possible using a single bi-directional data line
● Low-cost solution due to high integration level with minimum external circuitry requirements
● Supply voltage range 4.5V to 5.5V
Benefits
● Low BOM list due to high integration
● Use of low-cost 13MHz crystal
● Lowest average current consumption for application due to self polling feature
● Reuse of Atmel® ATA5743 software
● World-wide coverage with one PCB due to 3 versions are pin compatible
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1.
Description
The Atmel® ATA5723C/ATA5724C/ATA5728C is a multi-chip PLL receiver device supplied in an SSO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems with data rates from 1Kbit/s to
10kBbit/s in Manchester or bi-phase code. Its main applications are in the areas of keyless entry systems, tire pressure
monitoring systems, telemetering, and security technology systems. It can be used in the frequency receiving range of
f0 = 312.5MHz to 317.5MHz, f0 = 431.5MHz to 436.5MHz or f0 = 868MHz to 870MHz for ASK or FSK data transmission. All
the statements made below refer to 315MHz, 433MHz and 868.3MHz applications.
Figure 1-1. System Block Diagram
UHF ASK/FSK
Remote Control Transmitter
UHF ASK/FSK
Remote Control Receiver
T5750/53/54
ATA5723C/
ATA5724C/
ATA5728C
1 to 5 Micro-
controller
Demod.
IF Amp
Control
XTO
XTO
PLL
Antenna Antenna
VCO
PLL
Power
amp.
LNA
VCO
Figure 1-2. Block Diagram
FSK/ASK
Demodulator
and Data Filter
Dem_out
Data
Interface
CDEM
RSSI
DATA
RSSI
Limiter out
RSSI
POLLING/_ON
SENS
IF
Amp.
Sensitivity
Reduction
Polling Circuit
and Control Logic
DATA_CLK
MODE
AVCC
AGND
DGND
DVCC
4. Order
f0 = 1MHz
FE
CLK
IC_ACTIVE
Standby
Logic
LPF
g = 2.2MHz
f
IF
Amp.
Loop
Filter
XTAL2
XTAL1
XTO
Poly-LPF
g = 7MHz
f
f
LC-VCO
f
:2
or :3
LNAREF
LNA_IN
f
LNA
:2
or :4
:128
or :64
LNAGND
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
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2.
Pin Configuration
Figure 2-1. Pinning SSO20
SENS
IC_ACTIVE
CDEM
1
2
3
4
5
6
7
8
9
20 DATA
19 POLLING/_ON
18 DGND
AVCC
17 DATA_CLK
16 MODE
TEST1
ATA5723C/
ATA5724C/
ATA5728C
RSSI
15 DVCC
AGND
14 XTAL2
LNAREF
LNA_IN
13 XTAL1
12 TEST3
11 TEST2
LNAGND 10
Table 2-1. Pin Description
Pin
1
Symbol
Function
SENS
IC_ACTIVE
CDEM
Sensitivity-control resistor
2
IC condition indicator: Low = sleep mode, High = active mode
Lower cut-off frequency data filter
Analog power supply
3
4
AVCC
5
TEST 1
RSSI
Test pin, during operation at GND
RSSI output
6
7
AGND
Analog ground
8
LNAREF
LNA_IN
LNAGND
TEST 2
TEST 3
XTAL1
High-frequency reference node LNA and mixer
RF input
9
10
11
12
13
14
15
DC ground LNA and mixer
Do not connect during operating
Test pin, during operation at GND
Crystal oscillator XTAL connection 1
Crystal oscillator XTAL connection 2
Digital power supply
XTAL2
DVCC
Selecting 315MHz/other versions
16
MODE
Low: 315MHz version (Atmel ATA5723C)
High: 433MHz/868MHz versions (Atmel ATA5724C/ATA5728C)
17
18
19
20
DATA_CLK
DGND
Bit clock of data stream
Digital ground
POLLING/_ON
DATA
Selects polling or receiving mode; Low: receiving mode, High: polling mode
Data output/configuration input
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3.
RF Front-end
The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input signal into about 1MHz IF signal
with a typical image rejection of 30dB. According to Figure Figure 1-2 on page 3 the front-end consists of an LNA (low noise
amplifier), LO (local oscillator), I/Q mixer, polyphase low-pass filter and an IF amplifier.
The PLL generates the drive frequency fLO for the mixer using a fully integrated synthesizer with integrated low noise
LC-VCO (voltage controlled oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency
f
REF = fXTO/2 (868MHz and 433MHz versions) or fREF = fXTO/3 (315MHz version). The integrated LC-VCO generates two or
four times the mixer drive frequency fVCO. The I/Q signals for the mixer are generated with a divide by two or four circuit
(fLO = fVCO/2 for 868MHz version, fLO = fVCO/4 for 433MHz and 315MHz versions). fVCO is divided by a factor of 128 or 64 and
feeds into a phase frequency detector and is compared with fREF. The output of the phase frequency detector is fed into an
integrated loop filter and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using
the following formula:
f
REF = fLO/128 for 868MHz band, fREF = fLO/64 for 433MHz bands, fREF = fLO/64 for 315MHz bands.
The XTO is a two-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage
signal, so that there is only a small voltage at the crystal oscillator frequency at pins XTAL1 and XTAL2. According to
Figure 3-1, the crystal should be connected to GND with two capacitors CL1 and CL2 from XTAL1 and XTAL2 respectively.
The value of these capacitors are recommended by the crystal supplier. Due to an inductive impedance at steady state
oscillation and some PCB parasitics, a lower value of CL1 and CL2 is normally necessary.
The value of CLx should be optimized for the individual board layout to achieve the exact value of fXTO and hence of fLO. (The
best way is to use a crystal with known load resonance frequency to find the right value for this capacitor.) When designing
the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be
considered.
Figure 3-1. XTO Peripherals
V
S
DVCC
XTAL2
XTAL1
TEST3
TEST2
C
C
L2
L1
The nominal frequency fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula
(low-side injection):
f
LO = fRF – fIF
To determine fLO, the construction of the IF filter must be considered. The nominal IF frequency is fIF = 950kHz. To achieve a
good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed
relationship between fIF and fLO
.
fIF = fLO/318 for the 315MHz band (Atmel® ATA5723C)
f
f
IF = fLO/438 for the 433.92MHz band (Atmel ATA5724C)
IF = fLO/915 for the 868.3MHz band (Atmel ATA5728C)
The relationship is designed to achieve the nominal IF frequency of:
f
f
f
IF = 987kHz for the 315MHz and BIF = 300kHz (Atmel ATA5723C)
IF = 987kHz for the 433.92MHz and BIF = 300kHz (Atmel ATA5724C)
IF = 947.8kHz for the 868.3MHz and BIF = 600kHz (Atmel ATA5728C)
The RF input either from an antenna or from an RF generator must be transformed to the RF input pin LNA_IN. The input
impedance of this pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence
the input matching. The RF receiver Atmel ATA5723C/ATA5724C/ATA5728C exhibits its highest sensitivity if the LNA is
power matched. Because of this, matching to a SAW filter, a 50Ω or an antenna is easier. Figure 14-1 on page 29 shows a
typical input matching network for fRF = 315MHz, fRF = 433.92MHz or fRF = 868.3MHz to 50Ω. The input matching network
shown in Table 14-2 on page 29 is the reference network for the parameters given in the electrical characteristics.
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
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4.
Analog Signal Processing
4.1
IF Filter
The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is:
fIF = 987kHz for the 315MHz and BIF = 300kHz (Atmel® ATA5723C)
f
f
IF = 987kHz for the 433.92MHz and BIF = 300kHz (Atmel ATA5724C)
IF = 947.9kHz for the 868.3MHz and BIF = 600kHz (Atmel ATA5728C)
The nominal bandwidth is 300kHz for Atmel ATA5723C and Atmel ATA5724C and 600kHz for Atmel ATA5728C.
4.2
Limiting RSSI Amplifier
The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The
dynamic range of this amplifier is ΔRRSSI = 60dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is
maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of
the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier
is exceeded if the RF input signal is approximately 60dB higher compared to the RF input signal at full sensitivity.
The S/N ratio is not affected by the dynamic range of the RSSI amplifier in FSK mode because only the hard limited signal
from a high-gain limiting amplifier is used by the demodulator.
The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength
of different transmitters can be distinguished. The usable input power range PRef is –100dBm to –55dBm.
Figure 4-1. RSSI Characteristics Atmel ATA5724C
RSSI Characteristics
3.5
4.5V -40 C
°
5V -40 C
°
5.5V -40 C
3
2.5
2
°
4.5V 25 C
°
5V 25 C
°
5.5V 25 C
°
4.5V 85 C
°
5V 85 C
°
5.5V 85 C
°
4.5V 105 C
°
1.5
5V 105 C
°
5.5V 105 C
°
1
-120
-110
-100
-90
-80
-70
-60
-50
-40
PIN (dBm)
The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the
value of the external resistor RSens. RSens is connected between pin SENS and GND or VS. The output of the comparator is
fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity.
If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the pin SENS directly to
GND to get the maximum sensitivity.
If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of
RSens, and the maximum sensitivity is defined by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends
on the signal strength at the output of the RSSI amplifier.
Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the
electrical characteristics refer to a specific input matching. This matching is described and illustrated in Section 14. “Data
Interface” on page 29.
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RSens can be connected to VS or GND using a microcontroller. The receiver can be switched from full sensitivity to reduced
sensitivity or vice versa at any time. In polling mode, the receiver does not wake up if the RF input signal does not exceed
the selected sensitivity. If the receiver is already active, the data stream at pin DATA disappears when the input signal is
lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 4-2 “Steady L State
Limited DATA Output Pattern” is issued at pin DATA to indicate that the receiver is still active (see Figure 13-2 on page 27).
Figure 4-2. Steady L State Limited DATA Output Pattern
DATA
tDATA_min
tDATA_L_max
4.3
FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating
mode of the demodulator is set using the bit ASK/_FSK in the OPMODE register. Logic L sets the demodulator to FSK,
applying H to ASK mode.
In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value
where a good signal to noise ratio is achieved. This circuit also implements the effective suppression of any kind of in-band
noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10dB the data
signal can be detected properly. However, better values are found for many modulation schemes of the competing
transmitter.
The FSK demodulator is intended to be used for an FSK deviation of 10kHz ≤ Δf ≤ 100kHz. The data signal in FSK mode can
be detected if the S/N (ratio to suppress in-band noise signals) exceeds about 2dB. This value is valid for all modulation
schemes of a disturber signal.
The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The
data filter improves the S/N ratio as its pass-band can be adopted to the characteristics of the data signal. The data filter
consists of a 1st order high-pass and a 2nd order low-pass filter.
The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of
the high-pass filter is defined by the following formula:
1
---------------------------------------------------------
fcu_DF =
2 × π × 30 kΩ × CDEM
In self-polling mode the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be
increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter
requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics.
The cut-off frequency of the low-pass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is
defined in the OPMODE register (refer to Section 11. “Configuring the Receiver” on page 22). The BR_Range must be set in
accordance to the baud-rate used.
The Atmel® ATA5723C/ATA5724C/ATA5728C is designed to operate with data coding where the DC level of the data signal
is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always
remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2dB in that condition.
Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the
electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
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5.
Receiving Characteristics
The Atmel® RF receiver ATA5723C/ATA5724C/ATA5728C can be operated with and without a SAW front-end filter. In a
typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving
frequency response without a SAW front-end filter is illustrated in Figure 5-1. This example relates to ASK mode. FSK mode
exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion
loss of about 3dB must be considered, but the overall selectivity is much better.
When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the
IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation
of the Atmel ATA5723C/ATA5724C/ATA5728C. Low-cost crystals are specified to be within ±90ppm over tolerance,
temperature, and aging. The XTO deviation of the Atmel ATA5723C/ATA5724C/ATA5728C is an additional deviation due to
the XTO circuit. This deviation is specified to be ±10ppm worst case for a crystal with CM = 7fF. If a crystal of ±90ppm is
used, the total deviation is ±100ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are
equivalent in ASK mode but not in FSK mode.
Figure 5-1. Narrow Band Receiving Frequency Response Atmel ATA5724C
Image Rejection versus RF Frequency
10
0
4.5V -40 C
°
5V -40 C
°
-10
-20
-30
-40
-50
-60
-70
5.5V -40 C
°
4.5V 25 C
°
5V 25 C
°
5.5V 25 C
°
4.5V 105 C
°
5V 105 C
°
5.5V 105 C
°
430
431
432
433
434
435
436
437
438
(MHz)
6.
Polling Circuit and Control Logic
The receiver is designed to consume less than 1mA while being sensitive to signals from a corresponding transmitter. This is
achieved using the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-
check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active
and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most
of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is
disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the
user to meet the specifications in terms of current consumption, system response time, data rate etc.
The receiver is very flexible with regards to the number of connection wires to the microcontroller. It can be either operated
by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional
ports.
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7.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived
from the crystal oscillator (XTO) in combination with a divide by 28 or 30 circuit. According to Section 3. “RF Front-end” on
page 5, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating
frequency of the local oscillator (fLO). The basic clock cycle for Atmel® ATA5724C and Atmel ATA5728C is TClk 28/fXTO giving
T
T
Clk = 2.066µs for fRF = 868.3MHz and TClk = 2.069µs for fRF = 433.92MHz. For Atmel ATA5723C the basic clock cycle is
Clk = 30/fREF giving TClk = 2.0382µs for fRF = 315MHz.
TClk controls the following application-relevant parameters:
●
●
●
●
●
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (fIF0)
Most applications are dominated by three transmission frequencies: fTransmit = 315MHz is mainly used in USA,
Transmit = 868.3MHz and 433.92MHz in Europe. All timings are based on TClk. For the aforementioned frequencies, TClk is
given as:
f
●
●
●
Application 315MHz band (fXTO = 14.71875MHz, fLO = 314.13MHz, TClk = 2.0382µs)
Application 868.3MHz band (fXTO = 13.55234MHz, fLO = 867.35MHz, TClk = 2.066µs)
Application 433.92MHz band (fXTO = 13.52875MHz, fLO = 432.93MHz, TClk = 2.0696µs)
For calculation of TClk for applications using other frequency bands, see table in Section 18. “Electrical Characteristics Atmel
ATA5724C, ATA5728C” on page 34.
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the
OPMODE register. This clock cycle TXClk is defined by the following formulas:
BR_Range = BR_Range0:
BR_Range1:
TXClk = 8 × TClk
TXClk = 4 × TClk
TXClk = 2 × TClk
TXClk = 1 × TClk
BR_Range2:
BR_Range3:
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8.
Polling Mode
According to Figure 8-1 on page 11, the receiver stays in polling mode in a continuous cycle of three different modes. In
sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff
.
During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the
incoming data stream is analyzed bit-by-bit and compared with a valid transmitter signal. If no valid signal is present, the
receiver is set back to sleep mode after the period TBit-check. This period varies according to each check as it is a statistical
process. An average value for TBitcheck is given in the electrical characteristics. During TStartup and TBit-check, the current
consumption is IS = ISon. The condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in
polling mode is dependent on the duty cycle of the active mode and can be calculated as:
I
× T
+ I
× (T
+ T
)
Bit-check
Soff
Sleep
Son
Startup
--------------------------------------------------------------------------------------------------------
=
I
Spoll
T
+ T
+ T
Startup Bit-check
Sleep
During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted
command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on
the polling parameters TSleep, TStartup, TBit-check and the start-up time of a connected microcontroller, TStart_microcontroller. Thus,
T
Bit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested.
The following formula indicates how to calculate the preburst length.
Preburst ≥ TSleep + TStartup + TBit-check + TStart_microcontroller
T
8.1
Sleep Mode
The length of period TSleep is defined by the 5-bit word sleep of the OPMODE register, the extension factor XSleep (according
to Table 11-8 on page 24), and the basic clock cycle TClk. It is calculated to be:
TSleep = Sleep × XSleep × 1024 × TClk
The maximum value of TSleep is about 60ms if XSleep is set to 1. The time resolution is about 2ms in that case. The sleep time
can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to “1”.
Setting the configuration word sleep to its maximal value puts the receiver into a permanent sleep mode. The receiver
remains in this state until another value for Sleep is programmed into the OPMODE register. This is particularly useful when
several devices share a single data line. (It can also be used for microcontroller polling: using pin POLLING/_ON, the
receiver can be switched on and off.)
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Figure 8-1. Polling Mode Flow Chart
Sleep Mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic are
enabled.
Output level on Pin IC_ACTIVE = > low
Sleep:
XSleep
TClk
TStartup
5-bit word defined by Sleep 0 to
Sleep 4 in OPMODE register
IS = ISoff
TSleep = Sleep x XSleep x 1024 x TClk
:
Extension factor defined by
XSleepStd according to Table 11-8
:
Basic clock cycle defined by fXTO
and Pin MODE
Start-up Mode:
:
Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud 0 and Baud 1 in
the OPMODE register.
The signal processing circuits are
enabled. After the start-up time (TStartup
all circuits are in stable
)
condition and ready to receive.
Output level on Pin IC_ACTIVE = > high
IS = ISon
TStartup
Bit-check Mode:
The incoming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
TBit-check
:
Depends on the result of the bit check
If the bit check is ok, TBit-check
depends on the number of bits to be
checked (NBit-check) and on the
data rate used.
Output level on Pin IC_ACTIVE = > high
IS = ISon
TBit-check
Bit Check
OK ?
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on TClk. The baud-rate range is
defined by Baud 0 and Baud 1 in the
OPMODE register.
NO
YES
Receiving Mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
Polling/_ON.
Output level on Pin IC_ACTIVE = > high
IS = ISon
OFF Command
8.2
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding
transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal
edges are continuously compared to a programmable time window. The maximum number of these edge-to-edge tests,
before the receiver switches to receiving mode, is also programmable.
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8.3
Configuring the Bit Check
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify one bit. This is valid for
Manchester, bi-phase, and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6,
or 9 bits using the variable NBit-check in the OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively.
If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a
valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is
not dependent on NBit-check. Figure 8-2 shows an example where three bits are tested successfully and the data signal is
transferred to pin DATA.
Figure 8-2. Timing Diagram for Complete Successful Bit Check
Bit Check ok
(Number of checked Bits: 3)
IC_ACTIVE
Bit Check
1/2 Bit
1/2 Bit 1/2 Bit
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Data_out (DATA)
TStart-up
TBit-check
Start-up Mode
Start-check Mode
Receiving Mode
According to Figure 8-3, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee
is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check continues. If tee is smaller than
T
Lim_min or tee exceeds TLim_max, the bit check is terminated and the receiver switches to sleep mode.
Figure 8-3. Valid Time Window for Bit Check
1/fSig
tee
Dem_out
TLim_min
TLim_max
For best noise immunity using a low span between TLim_min and TLim_max is recommended. This is achieved using a fixed
frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or a “10101...” sequence in Manchester or bi-phase
is suitable for this. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±30%
regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the
bit-check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below.
T
Lim_min = Lim_min × TXClk
TLim_max = (Lim_max – 1) × TXClk
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The
time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined
according to the Section 8.6 “Digital Signal Processing” on page 14. The lower limit should be set to Lim_min ≥ 10. The
maximum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving
mode due to noise.
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Figure 8-4, Figure 8-5, and Figure 8-6 illustrate the bit check for the bit-check limits Lim_min = 14 and Lim_max = 24. When
the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/FSK demodulator
(Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the
cycle TXClk
.
Figure 8-4 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min
and Lim_max at the occurrence of a signal edge. In Figure 8-5 the bit check fails as the value CV_Lim is lower than the limit
Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 8-6.
Figure 8-4. Timing Diagram During Bit Check
Bit Check ok
Bit Check ok
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit Check
1/2 Bit
1/2 Bit
1/2 Bit
Dem_out
Bit-check
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9 10 11 12 13 141516 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1 2 3 4
counter
TXClk
TStart-up
TBit-check
Start-up Mode
Bit-check Mode
Figure 8-5. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
(Lim_min = 14, Lim_max = 24)
Bit Check failed (CV_Lim_ < Lim_min)
IC_ACTIVE
Bit Check
1/2 Bit
Dem_out
Bit-check
0
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9 10 1112
0
counter
TStart-up
TBit-check
Bit-check Mode
TSleep
Start-up Mode
Sleep Mode
Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)
(Lim_min = 14, Lim_max = 24)
Bit Check failed (CV_Lim ≥ Lim_max)
IC_ACTIVE
Bit Check
1/2 Bit
Dem_out
Bit-check
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9 10 11 12 13 1415 16 17 18 19 2021 222324
0
counter
TStart-up
TBit-check
Bit-check Mode
TSleep
Start-up Mode
Sleep Mode
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8.4
Duration of the Bit Check
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The
bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the
electrical characteristics. TBit-check depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a
lower value for TBit-check resulting in a lower current consumption in polling mode.
In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the
checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check requiring a higher value for
the transmitter pre-burst TPreburst
.
8.5
8.6
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to
Figure 8-2 on page 12, the internal data signal is switched to pin DATA in that case, and the data clock is available after the
start bit has been detected (see Figure 9-1 on page 17). A connected microcontroller can be woken up by the negative edge
at pin DATA or by the data clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling
mode explicitly.
Digital Signal Processing
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into
the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 8-7 illustrates how
Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can
change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an
integral multiple of TXClk
.
The minimum time period between two edges of the data signal is limited to tee ≥ TDATA_min. This implies an efficient
suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases
the interrupt handling of a connected microcontroller.
The maximum time period for DATA to stay low is limited to TDATA_L_max. This function is employed to ensure a finite
response time in programming or switching off the receiver via pin DATA. TDATA_L_max is therefore longer than the maximum
time period indicated by the transmitter data stream. Figure 8-9 on page 15 gives an example where Dem_out remains Low
after the receiver has switched to receiving mode.
Figure 8-7. Synchronization of the Demodulator Output
TXClk
Clock bit-check
counter
Dem_out
Data_out (DATA)
tee
Figure 8-8. Debouncing of the Demodulator Output
Dem_out
Data_out (DATA)
tDATA_min
tDATA_min
tDATA_min
tee
tee
tee
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Figure 8-9. Steady L State Limited DATA Output Pattern after Transmission
IC_ACTIVE
Bit Check
Dem_out
Data_out (DATA)
tDATA_min
tDATA_L_max
Start-up Mode
Bit-check Mode
Receiving Mode
After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE
register, the output signal at pin DATA is high or random noise pulses appear at pin DATA (see Section 10. “Digital Noise
Suppression” on page 20). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher
than TDATA_min
.
8.7
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON.
When using pin DATA, this pin must be pulled to low by the connected microcontroller for the period t1. Figure 8-10 on page
15 illustrates the timing of the OFF command (see Figure 13-2 on page 27). The minimum value of t1 depends on the
BR_Range. The maximum value for t1 is not limited; however, exceeding the specified value to prevent erasing the reset
marker is not recommended. Note also that an internal reset for the OPMODE and the LIMIT register is generated if t1
exceeds the specified values. This item is explained in more detail in the Section 11. “Configuring the Receiver” on page 22.
Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to “1” during the register configuration. Only
one sync pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time TSleep elapses after the OFF
command. Note that the capacitive load at pin DATA is limited (see Section 14. “Data Interface” on page 29).
Figure 8-10. Timing Diagram of the OFF Command using Pin DATA
IC_ACTIVE
t1
t2
t3
t5
t4
t10
t7
Out1
(Microcontroller)
X
X
Data_out (DATA)
Serial bi-directional
Data Line
Bit 1
("1")
(Start Bit)
OFF-command
TSleep
TStart-up
Receiving Mode
Sleep Mode
Start-up Mode
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Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON
IC_ACTIVE
ton2
ton3
Bit Check ok
POLLING/_ON
X
X
X
Data_out (DATA)
Serial bi-directional
Data Line
X
Receiving Mode
Sleep Mode Start-up Mode Bit-check Mode
Receiving Mode
Figure 8-12. Activating the Receiving Mode using Pin POLLING/_ON
IC_ACTIVE
ton1
POLLING/_ON
X
Data_out (DATA)
Serial bi-directional
Data Line
X
Sleep Mode
Start-up Mode
Receiving Mode
Figure 8-11 illustrates how to set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must
be held to low for the time period ton2. After the positive edge on pin POLLING/_ON and the delay ton3, the polling mode is
active and the sleep time TSleep elapses.
Using the POLLING/_ON command is faster than using pin DATA; however, this requires the use of an additional connection
to the microcontroller.
Figure 8-12 illustrates how to set the receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must
be held to low. After the delay ton1, the receiver changes from sleep mode to start-up mode regardless of the programmed
values for TSleep and NBit-check. As long as POLLING/_ON is held to low, the values for TSleep and NBit-check is ignored, but not
deleted (see Section 10. “Digital Noise Suppression” on page 20).
If the receiver is polled exclusively by a microcontroller, TSleep must be programmed to 31 (permanent sleep mode). In this
case the receiver remains in sleep mode as long as POLLING/_ON is held to high.
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9.
Data Clock
The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock,
a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and bi-phase coded
signals.
9.1
Generation of the Data Clock
After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at
pin DATA. In receiving mode, the data clock control logic (Manchester/bi-phase demodulator) is active and examines the
incoming data stream. This is done, as with the bit check, by subsequent time frame checks where the distance between two
edges is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page 17, only two distances
between two edges in Manchester and bi-phase coded signals are valid (T and 2T).
The limits for T are the same as used with the bit check. They can be programmed in the LIMIT-register (Lim_min and
Lim_max, see Table 11-10 on page 25 and Table 11-11 on page 25).
The limits for 2T are calculated as follows:
Lower limit of 2T:
Upper limit of 2T:
Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2
Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2
(If the result for ‘Lim_min_2T’ or ‘Lim_max_2T’ is not an integer value, it is rounded up.)
The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the
delay tDelay after the edge on pin DATA (see Figure 9-1 on page 17).
If the data clock control logic detects a timing or logical error (Manchester code violation), as illustrated in Figure 9-2 on page
18 and Figure 9-3 on page 18, it stops the output of the data clock. The receiver remains in receiving mode and starts with
the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with
the generation of the data clock (see Figure 9-4 on page 18).
Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. If the bit check is set to 0
or the receiver is set to receiving mode using the pin POLLING/_ON, the data clock is available if the data clock control logic
has detected the distance 2T (Start bit).
Note that for bi-phase-coded signals, the data clock is issued at the end of the bit.
Figure 9-1. Timing Diagram of the Data Clock
Preburst
Data
Bit Check ok
'1'
T
2T
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
tDelay
tP_Data_Clk
Bit-check Mode
Start bit
Receiving Mode,
data clock control logic active
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Figure 9-2. Data Clock Disappears Because of a Timing Error
Data
Timing error
'1'
Tee < TLim_min or TLim_max < Tee < TLim_min_2T or Tee > TLim_max_2T
Tee
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Receiving Mode,
data clock control
logic active
Receiving Mode,
bit check active
Figure 9-3. Data Clock Disappears Because of a Logical Error
Data
Logical error (Manchester code violation)
'1'
'1'
'1'
'0'
'1'
'1'
'?'
'0'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Receiving Mode,
data clock control
logic active
Receiving Mode,
bit check active
Figure 9-4. Output of the Data Clock After a Successful Bit Check
Data
Bit Check ok
'1'
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Dem_out
Data_out (DATA)
DATA_CLK
Start bit
Receiving Mode,
bit check active
Receiving Mode,
data clock control
logic active
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The delay of the data clock is calculated as follows: tDelay = tDelay1 + tDelay2
tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1 depends on the capacitive
load CL at pin DATA and the external pull-up resistor Rpup. For the falling edge, tDelay1 depends additionally on the external
voltage VX (see Figure 9-5, Figure 9-6 and Figure 13-2 on page 27). When the level of Data_In is equal to the level of
Data_Out, the data clock is issued after an additional delay tDelay2
.
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at pin DATA is exceeded, the
data clock disappears (see Section 14. “Data Interface” on page 29).
Figure 9-5. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
VX
VIH = 0.65 VS
VS
VII = 0.35
Serial bi-directional
Data Line
Data_In
DATA_CLK
tDelay1
tDelay2
tDelay tP_Data_Clk
Figure 9-6. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data_Out
VX
VS
VS
VIH = 0.65
VII = 0.35
Serial bi-directional
Data Line
Data_In
DATA_CLK
tDelay1
tDelay2
tDelay tP_Data_Clk
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10. Digital Noise Suppression
After a data transmission, digital noise appears on the data output (see Figure 10-1). To prevent digital noise keeping the
connected microcontroller busy, it can be suppressed in two different ways:
●
●
Automatic noise suppression
Controlled noise suppression by the microcontroller
10.1 Automatic Noise Suppression
The receiver changes to bit-check mode at the end of a valid data stream if the bit Noise_Disable (Table 11-9 on page 24) in
the OPMODE register is set to 1 (default). The digital noise is suppressed, and the level at pin DATA is high. The receiver
changes back to receiving mode, if the bit check was successful.
This method of noise suppression is recommended if the data stream is Manchester or bi-phase coded and is active after
power on.
Figure 10-3 illustrates the behavior of the data output at the end of a data stream. If the last period of the data stream is a
high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-
rate range.
Figure 10-1. Output of Digital Noise at the End of the Data Stream
Bit Check ok
Bit Check ok
Preburst
Data
Digital Noise
Digital Noise Preburst
Data
Digital Noise
Data_out (DATA)
DATA_CLK
Bit-check
mode
Receiving Mode,
data clock control
logic active
Receiving Mode,
bit check active
Receiving Mode,
data clock control
logic active
Receiving Mode,
bit check active
Figure 10-2. Automatic Noise Suppression
Bit Check ok
Bit Check ok
Preburst
Data
Preburst
Data
Data_out (DATA)
DATA_CLK
Bit-check
Mode
Receiving Mode,
data clock control
logic active
Bit-check
Mode
Receiving Mode,
data clock control
logic active
Bit-check
Mode
Figure 10-3. Occurrence of a Pulse at the End of the Data Stream
Timing error
tee < TLim_min or TLim_max < tee < tLim_min_2T or tee > TLim_max_2T
Tee
Data Stream
'1'
Digital Noise
'1'
'1'
Dem_out
Data_out (DATA)
DATA_CLK
Tpulse
Receiving Mode,
data clock control
logic active
Bit-check Mode
20
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10.2 Controlled Noise Suppression by the Microcontroller
Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see Table 11-9 on page 24) in the OPMODE
register is set to 0. To suppress the noise, the pin POLLING/_ON must be set to low. The receiver remains in receiving
mode. The OFF command then causes a change to start-up mode. The programmed sleep time (see Table 11-7 on page 24)
is not executed because the level at pin POLLING/_ON is low; however, the bit check is active in this case. The OFF
command also activates the bit check if the pin POLLING/_ON is held to low. The receiver changes back to receiving mode
if the bit check was successful. To activate the polling mode at the end of the data transmission, the pin POLLING/_ON must
be set to high. This way of suppressing the noise is recommended if the data stream is not Manchester or bi-phase coded.
Figure 10-4. Controlled Noise Suppression
Bit Check ok
OFF-command
Bit Check ok
Serial bi-directional
Data Line
Preburst
Data Digital Noise
Preburst
Data
Digital Noise
(DATA_CLK)
POLLING/_ON
Bit-check
Mode
Receiving Mode
Start-up Bit-check
Mode Mode
Receiving Mode
Sleep
Mode
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11. Configuring the Receiver
The Atmel® ATA5723C/ATA5724C/ATA5728C receiver is configured using two 12-bit RAM registers called OPMODE and
LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to
a voltage drop, this condition is indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must
be reprogrammed. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default
mode, there is no need to program the registers. Table 11-3 on page 22 shows the structure of the registers. According to
Table 11-1, bit 1 defines whether the receiver is set back to polling mode using the OFF command (see “Receiving Mode” on
page 14) or whether it is programmed. Bit 2 represents the register address. It selects the appropriate register to be
programmed. For high programming reliability, bit 15 (Stop bit), at the end of the programming operation, must be set to 0.
Table 11-1. Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1
Bit 2
Action
1
0
0
x
1
0
The receiver is set back to polling mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Table 11-2. Effect of Bit 15 on Programming the Register
Bit 15
Action
0
1
The values are written into the register (OPMODE or LIMIT)
The values are not written into the register
Table 11-3. Effect of the Configuration Words within the Registers
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
OFF command
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
OPMODE register
Modu-
lation
Noise
Suppression
BR_Range
NBit-check
BitChk1 BitChk0
Sleep
XSleep
0
1
0
ASK/
_FSK
Noise_
Disable
Baud1
0
Baud0
0
Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 XSleepStd
Default
values of
Bit 3...14
0
1
0
0
0
1
1
0
0
1
–
–
LIMIT register
–
–
Lim_min
Lim_max
Lim_
0
0
Lim_
min5
Lim_
min4
Lim_
min3
Lim_
min2
Lim_
min1
Lim_
min0
Lim_
max5
Lim_
max4
Lim_
Lim_
max1
Lim_
max0
0
–
max3
max2
Default
values of
Bit 3...14
0
1
0
1
0
1
1
0
1
0
0
1
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The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each
word.
BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check
limits TLim_min and TLim_max as shown in Table 11-10 on page 25 and Table 11-11 on page 25.
Table 11-4. Effect of the configuration word BR_Range
BR_Range
Baud1
Baud0
Baud-rate Range/Extension Factor for Bit-check Limits (XLim)
BR_Range0
0
0
(BR_Range0 = 1.0Kbit/s to 1.8Kbit/s)
XLim = 8 (default)
BR_Range1
0
1
1
1
0
1
(BR_Range1 = 1.8Kbit/s to 3.2Kbit/s)
XLim = 4
BR_Range2
(BR_Range2 = 3.2Kbit/s to 5.6Kbit/s)
XLim = 2
BR_Range3
(BR_Range3 = 5.6Kbit/s to 10Kbit/s)
XLim = 1
Table 11-5. Effect of the Configuration word NBit-check
NBit-check
BitChk1
BitChk0
Number of Bits to be Checked
0
0
1
1
0
1
0
1
0
3 (default)
6
9
Table 11-6. Effect of the Configuration Bit Modulation
Modulation
Selected Modulation
ASK/_FSK
–
0
1
FSK (default)
ASK
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Table 11-7. Effect of the Configuration Word Sleep
Sleep
Start Value for Sleep Counter
Sleep4
Sleep3
Sleep2
Sleep1
Sleep0
(TSleep = Sleep × XSleep × 1024 × TClk)
0 (Receiver polls continuously until a valid signal
occurs)
0
0
0
0
0
If XSleep = 1
TSleep = 2.11ms for fRF = 868.3MHz,
TSleep = 2.12ms for fRF = 433.92MHz
TSleep = 2.08ms for fRF = 315MHz
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
2
3
...
...
...
...
...
...
If XSleep = 1
T
Sleep = 12.69ms for fRF = 868.3MHz,
0
0
1
1
0
TSleep = 12.71ms for fRF = 433.92MHz
TSleep = 12.52ms for fRF = 315MHz
...
1
...
1
...
1
...
0
...
1
...
29
1
1
1
1
0
30
1
1
1
1
1
31 (permanent sleep mode)
Table 11-8. Effect of the Configuration Bit XSleep
XSleep
Extension Factor for Sleep Time
XSleepStd
(TSleep = Sleep × XSleep × 1024 × TClk)
0
1
1 (default)
8
Table 11-9. Effect of the Configuration Bit Noise Suppression
Noise Suppression
Noise_Disable
Suppression of the Digital Noise at Pin DATA
Noise suppression is inactive
0
1
Noise suppression is active (default)
24
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
Table 11-10. Effect of the Configuration Word Lim_min
Lim_min(1) (Lim_min < 10 is not Applicable)
Lower Limit Value for Bit Check
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min × XLim × TClk)
0
0
0
..
0
0
0
..
1
1
1
..
0
0
1
..
1
1
0
..
0
1
0
..
10
11
12
21 (default, BR_Range0)
(TLim_min = 347µs for fRF = 868.3MHz
TLim_min = 347µs for fRF = 433.92MHz
TLim_min = 342µs for fRF = 315MHz)
0
1
0
1
0
1
..
1
1
1
..
1
1
1
..
1
1
1
..
1
1
1
..
0
1
1
..
1
0
1
61
62
63
Note:
1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 17).
Table 11-11. Effect of the Configuration Word Lim_max
Lim_max(1) (Lim_max < 12 is not applicable)
Upper Limit Value for Bit Check
Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (TLim_max = (Lim_max – 1) × XLim × TClk
)
0
0
0
..
0
0
0
..
1
1
1
..
1
1
1
..
0
0
1
..
0
1
0
..
12
13
14
41 (default, BR_Range0)
(TLim_max = 661µs for fRF = 868.3MHz
TLim_max = 662µs for fRF = 433.92MHz
TLim_max = 652µs for fRF = 315MHz)
1
0
1
0
0
1
..
1
1
1
..
1
1
1
..
1
1
1
..
1
1
1
..
0
1
1
..
1
0
1
61
62
63
Note:
1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 17).
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
25
9248D–RKE–10/14
12. Conservation of the Register Information
The Atmel® ATA5723C/ATA5724C uses an integrated power-on reset and brown-out detection circuitry as a mechanism to
preserve the RAM register information.
According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage
VThReset. The default parameters are programmed into the configuration registers in that condition. The POR is cancelled
after the minimum reset period tRst when VS exceeds VThReset. A POR is also generated when the supply voltage of the
receiver is turned on.
To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the
fixed frequency fRM at a 50% duty-cycle. RM can be cancelled using a low pulse t1 at pin DATA. The RM has the following
characteristics:
●
fRM is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be misinterpreted by the
connected microcontroller.
●
If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled accidentally if t1 is applied as
described in the proposal in Section 13. “Programming the Configuration Register” on page 27.
Using this conservation mechanism, the receiver cannot lose its register information without communicating this condition
using the reset marker RM.
Figure 12-1. Generation of the Power-on Reset
VS
VThreset
POR
tRst
Data_out (DATA)
X
1/fRM
26
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
13. Programming the Configuration Register
Figure 13-1. Timing of the Register Programming
IC_ACTIVE
t1
t2
t3
t5
t9
t8
t4
t6
t7
Out1
(Microcontroller)
X
X
Data_out (DATA)
Serial bi-directional
Data Line
Bit 1
("0")
(Start Bit)
Bit 2
("1")
(Register
select)
Bit 14
("0")
(Poll 8)
Bit 15
("0")
(Stop Bit)
TSleep TStart-up
Programming Frame
Receiving
Mode
Sleep Start-up
Mode Mode
Figure 13-2. Data Interface
V
X = 5V to 20V
ATA5723C
ATA5724C
ATA5728C
Microcontroller
VS = 4.5V to 5.5V
Rpup
DATA
I/O
0V/5V
0V to 20V
Input
Interface
Data_in
Serial bi-directional data line
CL
ID
Data_out
Out1 (Microcontroller)
The configuration registers are serially programmed using the bi-directional data line as shown in Figure 13-1 and
Figure 13-2.
To start programming, the serial data line DATA is pulled to low by the microcontroller for the time period t1. When DATA
has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, the
receiver emits 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming
window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. The individual
bits are set within the programming window. If the microcontroller pulls down pin DATA for the time period t7 during t5, the
corresponding bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 15 bits are programmed this way.
The time frame to program a bit is defined by t6.
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
27
9248D–RKE–10/14
Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack)
occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack
should be used to verify that the mode word was correctly transferred to the register. The register must be programmed
twice in that case.
A register can be programmed when the receiver is in both sleep-mode and active mode. During programming, the LNA, LO,
low-pass filter, IF-amplifier, and the FSK/MSK demodulator are disabled. The t1 pulse is used to start the programming or to
switch the receiver back to polling mode (OFF command). (The receiver is switched back to polling mode with the OFF
command if bit 1 is set to “1”.) The following convention should be considered for the length of the programming start pulse
t1:
Using a t1 value of t1 (min) < t1 < 5632 TClk (where t1 (min) is the minimum specified value for the relevant BR_Range)
when the receiver is active i.e., not in reset mode initiates the programming or OFF command. However, if this t1 value is
used when the receiver is in reset mode, programming or OFF command is NOT initiated and RM remains present at pin
DATA. Note, the RM cannot be deleted when using this t1 value.
Using a t1 value of t1 > 7936 × TClk, programming or OFF command is initiated when the receiver is in both reset mode and
active mode. The registers PMODE and LIMIT are set to the default values and the RM is deleted, if present. This t1 values
can be used if the connected microcontroller detects an RM. Additionally, this t1 value can generally be used if the receiver
operates in default mode.
Note that the capacitive load at pin DATA is limited.
28
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
14. Data Interface
The data interface (see Figure 13-2 on page 27) is designed for automotive requirements. It can be connected using the pull-
up resistor Rpup up to 20V and is short-circuit-protected.
The applicable pull-up resistor Rpup depends on the load capacity CL at pin DATA and the selected BR_range (see
Table 14-1).
Table 14-1. Applicable Rpup
-
BR_range
Applicable Rpup
1.6kΩ to 47kΩ
1.6kΩ to 22kΩ
1.6kΩ to 12kΩ
1.6kΩ to 5.6kΩ
1.6kΩ to 470kΩ
1.6kΩ to 220kΩ
1.6kΩ to 120kΩ
1.6kΩ to 56kΩ
B0
B1
B2
B3
B0
B1
B2
B3
CL ≤ 1nF
CL ≤ 100pF
Figure 14-1. Application Circuit: fRF = 315MHz(1), 433.92MHz or without SAW Filter
VS
RSSI
C7
4.7μF
10%
IC_ACTIVE
+
R2
Sensitivity Reduction
VX = 5V to 20V
56kΩ to 150kΩ
GND
R3
1.6kΩ
C14
39nF
5%
1
2
3
20
19
18
17
16
SENS
DATA
DATA
IC_ACTIVE POLLING/_ON
POLLING/_ON
CDEM
DGND
DATA_CLK
MODE
DATA_CLK
4
5
6
7
AVCC
TEST1
RSSI
C12
ATA5723C
C13
10nF
10%
10nF
10%
ATA5724C
ATA5728C
15
14
DVCC
XTAL2
CL2
CL1
AGND
F
crystal
8
9
13
12
11
C17
RF_IN
LNAREF
LNA_IN
XTAL1
TEST3
TEST2
10
C16
LNAGND
L1
Note:
For 315MHz application pin MODE must be connected to GND.
Table 14-2. Input Matching to 50Ω
LNA Matching
Crystal Frequency
fXTAL (MHz)
RF Frequency (MHz)
C16 (pF)
C17 (pF)
L1 (nH)
39
315
Not connected
Not connected
1
3
3
3
14.71875
13.52875
13.55234
433.92
868.3
20
6.8
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
29
9248D–RKE–10/14
15. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
Max.
6
Unit
V
Supply voltage
Power dissipation
Ptot
1000
150
+125
+105
10
mW
°C
Junction temperature
Storage temperature
Ambient temperature
Maximum input level, input matched to 50Ω
Tj
Tstg
–55
–40
°C
Tamb
Pin_max
°C
dBm
16. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
100
K/W
30
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
17. Electrical Characteristics Atmel ATA5723C
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
fRF = 315MHz
14.71875MHz Oscillator
Variable Oscillator
Test
No. Parameter Conditions
Symbol
Min.
Typ.
Max.
Min.
Typ. Max.
Min.
Typ.
Max.
Unit Type*
1
Basic Clock Cycle of the Digital Circuitry
Basic clock
cycle
1.1
TClk
2.0382
2.0382
30/fXTO
30/fXTO
µs
A
A
BR_Range0
BR_Range1
BR_Range2
BR_Range3
16.3057
8.1528
4.0764
2.0382
16.3057
8.1528
4.0764
2.0382
8 × TClk
4 × TClk
2 × TClk
1 × TClk
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
Extended
1.2 basic clock
cycle
TXClk
2
Polling Mode
Sleep time
(see
Figure 8-1,
Figure 8-10
and
Sleep and
XSleep are
defined in the
OPMODE
register
Sleep ×
Sleep ×
XSleep ×
1024 ×
2.0382
Sleep ×
Sleep ×
XSleep
×
2.1
TSleep
XSleep
×
XSleep
×
ms
A
A
1024 ×
2.0382
1024 × TClk
1024 × TClk
Figure 13-1)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1827
1044
1044
653
1827
1044
1044
653
896.5
512.5
512.5
320.5
× TClk
896.5
512.5
512.5
320.5
× TClk
µs
µs
µs
µs
µs
Start-up time
(see Figure
8-1 and
2.2
TStartup
Figure 8-4)
Average bit-
check time
while polling,
no RF applied
(see Figure 8-5
and Figure 8-6)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Time for bit
2.3 check (see
Figure 8-1
TBit-check
C
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
ms
ms
ms
ms
Bit-check time
for a valid input
signal fSig (see
Figure 8-5)
Time for bit
2.4 check (see
Figure 8-1
TBit-check
C
N
N
N
N
Bit-check = 0
Bit-check = 3
Bit-check = 6
Bit-check = 9
1 × TXClk
3/fSig
6/fSig
1 × TXClk
3.5/fSig
6.5/fSig
9.5/fSig
1 × TXClk
3/fSig
6/fSig
1 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
9/fSig
9/fSig
3
Receiving Mode
Intermediate
frequency
3.1
fIF
987
fIF = fLO/318
kHz
A
A
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
1.8
3.2
5.6
1.8
3.2
5.6
BR_Range0 × 2 µs/TClk
BR_Range1 × 2 µs/TClk
BR_Range2 × 2 µs/TClk
BR_Range3 × 2 µs/TClk
Kbit/s
Kbit/s
Kbit/s
Kbit/s
Baud-rate
range
3.2
BR_Range
10.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
31
9248D–RKE–10/14
17. Electrical Characteristics Atmel ATA5723C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
fRF = 315MHz
14.71875MHz Oscillator
Variable Oscillator
Min. Typ. Max.
Test
No. Parameter Conditions
Symbol
Min.
Typ.
Max.
Min.
Typ. Max.
Unit Type*
Minimum
time period
between
edges at pin
DATA
BR_Range =
BR_Range0
163.06
81.53
40.76
20.38
163.06
81.53
40.76
20.38
10 × TXClk
10 × TXClk
10 × TXClk
10 × TXClk
10 × TXClk µs
(see Figure BR_Range1
10 × TXClk µs
10 × TXClk µs
10 × TXClk µs
3.3 4-2 and
BR_Range2
Figure 8-8, BR_Range3
Figure 8-9)
tDATA_min
A
(With the
exception of
parameter
TPulse
Maximum
Low period at BR_Range0
)
BR_Range =
2120
tDATA_L_max 1060
2120
1060
530
130 × TXClk
130 × TXClk
130 × TXClk
130 × TXClk
130 × TXClk µs
130 × TXClk µs
130 × TXClk µs
130 × TXClk µs
3.4 pin DATA
(see
BR_Range1
BR_Range2
A
A
530
265
Figure 4-2) BR_Range3
265
Delay to
activate the
3.5 start-up
Ton1
Ton2
Ton3
TPulse
19.36
16.3
21.4
9.5 × TClk
10.5 × TClk µs
mode (see
Figure 8-12)
OFF
command at
pin
POLLING/
_ON (see
Figure 8-11)
3.6
8 × TClk
µs
A
A
C
Delay to
activate the
3.7 sleep mode
(see
17.32
19.36
8.5 × TClk
9.5 × TClk
µs
Figure 8-11)
Pulse on pin
DATA at the BR_Range =
end of a data BR_Range0
stream
(see
Figure 10-3) BR_Range3
16.3
8.15
4.07
2.04
16.3
8.15
4.07
2.04
8 × TClk
4 × TClk
2 × TClk
1 × TClk
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
3.8
BR_Range1
BR_Range2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
32
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
17. Electrical Characteristics Atmel ATA5723C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 315MHz unless otherwise specified
(For typical values: VS = 5V, Tamb = 25°C).
fRF = 315MHz
14.71875MHz Oscillator
Variable Oscillator
Min. Typ. Max.
Test
No. Parameter Conditions
Symbol
Min. Typ. Max.
Min.
Typ. Max.
Unit Type*
4
Configuration of the Receiver (see Figure 12-1 and Figure 13-1)
Frequency is
stable within
50ms after
POR
Frequency of
4.1 the reset
marker
1/
1/
fRM
119.78
119.78
(4096 ×
TClk
(4096 ×
TClk)
Hz
A
A
)
BR_Range =
BR_Range0
Programming BR_Range1
3310
2242
1708
1441
16175
11479
11479
11479
11479
1624 × TClk
1100 × TClk
838 × TClk
707 × TClk
7936 × TClk
5632 × TClk µs
5632 × TClk µs
5632 × TClk µs
5632 × TClk µs
µs
4.2
t1
start pulse
BR_Range2
BR_Range3
after POR
Programming
delay period
384.5 ×
TClk
385.5 ×
µs
4.3
4.4
t2
t3
783
261
785
261
A
A
TClk
Synchroniza-
tion pulse
128 × TClk
63.5 × TClk
128 × TClk µs
63.5 × TClk µs
Delay until of
4.5 the program
window starts
t4
129
129
A
Programming
window
4.6
t5
t6
t7
522
1044
130.5
522
1044
522
256 × TClk
512 × TClk
64 × TClk
256 × TClk µs
512 × TClk µs
256 × TClk µs
A
A
C
Time frame
4.7
of a bit
Programming
pulse
4.8
Equivalent
4.9 acknowledge
pulse: E_Ack
t8
t9
261
526
916
261
526
916
128 × TClk
258 × TClk
128 × TClk µs
258 × TClk µs
A
A
A
Equivalent
4.10
time window
OFF-bit
4.11 programming
window
449.5 ×
TClk
449.5 ×
µs
t10
TClk
5
Data Clock (see Figure 9-1 and Figure 9-6)
Minimum
delay time
between
edge at
DATA and
DATA_CLK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
0
0
0
0
16.3057
8.1528
4.0764
2.0382
0
0
0
0
1 × TXClk
1 × TXClk
1 × TXClk
1 × TXClk
µs
µs
µs
µs
5.1
tDelay2
C
A
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Pulse width
of negative
pulse at pin
DATA_CLK
65.2
65.2
32.6
16.3
8.15
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
µs
µs
µs
µs
5.2
tP_DATA_CLK 32.6
16.3
8.15
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
33
9248D–RKE–10/14
18. Electrical Characteristics Atmel ATA5724C, ATA5728C
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92MHz and f0 = 868.3MHz unless otherwise
specified (for typical values: VS = 5V, Tamb = 25°C).
fRF = 433.92MHz
fRF = 868.3MHz,
13.52875MHz Oscillator 13.55234MHz Oscillator
Variable Oscillator
Test
No. Parameter
Conditions
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
6
Basic Clock Cycle of the Digital Circuitry
Basic clock
TClk
6.1
2.0696
2.0696 2.066
16.557 16.528
2.066
28/fXTO
28/fXTO
µs
A
A
cycle
BR_Range0
Extended
16.557
8.278
4.139
2.069
16.528
8.264
4.132
2.066
8 × TClk
4 × TClk
2 × TClk
1 × TClk
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
BR_Range1
BR_Range2
BR_Range3
8.278
4.139
2.069
8.264
4.132
2.066
6.2 basic clock
cycle
TXClk
7
Polling Mode
Sleep time
(see
Figure 8-1,
Figure 8-10
and
Sleep and
XSleep are
defined in the
OPMODE
register
Sleep ×
Sleep × Sleep ×
XSleep XSleep
1024 × 1024 ×
Sleep ×
XSleep ×
1024 ×
2.066
Sleep ×
Sleep ×
XSleep
×
×
×
7.1
TSleep
XSleep
×
XSleep
×
ms
A
A
1024 ×
2.0696
1024 × TClk
1024 × TClk
2.0696 2.066
Figure 13-1)
Start-up time BR_Range0
1855
1060
1060
663
1855
1060
1060
663
1852
1058
1058
662
1852
1058
1058
662
896.5
512.5
512.5
320.5
× TClk
896.5
512.5
512.5
320.5
× TClk
µs
µs
µs
µs
µs
(see
BR_Range1
BR_Range2
BR_Range3
7.2 Figure 8-1
and
TStartup
Figure 8-4)
Average bit-
check time
while polling,
no RF applied
(see Figure 8-
8 on page 14
and Figure 8-9
on page 15)
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Time for bit
7.3 check (see
Figure 8-1
TBit-check
C
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
0.45
0.24
0.14
0.08
ms
ms
ms
ms
Bit-check time
for a valid
input signal fSig
Time for bit (see Figure 8-
7.4 check (see
Figure 8-1
5 on page 13) TBit-check
C
N
N
N
N
Bit-check = 0
Bit-check = 3
Bit-check = 6
Bit-check = 9
1 × TXClk
3/fSig
6/fSig
1 × TXClk 1 × TXClk
1 × TXClk 1 × TXClk
1 × TClk
3.5/fSig
6.5/fSig
9.5/fSig
ms
ms
ms
ms
3.5/fSig
6.5/fSig
9.5/fSig
3/fSig
6/fSig
9/fSig
3.5/fSig
6.5/fSig
9.5/fSig
3/fSig
6/fSig
9/fSig
9/fSig
8
Receiving Mode
fIF = fLO/438 for the 433.92MHz
band (Atmel ATA5724C)
fIF =fLO/915 for the 868.3MHz band
(Atmel ATA5728C)
Intermediate
frequency
8.1
fIF
987
947.9
kHz
A
A
BR_Range0
BR_Range1
BR_Range2
BR_Range3
1.0
1.8
3.2
5.6
1.8
3.2
5.6
1.0
1.8
3.2
5.6
1.8
3.2
5.6
BR_Range0 × 2 µs/TClk
BR_Range1 × 2 µs/TClk
BR_Range2 × 2 µs/TClk
BR_Range3 × 2 µs/TClk
Kbit/s
Kbit/s
Kbit/s
Kbit/s
Baud-rate
range
BR_Rang
e
8.2
10.0
10.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
34
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
18. Electrical Characteristics Atmel ATA5724C, ATA5728C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92MHz and f0 = 868.3MHz unless otherwise
specified (for typical values: VS = 5V, Tamb = 25°C).
fRF = 433.92MHz
fRF = 868.3MHz,
13.52875MHz Oscillator 13.55234MHz Oscillator
Variable Oscillator
Min. Typ. Max.
Test
Conditions
No. Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
Minimum
time period
between
BR_Range =
edges at pin
DATA (see
Figure 4-2,
8.3 Figure 8-8,
and
BR_Range0
BR_Range1
BR_Range2
BR_Range3
165.5
82.8
41.4
20.7
165.5
82.8
41.4
20.7
165.3
82.6
41.3
20.6
165.3 10 × TXClk
10 × TXClk µs
82.6
41.3
20.6
10 × TXClk
10 × TXClk
10 × TXClk
10 × TXClk µs
10 × TXClk µs
10 × TXClk µs
tDATA_min
A
Figure 8-9)
(With the
exception of
parameter
TPulse
)
Maximum
BR_Range =
Low period at BR_Range0
2152
tDATA_L_max 1076
2152
1076
538
2148
1074
537
2148 130 × TXClk
1074 130 × TXClk
130 × TXClk µs
130 × TXClk µs
130 × TXClk µs
130 × TXClk µs
8.4 pin DATA
BR_Range1
BR_Range2
BR_Range3
A
A
(see
538
269
537
130 × TXClk
Figure 4-2)
269
268.5
268.5 130 × TXClk
Delay to
activate the
8.5 start-upmode
(see
Ton1
Ton2
Ton3
TPulse
19.6
16.5
17.6
21.7
19.6
16.5
17.6
21.7
9.5 × TClk
10.5 × TClk µs
Figure 8-12)
OFF
command at
pin
POLLING/
8.6
8 × TClk
µs
A
A
C
_ON (see
Figure 8-11)
Delay to
activate the
8.7 sleep mode
(see
19.6
19.6
8.5 × TClk
9.5 × TClk
µs
Figure 8-11)
Pulse on pin
DATA at the BR_Range =
end of a data BR_Range0
stream
(see
16.557
8.278
4.139
2.069
16.557 16.528
16.528
8.264
4.132
2.066
8 × TClk
4 × TClk
2 × TClk
1 × TClk
8 × TClk
4 × TClk
2 × TClk
1 × TClk
µs
µs
µs
µs
8.8
BR_Range1
BR_Range2
8.278
4.139
2.069
8.264
4.132
2.066
Figure 10-3) BR_Range3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
35
9248D–RKE–10/14
18. Electrical Characteristics Atmel ATA5724C, ATA5728C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92MHz and f0 = 868.3MHz unless otherwise
specified (for typical values: VS = 5V, Tamb = 25°C).
fRF = 433.92MHz
fRF = 868.3MHz,
13.52875MHz Oscillator 13.55234MHz Oscillator
Variable Oscillator
Min. Typ. Max.
Test
Conditions
No. Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit Type*
9
Configuration of the Receiver (see Figure 12-1 and Figure 13-1)
Frequency is
Frequency of
1/
1/
stable within
9.1 the reset
marker
fRM
117.9
117.9
118.2
118.2
(4096 ×
TClk
(4096 ×
TClk)
Hz
A
A
50ms after
POR
)
BR_Range =
BR_Range0
Programming BR_Range1
3361
2276
1734
1463
16425
11656
11656
11656
11656
3355
2272
1731
1460
11636 1624 × TClk
11636 1100 × TClk
11636 838 × TClk
11636 707 × TClk
7936 × TClk
5632 × TClk µs
5632 × TClk µs
5632 × TClk µs
5632 × TClk µs
µs
9.2
t1
start pulse
BR_Range2
BR_Range3
after POR
Programming
delay period
384.5 ×
385.5 ×
µs
9.3
9.4
t2
t3
796
265
798
265
794
264
796
TClk
A
A
TClk
Synchroniza-
tion pulse
264
131
529
128 × TClk
63.5 × TClk
256 × TClk
128 × TClk µs
63.5 × TClk µs
Delay until of
9.5 the program
window starts
t4
131
131
131
A
Programming
window
9.6
t5
t6
t7
530
1060
132
530
1060
530
529
1058
132
256 × TClk µs
512 × TClk µs
256 × TClk µs
A
A
C
Time frame
9.7
1058 512 × TClk
of a bit
Programming
pulse
9.8
529
264
533
929
64 × TClk
128 × TClk
258 × TClk
Equivalent
9.9 acknowledge
pulse: E_Ack
t8
t9
265
534
930
265
534
930
264
533
929
128 × TClk µs
258 × TClk µs
A
A
A
Equivalent
9.10
time window
OFF-bit
9.11 programming
window
449.5 ×
TClk
449.5 ×
µs
t10
TClk
10 Data Clock (see Figure 9-1 and Figure 9-6)
Minimum
delay time
between
edge at DATA BR_Range2
and
BR_Range =
BR_Range0
BR_Range1
0
0
0
0
16.557
8.278
4.139
2.069
0
0
0
0
16.528
8.264
4.132
2.066
0
0
0
0
1 × TXClk
1 × TXClk
1 × TXClk
1 × TXClk
µs
µs
µs
µs
10.1
10.2
tDelay2
C
A
BR_Range3
DATA_CLK
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
Pulse width of
negative
pulse at pin
DATA_CLK
66.2
62.2
33.1
16.5
8.3
66.1
33.0
16.5
8.25
66.1
33.0
16.5
8.25
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
4 × TXClk
µs
µs
µs
µs
tP_DATA_CLK 33.1
16.5
8.3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
36
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
19. Electrical Characteristics Atmel ATA5723C/24C/28C
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz,
unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C)
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit Type*
11 Current Consumption
Sleep mode
(XTO and polling logic active)
ISoff
170
290
µA
A
A
IC active (start-up-, bit-check-, receiving
mode) Pin DATA = H
FSK
ASK
11.1 Current consumption
ISon
8.5
8.0
11.0
10.4
mA
mA
12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to Figure 14-1 on page 29 Referred to RFIN)
LNA/mixer/IF amplifier
868MHz
433MHz
315MHz
–18
–23
–24
12.1 Third-order intercept point
IIP3
dBm
C
12.2 LO spurious emission
12.3 System noise figure
Required according to I-ETS 300220
With power matching |S11| < –10dB
ISLORF
NF
–70
5
–57
dBm
dB
A
B
(14.15 –
j73.53)
At 868.3MHz
AT 433.92MHz
At 315MHz
Ω
Ω
Ω
(19.3 –
j113.3)
12.4 LNA_IN input impedance
ZiLNA_IN
C
(26.97 –
j158.7)
At 868.3MHz
AT 433.92MHz
At 315MHz
–27.7
–32.7
–33.7
12.5 1 dB compression point
12.6 Image rejection
IP1db
dBm
dB
C
A
C
Within the complete image band
20
30
BER ≤ 10-3,
FSK mode
ASK mode
12.7 Maximum input level
13 Local Oscillator
Pin_max
–10
–10
dBm
dBm
Atmel ATA5728C
Atmel ATA5724C
Atmel ATA5723C
868
431.5
312.5
870
436.5
317.5
MHz
MHz
MHz
Operating frequency range
VCO
13.1
fVCO
A
fosc = 868.3MHz at 10MHz
13.2 Phase noise local oscillator fosc = 433.92MHz at 10MHz
fosc = 315MHz at 10MHz
–140
–143
–143
–130
–133 dBC/Hz
–133
L (fm)
B
B
13.3 Spurious of the VCO
At ±fXTO
–55
–45
dBC
XTO pulling,
appropriate load capacitance must be
connected to XTAL, crystal CL1 and
CL2
fXTAL = 14.71875MHz (315MHz band)
fXTAL = 13.52875MHz (433MHz band)
fXTAL = 13.55234MHz (868MHz band)
13.4 XTO pulling
B
B
fXTO
–10ppm
fXTAL +10ppm MHz
Series resonance resistor of
13.5
Parameter of the supplied crystal
RS
120
Ω
the crystal
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
37
9248D–RKE–10/14
19. Electrical Characteristics Atmel ATA5723C/24C/28C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz,
unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C)
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit Type*
Static capacitance at pin
XTAL1 to GND
Parameter of the supplied crystal and
board parasitics
13.6
13.7
CL1
–5%
18
+5%
pF
pF
kΩ
B
B
B
Static capacitance at pin
XTAL2 to GND
Parameter of the supplied crystal and
board parasitics
CL2
–5%
18
+5%
C0 < 1.8pF, CL = 9pF
1.5
fXTAL = 14.71875MHz
Crystal series resistor Rm at
start-up
13.8
C0 < 2.0pF, CL = 9pF
fXTAL = 13.52875MHz
fXTAL = 13.55234MHz
1.5
kΩ
B
14 Analog Signal Processing (Input Matched According to Figure 14-1 on page 29 Referred to RFIN)
ASK (level of carrier)
BER ≤ 10-3, 100% Mod
fin = 315MHz/433.92MHz
VS = 5V, Tamb = 25°C
fIF = 987kHz
Input sensitivity ASK
300kHz IF Filter
(Atmel
14.1
PRef_ASK
BR_Range0
BR_Range1
BR_Range2
BR_Range3
–111
–113
–115
dBm
dBm
dBm
dBm
B
B
B
B
ATA5723C/ATA5724C)
–109.5 –111.5 –113.5
–109
–107
–111
–109
–113
–111
ASK (level of carrier)
BER ≤ 10-3, 100% Mod
fin = 868.3MHz
VS = 5V, Tamb = 25°C
fIF = 948kHz
Input sensitivity ASK
14.2 600kHz IF Filter
(Atmel ATA5728C)
PRef_ASK
BR_Range0
BR_Range1
BR_Range2
BR_Range3
–109
–111
–113
dBm
dBm
dBm
dBm
B
B
B
B
–107.5 –109.5 –111.5
–107
–105
–109
–107
–111
–109
Sensitivity variation ASK for
the full operating range
300kHz and 600kHz
14.3 compared to Tamb = 25°C,
fin = 315MHz/433.92MHz/868.3MHz
ΔPRef
+2.5
–1.5
dB
B
VS = 5V (Atmel ATA5723C/ PASK = PRef_ASK + ΔPRef
ATA5724C/ATA5728C)
300kHz version (Atmel
ATA5723C/ATA5724C)
fin = 315MHz/433.92MHz
fIF = 987kHz
ΔPRef
+5.5
+7.5
–1.5
–1.5
dB
dB
B
fIF = –110kHz to +110kHz
Sensitivity variation ASK for
full operating range including
IF filter compared to
fIF = –140kHz to +140kHz
PASK = PRef_ASK + ΔPRef
14.4
600kHz version (Atmel ATA5728C)
fin = 868.3MHz
Tamb = 25°C, VS = 5V
fIF = 948kHz
ΔPRef
+5.5
+7.5
–1.5
–1.5
dB
dB
B
fIF = –210kHz to +210kHz
fIF = –270kHz to +270kHz
PASK = PRef_ASK + ΔPRef
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
38
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
19. Electrical Characteristics Atmel ATA5723C/24C/28C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz,
unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C)
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit Type*
BER ≤ 10-3
fin = 315MHz/433.92MHz
VS = 5V, Tamb = 25°C
fIF = 987kHz
BR_Range0
df = ±16kHz
df = ±10kHz to ±30kHz
PRef_FSK
–104
–102
–107
–105
–108.5 dBm
–108.5 dBm
B
B
B
B
Input sensitivity FSK
300kHz IF filter
(Atmel
BR_Range1
df = ±16kHz
df = ±10kHz to ±30kHz
14.5
PRef_FSK
–102
–100
–106.5 dBm
–106.5 dBm
ATA5723C/ATA5724C)
BR_Range2
df = ±16kHz
df = ±10kHz to ±30kHz
PRef_FSK –100.5 –103.5
–98.5
–105
–105
dBm
dBm
BR_Range3
df = ±16kHz
df = ±10kHz to ±30kHz
PRef_FSK
–98.5
–96.5
–101.5
–103
–103
dBm
dBm
BER ≤ 10-3
fin = 868.3MHz
VS = 5V, Tamb = 25°C
fIF = 948kHz
BR_Range0
df = ±16kHz to ±28kHz
df = ±10kHz to ±100kHz
PRef_FSK
PRef_FSK
PRef_FSK
PRef_FSK
–102
–100
–105
–103
–106.5 dBm
–106.5 dBm
B
B
B
B
Input sensitivity FSK
14.6 600kHz IF filter
(Atmel ATA5728C)
BR_Range1
df = ±16kHz ±28kHz
df = ±10kHz to ±100kHz
–100
–98
–104.5 dBm
–104.5 dBm
BR_Range2
df = ±18kHz ±31kHz
df = ±13kHz to ±100kHz
–98.5
–96.5
–101.5
–99.5
–103
–103
dBm
dBm
BR_Range3
df = ±25kHz ±44kHz
df = ±20kHz to ±100kHz
–96.5
–94.5
–101
–101
dBm
dBm
Sensitivity variation FSK for
the full operating range
300 kHz and 600 kHz versions
14.7 compared to Tamb = 25°C,
fin = 315MHz/433.92MHz/868.3MHz
ΔPRef
+3
–1.5
dB
B
VS = 5V (Atmel ATA5723C/ PFSK = PRef_FSK + ΔPRef
ATA5724C/ATA5728C)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
39
9248D–RKE–10/14
19. Electrical Characteristics Atmel ATA5723C/24C/28C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz,
unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C)
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit Type*
300kHz version (ATA5723C/ATA5724C)
fin = 315MHz/433.92MHz
fIF = 987kHz
fIF = –110kHz to +110kHz
fIF = –140kHz to +140kHz
fIF = –180kHz to +180kHz
PFSK = PRef_FSK + ΔPRef
ΔPRef
+6
+8
+11
–2
–2
–2
dB
dB
dB
B
B
Sensitivity variation FSK for
the full operating range
14.8 including IF filter compared
to Tamb = 25°C,
600kHz version (Atmel ATA5728C)
fin = 868.3MHz
fIF = 948kHz
VS = 5V
fIF = –150kHz to +150kHz
ΔPRef
+6
+8
+11
–2
–2
–2
dB
dB
dB
fIF = –200kHz to +200kHz
fIF = –260kHz to +150kHz
PFSK = PRef_FSK + ΔPRef
S/N ratio to suppress in-
band noise signals. Noise
signals may have any
modulation scheme
ASK mode
FSK mode
SNRASK
SNRFSK
10
2
12
3
dB
dB
14.9
C
A
Dynamic range RSSI
amplifier
14.10
ΔRRSSI
60
20
dB
14.11 RSSI output voltage range
14.12 RSSI gain
VRSSI
GRSSI
1
3.5
V
A
A
mV/dB
1
---------------------------------------------------------
=
fcu_DF
Lower cut-off frequency of
the data filter
2 × π × 30 kΩ × CDEM
14.13
fcu_DF
0.11
0.16
0.20
kHz
B
CDEM = 33nF
BR_Range0 (default)
BR_Range1
BR_Range2
39
22
12
8.2
nF
nF
nF
nF
Recommended CDEM for
14.14
CDEM
C
C
best performance
BR_Range3
BR_Range0 (default)
BR_Range1
BR_Range2
270
156
89
1000
560
320
180
µs
µs
µs
µs
Edge-to-edge time period of
14.15 the input data signal for full
sensitivity
tee_sig
BR_Range3
50
Upper cut-off frequency programmable
in 4 ranges using a serial mode word
Upper cut-off frequency data BR_Range0 (default)
2.8
4.8
8.0
3.4
6.0
10.0
19.0
4.0
7.2
12.0
23.0
kHz
kHz
kHz
kHz
14.16
B
filter
BR_Range1
BR_Range2
BR_Range3
fu
15.0
300kHz version (ATA5723C/ATA5724C)
RSense connected from pin SENS
to VS, input matched according to
Figure 14-1 “Application Circuit”,
fin = 315MHz/433.92MHz,
dBm
(peak
level)
14.17 Reduced sensitivity
VS = 5V, Tamb = +25°C
RSense = 56kΩ
RSense = 100kΩ
PRef_Red
PRef_Red
–74
–83
–79
–88
–83
–93
dBm
dBm
B
B
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
40
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
19. Electrical Characteristics Atmel ATA5723C/24C/28C (Continued)
All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 868.3MHz, f0 = 433.92MHz and f0 = 315MHz,
unless otherwise specified. (For typical values: VS = 5V, Tamb = 25°C)
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit Type*
600kHz version (Atmel ATA5728C)
RSense connected from pin SENS
to VS, input matched according to
Figure 14-1 “Application Circuit”,
fin = 868.3MHz,
dBm
(peak
level)
14.18 Reduced sensitivity
VS = 5V, Tamb = +25°C
RSense = 56kΩ
RSense = 100kΩ
RSense = 56kΩ
PRef_Red
PRef_Red
–63
–72
–68
–77
–73
–82
dBm
dBm
B
B
5
5
0
0
0
0
dB
dB
Reduced sensitivity variation
over full operating range
14.19
14.20
RSense = 100kΩ
ΔPRed
C
PRed = PRef_Red + ΔPRed
Values relative to RSense = 56kΩ
RSense = 56kΩ
0
dB
dB
dB
dB
Reduced sensitivity variation
for different values of RSense
RSense = 68kΩ
RSense = 82kΩ
ΔPRed
–3.5
–6.0
–9.0
C
A
RSense = 100kΩ
14.21 Threshold voltage for reset
15 Digital Ports
VThRESET
1.95
2.8
3.75
V
Data output
- Saturation voltage Low
Iol ≤ 12mA
Iol = 2mA
Vol
Vol
Voh
Iqu
Iol_lim
tamb_sc
0.35
0.08
0.8
0.3
20
20
45
85
V
V
V
µA
mA
°C
- max voltage at pin DATA
- quiescent current
15.1 - short-circuit current
- ambient temp. in case of
permanent short-circuit
Data input
Voh = 20V
Vol = 0.8V to 20V
Voh = 0V to 20V
13
30
A
- Input voltage Low
- Input voltage High
VIl
Vich
0.35 ×
VS
V
V
0.65 × VS
DATA_CLK output
- Saturation voltage Low
- Saturation voltage High
IDATA_CLK = 1mA
IDATA_CLK = –1mA
Vol
Voh
0.1
VS –
0.15V
0.4
0.4
V
V
15.2
A
VS –
0.4V
IC_ACTIVE output
- Saturation voltage Low
- Saturation voltage High
IIC_ACTIVE = 1mA
IIC_ACTIVE = –1mA
Vol
Voh
0.1
VS –
0.15V
V
V
15.3
A
A
VS –
0.4V
POLLING/_ON input
15.4 - Low level input voltage
- High level input voltage
Receiving mode
Polling mode
VIl
VIh
0.2 × VS
V
V
0.8 × VS
0.8 × VS
MODE pin
15.5
Test input must always be set to high
Test input must always be set to low
A
A
- High level input voltage
VIh
VIl
V
V
TEST 1 pin
15.6
- Low level input voltage
0.2 × VS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
41
9248D–RKE–10/14
20. Ordering Information
Extended Type Number
ATA5723P3C-TKQW
ATA5724P3C-TKQW
ATA5728P6C-TKQW
Package
SSO20
SSO20
SSO20
MOQ
4,000
4,000
4,000
Remarks
315MHz version
433MHz version
868MHz version
21. Package Information
E1
D
L
b
E
e
20
11
technical drawings
according to DIN
specifications
Dimensions in mm
1
10
COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol MIN
NOM
1.0
MAX NOTE
A
A1
A2
D
0.9
0.05
0.85
6.4
1.1
0.15
0.95
6.6
0.1
0.9
6.5
E
6.3
6.4
6.5
E1
L
4.3
4.4
4.5
0.5
0.6
0.7
C
0.1
0.15
0.25
0.65 BSC
0.2
b
e
0.2
0.3
04/16/14
TITLE
DRAWING NO.
6.543-5182.01-4
REV.
GPC
Package Drawing Contact:
packagedrawings@atmel.com
Package: SSO20
4.4mm
1
42
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
9248D–RKE–10/14
22. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
• Section 20 “Ordering Information” on page 42 updated
• Section 21 “Package Information” on page 42 updated
• Put datasheet in the latest template
9248D-RKE-10/14
9248C-RKE-08/14
ATA5723C/ATA5724C/ATA5728C [DATASHEET]
43
9248D–RKE–10/14
X
X X X X
X
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