ATA6620N-TAQY [ATMEL]
LIN Bus Transceiver with Integrated Voltage Regulator; LIN总线收发器，集成稳压器
| 型号： | ATA6620N-TAQY |
| 厂家： | 
ATMEL |
| 描述： | LIN Bus Transceiver with Integrated Voltage Regulator |
| 文件： | 总22页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40V
• Operating Voltage VS = 5V to 18V
• Typically 10 µA Supply Current During Sleep Mode
• Typically 40 µA Supply Current in Silent Mode
• Linear Low-drop Voltage Regulator:
– Normal Mode: VCC = 5V ±2%/50 mA
– Silent Mode: VCC = 5V ±7%/50 mA
– Sleep Mode: VCC is Switched Off
LIN Bus
• VCC Undervoltage Detection with Reset Output NRES (10 ms Reset Time)
• Voltage Regulator is Short-circuit and Over-temperature Protected
• LIN Physical Layer According to LIN Specification Revision 2.0
• Wake-up Capability via LIN Bus (90 µs Dominant)
• TXD Time-out Timer (9 ms)
• 60V Load-dump Protection at LIN Pin
• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
• High EMC Level
Transceiver
with Integrated
Voltage
Regulator
• 5V CMOS-compatible I/O Pins to MCU
• ESD HBM 6 kV at Pins LIN and VS
• Interference and Damage Protection According to ISO/CD7637
• Package: SO8
ATA6620N
1. Description
ATA6620N is a fully integrated LIN transceiver, designed according to the LIN specifi-
cation 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage
regulator and bus transceiver makes it possible to develop simple, but powerful, slave
nodes in LIN Bus systems. ATA6620N is designed to handle the low-speed data com-
munication in vehicles (for example, in convenience electronics). Improved slope
control at the LIN driver ensures secure data communication up to 20 kBaud with an
RC oscillator for the protocol handling. The bus output is designed to withstand high
voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication
off; VCC voltage on) guarantee minimized current consumption.
4850H–AUTO–12/07
Figure 1-1. Block Diagram
1
VS
VCC
ATA6620N
Normal and
Pre-normal
Mode
RXD
5
Receiver
LIN
4
Filter
VCC
Wake-up Bus Timer
Slew Rate Control
Short Circuit and
Overtemperature
Protection
TXD
6
TXD
Time-out
Timer
VCC
8
Normal Mode
Voltage Regulator
5V/50 mA/2%
Sleep
Mode
VCC
Switched
EN
2
NRES
Control
Unit
7
Undervoltage Reset
Silent Mode
Voltage Regulator
5V/50 mA/7%
GND
3
Off
2. Pin Configuration
Figure 2-1. Pinning SO8
VS
EN
1
2
3
4
8
7
6
5
VCC
NRES
TXD
GND
LIN
RXD
Table 2-1.
Pin Description
Pin
1
Symbol
VS
Function
Battery supply
2
EN
Enables Normal mode if the input is high
Ground
3
GND
LIN
4
LIN bus line input/output
5
RXD
TXD
NRES
VCC
Receive data output
6
Transmit data input, active low output
Output undervoltage reset, low at reset
Output voltage regulator 5V/50 mA
7
8
2
ATA6620N
4850H–AUTO–12/07
ATA6620N
3. Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is VS = 5V to 18V. An undervoltage detection is implemented to disable
transmission if VS falls below 5V, in order to avoid false bus messages. After switching on VS,
the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is,
5V/50 mA output capability).
The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.
3.3
3.4
Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift
up to 3V for supply voltage above 9V at the VS pin.
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the
microcontroller and other ICs on the PCB. It is protected against overload by means of current
limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will
cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun
.
3.5
Undervoltage Reset Output (NRES)
This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the under-
voltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 4-7 on page 11)
except the IC is switched into Sleep mode. Even if VCC = 0V the NRES stays low, because it is
internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS < 1.5V
and then becomes highly resistive.
The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its
nominal value.
3.6
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–40V to +60V. This pin exhibits no reverse current from the LIN bus to VS, even in the case of a
GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita-
tion; that is, during current limitation, as the chip temperature increases, the current decreases.
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4850H–AUTO–12/07
3.7
3.8
Input/Output Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled
to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resis-
tor), the LIN output transistor is turned off and the bus is in the recessive state.
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 4 ms, the
LIN bus driver is switched to the recessive state. To reset this dominant time-out mode, TXD
must be switched to high (> 10 µs) before normal data transmission can be started.
3.9
Output Pin (RXD)
This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is
reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The
output has an internal pull-up structure with typically 5 kΩ to VCC. The AC characteristics are
measured with an external load capacitor of 20 pF.
The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off.
3.10 Enable Input Pin (EN)
This pin controls the operation mode of the interface. After power up of VS (battery), the IC
switches to Pre-normal mode, even if EN is low or unconnected (internal pull-down resistor). If
EN is high, the interface is in Normal mode.
A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN
while TXD is low forces the device to Sleep mode.
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4850H–AUTO–12/07
ATA6620N
4. Mode of Operation
Figure 4-1. Mode of Operation
a: VS > 5V
Unpowered Mode
b: VS < 4V
VBatt = 0
c: Bus wake-up event
d: NRES switches to low
a
b
Pre-normal Mode
b
VCC: 5V/2%/50 mA with undervoltage
monitoring
Communication: OFF
b
c + d
d
EN = 1
c
b
Go to silent command
EN = 0
Silent Mode
VCC: 5V/7%/50 mA
TXD = 1
Local wake-up event
Normal Mode
with undervoltage monitoring
Communication: OFF
EN = 1
VCC: 5V/2%/50 mA
with undervoltage
monitoring
Go to sleep command
EN = 0
Sleep Mode
VCC: switched off
Communication: OFF
TXD = 0
Communication: ON
Local wake-up event
EN = 1
Table 4-1.
Mode of
Mode of Operation
Communication
Operation
Pre-normal
Normal
VCC
5V
5V
5V
0V
RXD
5V
LIN
OFF
ON
Recessive
Recessive
Recessive
Recessive
5V
Silent
OFF
OFF
5V
Sleep
0V
4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN
specification 2.0. The VCC voltage regulator operates with a 5V output voltage, with a low toler-
ance of ±2% and a maximum output current of 50 mA.
If an undervoltage condition occurs, NRES is switched to low and the ATA6620N changes state
to Pre-normal mode. All features are available.
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4850H–AUTO–12/07
4.2
Modes of Reduced Current Consumption
4.2.1
Silent Mode
A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to
be logic high during the Mode Select window (Figure 4-2 on page 6). For EN and TXD either two
independent outputs can be used, or two outputs from the same microcontroller port; in the sec-
ond case, the mode change is only one command.
In Silent mode the transmission path is disabled. Supply current from VBatt is typically
IVSsi = 40 µA with no load at the VCC regulator.
The overall supply current from VBatt is the result of 40 µA plus the VCC regulator output current
IVCCs
.
The 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. In
Silent mode the internal slave termination between pin LIN and pin VS is disabled to minimize
the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typ-
ically 10 µA) between pin LIN and pin VS is present.
The Silent mode voltage is sufficient to run an external microcontroller on the ECU, for example
in Power Down mode. The undervoltage reset is VCCthS < 4.4V. If an undervoltage condition
occurs, NRES is switched to low and the ATA6620N changes state to Pre-normal mode.
A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period
(tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal
mode, then the internal LIN slave termination resistor is switched on. The remote wake-up
request is indicated by a low level at pin RXD to interrupt the microcontroller and a high level at
pin TXD(Figure 4-3 on page 7).
With EN high, ATA6620N switches directly from Silent- via Pre-normal to Normal mode.
Figure 4-2. Switch to Silent Mode
Silent Mode
Normal Mode
EN
Mode select window
TXD
td = 3.2 µs
NRES
VCC
Delay time silent mode
t
d_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
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4850H–AUTO–12/07
ATA6620N
Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode
Normal Mode
Pre-normal Mode
LIN Bus
VLIN < 0.4 VS
TXD
RXD
High
High
Low
Bus wake-up filtering
time tbus
VCC
Silent mode
Pre-normal mode
Normal mode
EN High
Regulator Wake-up Time
Node ln silent mode
EN
NRES
If undervoltage switch to pre-normal mode
Undervoltage detection active
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4850H–AUTO–12/07
4.2.2
Sleep Mode
A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to
be logic low during the Mode Select window (Figure 4-4). We recommend using the same micro-
controller port for EN as for TXD; in this case the mode change is only one command.
In Sleep mode the transmission path is disabled. Supply current from VBatt is typically
IVSsleep = 10 µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave
termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin
LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and
pin VS is present.
A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period
(tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal
mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched
on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcon-
troller and a high level at pin TXD (Figure 4-5 on page 9).
With EN high you can switch directly from Silent to Normal mode. In the application where the
ATA6620N supplies the microcontroller, the wake-up from Sleep mode is only possible via pin
LIN.
If the device is switched into Sleep mode, VCC ramps down without generating an undervoltage
reset at pin NRES.
Figure 4-4. Switch to Sleep Mode
Sleep Mode
Normal Mode
EN
Mode select window
TXD
td = 3.2 µs
NRES
VCC
Delay time sleep mode
t
d_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
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4850H–AUTO–12/07
ATA6620N
Figure 4-5. LIN Wake-up Diagram from Sleep Mode
Normal Mode
Pre-normal Mode
VLIN < 0.4 VS
LIN Bus
TXD
RXD
VCC
Low or floating
Low
Bus wake-up filtering time
tbus
On state
Off state
Regulator wake-up time
EN High
EN
Node in sleep mode
Low or floating
Reset
time
NRES
Microcontroller start-up
time delay
4.2.3
Wake Up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN
If the ATA6620N is in Sleep mode or Silent mode and the voltage at the LIN Bus falls to a value
lower than VLINL < VS – 3.3V (see “Electrical Characteristics” numbers 9.5 and 9.6) but higher
than 0.6 × VS, then a wake up is detected and the circuit switches to pre-normal mode and the
internal NMOS- transistor connected to the pin TXD is switched on and pulls down the pin TXD
to Ground. The following figure shows the corresponding diagram for the wake-up from silent
mode. The wake-up process from Sleep mode works analogue to this.
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4850H–AUTO–12/07
Figure 4-6. Wake Up from Silent Mode at an Insufficient Falling Edge at Pin LIN
Normal Mode
Pre-normal Mode
LIN Bus
VLIN < VS - 1V and
VLIN > 0.6 VS
High
TXD
RXD
Low
Low
High
Wake-up filtering
time t WAKE
VCC
Silent mode
Pre-normal mode
Normal mode
EN High
Regulator Wake-up Time
Node ln silent mode
EN
NRES
If undervoltage switch to pre-normal mode
Undervoltage detection active
When designing the complete system it has to be considered, that in this case (only in pre-nor-
mal mode) the pin TXD of the ATA6620N works as an output.
4.3
Pre-normal Mode
At system power-up the device automatically switches to Pre-normal mode. The voltage regula-
tor is switched on (VCC = 5V/50 mA) (see Figure 4-7 on page 11) after typically tVCC > 300 µs.
The NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN
communication is switched off, and the undervoltage detection is active.
A power-down of VBatt (VS < 4.15V) during Silent or Sleep mode switches into Pre-normal mode
after powering up the IC. During this mode the TXD pin is an output.
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ATA6620N
4850H–AUTO–12/07
ATA6620N
4.4
Unpowered Mode
If battery voltage is connected to the application circuit (Figure 4-7), the voltage at the VS pin
increases due to the block capacitor. When VS is higher than the VS undervoltage threshold,
VSth, the IC-mode changes from Unpowered to Pre-normal mode. The VCC output voltage
reaches nominal value after tVCC. This time depends on the VCC capacitor and the load.
NRES is low for the reset time delay tReset; no mode change is possible during this time.
Figure 4-7.
V
CC Voltage Regulator: Ramp Up and Undervoltage
VS
12V
5.5V
3V
VCC
5V
Vthun
NRES
5V
tVCC
tres
tes_f
5. Fail-safe Features
• During a short circuit at LIN, the output limits the output current to IBUS_LIM. Due to the power
dissipation, the chip temperature exceeds tLINoff and the LIN output is switched off. The chip
cools down and after a hysteresis of thys, switches the output on again. During LIN
overtemperature switch-off, the VCC regulator works independently.
• There are now reverse currents < 3 µA at pin LIN during loss of VBatt or GND. This is optimal
behavior for bus systems where some slave nodes are supplied from battery or ignition.
• During a short circuit at VCC, the output limits the output current to IVCCn. Because of
undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC
switches into Pre–normal mode. If the chip temperature exceeds the value tVCCoff, the VCC
output switches off. The chip cools down and after a hysteresis of thys, switches the output on
again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is
switched off from the microcontroller.The microcontroller can then start with normal
operation.
• Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is
disconnected.
• Pin RXD is set floating if VBatt is disconnected.
• Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is
disconnected.
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4850H–AUTO–12/07
6. Voltage Regulator
The voltage regulator needs an external capacitor for compensation and to smooth the distur-
bances from the microcontroller. It is recommend to use an tantalum capacitor with C > 10 µF
and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the
customer, depending on the application.
During mode change from Silent to Normal mode, the voltage regulator ramps up to 6V for only
a few microseconds before it drops back to 5V. This behavior depends on the value of the load
capacitor. With 4.7 µF, the overshoot voltage has its greatest value. This voltage decreases with
higher or lower load capacitors.
With this special SO8 package (fused lead frame to pin3) an Rthja of 80 K/W is achieved.
Therefore it is recommended to connect pin 3 with a wide GND plate on the printed board to get
a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is
needed for the application.
Figure 6-1 shows the safe operating area of the ATA6620N.
Figure 6-1. Save Operating Area versus VCC Output Current and Supply Voltage VS at Differ-
ent Ambient Temperatures with Rthja = 80 K/W
60.00
Iout_85: Tamb = 85˚C
Iout_95: Tamb = 95˚C
Iout_105: Tamb = 105˚C
50.00
40.00
30.00
20.00
10 . 0 0
0.00
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC
output via an external power supply while the VS pin of the system basis chip is disconnected.
This behavior is no problem for the system basis chip.
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4850H–AUTO–12/07
ATA6620N
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Supply voltage VS
VS
–0.3
+40
V
Pulse time ≤ 500 ms
T = 25°C
Output current IVCC ≤ 50 mA
VS
VS
+40
27
V
V
Pulse time ≤ 2 min
T = 25°C
Output current IVCC ≤ 50 mA
Logic pins (RXD, TXD, EN, NRES)
Output current NRES
–0.3
–2
+6.5
+2
V
INRES
mA
LIN
- DC voltage
- Transient voltage
–40
–150
+60
+100
V
V
VCC
- DC voltage
–0.3
–6
+6.5
+6
V
ESD (DIN EN 6100–4–2)
Pin LIN, VS versus GND according to LIN
specification EMC Evaluation V 1.3
kV
kV
HBM ESD S5.1 – all pins
–3
+3
CDM ESD STM 5.3.1–1999
- All pins
–1000
–40
+1000
+150
+150
+125
V
Junction temperature
Tj
Ts
Ta
°C
°C
°C
Storage temperature
–55
Operating ambient temperature
–40
Thermal resistance junction to ambient
(free air)
Rthja
145
K/W
Special heat sink at GND (pin 3) on PCB
Thermal shutdown of VCC regulator
Thermal shutdown of LIN output
Thermal shutdown hysteresis
Rthja
TVCCoff
TLINoff
Thys
80
160
160
10
K/W
°C
150
150
170
170
°C
°C
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8. Electrical Characteristics
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
VS Pin
Nominal DC voltage
range
1.1
VS
VS
5
13.5
18
V
A
Sleep mode
Supply current in Sleep
mode
V
V
lin > VBatt – 0.5V
Batt < 14V
1.2
1.3
VS
VS
IVSsleep
10
40
20
50
µA
µA
A
A
(25°C to 125°C)
Bus recessive;
VBatt < 14V
(25°C to 125°C)
Supply current in Silent
mode
IVSsi
Without load at VCC
Supply current in
Normal mode
Bus recessive
Without load at VCC
1.4
1.5
1.6
1.7
1.8
VS
VS
VS
VS
VS
VS
IVSrec
IVSdom
PORth
PORhys
VSth
4
mA
mA
V
A
A
D
D
A
A
Supply current in
Normal mode
Bus dominant
55
3.3
VCC load current 50 mA
Power On Reset
threshold
3
Power On Reset
threshold hysteresis
0.1
4.5
0.2
V
VS undervoltage
threshold
4.15
5
8
V
VS undervoltage
threshold hysteresis
1.9
VSth_hys
V
2
RXD Output Pin
Normal mode;
2.1
Low level input current VLIN = 0V
VRXD = 0.4V
RXD
IRXD
2
3
5
5
mA
A
2.2
2.3
3
Low level output voltage IRXD = 1 mA
Internal resistor to VCC
RXD
RXD
VRXDL
RRXD
0.3
7
V
A
A
kΩ
TXD Input/Output Pin
3.1
Low level voltage input
TXD
TXD
TXD
TXD
VTXDL
VTXDH
RTXD
ITXD
–0.3
3.5
125
–3
+1.5
V
V
A
A
A
A
VCC
+
3.2
3.3
3.4
High level voltage input
0.3V
Pull-up resistor
VTXD = 0V
TXD = 5V
250
5
600
kΩ
µA
High level leakage
current
V
+3
Pre-normal mode
VTXD = 0.4V to 5V
3.5
Low-level output current
TXD
ITXDwake
2
8
mA
A
4
EN Input Pin
4.1
Low level voltage input
EN
EN
VENL
VENH
–0.3
3.5
+1.5
V
V
A
A
VCC
+
4.2
High level voltage input
0.3V
4.3
4.4
Pull-down resistor
VEN = 5V
EN
EN
REN
IEN
125
–3
250
600
+3
kΩ
A
A
Low level input current VEN = 0V
µA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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ATA6620N
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
5
NRES Output Pin
VS ≥ 5.5V;
INRES = –1 mA
5.1
High level output voltage
NRES
NRES
VNRESH
4.5
V
A
VS ≥ 5.5V;
5.2
Low level output voltage INRES = +1 mA
INRES = +250 µA
VNRESL
VNRESL
0.2
0.14
V
V
A
A
10 kΩto VCC;
5.3
5.4
Low level output low
NRES
NRES
NRES
VNRESLL
tReset
0.2
13
3
V
A
A
A
VCC = 0.8V
VVS ≥ 5.5V
Undervoltage reset time
7
ms
µs
C
NRES = 20 pF
Reset debounce time for VVS ≥ 5.5V
falling edge CNRES = 20 pF
5.5
6
tres_f
Voltage Regulator VCC Pin in Normal and Pre-normal Mode
5.5V < VS < 18V
(0 mA – 50 mA)
6.1
Output voltage VCC
VCC
VCC
VCCnor
VCClow
4.9
5.1
5.1
V
V
A
A
Output voltage VCC at
low VS
VVS
– VD
6.2
3.3V < VS < 5.5V
6.3
6.4
6.5
6.6
6.7
Regulator drop voltage VS > 4.0V, IVCC = –20 mA VCC
Regulator drop voltage VS > 4.0V, IVCC = –50 mA VCC
Regulator drop voltage VS > 3.3V, IVCC = –15 mA VCC
VD
VD
250
500
200
mV
mV
mV
mA
mA
A
A
A
A
A
VD
Output current
VS > 3V
VCC
VCC
IVCC
IVCCs
–50
Output current limitation VS > 0V
–200
–130
2.2
1Ω < ESR < 5Ω at
100 kHz
6.8
6.9
Load capacity
VCC
VCC
VCC
VCC
Cload
VthunN
Vhysthun
tVCC
1.8
4.4
30
µF
V
D
A
A
A
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
4.8
Hysteresis of
Referred to VCC
undervoltage threshold VS > 5.5V
6.10
mV
µs
Ramp up time VS > 5.5V CVCC = 4.7 µF
6.11
7
300
to VCC > 4.9V
No load
Voltage Regulator VCC Pin in Silent Mode
5.5V < VS < 18V
Output voltage VCC
7.1
VCC
VCCnor
4.65
5.35
V
A
(0 mA – 50 mA)
Output voltage VCC at
low VS
3.3V < VS < 5.5V
(0 mA – 50 mA)
VVS
– VD
7.2
7.3
VCC
VCC
VCClow
VD
5.1
V
A
A
Regulator drop voltage VS > 3.3V, IVCC = 15 mA
200
mV
At VCC undervoltage
threshold the state
switches back to
Pre-normal mode
Referred to VCC
VS > 5.5
7.4
VCC
VthunS
3.9
4.4
V
A
Hysteresis of
undervoltage
threshold
Referred to VCC
VS > 5.5V
7.5
7.6
VCC
VCC
Vhysthun
IVCCs
40
mV
mA
D
A
Output current limitation VS > 0V
–200
–130
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
15
4850H–AUTO–12/07
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
8
10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps
Driver recessive output
voltage
8.1
8.2
8.3
8.4
8.5
8.6
Load1/Load2
VS = 7V
LIN
LIN
LIN
LIN
LIN
LIN
VBUSrec
V_LoSUP
V_HiSUP
V_LoSUP_1k
V_HiSUP_1k
RLIN
0.9 × VS
VS
1.2
2
V
V
A
A
A
A
A
A
V
Driver dominant voltage
Rload = 500 Ω
VVS = 18V
Driver dominant voltage
Driver dominant voltage
Driver dominant voltage
Pull–up resistor to VS
V
Rload = 500 Ω
VVS = 7V
Rload = 1000 Ω
0.6
0.8
20
V
VVS = 18V
V
Rload = 1000 Ω
The serial diode is
mandatory
30
60
kΩ
Self-adapting current
limitation
VBUS = VBatt_max
Tj = 125°C
Tj = 27°C
Tj = –40°C
52
100
120
110
170
230
mA
mA
mA
8.7
8.8
LIN
LIN
IBUS_LIM
A
A
Input leakage current at Input Leakage current
the receiver including
pull–up resistor as
specified
Driver off
VBUS = 0V
VBatt = 12V
IBUS_PAS_dom
–1
mA
µA
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
Leakage current LIN
recessive
8.9
LIN
LIN
IBUS_PAS_rec
15
20
A
A
VBUS ≥ VBatt
Leakage current when
control unit
disconnected from
ground.
Loss of local ground
must not affect
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
8.10
IBUS_NO_gnd
–10
+0.5
+10
µA
communication in the
residual network
Node has to sustain the
current that can flow
under this condition.
Bus must remain
operational under this
condition
VBatt disconnected
VSUP_Device = GND
0V < VBUS < 18V
8.11
LIN
LIN
IBUS
0.5
3
µA
V
A
A
9
LIN Bus Receiver
Center of receiver
threshold
VBUS_CNT
=
0.475 ×
0.5 ×
VS
0.525 ×
9.1
VBUS_CNT
(Vth_dom + Vth_rec)/2
VS
VS
9.2
9.3
Receiver dominant state VEN = 5V
Receiver recessive state VEN = 5V
Receiver input
LIN
LIN
VBUSdom
VBUSrec
–27
0.4 × VS
V
V
A
A
0.6 × VS
40
0.028 ×
0.175 ×
9.4
V
hys = Vth_rec – Vth_dom
LIN
VBUShys
0.1 × VS
V
A
hysteresis
VS
VS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
16
ATA6620N
4850H–AUTO–12/07
ATA6620N
8. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = –40°C to 125°C
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Wake detection LIN
High level input voltage
9.5
LIN
VLINH
VS – 1V
VS + 0.3V
V
A
Wake detection LIN
Low level input voltage
9.6
10
ILIN = typically –3 mA
LIN
VLINL
–27
VS – 3.3V
V
A
Internal Timers
Dominant time for
wake–up via LIN bus
10.1
VLIN = 0V
VEN = 5V
tbus
30
5
90
150
20
µs
µs
A
A
Time delay for mode
change from Pre-normal
into Normal mode via
pin EN
10.2
tnorm
Time delay for mode
change from Normal
mode to Sleep mode via
pin EN
10.3
10.4
VEN = 0V
tsleep
2
6
7
15
20
µs
A
A
TXD dominant time out
timer
VTXD = 0V
tdom
10
ms
THRec(max) = 0.744 × VS;
THDom(max) = 0.581 × VS;
VS = 7.0V to 18V;
tBit = 50 ms
D1 = tbus_rec(min)/(2 × tBit)
10.5 Duty cycle 1
10.6 Duty cycle 2
D1
D2
0.396
A
A
THRec(min) = 0.422 × VS;
THDom(min) = 0.284 × VS;
VS = 7.0V to 18V;
0.581
tBit = 50ms
D2 = tbus_rec(max)/(2 × tBit)
Slope time falling and
rising edge at LIN
tSLOPE_fall
tSLOPE_rise
10.7
3.5
5
22.5
40
µs
µs
A
A
Time delay for mode
10.8 change from Silent- into VEN = 5V
Normal mode via EN
ts_n
15
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions (CRXD): 20 pF; Rpull-up = 2.4 kΩ
11
Propagation delay of
receiver Switch to Sleep
mode (see Figure 8-1 on
page 18)
11.1
trx_pd = max(trx_pdr, trx_pdf
)
trx_pd
6
µs
µs
A
A
Symmetry of receiver
11.2 propagation delay rising trx_sym = trx_pdr – trx_pdf
edge minus falling edge
trx_sym
–2
+2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
17
4850H–AUTO–12/07
Figure 8-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting Node)
tBus_rec(min)
tBus_dom(max)
Thresholds of
THRec(max)
receiving node 1
THDom(max)
VS
(Transceiver supply
of transmitting node)
LIN Bus Signal
Thresholds of
THRec(min)
THDom(min)
receiving node 2
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving Node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving Node2)
trx_pdr(2)
trx_pdf(2)
18
ATA6620N
4850H–AUTO–12/07
ATA6620N
Figure 8-2. Application Circuit
VBAT
1
VCC
ATA6620N
Normal
and
Pre-normal
Mode
VS
22 µF
RXD
5
100 nF
Receiver
LIN
4
LIN-BUS
220 pF
Filter
VCC
Wake Up Bus Timer
Slew Rate Control
Short-circuit and
Overtemperature
Protection
TXD
6
TXD
Time-out
Timer
VCC
8
Normal Mode
Voltage Regulator
5V/50 mA/2%
Sleep
Mode
VCC
Control
Unit
EN
2
NRES
7
Undervoltage Reset
Switched
Off
Silent Mode
Voltage Regulator
5V/50 mA/7%
GND
3
10 µF
100 nF
19
4850H–AUTO–12/07
9. Ordering Information
Extended Type Number
Package
Remarks
ATA6620N-TAQY
SO8
LIN system basis chip, Pb-free, 4k, taped and reeled
10. Package Information
Package: SO 8
Dimensions in mm
5±0.2
4.9±0.1
3.7±0.1
3.8±0.1
6±0.2
0.4
1.27
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Drawing-No.: 6.541-5031.01-4
Issue: 1; 15.08.06
20
ATA6620N
4850H–AUTO–12/07
ATA6620N
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No. History
4850H-AUTO-12/07 • Section 3.1 “Physical Layer Compatibility” on page 3 added
4850G-AUTO-10/07 • Section 9 “Ordering Information” on page 20 changed
• Put datasheet in a new template
• Capital T for time generally changed in a lower case t
• Section 3.4 “Undervoltage Reset Output (NRES) on page 3 changed
• Section 4.2.2 “Sleep Mode” on page 8 changed
4850F-AUTO-07/07
• Section 6 “Voltage Regulator” on page 12 changed
• Section 7 “Absolute Maximum Ratings” on page 13 changed
• Section 8 “Electrical Characteristics” numbers 5.2, 5.3 and 6.8 on page 15
changed
• Put datasheet in a new template
• ATA6620 in ATA6620N renamed
• Figure 1-1 “Block Diagram” on page 2 changed
• Table 2-1 “Pin Description” on page 2 changed
• Section 4-2 “Modes of Reduced Current Consumption” on page 6 changed
• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 7 changed
4850E-AUTO-04/07
• Section 4.2.2 “Sleep Mode” on page 8 changed
• Figure 4-5 “LIN Wake-up Diagram from Sleep Mode” changed
• Section 4.2.3 “Wake-up from Sleep/Silent Mode at an Insufficient Falling Edge at
pin LIN” on page 9 added
• Section 4.3 “Pre-normal Mode” on page 10 changed
• Section 8 “Electrical Characteristics” on pages 14 to 17 changed
• Figure 8-2 “Application Circuit” on page 19 changed
• Section 3.5 “Bus Pin (LIN)” on page 3 changed
• Figure 4-1 “Mode of Operation” on page 4 changed
• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 6 changed
• Section 4.4 “Pre-normal Mode” on page 7 changed
4850D-AUTO-02/06
• Section 6 “Voltage Regulator” on page 10 changed
• Figure 6-1 “Save Operating Area versus VCC Output Current and Supply Voltage
VS at Different Ambient Temperatures” on page 10 changed
• Table “Absolute Maximum Ratings” on page 11 changed
• Table “Electrical Characteristics” from pages 12 to 15 changed
21
4850H–AUTO–12/07
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4850H–AUTO–12/07
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