ATAR862X-YYY-TNQD4_技术文档

Features

• Single Package Fully-integrated ROM Mask 4-bit Microcontroller with RF Transmitter

• Low Power Consumption in Sleep Mode (< 1 µA Typically)

• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)

• 2.0 V to 4.0 V Operation Voltage for Single Li-cell Power Supply

• -40°C to +125°C Operation Temperature

• SSO24 Package

• About Seven External Components

• Flash Controller for Application Program Available

Microcontroller

with UHF

ASK/FSK

Description

The ATAR862-4 is a single package triple-chip circuit. It combines a UHF ASK/FSK

transmitter with a 4-bit microcontroller and a 512-bit EEPROM. It supports highly

integrated solutions in car access and tire pressure monitoring applications, as well as

manifold applications in the industrial and consumer segment. It is available for the

transmitting frequency range of 429 MHz to 439 MHz with data rates up to 32 kbaud

Manchester coded.

Transmitter

ATAR862-4

Preliminary

For further frequency ranges such as 310 MHz to 330 MHz and 868 MHz to 928 MHz

separate datasheets are available.

The device contains a ROM mask version microcontroller and an additional data

EEPROM.

Figure 1. Application Diagram

ATAR862-4

Antenna

UHF ASK/FSK

Receiver

Micro-

controller

PLL-

Transmitter

Micro-

controller

Keys

Rev. 4552C–4BMCU–01/04

Pin Configuration

Figure 2. Pinning SSO24

XTAL

VS

1

2

3

4

5

6

7

8

9

24 ANT1

23 ANT2

GND

22 PA_ENABLE

21 CLK

ENABLE

NRESET

BP63/T3I

BP20/NTE

BP23

20 BP60/T3O

19 OSC2

18 OSC1

17 BP50/INT6

16 BP52/INT1

15 BP53/INT1

14 BP40/SC/INT3

13 VDD

BP41/T2I/VMI

BP42/T2O 10

BP43/SD/INT3 11

VSS 12

Pin Description: RF Part

Symbol

Function

Configuration

VS

1.5k

1.2k

1

XTAL

Connection for crystal

XTAL

182 µA

2

3

VS

Supply voltage

Ground

ESD protection circuitry (see Figure 8 on page 11)

GND

ENABLE

200k

4

ENABLE

Enable input

2

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Pin Description: RF Part (Continued)

Symbol

Function

Configuration

VS

Clock output signal for microcontroller,

the clock output frequency is set by the

crystal to f_XTAL/4

100

CLK

21

CLK

PA_ENABLE

50k

Uref=1.1V

Switches on power amplifier, used for

ASK modulation

22

PA_ENABLE

20 µA

ANT1

23

24

ANT2

ANT1

Emitter of antenna output stage

Open collector antenna output

ANT2

Pin Description: Microcontroller Part

Name

Type

Function

Alternate Function

Pin No.

13

Reset State

V_DD

–

Supply voltage

Circuit ground

–

NA

V_SS

12

NTE-test mode enable, see section “Master Reset” on

page 21

BP20

BP40

BP41

I/O

Bi-directional I/O line of Port 2.0

Bi-directional I/O line of Port 4.0

Bi-directional I/O line of Port 4.1

7

14

9

Input

SC-serial clock or INT3 external interrupt input

VMI voltage monitor input or T2I external clock input

Timer 2

BP42

BP43

BP50

BP52

BP53

BP60

BP63

I/O

Bi-directional I/O line of Port 4.2

Bi-directional I/O line of Port 4.3

Bi-directional I/O line of Port 5.0

Bi-directional I/O line of Port 5.2

Bi-directional I/O line of Port 5.3

Bi-directional I/O line of Port 6.0

Bi-directional I/O line of Port 6.3

T2O Timer 2 output

10

11

17

16

15

20

6

Input

SD serial data I/O or INT3-external interrupt input

INT6 external interrupt input

INT1 external interrupt input

T3O Timer 3 output

T3I Timer 3 input

4-MHz crystal input or 32-kHz crystal input or external

clock input or external trimming resistor input

OSC1

I

Oscillator input

18

Input

4-MHz crystal output or 32-kHz crystal output or external

clock input

OSC2

O

Oscillator output

19

5

Input

I/O

NRESET

I/O

Bi-directional reset pin

–

3

4552C–4BMCU–01/04

UHF ASK/FSK Transmitter Block

Features

• Integrated PLL Loop Filter

• ESD Protection (4 kV HBM/200 V MM, Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2

• Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically)

• Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Connecting an Additional Capacitor between the XTAL Load Capacitor and the Open-

drain Output of the Modulating Microcontroller

• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

• Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40°C to +125°C

• Single-ended Antenna Output with High Efficient Power Amplifier

• External CLK Output for Clocking the Microcontroller

• 125°C Operation for Tire Pressure Systems

Description

The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates up to

32 kbaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems.

4

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 3. Block Diagram

ATAR862-4

ENABLE

Power up/

down

CLK

f

4

f

32

PFD

CP

VS

PA_ENABLE

ANT2

GND

LF

XTAL

ANT1

PA

VCO

XTO

PLL

OSC2

OSC1

V

DD

V

SS

Microcontroller

UTCM

Brown-out protect.

RESET

RC

Crystal

External

NRESET

oscillators oscillators clock input

Timer 1

Voltage monitor

External input

Clock management

interval- and

watchdog timer

T2I

Timer 2

VMI

8-/12-bit timer

with modulator

T2O

BP10

BP13

ROM

RAM

256 x 4 bit

Port 1

4 K x 8 bit

SD

SC

SSI

Serial interface

Timer 3

BP20/NTE

BP23

4-bit CPU core

T3O

T3I

BP21

BP22

8-bit

timer/counter

with modulator

and demodulator

I/O bus

Data direction +

alternate function

Data direction +

interrupt control

Data direction +

alternate function

EEPROM

32 x 16 bit

Port 4

Port 6

Port 5

BP51

INT6

BP40

INT3

SC

BP41BP42 BP43 BP50

BP52 BP53 BP60

INT1 T3O

BP63

T3I

T2O

INT6

VMI

T2I

INT3

SD

INT1

5

4552C–4BMCU–01/04

General Description

The fully-integrated PLL transmitter that allows particularly simple, low-cost RF minia-

ture transmitters to be assembled. The VCO is locked to 32 × f_XTAL, thus, a 13.56 MHz

crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral

elements are integrated.

The XTO is a series resonance oscillator so that only one capacitor together with a

crystal connected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs maximum < 1 ms until the PLL is

locked and the CLK output is stable. A wait time of ≥ 1 ms until the CLK is used for the

microcontroller and the PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly

independent from the load impedance. The delivered output power is controlled via the

connected load impedance.

This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A

high power efficiency of η= P_out/(I_S,PA× V_S) of 36% for the power amplifier results when

an optimized load impedance of Z_Load= (166 + j223) Ω is used at 3 V supply voltage.

Functional

Description

If ENABLE = L and PA_ENABLE = L, the circuit is in standby mode consuming only a

very small amount of current so that a lithium cell used as power supply can work for

several years.

With ENABLE = H, the XTO, PLL and the CLK driver are switched on. If PA_ENABLE

remains L, only the PLL and the XTO are running and the CLK signal is delivered to the

microcontroller. The VCO locks to 32 times the XTO frequency.

With ENABLE = H and PA_ENABLE = H, the PLL, XTO, CLK driver and the power

amplifier are on. With PA_ENABLE, the power amplifier can be switched on and off,

which is used to perform the ASK modulation.

ASK Transmission

FSK Transmission

The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for

t ≥ 1 ms, then the CLK signal can be taken to clock the microcontroller and the output

power can be modulated by means of pin PA_ENABLE. After transmission,

PA_ENABLE is switched to L and the microcontroller switches back to internal clocking.

The PLL transmitter block is switched back to standby mode with ENABLE = L.

The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for

t ≥ 1 ms, then the CLK signal can be taken to clock the microcontroller and the power

amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modula-

tion. The microcontroller starts to switch on and off the capacitor between the XTAL load

capacitor and GND with an open-drain output port, thus changing the reference

frequency of the PLL. If the switch is closed, the output frequency is lower than if the

switch is open. After transmission PA_ENABLE is switched to L and the microcontroller

switches back to internal clocking. The PLL transmitter block is switched back to

standby mode with ENABLE = L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when

the following tolerances are considered.

6

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 4. Tolerances of Frequency Modulation

~

V_S

C_Stray2

C_Stray1

XTAL

C_ML_M

R_S

C₄

C₀

Crystal equivalent circuit

C₅

C_Switch

Using C₄= 9.2 pF ±2%, C₅= 6.8 pF ±5%, a switch port with CS_witch= 3 pF ±10%, stray

capacitances on each side of the crystal of C_Stray1= C_Stray2= 1 pF ±10%, a parallel

capacitance of the crystal of C₀= 3.2 pF ±10% and a crystal with C_M= 13 fF ±10%, an

FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz

results.

CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is

CMOS compatible if the load capacitance is lower than 10 pF.

Clock Pulse Take Over

The clock of the crystal oscillator can be used for clocking the microcontroller. The

microcontroller block has the special feature of starting with an integrated RC-oscillator

to switch on the PLL transmitter block with ENABLE = H, and after 1 ms to assume the

clock signal of the transmission IC, so the message can be sent with crystal accuracy.

Output Matching and Power

Setting

The output power is set by the load impedance of the antenna. The maximum output

power is achieved with a load impedance of Z_Load,opt= (166 + j223) Ω. There must be a

low resistive path to V_Sto deliver the DC current.

The delivered current pulse of the power amplifier is 9 mA and the maximum output

power is delivered to a resistive load of 465 Ω if the 1.0 pF output capacitance of the

power amplifier is compensated by the load impedance.

An optimum load impedance of:

Z_Load= 465 Ω || j/(2 × π 1.0 pF) = (166 + j223) Ω thus results for the maximum output

power of 7.5 dBm.

The load impedance is defined as the impedance seen from the PLL transmitter block’s

ANT1, ANT2 into the matching network. Do not confuse this large signal load imped-

ance with a small signal input impedance delivered as input characteristic of RF

amplifiers and measured from the application into the IC instead of from the IC into the

application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 465 Ω where the

parallel imaginary part should be kept constant.

Output power measurement can be done with the circuit shown in Figure 5 on page 8.

Note that the component values must be changed to compensate the individual board

parasitics until the PLL transmitter block has the right load impedance

Z_Load,opt= (166 + j223) Ω. Also the damping of the cable used to measure the output

power must be calibrated.

7

4552C–4BMCU–01/04

Figure 5. Output Power Measurement

V_S

C₁= 1n

L₁= 33n

Power

meter

ANT1

ANT2

Z = 50 Ω

Z_Lopt

C₂= 2.2p

R

in

50 Ω

~

Application Circuit

For the supply-voltage blocking capacitor C₃, a value of 68 nF/X7R is recommended

(see Figure 6 on page 9 and Figure 7 on page 10). C₁and C₂are used to match the loop

antenna to the power amplifier where C₁typically is 8.2 pF/NP0 and C₂is 6 pF/NP0

(10 pF + 15 pF in series); for C₂two capacitors in series should be used to achieve a

better tolerance value and to have the possibility to realize the Z_Load,optby using

standard valued capacitors.

C₁forms together with the pins of PLL transmitter block and the PCB board wires a

series resonance loop that suppresses the 1^stharmonic, thus, the position of C₁on the

PCB is important. Normally the best suppression is achieved when C₁is placed as close

as possible to the pins ANT1 and ANT2.

The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the

loop antenna is too high.

L1 (≈ 50 nH to 100 nH) can be printed on PCB. C4 should be selected so the XTO runs

on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a

15 pF load-capacitance crystal.

8

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 6. ASK Application Circuit

VS

L1

C4

XTAL

1

XTO

VCO

LF

PA

24

ANT1

XTAL

Loop

C1

Antenna

VS

C2

VS

2

23

ANT2

CP

C3

PFD

GND

3

22

PA_ENABLE

32

f

PLL

ENABLE

4

21

f

CLK

Power up/down

NRESET

5

BP60/T3O

20

BP63/T3I

6

OSC2

19

BP20/NTE

7

OSC1

18

BP23

8

BP50/INT6

S1

17

BP41/T2I/VMI

9

BP52/INT1

S2

16

BP42/T2O

10

BP53/INT1

S3

15

BP43/SD/

INT3

BP40/SC/INT3

17

11

VSS

12

VDD

13

VS

9

4552C–4BMCU–01/04

Figure 7. FSK Application Circuit

VS

L1

C4

XTAL

1

XTO

VCO

LF

PA

24

23

22

ANT1

C5

XTAL

VS

Loop

Antenna

C1

C2

VS

2

3

ANT2

CP

C3

PFD

GND

PA_ENABLE

32

f

PLL

ENABLE

4

21

f

CLK

Power up/down

NRESET

BP60/T3O

20

5

BP63/T3I

OSC2

19

6

BP20/NTE

OSC1

18

7

BP23

BP50/INT6

17

S1

S2

S3

8

BP41/T2I/VMI

9

BP52/INT1

16

BP42/T2O

10

BP53/INT1

15

BP43/SD/

INT3

BP40/SC/INT3

17

11

VSS

12

VDD

13

VS

10

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 8. ESD Protection Circuit

VS

ANT1

CLK

PA_ENABLE

ANT2

XTAL

ENABLE

GND

Absolute Maximum Ratings: RF Part

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

V_S

Min.

Max.

5

Unit

V

Supply voltage

Power dissipation

Junction temperature

Storage temperature

Ambient temperature

P_tot

100

150

+125

mW

°C

T_j

T_stg

-55

T_amb

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

R_thJA

135

K/W

Electrical Characteristics

V_S= 2.0 V to 4.0 V, T_amb= -40° C to +125°C unless otherwise specified.

Typical values are given at V_S= 3.0 V and T_amb= 25° C. All parameters are referred to GND (Pin 3).

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Power down,

V_ENABLE< 0.25 V, -40°C to +85°C

350

7

nA

µA

nA

Supply current

V_PA-ENABLE< 0.25 V, -85°C to +125°C

I_{S_Off}

V_PA-ENABLE< 0.25 V, +25°C

<10

(100% correlation tested)

Power up, PA off, V_S= 3 V

Supply current

Output power

I_S

3.7

9

4.8

11.6

10

mA

V_ENABLE> 1.7 V, V_PA-ENABLE< 0.25 V

Power up, V_S= 3.0 V

V_ENABLE> 1.7 V, V_PA-ENABLE> 1.7 V

I_{S_Transmit}

P_Ref

V_S= 3.0 V, T_amb= 25°C

f = 433.92 MHz, Z_Load= (166 + j233) Ω

5.5

7.5

dBm

11

4552C–4BMCU–01/04

Electrical Characteristics (Continued)

V_S= 2.0 V to 4.0 V, T_amb= -40° C to +125°C unless otherwise specified.

Typical values are given at V_S= 3.0 V and T_amb= 25° C. All parameters are referred to GND (Pin 3).

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

T_amb= -40°C to +85°C

V_S= 3.0 V

V_S= 2.0 V

Output power variation for the full

temperature range

∆P_Ref

-1.5

-4.0

dB

T_amb= -40°C to +125°C

Output power variation for the full V_S= 3.0 V

∆P_Ref

-2.0

-4.5

dB

temperature range

V_S= 2.0 V

P_Out= P_Ref+ ∆P_Ref

Achievable output-power range

Selectable by load impedance

P_{Out_typ}

0

7.5

dBm

f_CLK= f₀/128

Load capacitance at pin CLK = 10 pF

f_O± 1 × f_CLK

f_O± 4 × f_CLK

Spurious emission

-55

-52

dBc

other spurious are lower

f_XTO= f₀/32

f_XTAL= resonant frequency of the

XTAL, C_M≤10 fF, load capacitance

selected accordingly

Oscillator frequency XTO

(= phase comparator frequency)

f_XTO

T_amb= -40°C to +85°C

T_amb= -40°C to +125°C

-30

-40

f_XTAL

+30

+40

ppm

PLL loop bandwidth

250

-116

-86

kHz

Phase noise of phase

comparator

Referred to f_PC= f_XT0,

25 kHz distance to carrier

-110

-80

dBc/Hz

In loop phase noise PLL

25 kHz distance to carrier

dBc/Hz

at 1 MHz

at 36 MHz

-94

-125

-90

-121

dBc/Hz

Phase noise VCO

Frequency range of VCO

f_VCO

429

439

MHz

Clock output frequency (CMOS

microcontroller compatible)

f₀/128

MHz

V_0h

V_0l

V_S× 0.8

V

Voltage swing at pin CLK

C_Load≤10 pF

V_S× 0.

2

Series resonance R of the crystal

Capacitive load at pin XT0

Rs

110

7

Ω

pF

Duty cycle of the modulation signal =

50%

FSK modulation frequency rate

ASK modulation frequency rate

0

32

kHz

Duty cycle of the modulation signal =

50%

32

Low level input voltage

High level input voltage

Input current high

V_Il

V_Ih

I_In

0.25

V

µA

ENABLE input

1.7

20

Low level input voltage

High level input voltage

Input current high

V_Il

V_Ih

I_In

0.25

V

µA

PA_ENABLE input

5

12

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Microcontroller Block

Features

• Extended Temperature Range for High Temperature up to 125° C

• 4-Kbyte ROM, 256 × 4-bit RAM

• 11 Bi-directional I/Os

• Up to Seven External/Internal Interrupt Sources

• Multifunction Timer/Counter

– IR Remote Control Carrier Generator

– Biphase-, Manchester- and Pulse-width Modulator and Demodulator

– Phase Control Function

• Programmable System Clock with Prescaler and Five Different Clock Sources

• Supply-voltage Range (2.0 V to 4.0 V)

• Very Low Sleep Current (< 1 µA)

• 32 × 16-bit EEPROM

• Synchronous Serial Interface (2-wire, 3-wire)

• Watchdog, POR and Brown-out Function

• Voltage Monitoring Inclusive Lo_BAT Detect

• Flash Controller T48C862 Available (SSO24)

Description

The ATAR862-4 is a member of Atmel’s family of 4-bit single-chip microcontrollers. The

ATAR862-4 is suitable for the transmitter side as well as the receiver side. It contains

ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters with

modulator and demodulator function, voltage supervisor, interval timer with watchdog

function and a sophisticated on-chip clock generation with external clock input, inte-

grated RC-oscillator, 32-kHz and 4-MHz crystal-oscillators. The ATAR862-4 has an

EEPROM as a third chip in one package.

Figure 9. Block Diagram

V

OSC1 OSC2

SS DD

Brown-out protect.

RESET

RC

Crystal

External

UTCM

oscillators oscillators clock input

Timer 1

Voltage monitor

External input

Clock management

interval- and

watchdog timer

T2I

Timer 2

VMI

8/12-bit timer

T2O

BP10

BP13

ROM

4 K x 8 bit

RAM

256 x 4 bit

Port 1

with modulator

SD

SC

SSI

Serial interface

Timer 3

MARC4

BP20/NTE

T3O

T3I

4-bit CPU core

BP21

BP22

BP23

8-bit

timer / counter

with modulator

and demodulator

I/O bus

Data direction +

alternate function

Data direction +

interrupt control

Data direction +

alternate function

Port 4

Port 6

Port 5

BP40

INT3

SC BP41

VMI

BP42

T2O

BP50

INT6

BP52

INT1

BP60

T3O

BP63

T3I

BP43

INT3

SD

BP51

INT6

BP53

INT1

T2I

13

4552C–4BMCU–01/04

Introduction

The ATAR862-4 is a member of Atmel’s family of 4-bit single-chip microcontrollers. It

contains ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction

timer/counters, voltage supervisor, interval timer with watchdog function and a sophisti-

cated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal

oscillators.

Table 1. Available Variants

Version

Type

ROM

E2PROM Peripheral

64-bytes

Packages

SSO24

Flash

device

T48C862

ATAR862

4-Kbyte EEPROM

4-Kbyte Mask ROM

Production

64-bytes

SSO24

MARC4 Architecture The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and

on-chip peripherals. The CPU is based on the Harvard architecture with physically

General Description

separated program memory (ROM) and data memory (RAM). Three independent

buses, the instruction bus, the memory bus and the I/O bus, are used for parallel

communication between ROM, RAM and peripherals. This enhances program execution

speed by allowing both instruction prefetching, and a simultaneous communication to

the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller

with associated eight prioritized interrupt levels supports fast and efficient processing of

hardware events. The MARC4 is designed for the high-level programming language

qFORTH. The core includes both an expression and a return stack. This architecture

enables high-level language programming without any loss of efficiency or code density.

Figure 10. MARC4 Core

MARC4 CORE

X

Reset

RAM

Y

Program

memory

PC

SP

RP

256 x 4-bit

Reset

Clock

Instruction

bus

Memory bus

CCR

Instruction

decoder

TOS

System

clock

ALU

Interrupt

controller

Sleep

I/O bus

On-chip peripheral modules

Components of

MARC4 Core

The core contains ROM, RAM, ALU, program counter, RAM address registers, instruc-

tion decoder and interrupt controller. The following sections describe each functional

block in more detail.

14

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

ROM

The program memory (ROM) is mask programmed with the customer application

program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit

wide program counter, thus predefining a maximum program bank size of 4 Kbytes. An

additional 1-Kbyte of ROM exists, which is reserved for quality control self-test software

The lowest user ROM address segment is taken up by a 512-bytes Zero page which

contains predefined start addresses for interrupt service routines and special subrou-

tines accessible with single byte instructions (SCALL).

The corresponding memory map is shown in Figure 11. Look-up tables of constants can

also be held in ROM and are accessed via the MARC4’s built-in table instruction.

Figure 11. ROM Map of the Microcontroller Block

1F8h

1F0h

FFFh

1E8h

1E0h

1C0h

180h

140h

100h

0C0h

080h

040h

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

ROM

(4 K x 8 bit)

Zero

page

7FFh

020h

018h

010h

008h

000h

1FFh

000h

$RESET

008h

000h

Zero page

$AUTOSLEEP

RAM

The microcontroller block contains 256 × 4-bit wide static random access memory

(RAM), which is used for the expression stack. The return stack and data memory are

used for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM

address registers SP, RP, X and Y.

Expression Stack

The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All

arithmetic, I/O and memory reference operations take their operands, and return their

results to the expression stack. The MARC4 performs the operations with the top of

stack items (TOS and TOS-1). The TOS register contains the top element of the expres-

sion stack and works in the same way as an accumulator. This stack is also used for

passing parameters between subroutines and as a scratch pad area for temporary

storage of data.

Return Stack

The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for

storing return addresses of subroutines, interrupt routines and for keeping loop index

counts. The return stack can also be used as a temporary storage area.

The MARC4 instruction set supports the exchange of data between the top elements of

the expression stack and the return stack. The two stacks within the RAM have a user

definable location and maximum depth.

15

4552C–4BMCU–01/04

Figure 12. RAM Map

RAM

(256 x 4-bit)

Autosleep

Expression stack

3

0

FCh

FFh

TOS

TOS-1

TOS-2

SP

Global

variables

X

Y

4-bit

Expression

stack

Return stack

SP

TOS-1

11

0

RP

Return

stack

RP

04h

00h

Global

v

ariables

07h

03h

12-bit

Registers

The microcontroller has seven programmable registers and one condition code register

(see Figure 13).

Program Counter (PC)

The program counter is a 12-bit register which contains the address of the next instruc-

tion to be fetched from the ROM. Instructions currently being executed are decoded in

the instruction decoder to determine the internal micro-operations. For linear code (no

calls or branches), the program counter is incremented with every instruction cycle. If a

branch-, call-, return-instruction or an interrupt is executed, the program counter is

loaded with a new address. The program counter is also used with the table instruction

to fetch 8-bit wide ROM constants.

Figure 13. Programming Mode l

11

0

PC

Program counter

0

7

0

RP

SP

Return stack pointer

Expression stack pointer

0

7

X

Y

RAM address register (X)

RAM address register (Y)

0

3

Top of stack register

TOS

CCR

3

Condition code register

C

--

B

I

Interrupt enable

Branch

Reserved

Carry / borrow

16

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

RAM Address Registers

The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.

These registers allow access to any of the 256 RAM nibbles.

Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the

expression stack. The pointer is automatically pre-incremented if a nibble is moved onto

the stack or post-decremented if a nibble is removed from the stack. Every post-

decrement operation moves the item (TOS-1) to the TOS register before the SP is

decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate

the start address of the expression stack area.

Return Stack Pointer (RP)

The return stack pointer points to the top element of the 12-bit wide return stack. The

pointer automatically pre-increments if an element is moved onto the stack, or it post-

decrements if an element is removed from the stack. The return stack pointer incre-

ments and decrements in steps of 4. This means that every time a 12-bit element is

stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH

compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial-

ized via >RP FCh.

RAM Address Registers

(X and Y)

The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation

moves the addressed nibble onto the TOS. A store operation moves the TOS to the

addressed RAM location. By using either the pre-increment or post-decrement address-

ing mode arrays in the RAM can be compared, filled or moved.

Top of Stack (TOS)

The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory

reference and I/O operations use this register. The TOS register receives data from the

ALU, ROM, RAM or I/O bus.

Condition Code Register

(CCR)

The 4-bit wide condition code register contains the branch, the carry and the interrupt

enable flag. These bits indicate the current state of the CPU. The CCR flags are set or

reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow

direct manipulation of the condition code register.

Carry/Borrow (C)

Branch (B)

The carry/borrow flag indicates that the borrowing or carrying out of arithmetic logic unit

(ALU) occurred during the last arithmetic operation. During shift and rotate operations,

this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.

The branch flag controls the conditional program branching. Should the branch flag has

been set by a previous instruction, a conditional branch will cause a jump. This flag is

affected by arithmetic, logic, shift, and rotate operations.

Interrupt Enable (I)

The interrupt enable flag globally enables or disables the triggering of all interrupt

routines with the exception of the non-maskable reset. After a reset or while executing

the DI instruction, the interrupt enable flag is reset, thus disabling all interrupts. The core

will not accept any further interrupt requests until the interrupt enable flag has been set

again by either executing an EI or SLEEP instruction.

17

4552C–4BMCU–01/04

ALU

The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top

two elements of the expression stack (TOS and TOS-1) and returns the result to the

TOS. The ALU operations affects the carry/borrow and branch flag in the condition code

register (CCR).

Figure 14. ALU Zero-address Operations

RAM

TOS-1

TOS-2

TOS-3

SP

TOS

TOS-4

ALU

CCR

I/O Bus

The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-

cation between the core and the on-chip peripherals take place via the I/O bus and the

associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a

direct read or write access to one of the 16 primary I/O addresses. More about the I/O

access to the on-chip peripherals is described in the section “Peripheral Modules” on

page 30. The I/O bus is internal and is not accessible by the customer on the final micro-

controller device, but it is used as the interface for the MARC4 emulation (see section

“Emulation” on page 98).

Instruction Set

The MARC4 instruction set is optimized for the high level programming language

qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to

generate a fast and compact program code. The CPU has an instruction pipeline allow-

ing the controller to prefetch an instruction from ROM at the same time as the present

instruction is being executed. The MARC4 is a zero-address machine, the instructions

contain only the operation to be performed and no source or destination address fields.

The operations are implicitly performed on the data placed on the stack. There are one-

and two-byte instructions which are executed within 1 to 4 machine cycles. A MARC4

machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions

are only one byte long and are executed in a single machine cycle. For more information

refer to the “MARC4 Programmer’s Guide”.

Interrupt Structure

The MARC4 can handle interrupts with eight different priority levels. They can be gener-

ated from the internal and external interrupt sources or by a software interrupt from the

CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the

service routine in the ROM (see Table 2 on page 20). The programmer can postpone

the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An inter-

rupt occurrence will still be registered, but the interrupt routine only started after the

I-flag is set. All interrupts can be masked, and the priority individually software config-

ured by programming the appropriate control register of the interrupting module (see

section “Peripheral Modules” on page 30).

18

ATAR862-4 [Preliminary]

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ATAR862-4 [Preliminary]

Interrupt Processing

For processing the eight interrupt levels, the MARC4 includes an interrupt controller with

two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller

samples all interrupt requests during every non-I/O instruction cycle and latches these in

the interrupt pending register. If no higher priority interrupt is present in the interrupt

active register, it signals the CPU to interrupt the current program execution. If the inter-

rupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this

cycle a short call (SCALL) instruction to the service routine is executed and the current

PC is saved on the return stack. An interrupt service routine is completed with the RTI

instruction. This instruction resets the corresponding bits in the interrupt pending/active

register and fetches the return address from the return stack to the program counter.

When the interrupt enable flag is reset (triggering of interrupt routines is disabled), the

execution of new interrupt service routines is inhibited but not the logging of the interrupt

requests in the interrupt pending register. The execution of the interrupt is delayed until

the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt

request occurs while the corresponding bit in the pending register is still set (i.e., the

interrupt service routine is not yet finished).

It should be noted that automatic stacking of the RBR is not carried out by the hardware

and so if ROM banking is used, the RBR must be stacked on the expression stack by

the application program and restored before the RTI. After a master reset (power-on,

brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and

interrupt active register are all reset.

Interrupt Latency

The interrupt latency is the time from the occurrence of the interrupt to the interrupt ser-

vice routine being activated. This is extremely short (taking between 3 to 5 machine

cycles depending on the state of the core).

Figure 15. Interrupt Handling

INT7

7

6

5

INT7 active

RTI

INT5

INT5 active

RTI

INT3

4

INT2

3

INT3 active

RTI

INT2 pending

SWI0

2

1

0

INT2 active

RTI

INT0 pending

INT0 active

RTI

Main /

Autosleep

Main /

Autosleep

Time

19

4552C–4BMCU–01/04

Table 2. Interrupt Priority Table

Interrupt

Priority

ROM Address

Interrupt Opcode

Function

INT0

Lowest

040h

C8h (SCALL 040h)

Software interrupt (SWI0)

External hardware interrupt, any edge at BP52 or

BP53

INT1

INT2

INT3

|

080h

0C0h

100h

D0h (SCALL 080h)

D8h (SCALL 0C0h)

E8h (SCALL 100h)

Timer 1 interrupt

SSI interrupt or external hardware interrupt at BP40

or BP43

INT4

INT5

|

140h

180h

E8h (SCALL 140h)

F0h (SCALL 180h)

Timer 2 interrupt

Timer 3 interrupt

External hardware interrupt, at any edge at BP50 or

BP51

INT6

INT7

|

1C0h

1E0h

F8h (SCALL 1C0h)

FCh (SCALL 1E0h)

Highest

Voltage monitor (VM) interrupt

Table 3. Hardware Interrupts

Interrupt Mask

Interrupt

Register

Bit

Interrupt Source

P52M1, P52M2

P53M1, P53M2

Any edge at BP52

any edge at BP53

INT1

P5CR

INT2

INT3

INT4

T1M

SISC

T2CM

T1IM

SIM

Timer 1

SSI buffer full/empty or BP40/BP43 interrupt

Timer 2 compare match/overflow

T2IM

T3CM1

T3CM2

T3C

T3IM1

T3IM2

T3EIM

Timer 3 compare register 1 match

Timer 3 compare register 2 match

Timer 3 edge event occurs (T3I)

INT5

P50M1, P50M2

P51M1, P51M2

Any edge at BP50,

any edge at BP51

INT6

INT7

P5CR

VCM

VIM

External/internal voltage monitoring

Software Interrupts

The programmer can generate interrupts by using the software interrupt instruction

(SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The

software triggered interrupt operates exactly like any hardware triggered interrupt. The

SWI instruction takes the top two elements from the expression stack and writes the

corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using

the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled

for later execution.

Hardware Interrupts

In the microcontroller block, there are eleven hardware interrupt sources with seven

different levels. Each source can be masked individually by mask bits in the correspond-

ing control registers. An overview of the possible hardware configurations is shown in

Table 3 on page 20.

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ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Master Reset

The master reset forces the CPU into a well-defined condition. It is unmaskable and

is activated independent of the current program state. It can be triggered by either

initial supply power-up, a short collapse of the power supply, brown-out detection

circuitry, watchdog time-out, or an external input clock supervisor stage (see Figure 16).

A master reset activation will reset the interrupt enable flag, the interrupt pending regis-

ter and the interrupt active register. During the power-on reset phase, the I/O bus control

signals are set to reset mode, thereby, initializing all on-chip peripherals. All bi-direc-

tional ports are set to input mode.

Attention: During any reset phase, the BP20/NTE input is driven towards V_DDby an

additional internal strong pull-up transistor. This pin must not be pulled down to V_SS

during reset by any external circuitry representing a resistor of less than 150 kΩ.

Releasing the reset results in a short call instruction (opcode C1h) to the ROM address

008h. This activates the initialization routine $RESET which in turn has to initialize all

necessary RAM variables, stack pointers and peripheral configuration registers (see

Table 10 on page 32).

Figure 16. Reset Configuration

V

DD

Pull-up

CL

Reset

timer

res

Internal

reset

NRST

CL=SYSCL/4

V

Power-on

reset

DD

V

SS

V

DD

Brown-out

detection

V

SS

Watch-

dog

CWD

ExIn

res

Ext. clock

supervisor

Power-on Reset and

Brown-out Detection

The microcontroller block has a fully integrated power-on reset and brown-out detection

circuitry. For reset generation no external components are needed.

These circuits ensure that the core is held in the reset state until the minimum operating

supply voltage has been reached. A reset condition will also be generated should the

supply voltage drop momentarily below the minimum operating level except when a

power-down mode is activated (the core is in SLEEP mode and the peripheral clock is

stopped). In this power-down mode the brown-out detection is disabled.

Two values for the brown-out voltage threshold are programmable via the BOT bit in the

SC register.

21

4552C–4BMCU–01/04

A power-on reset pulse is generated by a V_DDrise across the default BOT voltage level

(1.7 V). A brown-out reset pulse is generated when V_DDfalls below the brown-out

voltage threshold. Two values for the brown-out voltage threshold are programmable via

the BOT bit in the SC register. When the controller runs in the upper supply voltage

range with a high system clock frequency, the high threshold must be used. When it

runs with a lower system clock frequency, the low threshold and a wider supply voltage

range may be chosen. For further details, see the electrical specification and the

SC register description for BOT programming.

Figure 17. Brown-out Detection

V

DD

2.0 V

1.7 V

t

d

t

CPU

Reset

BOT = '1'

BOT = '0'

t

d

CPU

Reset

t = 1.5 ms (typically)

d

BOT = 1, low brown-out voltage threshold 1.7 V (is reset value).

BOT = 0, high brown-out voltage threshold 2.0 V.

Watchdog Reset

The watchdog’s function can be enabled at the WDC register and triggers a reset with

every watchdog counter overflow. To suppress the watchdog reset, the watchdog

counter must be regularly reset by reading the watchdog register address (CWD). The

CPU reacts in exactly the same manner as a reset stimulus from any of the above

sources.

External Clock Supervisor

The external input clock supervisor function can be enabled if the external input clock is

selected within the CM and SC registers of the clock module. The CPU reacts in exactly

the same manner as a reset stimulus from any of the above sources.

Voltage Monitor

The voltage monitor consists of a comparator with internal voltage reference. It is used

to supervise the supply voltage or an external voltage at the VMI pin. The comparator for

the supply voltage has three internal programmable thresholds one lower threshold

(2.2 V), one middle threshold (2.6 V) and one higher threshold (3.0 V). For external

voltages at the VMI pin, the comparator threshold is set to V_BG= 1.3 V. The VMS bit

indicates if the supervised voltage is below (VMS = 0) or above (VMS = 1) this thresh-

old. An interrupt can be generated when the VMS bit is set or reset to detect a rising or

falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit

(VIM) is reset in the VMC register.

22

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 18. Voltage Monitor

V

DD

Voltage monitor

INT7

OUT

BP41/

VMI

IN

VMC :

VM2 VM1 VM0 VIM

VMST :

-

res VMS

Voltage Monitor Control/

Status Register

Primary register address: "F’hex"

Bit 3

Bit 2

Bit 1

Bit 0

VMC: Write

VMST: Read

VM2

VM1

VM0

VIM

Reset value: 1111b

Reset value: xx11b

–

Reserved

VMS

VM2:

VM1:

VM0:

Voltage monitor Mode bit 2

Voltage monitor Mode bit 1

Voltage monitor Mode bit 0

Table 4. Voltage Monitor Modes

VM2

VM1

VM0

Function

Disable voltage monitor

1

External (VIM input), internal reference threshold (1.3 V), interrupt

with negative slope

1

0

1

0

Not allowed

External (VMI input), internal reference threshold (1.3 V), interrupt

with positive slope

Internal (supply voltage), high threshold (3.0 V), interrupt with

negative slope

0

1

0

Internal (supply voltage), middle threshold (2.6 V), interrupt with

negative slope

Internal (supply voltage), low threshold (2.2 V), interrupt with

negative slope

0

1

0

Not allowed

VIM

Voltage Interrupt Mask bit

VIM = 0, voltage monitor interrupt is enabled

VIM = 1, voltage monitor interrupt is disabled

VMS

Voltage Monitor Status bit

VMS = 0, the voltage at the comparator input is below V_Ref

VMS = 1, the voltage at the comparator input is above V_Ref

23

4552C–4BMCU–01/04

Figure 19. Internal Supply Voltage Supervisor

Low threshold

VMS = 1

DD

Middle threshold

High threshold

V

3.0 V

2.6 V

2.2 V

Low threshold

Middle threshold

High threshold

VMS = 0

Figure 20. External Input Voltage Supervisor

Internal reference level

VMI

Interrupt positive slope

Negative slope

VMS = 1

VMS = 0

1.3 V

VMS = 0

Positive slope

t

Interrupt negative slope

Clock Generation

Clock Module

The microcontroller block contains a clock module with 4 different internal oscillator

types: two RC oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator.

The pins OSC1 and OSC2 are the interface to connect a crystal either to the 4-MHz, or

to the 32-kHz crystal oscillator. OSC1 can be used as input for external clocks or to

connect an external trimming resistor for the RC-oscillator 2. All necessary circuitry,

except the crystal and the trimming resistor, is integrated on-chip. One of these oscilla-

tor types or an external input clock can be selected to generate the system clock

(SYSCL).

In applications that do not require exact timing, it is possible to use the fully integrated

RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency

tolerance is better than ± 50%. The RC-oscillator 2 is a trimmable oscillator whereby the

oscillator frequency can be trimmed with an external resistor attached between OSC1

and V_DD. In this configuration, the RC-oscillator 2 frequency can be maintained stable

with a tolerance of ±15% over the full operating temperature and voltage range.

The clock module is programmable via software with the clock management register

(CM) and the system configuration register (SC). The required oscillator configuration

can be selected with the OS1 bit and the OS0 bit in the SC register. A programmable

4-bit divider stage allows the adjustment of the system clock speed. A special feature of

the clock management is that an external oscillator may be used and switched on and

off via a port pin for the power-down mode. Before the external clock is switched off, the

internal RC-oscillator 1 must be selected with the CCS bit and then the SLEEP mode

may be activated. In this state an interrupt can wake up the controller with the RC-

oscillator, and the external oscillator can be activated and selected by software. A

synchronization stage avoids too short clock periods if the clock source or the clock

speed is changed. If an external input clock is selected, a supervisor circuit monitors the

24

ATAR862-4 [Preliminary]

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ATAR862-4 [Preliminary]

external input and generates a hardware reset if the external clock source fails or drops

below 500 kHz for more than 1 ms.

Figure 21. Clock Module

RC

oscillator 1

Ext. clock

ExIn

OSC1

SYSCL

Oscin

ExOut

Stop

*

IN1

IN2

RCOut1

RC oscillator2

R_Trim

Cin

Stop Control

RCOut2

Stop

/2

4-MHz oscillator

Oscin

Divider

4Out

Stop

Oscout

32-kHz oscillator

Oscin

OSC2

Oscout

32Out

Sleep

WDL

*

Osc-Stop

Cin/16

32 kHz

SUBCL

CM: NSTOP CCS

CSS1 CSS0

mask option

SC:

BOT

- - -

OS1

OS0

Table 5. Clock Modes

Clock Source for SYSCL

CCS = 1 CCS = 0

Clock Source

for SUBCL

Mode OS1

OS0

RC-oscillator 1

(internal)

1

External input clock

C_in/16

RC-oscillator 2 with

external trimming

resistor

RC-oscillator 1

(internal)

2

0

1

C_in/16

RC-oscillator 1

(internal)

3

4

1

0

4-MHz oscillator

32-kHz oscillator

C_in/16

RC-oscillator 1

(internal)

32 kHz

The clock module generates two output clocks. One is the system clock (SYSCL) and

the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals

and the SUBCL can supply only the peripherals with clocks. The modes for clock

sources are programmable with the OS1 bit and OS0 bit in the SC register and the CCS

bit in the CM register.

Oscillator Circuits and

External Clock Input

Stage

The microcontroller block series consists of four different internal oscillators: two RC-

oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one external

clock input stage.

RC-oscillator 1

Fully Integrated

For timing insensitive applications, it is possible to use the fully integrated RC-

oscillator 1. It operates without any external components and saves additional costs.

The RC-oscillator 1 center frequency tolerance is better than ±50% over the full temper-

ature and voltage range. The basic center frequency of the RC-oscillator 1 is

f_O≈ 3.8 MHz. The RC-oscillator 1 is selected by default after power-on reset.

25

4552C–4BMCU–01/04

Figure 22. RC-oscillator 1

RC

oscillator 1

RcOut1

Stop

Osc-Stop

Control

External Input Clock

The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it

meets the specified duty cycle, rise and fall times and input levels. Additionally, the

external clock stage contains a supervisory circuit for the input clock. The supervisor

function is controlled via the OS1, OS0 bit in the SC register and the CCS bit in the CM

register. If the external input clock is missing for more than 1 ms and CCS = 0 is set in

the CM register, the supervisory circuit generates a hardware reset.

Figure 23. External Input Clock

Ext. input clock

RcOut1

ExOut

OSC1

OSC2

Ext.

Clock

ExIn

Osc-Stop

Stop

CCS

Res

or

Clock monitor

Ext.

Clock

Table 6. Supervisor Function Control Bits

OS1

OS0

CCS

Supervisor Reset Output (Res)

1

x

1

0

1

x

Enable

Disable

RC-oscillator 2 with External

Trimming Resistor

The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator

frequency can be trimmed with an external resistor between OSC1 and V_DD. In this

configuration, the RC-oscillator 2 frequency can be maintained stable with a tolerance of

±10% over the full operating temperature and a voltage range V_DDfrom 2.5 V to 6.0 V.

For example: An output frequency at the RC-oscillator 2 of 2 MHz can be obtained by

connecting a resistor R_ext= 360 kΩ (see Figure 24 on page 27).

26

ATAR862-4 [Preliminary]

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ATAR862-4 [Preliminary]

Figure 24. RC-oscillator 2

V

DD

RC

R

oscillator 2

ext

RcOut2

OSC1

R

Trim

Osc-Stop

Stop

OSC2

4-MHz Oscillator

The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator

connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary oscilla-

tor circuitry is integrated, except the actual crystal, resonator, C3 and C4.

Figure 25. 4-MHz Crystal Oscillator

OSC1

Oscin

4Out

*

XTAL

4 MHz

4-MHz

oscillator

Stop

C1

Osc-Stop

Oscout

OSC2

*

C2

mask option

Figure 26. Ceramic Resonator

C3

OSC1

Oscin

4Out

4-MHz

oscillator

Stop

*

Cer.

Res

C1

Osc-Stop

Oscout

OSC2

C4

*

C2

mask option

32-kHz Oscillator

Some applications require long-term time keeping or low resolution timing. In this case,

an on-chip, low power 32-kHz crystal oscillator can be used to generate both the

SUBCL and the SYSCL. In this mode, power consumption is greatly reduced. The

32-kHz crystal oscillator can not be stopped while the power-down mode is in operation.

27

4552C–4BMCU–01/04

Figure 27. 32-kHz Crystal Oscillator

OSC1

Oscin

32Out

32-kHz

oscillator

*

XTAL

32 kHz

C1

Oscout

OSC2

*

C2

mask option

Clock Management

The clock management register controls the system clock divider and synchronization

stage. Writing to this register triggers the synchronization cycle.

Clock Management Register

(CM)

Auxiliary register address: "3"hex

Bit 3

Bit 2

Bit 1

Bit 0

CM:

NSTOP

CCS

CSS1

CSS0

Reset value: 1111b

NSTOP

Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode

NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode

CCS

Core Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL

CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external

clock source or the internal RC-oscillator 2 with the external resistor at OSC1

generates SYSCL dependent on the setting of OS0 and OS1 in the system

configuration register

CSS1

CSS0

Core Speed Select 1

Core Speed Select 0

Table 7. Core Speed Select

CSS1

CSS0

Divider

Note

0

1

0

1

0

1

16

8

–

Reset value

4

–

2

28

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

System Configuration

Register (SC)

Primary register address: "3"hex

Bit 3

Bit 2

Bit 1

Bit 0

SC: write

BOT

–

OS1

OS0

Reset value: 1x11b

Brown-Out Threshold

BOT = 1, low brown-out voltage threshold (1.7 V)

BOT = 0, high brown-out voltage threshold (2.0 V)

OS1

OS0

Oscillator Select 1

Oscillator Select 0

Table 8. Oscillator Select

Mode

OS1

OS0

Input for SUBCL

C_in/16

Selected Oscillators

1

2

1

0

1

RC-oscillator 1 and external input clock

RC-oscillator 1 and RC-oscillator 2

C_in/16

RC-oscillator 1 and 4-MHz crystal

oscillator

3

1

0

C_in/16

RC-oscillator 1 and 32-kHz crystal

oscillator

4

32 kHz

Note:

If bit CCS = 0 in the CM register, the RC-oscillator 1 always stops.

Power-down Modes

The sleep mode is a shut-down condition which is used to reduce the average system

power consumption in applications where the microcontroller is not fully utilized. In this

mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruc-

tion. This instruction sets the interrupt enable bit (I) in the condition code register to

enable all interrupts and stops the core. During the sleep mode the peripheral modules

remain active and are able to generate interrupts. The microcontroller exits the sleep

mode by carrying out any interrupt or a reset.

The sleep mode can only be kept when none of the interrupt pending or active register

bits are set. The application of the $AUTOSLEEP routine ensures the correct function of

the sleep mode. For standard applications use the $AUTOSLEEP routine to enter the

power-down mode. Using the SLEEP instruction instead of the $AUTOSLEEP following

an I/O instruction requires to insert 3 non-I/O instruction cycles (for example NOP NOP

NOP) between the IN or OUT command and the SLEEP command.

The total power consumption is directly proportional to the active time of the microcon-

troller. For a rough estimation of the expected average system current consumption, the

following formula should be used:

I_total(V_DD, f_syscl) = I_Sleep+ (I_DD× t_active/t_total

)

I_DDdepends on V_DDand f_syscl

29

4552C–4BMCU–01/04

The microcontroller block has various power-down modes. During the sleep mode the

clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management

register (CM), it is programmable if the clock for the on-chip peripherals is active or

stopped during the sleep mode. If the clock for the core and the peripherals is stopped,

the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it is

selected it runs continuously independent of the NSTOP-bit. If the oscillator is stopped

or the 32-kHz oscillator is selected, power consumption is extremely low.

Table 9. Power-down Modes

RC-oscillator 1

Brown-

out

Function

RC-oscillator 2

4-MHz

External

Input

Clock

CPU

Core

Osc-

32-kHz

Oscillator

Mode

Stop⁽¹⁾

Oscillator

Active

RUN

NO

Active

STOP

RUN

YES

Power-

down

SLEEP

NO

RUN

YES

SLEEP

YES

STOP

Note:

1. Osc-Stop = SLEEP and NSTOP and WDL

Peripheral Modules

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O bus (see Figure 28 on page

31). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual

register addressing scheme has been adopted to enable direct addressing of the pri-

mary register. To address the auxiliary register, the access must be switched with an

auxiliary switching module. Thus, a single IN (or OUT) to the module address will read

(or write into) the module primary register. Accessing the auxiliary register is performed

with the same instruction preceded by writing the module address into the auxiliary

switching module. Byte wide registers are accessed by multiple IN- (or OUT-) instruc-

tions. For more complex peripheral modules, with a larger number of registers,

extended addressing is used. In this case, a bank of up to 16 subport registers are indi-

rectly addressed with the subport address. The first OUT instruction writes the subport

address to the subaddress register, the second IN or OUT instruction reads data from or

writes data to the addressed subport.

30

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 28. Example of I/O Addressing

Module M1

Module ASW

Module M2

Module M3

(Address Pointer)

Subaddress Reg.

Bank of

Primary Reg.

Aux. Reg.

Auxiliary Switch

Module

Subport Fh

Subport Eh

5

1

Subport 1

Subport 0

2

Primary Reg.

6

Primary Reg.

3

4

I/O bus

to other modules

Indirect Subport Access

Dual Register Access

Single Register Access

(Subport Register Write)

(Primary Register Write)

Prim._Data Addr. (M2)

(Primary Register Write)

3

OUT

6

Prim._Data Addr.(M3) OUT

1

2

Addr. (SPort) Addr. (M1) OUT

SPort _Data Addr. (M1) OUT

(Auxiliary Register Write)

(Primary Register Read)

Addr. (M3) IN

4

5

Addr. (M2) Addr. (ASW) OUT

Aux._Data Addr. (M2) OUT

(Subport Register Read)

Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN

1

2

(Primary Register Read)

Addr. (M2) IN

Example of

qFORTH

3

(Subport Register Write Byte)

program code

(Auxiliary Register Read)

1

2

Addr. (SPort) Addr. (M1) OUT

SPort _Data(lo) Addr. (M1) OUT

SPort _Data(hi) Addr. (M1) OUT

4

5

Addr. (M2) Addr. (ASW) OUT

Addr. (M2) IN

(Auxiliary Register Write Byte)

(Subport Register Read Byte)

Addr. (SPort) Addr. (M1) OUT

Addr. (M1) IN (hi)

1

2

4

5

Addr. (M2) Addr. (ASW) OUT

Aux._Data (lo) Addr. (M2) OUT

Aux._Data (hi) Addr. (M2) OUT

Addr. (M1) IN (lo)

Addr.(ASW) = Auxiliary Switch Module address

Addr.(Mx) = Module Mx address

Addr.(SPort) = Subport address

Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble)

SPort_Data(lo) = Data to be written into SubPort (low nibble)

SPort_Data(hi) = Data to be written into SubPort (high nibble)

Prim._Data

Aux._Data

= Data to be written into Primary Register

= Data to be written into Auxiliary Register

(lo) = SPort_Data (low nibble)

Prim._Data(lo)= Data to be written into Auxiliary Register (low nibble) (hi) = SPort_Data (high nibble)

31

4552C–4BMCU–01/04

Table 10. Peripheral Addresses

Write/

Read

Port Address

Name

P1DAT

P2DAT

P2CR

SC

Reset Value

1xx1b

Register Function

Module Type

1

W/R

W

Port 1 - data register/input data

Port 2 - data register/pin data

Port 2 - control register

M3

M2

M3

M2

M1

2

1111b

Auxiliary

3

1111b

W

1x11b

System configuration register

Watchdog reset

CWD

R

xxxxb

Auxiliary

CM

W

1111b

Clock management register

Port 4 - data register/pin data

Port 4 - control register (byte)

Port 5 - data register/pin data

Port 5 - control register (byte)

Port 6 - data register/pin data

Port 6 - control register (byte)

Data to Timer 1/2 subport

4

P4DAT

P4CR

P5DAT

P5CR

P6DAT

P6CR

T12SUB

W/R

W

1111b

Auxiliary

1111 1111b

1111b

5

W/R

W

Auxiliary

1111 1111b

1xx1b

6

W/R

W

Auxiliary

7

1111b

W

–

Subport address

0

1

T2C

W

–

0000b

1111b

0000b

1111b

1111 1111b

–

Timer 2 control register

Timer 2 mode register 1

Timer 2 mode register 2

Timer 2 compare mode register

Timer 2 compare register 1

Timer 2 compare register 2 (byte)

Reserved

M1

–

T2M1

T2M2

T2CM

T2CO1

T2CO2

–

2

3

4

5

6

7

–

Reserved

–

8

T1C1

T1C2

WDC

–

W

–

1111b

x111b

1111b

–

Timer 1 control register 1

Timer 1 control register 2

Watchdog control register

Reserved

M1

–

9

A

B-F

8

9

ASW

STB

W

R

1111b

xxxx xxxxb

1111b

1x11b

1111b

–

Auxiliary/switch register

Serial transmit buffer (byte)

Serial receive buffer (byte)

Serial interface control register 1

Serial interface status/control register

Serial interface control register 2

Data to/from Timer 3 subport

ASW

M2

M1

SRB

SIC1

SISC

SIC2

T3SUB

Auxiliary

W

W/R

W

W/R

A

B

Subport address

0

T3M

W

R

1111b

0000b

1111 1111b

xxxx xxxxb

1111 1111b

–

Timer 3 mode register

M1

–

1

T3CS

Timer 3 clock select register

Timer 3 compare mode register 1

Timer 3 compare mode register 2

Timer 3 compare register 1 (byte)

Timer 3 capture register (byte)

Timer 3 compare register 2 (byte)

Reserved

2

3

T3CM1

T3CM2

4

T3CO1

4

T3CP

5

T3CO2

W

–

6-F

T3C

T3ST

–

C

W

R

0000b

x000b

–

Timer 3 control register

Timer 3 status register

M3

–

D

E

F

–

Reserved

–

Reserved

–

VMC

VMST

W

R

1111b

xx11b

Voltage monitor control register

Voltage monitor status register

M3

32

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Bi-directional Ports

With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1

and Port 6 have a data width of 2 bits (bit 0 and bit 3). All ports may be used for data

input or output. All ports are equipped with Schmitt trigger inputs and a variety of mask

options for open-drain, open-source, full-complementary outputs, pull-up and pull-down

transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address

register of the respective port address and the Port Control Register (PxCR), to the

corresponding auxiliary register.

There are five different directional ports available:

Port 1

Port 2

Port 5

2-bit wide bi-directional port with automatic full bus width direction switching.

4-bit wide bitwise-programmable I/O port.

4-bit wide bitwise-programmable bi-directional port with optional strong

pull-ups and programmable interrupt logic.

Port 4

Port 6

4-bit wide bitwise-programmable bi-directional port also provides the I/O

interface to Timer 2, SSI, voltage monitor input and external interrupt input.

2-bit wide bitwise-programmable bi-directional port also provides the I/O

interface to Timer 3 and external interrupt input.

Bi-directional Port 1

In Port 1 the data direction register is not independently software programmable, the

direction of the complete port being switched automatically when an I/O instruction

occurs (see Figure 29 on page 34). The port is switched to output mode via an OUT

instruction and to input via an IN instruction. The data written to a port will be stored into

the output data latches and appears immediately at the port pin following the OUT

instruction. After RESET all output latches are set to "1" and the port is switched to input

mode. An IN instruction reads the condition of the associated pins.

Note:

Care must be taken when switching the bi-directional port from output to input. The

capacitive pin loading at this port in conjunction with the high resistance pull-ups may

cause the CPU to read the contents of the output data register rather than the external

input state. To avoid this, one of the following programming techniques should be used:

Use two IN-instructions and DROP the first data nibble. The first IN switches the port

from output to input and the DROP removes the first invalid nibble. The second IN reads

the valid pin state.

Use an OUT instruction followed by an IN instruction. Via the OUT instruction, the capac-

itive load is charged or discharged depending on the optional pull-up/pull-down

configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pull-down

resistors.

33

4552C–4BMCU–01/04

Figure 29. Bi-directional Port 1

V

DD

*

I/O Bus

Static

pull-up

(Data out)

Switched

pull-up

*

Q

D

BP1y

P1DATy

R

V

DD

Reset

(Direction)

*

OUT

S

R

Q

Static

pull-down

*) Mask options

Switched

pull-down

IN

NQ

Master reset

Bi-directional Port 2

As all other bi-directional ports, this port includes a bitwise programmable Control

Register (P2CR), which enables the individual programming of each port bit as input or

output. It also opens up the possibility of reading the pin condition when in output mode.

This is a useful feature for self testing and for serial bus applications.

Port 2, however, has an increased drive capability and an additional low resistance pull-

up/-down transistor mask option.

Care should be taken connecting external components to BP20/NTE. During any reset

phase, the BP20/NTE input is driven towards V_DDby an additional internal strong pull-up

transistor. This pin must not be pulled down (active or passive) to V_SSduring reset by

any external circuitry representing a resistor of less than 150 kΩ. This prevents the

circuit from unintended switching to test mode enable through the application circuitry at

pin BP20/NTE. Resistors less than 150 kΩ might lead to an undefined state of the

internal test logic thus disabling the application firmware.

To avoid any conflict with the optional internal pull-down transistors, BP20 handles the

pull-down options in a different way than all other ports. BP20 is the only port that

switches off the pull-down transistors during reset.

Figure 30. Bi-directional Port 2

V

DD

I/O Bus

Switched

pull-up

Static

Pull-up

*

(Data out)

*

D

Q

P2DATy

S

BP2y

V

DD

Master reset

I/O Bus

Static

Pull-down

*

S

*

Q

D

P2CRy

Switched

pull-down

* Mask options

(Direction)

34

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Port 2 Data Register (P2DAT)

Primary register address: "2"hex

Bit 3 *

Bit 2

Bit 1

Bit 0

P2DAT3

P2DAT2

P2DAT1

P2DAT0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

Port 2 Control Register (P2CR)

Auxiliary register address: "2"hex

Bit 3

Bit 2

Bit 1

Bit 0

P2CR3

P2CR2

P2CR1

P2CR0

Reset value: 1111b

Value: 1111b means all pins in input mode

Table 11. Port 2 Control Register

Code

3 2 1 0

x x x 1

x x x 0

x x 1 x

x x 0 x

x 1 x x

x 0 x x

1 x x x

0 x x x

Function

BP20 in input mode

BP20 in output mode

BP21 in input mode

BP21 in output mode

BP22 in input mode

BP22 in output mode

BP23 in input mode

BP23 in output mode

Bi-directional Port 5

As all other bi-directional ports, this port includes a bitwise programmable Control

Register (P5CR), which allows the individual programming of each port bit as input or

output. It also opens up the possibility of reading the pin condition when in output mode.

This is a useful feature for self testing and for serial bus applications.

The port pins can also be used as external interrupt inputs (see Figure 31 on page 36

and Figure 32 on page 36). The interrupts (INT1 and INT6) can be masked or indepen-

dently configured to trigger on either edge. The interrupt configuration and port direction

is controlled by the Port 5 Control Register (P5CR). An additional low resistance pull-

up/-down transistor mask option provides an internal bus pull-up for serial bus

applications.

The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of

address "5"h and the Port 5 Control Register (P5CR) to the corresponding auxiliary reg-

ister. The P5CR is a byte-wide register and is configured by writing first the low nibble

and then the high nibble (see section “Addressing Peripherals” on page 30).

35

4552C–4BMCU–01/04

Figure 31. Bi-directional Port 5

Switched

pull-up

I/O Bus

V

DD

Static

*

pull-up

V

DD

(Data out)

I/O Bus

*

D

Q

P5DATy

BP5y

V

S

DD

Master reset

IN enable

Static

Pull-down

*

Switched

pull-down

* Mask options

Figure 32. Port 5 External Interrupts

INT1

INT6

Data in

Bidir. Port

Data in

BP52

BP51

Bidir. Port

IN_Enable

I/O-bus

Data in

Bidir. Port

IN_Enable

Data in

BP53

BP50

Bidir. Port

IN_Enable

Decoder

P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1

Port 5 Data Register (P5DAT)

Primary register address: "5"hex

Bit 3

P5DAT3

Bit 2

Bit 1

Bit 0

P5DAT2

P5DAT1

P5DAT0

Reset value: 1111b

Port 5 Control Register (P5CR)

Byte Write

Auxiliary register address: "5"hex

Bit 3

Bit 2

Bit 1

Bit 0

P50M1

Bit 4

First write cycle

P51M2

Bit 7

P51M1

Bit 6

P50M2

Bit 5

Reset value: 1111b

Second write cycle

P53M2

P53M1

P52M2

P52M1

P5xM2, P5xM1 – Port 5x interrupt mode/direction code

36

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Table 12. Port 5 Control Register

Auxiliary Address: "5"hex

Code

First Write Cycle

Second Write Cycle

Code

3 2 1 0

x x 1 1

x x 0 1

x x 1 0

x x 0 0

1 1 x x

0 1 x x

1 0 x x

0 0 x x

Function

3 2 1 0

Function

BP50 in input mode – interrupt disabled

BP50 in input mode – rising edge interrupt

BP50 in input mode – falling edge interrupt

BP50 in output mode – interrupt disabled

BP51 in input mode – interrupt disabled

BP51 in input mode – rising edge interrupt

BP51 in input mode – falling edge interrupt

BP51 in output mode – interrupt disabled

x x 1 1

x x 0 1

x x 1 0

x x 0 0

1 1 x x

0 1 x x

1 0 x x

0 0 x x

BP52 in input mode – interrupt disabled

BP52 in input mode – rising edge interrupt

BP52 in input mode – falling edge interrupt

BP52 in output mode – interrupt disabled

BP53 in input mode – interrupt disabled

BP53 in input mode – rising edge interrupt

BP53 in input mode – falling edge interrupt

BP53 in output mode – interrupt disabled

Bi-directional Port 4

The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins

for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in

exactly the same way as bi-directional Port 2 (see Figure 33). Two additional multi-

plexes allow data and port direction control to be passed over to other internal modules

(Timer 2, VM or SSI). The I/O-pins for SC and SD line have an additional mode to gen-

erate an SSI-interrupt.

All four Port 4 pins can be individually switched by the P4CR-register. Figure 33 shows

the internal interfaces to bi-directional Port 4.

Figure 33. Bi-directional Port 4 and Port 6

V

I/O Bus

Intx

DD

*

Static

pull-up

*

PxMRy

V

DD

POut

Switched

pull-up

*

I/O Bus

D

Q

BPxy

PxDATy

S

V

DD

Master reset

I/O Bus

(Direction)

Static

pull-down

*

S

D

Q

PxCRy

Switched

pull-down

PDir

* Mask options

37

4552C–4BMCU–01/04

Port 4 Data Register (P4DAT)

Primary register address: "4"hex

Bit 3

Bit 2

Bit 1

Bit 0

P4DAT3

P4DAT2

P4DAT1

P4DAT0

Reset value: 1111b

Port 4 Control Register (P4CR)

Byte Write

Auxiliary register address: "4"hex

Bit 3

Bit 2

P41M1

Bit 6

Bit 1

P40M2

Bit 0

P40M1

Bit 4

First write cycle

P41M2

Bit 7

Reset value: 1111b

Bit 5

Second write cycle

P43M2

P43M1

P42M2

P42M1

P4xM2, P4xM1 – Port 4x interrupt mode/direction code

Table 13. Port 4 Control Register

Auxiliary Address: "4"hex

First Write Cycle

Second Write Cycle

Code

3 2 1 0

Function

3 2 1 0

Function

x x 1 1

x x 1 0

BP40 in input mode

BP40 in output mode

x x 1 1

x x 1 0

BP42 in input mode

BP42 in output mode

BP40 enable alternate function

(SC for SSI)

BP42 enable alternate function

(T2O for Timer 2)

x x 0 1

x x 0 x

BP40 enable alternate function

(falling edge interrupt input for

INT3)

x x 0 0

1 1 x x

BP43 in input mode

BP43 in output mode

1 1 x x

1 0 x x

BP41 in input mode

1 0 x x

0 1 x x

BP43 enable alternate function

(SD for SSI)

BP41 in output mode

BP43 enable alternate function

(falling edge interrupt input for

INT3)

BP41 enable alternate function

(VMI for voltage monitor input)

0 1 x x

0 0 x x

BP41 enable alternate function

(T2I external clock input for

Timer 2)

–

Bi-directional Port 6

The bi-directional Port 6 is a bitwise configurable I/O port and provides the external pins

for the Timer 3. As a normal port, it performs in exactly the same way as bi-directional

Port 6 (see Figure 33 on page 37). Two additional multiplexes allow data and port direc-

tion control to be passed over to other internal module (Timer 3). The I/O pin for T3I line

has an additional mode to generate a Timer 3 interrupt.

All two Port 6 pins can be individually switched by the P6CR register. Figure 33 on

page 37 shows the internal interfaces to bi-directional Port 6.

38

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Port 6 Data Register (P6DAT)

Primary register address: "6"hex

Bit 3

Bit 2

Bit 1

Bit 0

P6DAT3

–

P6DAT0

Reset value: 1xx1b

Port 6 Control Register (P6CR)

Auxiliary register address: "6"hex

Bit 3

Bit 2

Bit 1

Bit 0

P63M2

P63M1

P60M2

P60M0

Reset value: 1111b

P6xM2, P6xM1 – Port 6x interrupt mode/direction code

Table 14. Port 6 Control Register

Auxiliary Address: "6"hex

Write Cycle

Code

3 2 1 0

Function

3 2 1 0

1 1 x x

1 0 x x

Function

x x 1 1 BP60 in input mode

x x 1 0 BP60 in output mode

BP63 in input mode

BP63 in output mode

BP60 enable alternate port

x x 0 x

BP63 enable alternate port

function (T3I for Timer 3)

0 x x x

function (T3O for Timer 3)

Universal Timer/Counter/ The Universal Timer/counter/Communication Module (UTCM) consists of three timers

(Timer 1,Timer 2, Timer 3) and a Synchronous Serial Interface (SSI).

Communication Module

•

Timer 1 is an interval timer that can be used to generate periodical interrupts and as

prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

(UTCM)

•

Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).

Timer 3 is an 8-bit timer/counter with its own input (T3I) and output (T3O).

The SSI operates as two wire serial interface or as shift register for modulation and

demodulation. The modulator and demodulator units work together with the timers

and shift the data bits into or out of the shift register.

There is a multitude of modes in which the timers and the serial interface can work

together.

39

4552C–4BMCU–01/04

Figure 34. UTCM Block Diagram

SYSCL

from clock module

SUBCL

Timer 1

NRST

INT2

Watchdog

MUX

Interval / Prescaler

Timer 3

T1OUT

Control

Capture 3

8-bit Counter 3

Compare 3/1

Compare 3/2

Demodu-

lator 3

T3I

Modu-

lator 3

T3O

T2O

INT5

Timer 2

TOG3

4-bit Counter 2/1

Modu-

lator 2

Compare 2/1

Control

I/O bus

POUT

T2I

8-bit Counter 2/2

MUX DCG

INT4

Compare 2/2

SSI

TOG2

SCL

Receive buffer

8-bit shift register

Transmit buffer

SC

SD

MUX

Control

INT3

Timer 1

The Timer 1 is an interval timer which can be used to generate periodical interrupts and

as prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL

or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as

source for the Timer 1 interrupt. Because of other system requirements, the Timer 1 out-

put T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP

(CPU core -> sleep and OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0).

Nevertheless, the Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The

interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit

of the T1C2 register. The time interval for the timer output can be programmed via the

Timer 1 control register T1C1.

40

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

This timer starts running automatically after any power-on reset! If the watchdog

function is not activated, the timer can be restarted by writing into the T1C1 register with

T1RM = 1.

Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The

watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It

generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit

counter must be reset before it overflows. The application software has to accomplish

this by reading the CWD register.

After power-on reset the watchdog must be activated by software in the $RESET initial-

ization routine. There are two watchdog modes, in one mode the watchdog can be

switched on and off by software, in the other mode the watchdog is active and locked.

This mode can only be stopped by carrying out a system reset.

The watchdog timer operation mode and the time interval for the watchdog reset can be

programmed via the watchdog control register (WDC).

Figure 35. Timer 1 Module

SYSCL

SUBCL

WDCL

NRST

CL1

Prescaler

14 bit

Watchdog

4 bit

MUX

INT2

T1CS

T1BP

T1IM

T1OUT

T1MUX

Figure 36. Timer 1 and Watchdog

T1C1 T1RM T1C2 T1C1 T1C0

T1C2 T1BP T1IM

3

Write of the

T1C1 register

Decoder

T1IM=0

T1MUX

INT2

MUX for interval timer

T1IM=1

T1OUT

Q1 Q2 Q3 Q4 Q5

Q8

Q11

Q14

SUBCL

RES

CL1

CL

Q6

Q14

Watchdog

Divider / 8

Decoder

2

MUX for watchdog timer

RESET

(NRST)

Divider

RESET

WDCL

RES

WDL WDR WDT1 WDT0

WDC

Read of the

CWD register

Watchdog

mode control

41

4552C–4BMCU–01/04

Timer 1 Control Register 1

(T1C1)

Address: "7"hex - Subaddress: "8"hex

Bit 3 *

Bit 2

Bit 1

Bit 0

T1RM

T1C2

T1C1

T1C0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

T1RM

Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note: If WDL = 0, Timer 1 restart is impossible

T1C2

T1C1

T1C0

Timer 1 Control bit 2

Timer 1 Control bit 1

Timer 1 Control bit 0

The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval

depends on this divider and the Timer 1 input clock source. The timer input can be

supplied by the system clock, the 32-kHz oscillator or via the clock management. If the

clock management generates the SUBCL, the selected input clock from the RC oscilla-

tor, 4-MHz oscillator or an external clock is divided by 16.

Table 15. Timer 1 Control Bits

Time Interval with

SUBCL

Time Interval with

SUBCL = 32 kHz

Time Interval with

SYSCL = 2/1 MHz

T1C2

T1C1

T1C0

Divider

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SUBCL/2

SUBCL/4

61 µs

122 µs

1 µs/2 µs

2 µs/4 µs

4

8

SUBCL/8

244 µs

4 µs/8 µs

16

SUBCL/16

SUBCL/32

SUBCL/256

SUBCL/2048

SUBCL/16384

488 µs

8 µs/16 µs

32

0.977 ms

7.812 ms

62.5 ms

500 ms

16 µs/32 µs

256

2048

16384

128 µs/256 µs

1024 µs/2048 µs

8192 µs/16384 µs

42

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 1 Control Register 2

(T1C2)

Address: "7"hex - Subaddress: "9"hex

Bit 3 *

Bit 2

Bit 1

Bit 0

–

T1BP

T1CS

T1IM

Reset value: x111b

* Bit 3 -> MSB, Bit 0 -> LSB

T1BP

T1CS

T1IM

Timer 1 SUBCL ByPassed

T1BP = 1, TIOUT = T1MUX

T1BP = 0, T1OUT = SUBCL

Timer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see Figure 35 on page 41)

T1CS = 0, CL1 = SYSCL (see Figure 35 on page 41)

Timer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interrupt

T1IM = 0, enables Timer 1 interrupt

Watchdog Control Register

(WDC)

Address: "7"hex - Subaddress: "A"hex

Bit 3 *

WDL

Bit 2

Bit 1

Bit 0

WDR

WDT1

WDT0

Reset value: 1111b

* Bit 3 -> MSB, Bit 0 -> LSB

WDL

WDR

WatchDog Lock mode

WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit

WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no

effect. After the WDL-bit is cleared, the watchdog is active until a

system reset or power-on reset occurs.

WatchDog Run and stop mode

WDR = 1, the watchdog is stopped/disabled

WDR = 0, the watchdog is active/enabled

WDT1

WDT0

WatchDog Time 1

WatchDog Time 0

Both these bits control the time interval for the watchdog reset.

Table 16. Watchdog Time Control Bits

Delay Time to Reset with

SUBCL = 32 kHz

Delay Time to Reset with

WDT1

WDT0

Divider

512

SYSCL = 2/1 MHz

0.256 ms/0.512 ms

1.024 ms/2.048 ms

8.2 ms/16.4 ms

0

1

0

1

0

1

15.625 ms

62.5 ms

0.5 s

2048

16384

131072

4 s

65.5 ms/131 ms

43

4552C–4BMCU–01/04

Timer 2

8-/12-bit Timer for:

•

Interrupt, square-wave, pulse and duty cycle generation

Baud-rate generation for the internal shift register

Manchester and Biphase modulation together with the SSI

Carrier frequency generation and modulation together with the SSI

Timer 2 can be used as an interval timer for interrupt generation, as signal generator or

as baud-rate generator and modulator for the serial interface. It consists of a 4-bit and

an 8-bit up counter stage which both have compare registers. The 4-bit counter stages

of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with 4-bit prescaler. The

timer can also be configured as an 8-bit timer and a separate 4-bit prescaler.

The Timer 2 input can be supplied via the system clock, the external input clock (T2I),

the Timer 1 output clock, the Timer 3 output clock or the shift clock of the serial inter-

face. The external input clock T2I is not synchronized with SYSCL. Therefore, it is

possible to use Timer 2 with a higher clock speed than SYSCL. Furthermore, with that

input clock the Timer 2 operates in the power-down mode SLEEP (CPU core -> sleep

and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep and OSC-

Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit counter

stages of Timer 2 have an additional clock output (POUT).

Its output has a modulator stage that allows the generation of pulses as well as the gen-

eration and modulation of carrier frequencies. The Timer 2 output can modulate with the

shift register data output to generate Biphase- or Manchester code.

If the serial interface is used to modulate a bitstream, the 4-bit stage of Timer 2 has a

special task. The shift register can only handle bitstream lengths divisible by 8. For other

lengths, the 4-bit counter stage can be used to stop the modulator after the right bitcount

is shifted out.

If the timer is used for carrier frequency modulation, the 4-bit stage works together with

an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier

frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator

output for a programmable count of pulses.

For programming the time interval, the timer has a 4-bit and an 8-bit compare register.

For programming the timer function, it has four mode and control registers. The compar-

ator output of stage 2 is controlled by a special compare mode register (T2CM). This

register contains mask bits for the actions (counter reset, output toggle, timer interrupt)

which can be triggered by a compare match event or the counter overflow. This archi-

tecture enables the timer function for various modes.

The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register

(T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or

8-bit compare register and 4-bit compare register.

For 12-bit compare data value:

For 8-bit compare data value:

For 4-bit compare data value:

m = x +1

n = y +1

l = z +1

0 ≤x ≤4095

0 ≤y ≤255

0 ≤z ≤15

44

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 37. Timer 2

I/O-bus

P4CR

T2M1

T2M2

T2I

DCGO

8-bit Counter 2/2

RES OVF2

SYSCL

T2O

CL2/1

CL2/2

T1OUT

TOG3

SCL

4-bit Counter 2/1

RES OVF1

DCG

OUTPUT

POUT

TOG2

INT4

M2

to

T2C

Compare 2/1

CM1

Control

Compare 2/2

Modulator 3

MOUT

Biphase-,

Manchester-

modulator

Timer 2

modulator

output-stage

T2CO1

T2CM

T2CO2

SSI POUT

SO

Control

I/O-bus

SSI

Timer 2 Modes

Mode 1: 12-bit Compare

Counter

The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A com-

pare match signal of the 4-bit and the 8-bit stage generates the signal for the counter

reset, toggle flip-flop or interrupt. The compare action is programmable via the compare

mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output

(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.

Figure 38. 12-bit Compare Counter

POUT (CL2/1 /16)

CL2/1

OVF2

CM2

4-bit counter

4-bit compare

4-bit register

DCG

8-bit counter

8-bit compare

8-bit register

TOG2

INT4

RES

CM1

Timer 2

output mode

and T2OTM-bit

T2D1, 0

T2RM

T2OTM

T2IM

T2CTM

Mode 2: 8-bit Compare

Counter with 4-bit

Programmable Prescaler

Figure 39. 8-bit Compare Counter

DCGO

POUT

CL2/1

OVF2

CM2

4-bit counter

4-bit compare

4-bit register

DCG

8-bit counter

8-bit compare

8-bit register

TOG2

INT4

RES

CM1

Timer 2

output mode

and T2OTM-bit

T2D1, 0

T2RM

T2OTM

T2IM

T2CTM

The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this

mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit

prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output

(CM1) supplies the clock output (POUT) with clocks.

45

4552C–4BMCU–01/04

Mode 3/4: 8-bit Compare

Counter and 4-bit

Figure 40. 4-/8-bit Compare Counter

DCGO

Programmable Prescaler

T2I

CL2/2

OVF2

RES

CM2

DCG

8-bit counter

8-bit compare

8-bit register

TOG2

INT4

SYSCL

Timer 2

output mode

and T2OTM-bit

P4CR P41M2, 1

T2D1, 0

T2RM

T2OTM

T2IM

T2CTM

TOG3

T1OUT

SYSCL

SCL

CL2/1

4-bit counter

4-bit compare

4-bit register

MUX

RES

CM1

POUT

T2CS1, 0

In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit

prescaler and an 8-bit timer with an 2-bit prescaler or as a duty cycle generator. Only in

the mode 3 and mode 4, can the 8-bit counter be supplied via the external clock input

(T2I) which is selected via the P4CR register. The 4-bit prescaler is started via activating

of mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for

the 8-bit timer stage. The 4-bit stage can be used as prescaler for Timer 3, the SSI or to

generate the stop signal for modulator 2 and modulator 3.

Timer 2 Output Modes

The signal at the timer output is generated via modulator 2. In the toggle mode, the com-

pare match event toggles the output T2O. For high resolution duty cycle modulation 8

bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes

the DCG output is connected to T2O and switched on and off either by the toggle

flip-flop output or the serial data line of the SSI. Modulator 2 also has two modes to out-

put the content of the serial interface as Biphase or Manchester code.

The modulator output stage can be configured by the output control bits in the T2M2

register. The modulator is started with the start of the shift register (SIR = 0) and

stopped either by carrying out a shift register stop (SIR = 1) or compare match event of

stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler

has to be supplied with the internal shift clock (SCL).

Figure 41. Timer 2 Modulator Output Stage

DCGO

SO

TOG2

T2O

RE

Biphase/

Manchester

modulator

S3

M2

Toggle

S2

S1

FE

SSI

CONTROL

RES/SET

Modulator3

OMSK

M2

T2M2 T2OS2, 1, 0 T2TOP

46

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 2 Output Signals

Timer 2 Output Mode 1

Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 42. Interrupt Timer/Square Wave Generator – the Output Toggles with Each

Edge Compare Match Event

Input

Counter 2

T2R

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

0

1

Counter 2

CMx

INT4

T2O

Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 43. Pulse Generator – the Timer Output Toggles with the Timer Start if the

T2TS bit Is Set

Input

Counter 2

T2R

4095/

255

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

Counter 2

CMx

INT4

T2O

Toggle

by start

T2O

47

4552C–4BMCU–01/04

Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O

Figure 44. Pulse Generator – the Timer Toggles with Timer Overflow and Compare

Match

Input

Counter 2

T2R

4095/

255

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

Counter 2

CMx

OVF2

INT4

T2O

Timer 2 Output Mode 2

Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output,

and gated by the output flip-flop (M2)

Figure 45. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output

DCGO

1

2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5

Counter 2

TOG2

M2

T2O

Counter = compare register (=2)

Timer 2 Output Mode 3

Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output,

and gated by the SSI internal data output (SO)

Figure 46. Carrier Frequency Burst Modulation with the SSI Data Output

DCGO

1

2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1

Counter 2

TOG2

SO

Counter = compare register (=2)

Bit 0 Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9 Bit 10 Bit 11 Bit 12 Bit 13

T2O

48

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 2 Output Mode 4

Biphase Modulator: Timer 2 Modulates the SSI Internal Data Output (SO) to Biphase

Code

Figure 47. Biphase Modulation

TOG2

SC

8-bit SR-Data

0

1

0

1

0

1

SO

Bit 7

Bit 0

1

0

1

0

1

T2O

Data: 00110101

Timer 2 Output Mode 5

Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to

Manchester code

Figure 48. Manchester Modulation

TOG2

SC

8-bit SR-Data

0

1

0

1

0

1

SO

Bit 7

Bit 0

0

1

0

1

0

1

T2O

Bit 7

Bit 0

Data: 00110101

Timer 2 Output Mode 7

In this mode the timer overflow defines the period and the compare register defines the

duty cycle. During one period only the first compare match occurrence is used to toggle

the timer output flip-flop, until the overflow all further compare match are ignored. This

avoids the situation that changing the compare register causes the occurrence of sev-

eral compare match during one period. The resolution at the pulse-width modulation

Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.

PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)

Figure 49. PWM Modulation

Input clock

Counter 2/2

T2R

0

50

255

0

100

255

0

150 255

0

50

255

0

100

Counter 2/2

CM2

OVF2

INT4

load the next

T2CO2=150

load

T

compare value

T2O

T1

T2

T3

T1

T2

T

49

4552C–4BMCU–01/04

Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input

clock and its output function. All registers are indirectly addressed using extended

addressing as described in section “Addressing Peripherals” on page 30. The alternate

functions of the Ports BP41 or BP42 must be selected with the Port 4 control register

P4CR, if one of the Timer 2 modes require an input at T2I/BP41 or an output at

T2O/BP42.

Timer 2 Control Register (T2C)

Address: "7"hex - Subaddress: "0"hex

Bit 3

Bit 2

Bit 1

Bit 0

T2CS1

T2CS0

T2TS

T2R

Reset value: 0000b

T2CS1

T2CS0

Timer 2 Clock Select bit 1

Timer 2 Clock Select bit 0

Table 17. Timer 2 Clock Select Bits

T2CS1

T2CS0

Input Clock (CL 2/1) of Counter Stage 2/1

System clock (SYSCL)

0

1

0

1

0

1

Output signal of Timer 1 (T1OUT)

Internal shift clock of SSI (SCL)

Output signal of Timer 3 (TOG3)

T2TS

T2R

Timer 2 Toggle with Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with

T2R

Timer 2 Run

T2R = 0, Timer 2 stop and reset

T2R = 1, Timer 2 run

Timer 2 Mode Register 1

(T2M1)

Address: "7"hex - Subaddress: "1"hex

Bit 3

Bit 2

Bit 1

Bit 0

T2D1

T2D0

T2MS1

T2MS0

Reset value: 1111b

T2D1

T2D0

Timer 2 Duty cycle bit 1

Timer 2 Duty cycle bit 0

50

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Table 18. Timer 2 Duty Cycle Bits

Function of Duty Cycle Generator

T2D1

T2D0

(DCG)

Additional Divider Effect

1

0

1

0

1

0

Bypassed (DCGO0)

Duty cycle 1/1 (DCGO1)

Duty cycle 1/2 (DCGO2)

Duty cycle 1/3 (DCGO3)

/1

/2

/3

/4

T2MS1

T2MS0

Timer 2 Mode Select bit 1

Timer 2 Mode Select bit 0

Table 19. Timer 2 Mode Select Bits

Mode T2MS1 T2MS0 Clock Output (POUT)

Timer 2 Modes

12-bit compare counter; the

4-bit counter overflow (OVF1) DCG has to be bypassed in

this mode

1

2

1

0

8-bit compare counter with

4-bit compare output (CM1)

4-bit programmable prescaler

and duty cycle generator

8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler run,

the counter 2/1 starts after

writing mode 3

3

4

0

1

0

4-bit compare output (CM1)

8-bit compare counter clocked

by SYSCL or the external clock

input T2I, 4-bit prescaler stop

and resets

4-bit compare output (CM1)

Duty Cycle Generator

The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at

the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler

setting. The DCG-stage can also be used as additional programmable prescaler for

Timer 2.

Figure 50. DCG Output Signals

DCGIN

DCGO0

DCGO1

DCGO2

DCGO3

51

4552C–4BMCU–01/04

Timer 2 Mode Register 2

(T2M2)

Address: "7"hex - Subaddress: "2"hex

Bit 3

Bit 2

Bit 1

Bit 0

T2TOP

T2OS2

T2OS1

T2OS0

Reset value: 1111b

T2TOP

Timer 2 Toggle Output Preset

This bit allows the programmer to preset the Timer 2 output T2O.

T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)

T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)

Note: If T2R = 1, no output preset is possible

T2OS2

T2OS1

T2OS0

Timer 2 Output Select bit 2

Timer 2 Output Select bit 1

Timer 2 Output Select bit 0

Table 20. Timer 2 Output Select Bits

Output

Mode

T2OS2

T2OS1

T2OS0 Clock Output (POUT)

Toggle mode: a Timer 2 compare match toggles

the output flip-flop (M2) -> T2O

1

Duty cycle burst generator 1: the DCG output

signal (DCG0) is given to the output and gated by

the output flip-flop (M2)

2

3

1

0

Duty cycle burst generator 2: the DCG output

signal (DCGO) is given to the output and gated by

the SSI internal data output (SO)

1

Biphase modulator: Timer 2 modulates the SSI

internal data output (SO) to Biphase code

4

5

6

1

0

1

0

1

0

Manchester modulator: Timer 2 modulates the SSI

internal data output (SO) to Manchester code

SSI output: T2O is used directly as SSI internal

data output (SO)

7

8

0

1

0

PWM mode: an 8-/12-bit PWM mode

Not allowed

If one of these output modes is used the T2O alternate function of Port 4 must also be

activated.

Timer 2 Compare and

Compare Mode Registers

Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for

the 8-bit stage of Timer 2. The timer compares the contents of the compare register

current counter value and if it matches it generates an output signal. Dependent on the

timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop

as SSI clock or as a clock for the next counter stage.

In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit

compare value. In all other modes, the two compare registers work independently as a

4- and 8-bit compare register.

When assigned to the compare register a compare event will be suppressed.

52

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 2 Compare Mode

Register (T2CM)

Address: "7"hex - Subaddress: "3"hex

Bit 3

Bit 2

Bit 1

Bit 0

T2OTM

T2CTM

T2RM

T2IM

Reset value: 0000b

T2OTM Timer 2 Overflow Toggle Mask bit

T2OTM = 0, disable overflow toggle

T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output

flip-flop (TOG2). If the T2OTM bit is set, only a counter overflow can

generate an interrupt except on the Timer 2 output mode 7.

T2CTM Timer 2 Compare Toggle Mask bit

T2CTM = 0, disable compare toggle

T2CTM = 1, enable compare toggle, a match of the counter with the compare

register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and

when the T2CTM bit is set, only a match of the counter with the

compare register can generate an interrupt.

T2RM

T2IM

Timer 2 Reset Mask bit

T2RM = 0, disable counter reset

T2RM = 1, enable counter reset, a match of the counter with the compare register

resets the counter

Timer 2 Interrupt Mask bit

T2IM = 0, disable Timer 2 interrupt

T2IM = 1, enable Timer 2 interrupt

Table 21. Timer 2 Toggle Mask Bits

Timer 2 Output Mode

1, 2, 3, 4, 5 and 6

7

T2OTM

T2CTM

Timer 2 Interrupt Source

Compare match (CM2)

Overflow (OVF2)

0

1

x

1

Compare match (CM2)

Timer 2 COmpare Register 1

(T2CO1)

Address: "7"hex - Subaddress: "4"hex

Write cycle

Bit 3

Bit 2

Bit 1

Bit 0

Reset value: 1111b

In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.

Address: "7"hex - Subaddress: "5"hex

Timer 2 COmpare Register 2

(T2CO2) Byte Write

First write cycle

Bit 3

Bit 7

Bit 2

Bit 6

Bit 1

Bit 5

Bit 0

Bit 4

Reset value: 1111b

Second write cycle

53

4552C–4BMCU–01/04

Timer 3

Features

• Two Compare Registers

• Capture Register

• Edge Sensitive Input with Zero Cross Detection Capability

• Trigger and Single Action Modes

• Output Control Modes

• Automatically Modulation and Demodulation Modes

• FSK Modulation

• Pulse Width Modulation (PWM)

• Manchester Demodulation Together with SSI

• Biphase Demodulation Together with SSI

• Pulse-width Demodulation Together with SSI

Figure 51. Timer 3

TOG2 T3I

T3EIM

INT5

Control

Capture register

D

: T3M1

T3SM1

T3RM1

T3IM1

T3TM1

NQ

CL3

RES

8-bit counter

CM31

CM32

TOG3

C31

C32

8-bit comparator

Compare register 1

Compare register 2

Control

NQ

: T3M2

D

T3SM2

T3RM2

T3IM2

T3TM2

54

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 3 consists of an 8-bit up-counter with two compare registers and one capture

register. The timer can be used as event counter, timer and signal generator. Its output

can be programmed as modulator and demodulator for the serial interface. The two

compare registers enable various modes of signal generation, modulation and demo-

dulation. The counter can be driven by internal and external clock sources. For external

clock sources, it has a programmable edge-sensitive input which can be used as

counter input, capture signal input or trigger input. This timer input is synchronized with

SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop

-> yes), this timer input is stopped too. The counter is readable via its capture register

while it is running. In capture mode, the counter value can be captured by a programma-

ble capture event from the Timer 3 input or Timer 2 output.

A special feature of this timer is the trigger- and single-action mode. In trigger mode, the

counter starts counting triggered by the external signal at its input. In single-action

mode, the counter counts only one time up to the programmed compare match event.

These modes are very useful for modulation, demodulation, signal generation, signal

measurement and phase controlling. For phase controlling, the timer input is protected

against negative voltages and has zero-cross detection capability.

Timer 3 has a modulator output stage and input functions for demodulation. As modula-

tor it works together with Timer 2 or the serial interface. When the shift register is used

for modulation the data shifted out of the register is encoded bitwise. In all demodulation

modes, the decoded data bits are shifted automatically into the shift register.

Timer/Counter Modes

Timer 3 has 6 timer modes and 6 modulator/demodulator modes. The mode is set via

the Timer 3 Mode Register T3M.

In all these modes, the compare register and the compare-mode register belonging to it

define the counter value for a compare match and the action of a compare match. A

match of the current counter value with the content of one compare register triggers a

counter reset, a Timer 3 interrupt or the toggling of the output flip-flop. The compare

mode registers T3M1 and T3M2 contain the mask bits for enabling or disabling these

actions.

The counter can also be enabled to execute single actions with one or both compare

registers. If this mode is set the corresponding compare match event is generated only

once after the counter start.

Most of the timer modes use their compare registers alternately. After the start has been

activated, the first comparison is carried out via the compare register 1, the second is

carried out via the compare register 2, the third is carried out again via the compare

register 1 and so on. This makes it easy to generate signals with constant periods and

variable duty cycle or to generate signals with variable pulse and space widths.

If single-action mode is set for one compare register, the comparison is always carried

out after the first cycle via the other compare register.

The counter can be started and stopped via the control register T3C. This register also

controls the initial level of the output before start. T3C contains the interrupt mask for a

T3I input interrupt.

Via the Timer 3 clock-select register, the internal or external clock source can be

selected. This register selects also the active edge of the external input. An edge at the

external input T3I can generate also an interrupt if the T3EIM bit is set and the Timer 3 is

stopped (T3R = 0) in the T3C register.

55

4552C–4BMCU–01/04

Figure 52. Counter 3 Stage

TOG2 T3I

Control

T3EIM

INT5

Capture register

D

: T3M1

T3SM1

T3RM1

T3IM1

T3TM1

NQ

CL3

RES

8-bit counter

CM31

CM32

TOG3

C31

C32

8-bit comparator

Compare register 1

Compare register 2

Control

NQ

: T3M2

D

T3SM2

T3RM2

T3IM2

T3TM2

The status of the timer as well as the occurrence of a compare match or an edge detect

of the input signal is indicated by the status register T2ST. This allows identification of

the interrupt source because all these events share only one timer interrupt.

Timer 3 compares data values.

The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value

can be m for each of the Timer 3 compare registers.

The compare data value for the compare registers is: m = x +1 0 ≤x ≤255

Timer 3 – Mode 1:

Timer/Counter

The selected clock from an internal or external source increments the 8-bit counter. In

this mode, the timer can be used as event counter for external clocks at T3I or as timer

for generating interrupts and pulses at T3O. The counter value can be read by the

software via the capture register.

56

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 53. Counter Reset with Each Compare Match

T3R

0

1

2

3

0

1

2

3

4

5

0

1

2

3

0

1

2

3

Counter 3

CM31

CM32

INT5

T3O

Figure 54. Counter Reset with Compare Register 2 and Toggle with Start

CL3

T3R

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

Counter 3

CM31

CM32

INT5

T3O

Toggle

by start

T3O

Figure 55. Single Action of Compare Register 1

T3R

0

0 1 2 3 4 5 6 7 8 9 10 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1

Counter 3

CM31

CM32

T3O

Toggle by start

Timer 3 – Mode 2:

The counter is driven by an internal clock source. After starting with T3R, the first edge

from the external input T3I starts the counter. The following edges at T3I load the

current counter value into the capture register, reset the counter and restart it. The edge

can be selected by the programmable edge decoder of the timer input stage. If single-

action mode is activated for one or both compare registers the trigger signal restarts the

single action.

Timer/Counter, External

Trigger Restart and External

Capture (with T3I Input)

57

4552C–4BMCU–01/04

Figure 56. Externally Triggered Counter Reset and Start Combined with Single-action

Mode

T3R

0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X 0 1 2 3 4 5 6 7 8 9 10 0 1 2 X X X

X

Counter 3

T3EX

CM31

CM32

T3O

Timer 3 – Mode 3:

The counter is driven by an internal or external (T3I) clock source. The output toggle sig-

nal of Timer 2 resets the counter. The counter value before the reset is saved in the

capture register. If single-action mode is activated for one or both compare registers, the

trigger signal restarts the single actions. This mode can be used for frequency measure-

ments or as event counter with time gate (see section “Combination Mode 10:

Frequency Measurement or Event Counter with Time Gate” on page 85).

Timer/Counter, Internal

Trigger Restart and Internal

Capture (with TOG2)

Figure 57. Event Counter with Time Gate

T3R

T3I

0 0 1 2 3 4 5 6 7 8 9 10

11

0 1

2

4

0 1 2

3

Counter 3

TOG2

Capture

value = 4

T3CP-

Capture value = 0

Capture value = 11

Register

Timer 3 – Mode 4:

Timer/Counter

The timer runs as timer/counter in mode 1, but its output T3O is used as output for the

Timer 2 output signal.

Timer 3 – Mode 5:

The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the

Timer 2 output signal.

Timer/Counter, External

Trigger Restart and External

Capture (with T3I Input)

Timer 3 Modulator/Demodulator Modes

Timer 3 – Mode 6:

The Timer 3 counter is driven by an internal or external clock source. Its compare- and

Carrier Frequency Burst

Modulation Controlled by

Timer 2 Output Toggle Flip-

Flop (M2)

compare mode registers must be programmed to generate the carrier frequency via the

output toggle flip-flop. The output toggle flip-flop of Timer 2 is used to enable or disable

the Timer 3 output. Timer 2 can be driven by the toggle output signal of Timer 3 or

any other clock source (see section “Combination Mode 11: Burst Modulation 1” on

page 86).

58

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 3 – Mode 7:

Carrier Frequency Burst

The Timer 3 counter is driven by an internal or external clock source. Its compare- and

compare mode registers must be programmed to generate the carrier frequency via the

Modulation Controlled by SSI output toggle flip-flop. The output (SO) of the SSI is used to enable or disable the Timer

Internal Output (SO)

3 output. The SSI should be supplied with the toggle signal of Timer 2 (see section

“Combination Mode 12: Burst Modulation 2” on page 88).

Timer 3 – Mode 8:

FSK Modulation with Shift

Register Data (SO)

The two compare registers are used for generating two different time intervals. The SSI

internal data output (SO) selects which compare register is used for the output

frequency generation. A "0" level at the SSI data output enables the compare register 1.

A "1" level enables compare register 2. The compare- and compare-mode registers

must be programmed to generate the two frequencies via the output toggle flip-flop. The

SSI can be supplied with the toggle signal of Timer 2. The Timer 3 counter is driven by

an internal or external clock source. The Timer 2 counter is driven by the Counter 3

(TOG3) (see section “Combination Mode 13: FSK Modulation” on page 88).

Figure 58. FSK Modulation

T3R

0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1

Counter 3

CM31

CM32

0

1

0

SO

T3O

Timer 3 – Mode 9:

Pulse-width Modulation with

the Shift Register

The two compare registers are used for generating two different time intervals. The SSI

internal data output (SO) selects which compare register is used for the output pulse

generation. In this mode both compare- and compare-mode registers must be

programmed for generating the two pulse widths. It is also useful to enable the single-

action mode for extreme duty cycles. Timer 2 is used as baudrate generator and for the

trigger restart of Timer 3. The SSI must be supplied with a toggle signal of Timer 2. The

counter is driven by an internal or external clock source (see section “Combination

Mode 7: Pulse-width Modulation (PWM)” on page 83).

Figure 59. Pulse-width Modulation

TOG2

SIR

0

1

0

1

SO

SCO

T3R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 91011121314150 1 2 3 4 5 6 7 8 91011121314150 1 2 3 4

Counter 3

CM31

CM32

T3O

59

4552C–4BMCU–01/04

Timer 3 – Mode 10:

Manchester Demodulation/

Pulse-width Demodulation

For Manchester demodulation, the edge detection stage must be programmed to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage is used to generate the shift clock for the SSI. The compare register 1 match

event defines the correct moment for shifting the state from the input T3I as the decoded

bit into shift register – after that the demodulator waits for the next edge to synchronize

the timer by a reset for the next bit. The compare register 2 can also be used to detect a

time-out error and handle it with an interrupt routine (see section “Combination Mode 8:

Manchester Demodulation/ Pulse-width Demodulation” on page 83).

Figure 60. Manchester Demodulation

Timer 3

mode

Synchronize

1

Manchester demodulation mode

0

1

0

1

0

T3I

T3EX

SI

CM31=SCI

SR-DATA

1

0

1

0

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 6

BIT 5

Timer 3 – Mode 11:

Biphase Demodulation

In the Biphase demodulation mode, the timer operates like in Manchester demodulation

mode. The difference is that the bits are decoded via a toggle flip-flop. This flip-flop

samples the edge in the middle of the bitframe and the compare register 1 match event

shifts the toggle flip-flop output into shift register (see section “Combination Mode 9:

Biphase Demodulation” on page 84).

Figure 61. Biphase Demodulation

Timer 3

mode

Synchronize

0

Biphase demodulation mode

0

1

0

1

0

1

0

T3I

T3EX

Q1=SI

CM31=SCI

Reset

Counter 3

0

1

0

1

0

1

0

SR-DATA

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

60

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 3 – Mode 12:

Timer/Counter with External

Capture Mode (T3I)

The counter is driven by an internal clock source and an edge at the external input T3I

loads the counter value into the capture register. The edge can be selected with the

programmable edge detector of the timer input stage. This mode can be used for signal

and pulse measurements.

Figure 62. External Capture Mode

T3R

T3I

0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132333435363738394041

Counter 3

Capture

value = 35

T3CP-

Register

Capture value = 17

Capture value = X

Timer 3 Modulator for

Carrier Frequency Burst

Modulation

If the output stage operates as pulse-width modulator for the shift register, the output

can be stopped with stage 1 of Timer 2. For this task, the timer mode 3 must be used

and the prescaler must be supplied by the internal shift clock of the shift register.

The modulator can be started with the start of the shift register (SIR = 0) and stopped

either by a shift register stop (SIR = 1) or compare match event of stage 1 of Timer 2.

For this task, the Timer 2 must be used in mode 3 and the prescaler stage must be

supplied by the internal shift clock of the shift register.

Figure 63. Modulator 3

0

T3

M3

TOG3

1

Set Res

T3O

Timer 3 Mode T3O

T3TOP

2

MUX

6

7

9

MUX 1

MUX 2

MUX 3

SO

M2

3

other MUX 0

SSI/

Control

OMSK

T3M

Timer 3 Demodulator for The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and

pulse-width-coded signals.

Biphase, Manchesterand

Pulse-width-modulated

Signals

Figure 64. Timer 3 Demodulator 3

T3M

SCI

T3I

Demodulator 3

SI

T3EX

Res

CM31

Counter 3

Reset

Counter 3

Control

61

4552C–4BMCU–01/04

Timer 3 Registers

Timer 3 Mode Register (T3M)

Address: "B"hex - Subaddress: "0"hex

Bit 3

Bit 2

Bit 1

Bit 0

T3M3

T3M2

T3M1

T3M0

Reset value: 1111b

T3M3

Timer 3 Mode select bit 3

Timer 3 Mode select bit 2

Timer 3 Mode select bit 1

Timer 3 Mode select bit 0

T3M2

T3M1

T3M0

Table 22. Timer 3 Mode Select Bits

Mode T3M3 T3M2 T3M1 T3M0 Timer 3 Modes

1

Timer/counter with a read access

Timer/counter, external capture and external

trigger restart mode (T3I)

2

1

0

Timer/counter, internal capture and internal

trigger restart mode (TOG2)

3

4

5

1

0

1

0

1

Timer/counter mode 1 without output (T2O ->

T3O)

Timer/counter mode 2 without output (T2O ->

T3O)

6

7

8

1

0

1

0

1

0

Burst modulation with Timer 2 (M2)

Burst modulation with shift register (SO)

FSK modulation with shift register (SO)

Pulse-width modulation with shift register (SO)

and Timer 2 (TOG2), internal trigger restart

(SCO) -> counter reset

9

0

1

Manchester demodulation/pulse-width

demodulation⁽¹⁾(T2O -> T3O)

10

0

1

0

11

12

0

1

0

1

0

1

0

1

0

1

0

Biphase demodulation (T2O -> T3O)

Timer/counter with external capture mode (T3I)

13

Not allowed

14

15

16

Note:

1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All

other SSI modes are not allowed.

62

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 3 Control Register 1

(T3C) Write

Primary register address: "C"hex - Write

Bit 3

Bit 2

Bit 1

Bit 0

Write

T3EIM

T3TOP

T3TS

T3R

Reset value: 0000b

T3EIM

Timer 3 Edge Interrupt Mask

T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)

T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)

T3TOP

Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0"

T3TOP = 1, sets toggle output (M3) to "1"

Note: If T3R = 1, no output preset is possible

T3TS

T3R

Timer 3 Toggle with Start T3TS = 0, Timer 3 output is not toggled during the start

T3TS = 1, Timer 3 output is toggled if started with T3R

Timer 3 Run

T3R = 0, Timer 3 stop and reset

T3R = 1, Timer 3 run

Timer 3 Status Register 1

(T3ST) Read

Primary register address: "C"hex - Read

Bit 3

Bit 2

Bit 1

Bit 0

T3C1

Read

- - -

T3ED

T3C2

Reset value: x000b

T3ED

T3C2

T3C1

Timer 3 Edge Detect

This bit will be set by the edge-detect logic of Timer 3 input (T3I)

Timer 3 Compare 2

This bit will be set when a match occurs between Counter 3 and T3CO2

Timer 3 Compare 1

This bit will be set when a match occurs between Counter 3 and T3CO1

Note:

The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.

63

4552C–4BMCU–01/04

Timer 3 Clock Select Register

(T3CS)

Address: "B"hex - Subaddress: "1"hex

Bit 0

Bit 3

T3E1

Bit 2

T3E0

Bit 1

T3CS

T3CS1

T3CS0

Reset value: 1111b

T3E1

T3E0

Timer 3 Edge select bit 1

Timer 3 Edge select bit 0

Table 23. Timer 3 Edge Select Bits

T3E1

T3E0

Timer 3 Input Edge Select (T3I)

–

1

0

1

0

1

0

Positive edge at T3I pin

Negative edge at T3I pin

Each edge at T3I pin

T3CS1 Timer 3 Clock Source select bit 1

T3CS0 Timer 3 Clock Source select bit 0

Table 24. Timer 3 Clock Select Bits

T3CS1

TCS0

Counter 3 Input Signal (CL3)

System clock (SYSCL)

1

0

1

0

1

0

Output signal of Timer 2 (POUT)

Output signal of Timer 1 (T1OUT)

External input signal from T3I edge detect

Timer 3 Compare- and

Compare-mode Register

Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of

Timer 3. The timer compares the content of the compare register with the current

counter value. If both match, it generates a signal. This signal can be used for the

counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock

or as clock for the next counter stage. For each compare register, a compare-mode reg-

ister exists. These registers contain mask bits to enable or disable the generation of an

interrupt, a counter reset, or an output toggling with the occurrence of a compare match

of the corresponding compare register. The mask bits for activating the single-action

mode can also be located in the compare mode registers. When assigned to the com-

pare register a compare event will be suppressed.

64

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Timer 3 Compare-Mode

Register 1 (T3CM1)

Address: "B"hex - Subaddress: "2"hex

Bit 3

Bit 2

Bit 1

Bit 0

T3CM1

T3SM1

T3TM1

T3RM1

T3IM1

Reset value: 0000b

Timer 3 Single action Mask bit 1

T3SM1 = 0, disables single-action compare mode

T3SM1 = 1, enables single-compare mode. After this bit is set, the compare

register (T3CO1) is used until the next compare match.

T3TM1

T3RM1

T3IM1

Timer 3 compare Toggle action Mask bit 1

T3TM1 = 0, disables compare toggle

T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare

register (T3CO1) toggles the output flip-flop (TOG3).

Timer 3 Reset Mask bit 1

T3RM1 = 0, disables counter reset

T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare

register (T3CO1) resets the Counter 3.

Timer 3 Interrupt Mask bit 1

T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.

T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.

T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1.

Address: "B"hex - Subaddress: "3"hex

Timer 3 Compare Mode

Register 2 (T3CM2)

Bit 3

Bit 2

Bit 1

Bit 0

T3CM2

T3SM2

T3TM2

T3RM2

T3IM2

Reset value: 0000b

Timer 3 Single action Mask bit 2

T3SM2 = 0, disables single-action compare mode

T3SM2 = 1, enables single-compare mode. After this bit is set, the compare

register (T3CO2) is used until the next compare match.

T3TM2

T3RM2

T3IM2

Timer 3 compare Toggle action Mask bit 2

T3TM2 = 0, disables compare toggle

T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare

register (T3CO2) toggles the output flip-flop (TOG3).

Timer 3 Reset Mask bit 2

T3RM2 = 0, disables counter reset

T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare

register (T3CO2) resets the Counter 3.

Timer 3 Interrupt Mask bit 2

T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.

T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.

T3CM2 contains the mask bits for the match event of Counter 3 compare register 2.

The compare registers and corresponding counter reset masks can be used to program

the counter time intervals and the toggle masks can be used to program output signal.

The single-action mask can also be used in this mode. It starts operating after the timer

started with T3R.

65

4552C–4BMCU–01/04

Timer 3 COmpare Register 1

(T3CO1) Byte Write

Address: "B"hex - Subaddress: "4"hex

High Nibble

Bit 6 Bit 5

Second write cycle

First write cycle

Bit 7

Bit 3

Bit 4

Bit 0

Reset value: 1111b

Low Nibble

Bit 2 Bit 15

Timer 3 COmpare Register 2

(T3CO2) Byte Write

Address: "B"hex - Subaddress: "5"hex

High Nibble

Bit 6 Bit 5

Second write cycle

First write cycle

Bit 7

Bit 3

Bit 4

Bit 0

Reset value: 1111b

Low Nibble

Bit 2 Bit 15

Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the

capture register. In mode 1 and mode 4, it is possible to read the current counter value

directly out of the capture register. In the capture modes 2, 3, 5 and 12, a capture event

like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter

value into the capture register. This counter value can be read from the capture register.

Timer 3 CaPture Register

(T3CP) Byte Read

Address: "B"hex - Subaddress: "4"hex

High Nibble

Bit 6 Bit 5

First read cycle

Bit 7

Bit 3

Bit 4

Bit 0

Reset value: xxxxb

Low Nibble

Bit 2 Bit 15

Second read cycle

66

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Synchronous Serial

Interface (SSI)

SSI Features

–

2- and 3-wire NRZ

2-wire multi-chip link mode (MCL), additional internal 2-wire link for multi-

chip packaging solutions

•

With Timer 2

–

Biphase modulation

Manchester modulation

Pulse-width demodulation

Burst modulation

With Timer 3

–

Pulse-width modulation (PWM)

FSK modulation

Biphase demodulation

Manchester demodulation

Pulse-width demodulation

Pulse position demodulation

SSI Peripheral Configuration

The synchronous serial interface (SSI) can be used either for serial communication with

external devices such as EEPROMs, shift registers, display drivers, other microcon-

trollers, or as a means for generating and capturing on-chip serial streams of data.

External data communication takes place via the Port 4 (BP4),a multi-functional port

which can be software configured by writing the appropriate control word into the P4CR

register. The SSI can be configured in any of the following ways:

1. 2-wire external interface for bi-directional data communication with one data

terminal and one shift clock. The SSI uses the Port BP43 as a bi-directional

serial data line (SD) and BP40 as shift clock line (SC).

2. 3-wire external interface for simultaneous input and output of serial data, with a

serial input data terminal (SI), a serial output data terminal (SO) and a shift clock

(SC). The SSI uses BP40 as shift clock (SC), while the serial data input (SI) is

applied to BP43 (configured in P4CR as input.). Serial output data (SO) in this

case is passed through to BP42 (configured in P4CR to T2O) via the Timer 2

output stage (T2M2 configured in mode 6).

3. Timer/SSI combined modes – the SSI used together with Timer 2 or Timer 3 is

capable of performing a variety of data modulation and demodulation functions

(see section Timer). The modulating data is converted by the SSI into a continu-

ous serial stream of data which is in turn modulated in one of the timer functional

blocks. Serial demodulated data can be serially captured in the SSI and read by

the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI

can only be used as demodulator.

4. Internal Multi-Chip Link pads (MCL) – the SSI can also be used as an interchip

data interface for use in single package multi-chip modules or hybrids. For such

applications, the SSI is provided with two dedicated pads (MCL_SD and

MCL_SC) which act as a two-wire chip-to-chip link. The internal MCL can be

activated by the MCL control bit. Should these MCL pads be used by the SSI, the

standard SD and SC pins are not required and the corresponding Port 4 ports

are available as conventional data ports.

67

4552C–4BMCU–01/04

Figure 65. Block Diagram of the Synchronous Serial Interface

I/O-bus

Timer 2 / Timer 3

SIC1

SIC2

SISC

SI SCI

SO

INT3

Control

SC

SSI-Control

MCL_SC

Output

TOG2

POUT

T1OUT

SYSCL

SO

MCL_SD

SD

/2

SI

8-bit Shift Register

MSB

LSB

Shift_CL

STB

SRB

Transmit

Buffer

Receive

Buffer

I/O-bus

General SSI Operation

The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buff-

ers – the receive buffer (SRB) for capturing the incoming serial data and a transmit

buffer (STB) for intermediate storage of data to be serially output. Both buffers are

directly accessable by software. Transferring the parallel buffer data into and out of the

shift register is controlled automatically by the SSI control, so that both single byte

transfers or continuous bit streams can be supported.

The SSI can generate the shift clock (SC) either from one of several on-chip clock

sources or accept an external clock. The external shift clock is output on, or applied to

the Port BP40. Selection of an external clock source is performed by the Serial Clock

Direction control bit (SCD). In the combinational modes, the required clock is selected

by the corresponding timer mode.

The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a

9-bit Multi-Chip Link Mode (MCL), containing 8-bit data and 1-bit acknowledge, and a

corresponding 8-bit MCL mode without acknowledge. In both MCL modes the data

transmission begins after a valid start condition and ends with a valid stop condition.

External SSI clocking is not supported in these modes. The SSI should thus generate

and has full control over the shift clock so that it can always be regarded as an MCL Bus

Master device.

All directional control of the external data port used by the SSI is handled automatically

and is dependent on the transmission direction set by the Serial Data Direction (SDD)

control bit. This control bit defines whether the SSI is currently operating in Transmit

(TX) mode or Receive (RX) mode.

Serial data is organized in 8-bit telegrams which are shifted with the most significant bit

first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the

telegram for handshaking purposes (see section “MCL Bus Protocol” on page 72).

At the beginning of every telegram, the SSI control loads the transmit buffer into the shift

register and proceeds immediately to shift data serially out. At the same time, incoming

data is shifted into the shift register input. This incoming data is automatically loaded

into the receive buffer when the complete telegram has been received. Thus, data can

be simultaneously received and transmitted if required.

68

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ATAR862-4 [Preliminary]

Before data can be transferred, the SSI must first be activated. This is performed by

means of the SSI reset control (SIR) bit. All further operation then depends on the data

directional mode (TX/RX) and the present status of the SSI buffer registers shown by

the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the

(empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX

mode). The control logic ensures that data shifting is temporarily halted at any time, if

the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will

then automatically be set back to ‘1’ and data shifting resumed as soon as the applica-

tion software loads the new data into the transmit register (in TX mode) or frees the shift

register by reading it into the receive buffer (in RX mode).

A further activity status (ACT) bit indicates the present status of the serial communica-

tion. The ACT bit remains high for the duration of the serial telegram or if MCL stop or

start conditions are currently being generated. Both the current SRDY and ACT status

can be read in the SSI status register. To deactivate the SSI, the SIR bit must be set

high.

8-bit Synchronous Mode

Figure 66. 8-bit Synchronous Mode

SC

(Rising edge)

SC

(Falling edge)

0

1

0

1

0

1

DATA

Bit 7

0

Bit 0

1

SD/TO2

Bit 7

Bit 0

Data: 00110101

In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface

(see section “SSI Peripheral Configuration” on page 67). The serial data (SD) is

received or transmitted in NRZ format, synchronized to either the rising or falling edge of

the shift clock (SC). The choice of clock edge is defined by the Serial Mode Control bits

(SM0,SM1). It should be noted that the transmission edge refers to the SC clock edge

with which the SD changes. To avoid clock skew problems, the incoming serial input

data is shifted in with the opposite edge.

When used together with one of the timer modulator or demodulator stages, the SSI

must be set in the 8-bit synchronous mode 1.

In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and

the incoming serial data is shifted into the shift register. This first telegram is automati-

cally transferred into the receive buffer and the SRDY set to 0 indicating that the receive

buffer contains valid data. At the same time an interrupt (if enabled) is generated. The

SSI then continues shifting in the following 8-bit telegram. If, during this time the first

telegram has been read by the controller, the second telegram will also be transferred in

the same way into the receive buffer and the SSI will continue clocking in the next tele-

gram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI

will stop, temporarily holding the second telegram in the shift register until a certain point

of time when the controller is able to service the receive buffer. In this way no data is lost

or overwritten.

69

4552C–4BMCU–01/04

Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and

latch the present contents of the shift register into the receive buffer. This can be used

for clocking in a data telegram of less than 8 bits in length. Care should be taken to read

out the final complete 8-bit data telegram of a multiple word message before deactivat-

ing the SSI (SIR = 1) and terminating the reception. After termination, the shift register

contents will overwrite the receive buffer.

Figure 67. Example of 8-bit Synchronous Transmit Operation

SC

msb

lsb

1

msb

lsb msb

lsb

1

7

6

5

4

3

2

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

SD

SIR

tx data 1

tx data 2

tx data 3

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Write STB

(tx data 1)

Write STB Write STB

(tx data 2) (tx data 3)

Figure 68. Example of 8-bit Synchronous Receive Operation

SC

msb

7

lsb msb

lsb

1

msb

lsb

SD

6

5

4

3

2

1

0

7

6

5

4

3

2

0

7

6

5

4 3 2 1 0 7 6 5 4

rx data 1

rx data 2

rx data 3

SIR

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Read SRB

(rx data 1)

Read SRB

(rx data 2)

Read SRB

(rx data 3)

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ATAR862-4 [Preliminary]

9-bit Shift Mode (MCL)

In the 9-bit shift mode, the SSI is able to handle the MCL protocol described below. It

always operates as an MCL master device, i.e., SC is always generated and output by

the SSI. Both the MCL start and stop conditions are automatically generated whenever

the SSI is activated or deactivated by the SIR bit. In accordance with the MCL protocol,

the output data is always changed in the clock low phase and shifted in on the high

phase.

Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate

data direction for the first word must be set using the SDD control bit. The state of this

bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data

bits are, depending on the selected direction, either clocked into or out of the shift regis-

ter. During the 9th clock period, the port direction is automatically switched over so that

the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the

acknowledge bit received from the device is captured in the SSI Status Register (TACK)

where it can be read by the controller. In receive mode, the state of the acknowledge bit

to be returned to the device is predetermined by the SSI Status Register (RACK).

Changing the directional mode (TX/RX) should not be performed during the transfer of

an MCL telegram. One should wait until the end of the telegram which can be detected

using the SSI interrupt (IFN = 1) or by interrogating the ACT status.

Once started, a 9-bit telegram will always run to completion and will not be prematurely

terminated by the SIR bit. So, if the SIR bit is set to "1" in telegram, the SSI will complete

the current transfer and terminate the dialog with an MCL stop condition.

Figure 69. Example of MCL Transmit Dialog

Start

Stop

SC

SD

msb

lsb

0 A

msb

lsb

1

7

6

5

4

3

2

1

7

6

5

4

3

2

0 A

tx data 1

tx data 2

SRDY

ACT

Interrupt

IFN = 0)

Interrupt

IFN = 1)

SIR

SDD

Write STB

(tx data 1)

Write STB

(tx data 2)

71

4552C–4BMCU–01/04

Figure 70. Example of MCL Receive Dialog

Start

Stop

SC

msb

lsb

0 A

msb

lsb

1

SD

A

0

7

6

5

4

3

2

1

7

6

5

4

3

2

tx data 1

rx data 2

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

SIR

SDD

Write STB

(tx data 1)

Read SRB

(rx data 2)

8-bit Pseudo MCL Mode

MCL Bus Protocol

In this mode, the SSI exhibits all the typical MCL operational features except for the

acknowledge bit which is never expected or transmitted.

The MCL protocol constitutes a simple 2-wire bi-directional communication highway via

which devices can communicate control and data information. Although the MCL proto-

col can support multi-master bus configurations, the SSI in MCL mode is intended for

use purely as a master controller on a single master bus system. So all reference to

multiple bus control and bus contention will be omitted at this point.

All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit.

Normally the communication channel is opened with a so-called start condition, which

initializes all devices connected to the bus. This is then followed by a data telegram,

transmitted by the master controller device. This telegram usually contains an 8-bit

address code to activate a single slave device connected onto the MCL bus. Each slave

receives this address and compares it with its own unique address. The addressed

slave device, if ready to receive data, will respond by pulling the SD line low during the

9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting

this affirmative acknowledge then opens a connection to the required slave. Data can

then be passed back and forth by the master controller, each 8-bit telegram being

acknowledged by the respective recipient. The communication is finally closed by the

master device and the slave device put back into standby by applying a stop condition

onto the bus.

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ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 71. MCL Bus Protocol 1

(1)

(2)

(4)

(3)

(1)

SC

SD

Start

Data

valid

Data

valid

Stop

condition

change

condition

Bus not busy (1)

Both data and clock lines remain HIGH.

Start data transfer (2)

A HIGH to LOW transition of the SD line while the clock (SC)

is HIGH defines a START condition.

Stop data transfer (3)

Data valid (4)

A LOW to HIGH transition of the SD line while the clock (SC)

is HIGH defines a STOP condition.

The state of the data line represents valid data when,

after START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

Acknowledge

All address and data words are serially transmitted to and

from the device in eight-bit words. The receiving device

returns a zero on the data line during the ninth clock cycle to

acknowledge word receipt.

Figure 72. MCL Bus Protocol 2

SC

1

n

8

9

SD

Start

1st Bit

8th Bit

ACK

Stop

73

4552C–4BMCU–01/04

SSI Interrupt

The SSI interrupt INT3 can be generated either by an SSI buffer register status

(i.e., transmit buffer empty or receive buffer full), the end of SSI data telegram or on the

falling edge of the SC/SD pins on Port 4 (see section “Port 4 Control Register (P4CR)

Byte Write” on page 38). SSI interrupt selection is performed by the Interrupt FunctioN

control bit (IFN). The SSI interrupt is usually used to synchronize the software control of

the SSI and inform the controller of the present SSI status. The Port 4 interrupts can be

used together with the SSI or, if the SSI itself is not required, as additional external inter-

rupt sources. In either case this interrupt is capable of waking the controller out of sleep

mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and

the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropri-

ate control bits in P4CR register.

Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodula-

tion purposes, the 8-bit synchronous mode must be used. In this case, the unused Port

4 pins can be used as conventional bi-directional ports.

The modulation and demodulation stages, if enabled, operate as soon as the SSI is

activated (SIR = 0) and cease when deactivated (SIR = 1).

Due to the byte-orientated data control, the SSI (when running normally) generates

serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) func-

tion permits; however, the generation of bit streams of any length. The OMSK signal is

derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable

number of unrequired trailing data bits during the shifting out of the final data word in the

bit stream. The number of non-masked data bits is defined by the value pre-

programmed in the prescaler compare register. To use output masking, the modulator

stop mode bit (MSM) must be set to "0" before programming the final data word into the

SSI transmit buffer. This in turn, enables shift clocks to the prescaler when this final

word is shifted out. On reaching the compare value, the prescaler triggers the OMSK

signal and all following data bits are blanked.

Internal 2-wire Multi-chip Link Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be

used as chip-to-chip link for multi-chip applications. These pads can be activated by

setting the MCL-bit in the SISC-register.

Figure 73. Multi-chip Link

U505M

SCL

SDA

Multi chip link

MCL_SC

MCL_SD

V _DD

V_SS

BP40/SC

BP43/SD

Microcontroller

BP10

BP13

74

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 74. SSI Output Masking Function

CL2/1

Timer 2

4-bit counter 2/1

SCL

Compare 2/1

CM1

OMSK

Control

SO

SC

SSI-control

Output

SO

TOG2

POUT

T1OUT

SYSCL

SI

/2

8-bit shift register

MSB

LSB

Shift_CL

Serial Interface Registers

Serial Interface Control

Register 1 (SIC1)

Auxiliary register address: "9"hex

Bit 3

SIR

Bit 2

Bit 1

Bit 0

SCD

SCS1

SCS0

Reset value: 1111b

SIR

Serial Interface Reset

SIR = 1, SSI inactive

SIR = 0, SSI active

SCD

Serial Clock Direction

SCD = 1, SC line used as output

SCD = 0, SC line used as input

Note: This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 or 11

SCS1

SCS0

Serial Clock source Select bit 1

Serial Clock source Select bit 0

Note: with SCD = "0" the bits SCS1 and SCS0 are insignificant

Table 25. Serial Clock Source Select Bits

SCS1

SCS0

Internal Clock for SSI

SYSCL/2

1

0

1

0

1

0

T1OUT/2

POUT/2

TOG2/2

75

4552C–4BMCU–01/04

•

In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded

(SRDY = 1).

Setting SIR bit loads the contents of the shift register into the receive buffer

(synchronous 8-bit mode only).

In MCL modes, writing a 0 to SIR generates a start condition and writing a 1

generates a stop condition.

Serial Interface Control

Register 2 (SIC2)

Auxiliary register address: "A"hex

Bit 3

Bit 2

Bit 1

Bit 0

MSM

SM1

SM0

SDD

Reset value: 1111b

MSM

Modular Stop Mode

MSM = 1, modulator stop mode disabled (output masking off)

MSM = 0, modulator stop mode enabled (output masking on) - used in modulation

modes for generating bit streams which are not sub-multiples of 8 bits.

SM1

SM0

Serial Mode control bit 1

Serial Mode control bit 0

Table 26. Serial Mode Control Bits

Mode

SM1

SM0

SSI Mode

1

2

3

4

1

0

1

0

1

0

8-bit NRZ-Data changes with the rising edge of SC

8-bit NRZ-Data changes with the falling edge of SC

9-bit two-wire MCL mode

8-bit two-wire MCL mode (no acknowledge)

SDD

Serial Data Direction

SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set

by a transmit buffer write access.

SDD = 0, receive mode – SD line used as input (receive data). SRDY is set

by a receive buffer read access

Note: SDD controls port directional control and defines the reset function for the SRDY flag

76

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Serial Interface Status and

Control Register (SISC)

Primary register address: "A"hex

Bit 3

MCL

- - -

Bit 2

Bit 1

SIM

ACT

Bit 0

IFN

SRDY

Write

Read

RACK

TACK

Reset value: 1111b

Reset value: xxxxb

MCL

Multi-Chip Link activation

MCL = 1,multi-chip link disabled. This bit has to be set to "0" during

transactions to/from EEPROM

MCL = 0, connects SC and SD additionally to the internal multi-chip link pads

RACK

TACK

SIM

Receive ACKnowledge status/control bit for MCL mode

RACK = 0, transmit acknowledge in next receive telegram

RACK = 1, transmit no acknowledge in last receive telegram

Transmit ACKnowledge status/control bit for MCL mode

TACK = 0, acknowledge received in last transmit telegram

TACK = 1, no acknowledge received in last transmit telegram

Serial Interrupt Mask

SIM = 1, disable interrupts

SIM = 0, enable serial interrupt. An interrupt is generated.

IFN

Interrupt FuNction

IFN = 1, the serial interrupt is generated at the end of telegram

IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer

becomes empty/full in transmit/receive mode)

SRDY

ACT

Serial interface buffer ReaDY status flag

SRDY = 1, in receive mode: receive buffer empty

in transmit mode: transmit buffer full

SRDY = 0, in receive mode: receive buffer full

in transmit mode: transmit buffer empty

Transmission ACTive status flag

ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions

are currently in progress.

ACT = 0, transmission is inactive

Serial Transmit Buffer (STB) –

Byte Write

Primary register address: "9"hex

First write cycle

Bit 3

Bit 7

Bit 2

Bit 6

Bit 1

Bit 5

Bit 0

Bit 4

Reset value: xxxxb

Second write cycle

The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift regis-

ter and starts shifting with the most significant bit.

77

4552C–4BMCU–01/04

Serial Receive Buffer (SRB) –

Byte Read

Primary register address: "9"hex

First read cycle

Bit 7

Bit 3

Bit 6

Bit 2

Bit 5

Bit 1

Bit 4

Bit 0

Reset value: xxxxb

Second read cycle

The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant

bit first) and loads content into the receive buffer when complete telegram has been received.

Combination Modes

The UTCM consists of two timers (Timer 2 and Timer 3) and a serial interface. There is

a multitude of modes in which the timers and serial interface can work together.

The 8-bit wide serial interface operates as shift register for modulation and demodula-

tion. The modulator and demodulator units work together with the timers and shift the

data bits into or out of the shift register.

Combination Mode

Timer 2 and SSI

Figure 75. Combination Timer 2 and SSI

I/O-bus

P4CR

T2M1

T2M2

T2I

DCGO

RES

SYSCL

T1OUT

TOG3

SCL

T2O

CL2/1

CL2/2

4-bit counter 2/1

RES OVF1

8-bit counter 2/2

Output

DCG

POUT

Timer 2 - control

POUT CM1

OVF2

TOG2

Compare 2/1

T2C

Compare 2/2

MOUT

INT4

Biphase-,

Manchester-

modulator

Timer 2

modulator

output-stage

T2CO1

T2CM

T2CO2

SISC

TOG2

SO

Control

I/O-bus

SIC1

SIC2

Control

INT3

SO

TOG2

SC

SD

SCLI

SCL

POUT

T1OUT

SYSCL

SSI-control

MCL_SC

MCL_SD

Output

SO

SI

8-bit shift register

MSB

LSB

Shift_CL

STB

SRB

Transmit

buffer

Receive

buffer

I/O-bus

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ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Combination Mode 1:

Burst Modulation

SSI mode 1:

8-bit NRZ and internal data SO output to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4:

Timer 2 output mode 3:

8-bit compare counter with 4-bit programmable prescaler

and DCG

Duty cycle burst generator

Figure 76. Carrier Frequency Burst Modulation with the SSI Internal Data Output

DCGO

1

2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1

Counter 2

TOG2

SO

Counter = compare register (=2)

Bit 0 Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9 Bit 10 Bit 11 Bit 12 Bit 13

T2O

Combination Mode 2:

Biphase Modulation 1

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4:

Timer 2 output mode 4:

8-bit compare counter with 4-bit programmable prescaler

The modulator 2 of Timer 2 modulates the SSI internal

data output to Biphase code

Figure 77. Biphase Modulation 1

TOG2

SC

8-bit SR-data

0

1

0

1

0

1

SO

Bit 7

Bit 0

1

0

1

0

1

T2O

Data: 00110101

79

4552C–4BMCU–01/04

Combination Mode 3:

Manchester Modulation 1

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 1, 2, 3 or 4:

Timer 2 output mode 5:

8-bit compare counter with 4-bit programmable prescaler

The modulator 2 of Timer 2 modulates the SSI internal

data output to Manchester code

Figure 78. Manchester Modulation 1

TOG2

SC

8-bit SR-data

0

1

0

1

0

1

SO

Bit 7

Bit 0

0

1

0

1

0

1

T2O

Bit 7

Bit 0

Data: 00110101

Combination Mode 4:

Manchester Modulation 2

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3:

8-bit compare counter and 4-bit prescaler

Timer 2 output mode 5: The modulator 2 of Timer 2 modulates the SSI data output

to Manchester code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for

modulator 2. The SSI has a special mode to supply the prescaler with the shift clock.

The control output signal (OMSK) of the SSI is used as stop signal for the modulator.

Figure 79 on page 80 shows an example for a 12-bit Manchester telegram.

Figure 79. Manchester Modulation 2

SCLI

Buffer full

SIR

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SO

SC

MSM

Timer 2

Mode 3

SCL

Counter 2/1 = Compare Register 2/1 (= 4)

3

0

1

2

3

4

0

1

2

Counter 2/1

OMSK

T2O

80

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Combination Mode 5:

Biphase Modulation 2

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 2

modulator stage

Timer 2 mode 3:

8-bit compare counter and 4-bit prescaler

Timer 2 output mode 4: The modulator 2 of Timer 2 modulates the SSI data output

to Biphase code

The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for mod-

ulator 2. The SSI has a special mode to supply the prescaler via the shift clock. The

control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure

80 on page 81 shows an example for a 13-bit Biphase telegram.

Figure 80. Biphase Modulation

SCLI

Buffer full

SIR

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SO

SC

MSM

Timer 2

Mode 3

SCL

Counter 2/1 = Compare Register 2/1 (= 5)

0

1

2

3

4

5

0

1

2

2/1

Counter

OMSK

T2O

81

4552C–4BMCU–01/04

Combination Mode Timer 3 and SSI

Figure 81. Combination Timer 3 and SSI

I/O-bus

T3CS

T3M

T3I

T3EX

SC

SI

T3I

Demodu-

lator 3

CM31

RES

CP3

T3CP

T3EX

INT5

CL3

RES

Compare 3/1

SYSCL

T1OUT

POUT

8-bit counter 3

T3C

T3ST

TOG3

SO

T3O

Modulator 3

Control

Compare 3/2

Timer 3 - control

T3CM1

M2

T3CO1

T3CO2

T3CM2

SISC

SI

SC

SIC1

SIC2

Control

INT3

TOG2

SC

SI

POUT

T1OUT

SYSCL

SCLI

SSI-control

MCL_SC

MCL_SD

Output

SO

SI

8-bit shift register

MSB

LSB

Shift_CL

STB

SRB

Transmit buffer

Receive buffer

I/O-bus

Combination Mode 6:

FSK Modulation

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 8: FSK modulation with shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects which compare register is used for the output frequency generation. A "0"

level at the SSI data output enables the compare register 1 and a "1" level enables the

compare register 2. The compare and compare mode registers must be programmed to

generate the two frequencies via the output toggle flip-lop. The SSI can be supplied with

the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by

an internal or external clock source.

Figure 82. FSK Modulation

T3R

0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1 2 3 4 0

Counter 3

CM31

CM32

0

1

0

SO

T3O

82

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Combination Mode 7:

Pulse-width Modulation

(PWM)

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)

The two compare registers are used to generate two varied time intervals. The SSI data

output selects which compare register is used for the output pulse generation. In this

mode, both compare and compare mode registers must be programmed to generate the

two pulse width. It is also useful to enable the single-action mode for extreme duty

cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.

The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an

internal or external clock source.

Figure 83. Pulse-width Modulation

TOG2

SIR

0

1

0

1

SO

SCO

T3R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 91011121314150 1 2 3 4 5 6 7 8 91011121314150 1 2 3 4

Counter 3

CM31

CM32

T3O

Combination Mode 8:

Manchester Demodulation/

Pulse-width Demodulation

SSI mode 1:

8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3

For Manchester demodulation, the edge detection stage must be programmed to detect

each edge at the input. These edges are evaluated by the demodulator stage. The timer

stage is used to generate the shift clock for the SSI. A compare register 1 match event

defines the correct moment for shifting the state from the input T3I as the decoded bit

into shift register. After that, the demodulator waits for the next edge to synchronize the

timer by a reset for the next bit. The compare register 2 can be used to detect a time

error and handle it with an interrupt routine.

Before activating the demodulator mode the timer and the demodulator stage must be

synchronized with the bitstream. The Manchester code timing consists of parts with the

half bitlength and the complete bitlength. A synchronization routine must start the

demodulator after an interval with the complete bitlength.

The counter can be driven by any internal clock source. The output T3O can be used by

Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demod-

ulation. The input must programmed to detect the positive edge. The demodulator and

timer must be synchronized with the leading edge of the pulse. After that a counter

match with the compare register 1 shifts the state at the input T3I into the shift register.

The next positive edge at the input restarts the timer.

83

4552C–4BMCU–01/04

Figure 84. Manchester Demodulation

Timer 3

mode

Synchronize

1

Manchester demodulation mode

0

1

0

1

0

T3I

T3EX

SI

CM31=SCI

SR-DATA

1

0

1

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Combination Mode 9:

Biphase Demodulation

SSI mode 1:

8-bit shift register internal data input (SI) and the internal shift clock

(SCI) from the Timer 3

Timer 3 mode 11: Biphase demodulation with Timer 3

In the Biphase demodulation mode the timer works like in the Manchester demodulation

mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop

samples the edge in the middle of the bitframe and the compare register 1 match event

shifts the toggle flip-flop output into shift register. Before activating the demodulation the

timer and the demodulation stage must be synchronized with the bitstream. The

Biphase code timing consists of parts with the half bitlength and the complete bitlength.

The synchronization routine must start the demodulator after an interval with the com-

plete bitlength.

The counter can be driven by any internal clock source and the output T3O can be used

by Timer 2 in this mode.

Figure 85. Biphase Demodulation

Timer 3

mode

Synchronize

0

Biphase demodulation mode

0

1

0

1

0

1

0

T3I

T3EX

Q1=SI

CM31=SCI

Reset

Counter 3

0

1

0

1

0

1

0

SR-DATA

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

84

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Combination Mode Timer 2 and Timer 3

Figure 86. Combination Timer 2 and Timer 3

I/O-bus

T3CS

T3M

T3I

T3EX

T3I

SCI

SI

Demodu-

lator 3

CM31

RES

CP3

T3CP

T3EX

INT5

CL3

SYSCL

8-bit counter 3

T3C

T3ST

T1OUT

POUT

RES

TOG3

SO

T3O

Control

Modulator 3

Compare 3/1

Compare 3/2

Timer 3 - control

TOG2

M2

T3CO1

T3CO2

T3CM1

T3CM2

I/O-bus

SSI

T2M2

P4CR

T2M1

T2I

DCGO

T2O

TOG3

SYSCL

T1OUT

SCL

CL2/1

CL2/2

OUTPUT

MOUT

4-bit counter 2/1

RES OVF1

Compare 2/1

8-bit counter 2/2

RES OVF2

DCG

POUT

TOG2

M2

T2C

Timer 2 - control

Compare 2/2

Biphase-,

Manchester-

modulator

INT4

CM1

POUT

Timer 2

modulator 2

output-stage

T2CO1

T2CM

T2CO2

SO

SSI

I/O-bus

Control

(RE, FE, SCO, OMSK)

SSI

Combination Mode 10:

Frequency Measurement or

Timer 2 mode 1/2:

12-bit compare counter/8-bit compare counter and

4-bit prescaler

Event Counter with Time Gate

Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the Timer 3

Timer 3 mode 3:

Timer/Counter; internal trigger restart and internal

capture (with Timer 2 TOG2-signal)

The counter is driven by an external (T3I) clock source. The output signal (TOG2) of

Timer 2 resets the counter. The counter value before reset is saved in the capture

register. If single-action mode is activated for one or both compare registers, the trigger

signal restarts also the single actions. This mode can be used for frequency measure-

ments or as event counter with time gate.

85

4552C–4BMCU–01/04

Figure 87. Frequency Measurement

T3R

T3I

0 0 1 2 3 4 5 6 7 8 9 1011121314151617 0 1 2 3 4

5 6 7 8 9 101112131415161718 0 1 2 3 4 5

Counter 3

TOG2

T3CP-

Register

Capt. value = 18

Capture value = 0

Capture value = 17

Figure 88. Event Counter with Time Gate

T3R

T3I

0 0 1 2 3 4 5 6 7 8 9 10

11

0 1

2

4

0 1 2

3

Counter 3

TOG2

T3CP-

Register

Capture value = 0

Capture value = 11

Cap. val. = 4

Combination Mode 11:

Burst Modulation 1

Timer 2 mode 1/2:

12-bit compare counter/8-bit compare counter and

4-bit prescaler

Timer 2 output mode 1/6: Timer 2 compare match toggles the output flip-flop (M2)

to the Timer 3

Timer 3 mode 6:

Carrier frequency burst modulation controlled by Timer 2

output (M2)

The Timer 3 counter is driven by an internal or external clock source. Its compare and

compare mode registers must be programmed to generate the carrier frequency with

the output toggle flip-flop. The output toggle flip-flop (M2) of Timer 2 is used to enable

and disable the Timer 3 output. The Timer 2 can be driven by the toggle output signal of

Timer 3 (TOG3) or any other clock source.

Figure 89. Burst Modulation 1

CL3

0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01

5 0 1 01

50 1 01

501 01

5 01 01

501 01

5 01 01

Counter 3

CM1

CM2

TOG3

M3

3

0

1

2

3

0

1

2

3

Counter 2/2

TOG2

M2

T3O

86

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Combination Mode Timer 2, Timer 3 and SSI

Figure 90. Combination Timer 2, Timer 3 and SSI

I/O-bus

T3CS

T3M

T3I

T3EX

SCI

SI

Demodu-

lator 3

T3I

CM31

RES

CP3

T3CP

T3EX

SYSCL

T1OUT

POUT

RES

INT5

CL3

8-bit Counter 3

T3C

T3ST

TOG3

SO

T3O

Control

Modulator 3

Compare 3/1

Compare 3/2

Timer 3 - control

M2

TOG2

T3CO1

T3CO2

T3CM1

T3CM2

SSI

I/O-bus

P4CR

T2M1

T2M2

T2I

DCGO

T2O

TOG3

SYSCL

T1OUT

CL2/1

OUTPUT

MOUT

CL2/2

POUT

DCG

4-bit Counter 2/1

8-bit Counter 2/2

SCL

RES

OVF1

RES

OVF2

TOG2

M2

T2C

Compare 2/1

Compare 2/2

Timer 2 - control

Biphase-,

Manchester-

modulator

INT4

CM1

POUT

T2CO1

T2CM

T2CO2

SO

Control

Timer 2

I/O-bus

modulator 2

Control

(RE, FE,

SCO, OMSK)

output-stage

SIC1

SIC2

SISC

TOG2

INT3

SC

SI

SCLI

POUT

T1OUT

SYSCL

SSI-control

MCL_SC

Output

SO

MCL_SD

SI

SCL

_MSB8-bit shift register

LSB

Shift_CL

STB

SRB

Receive buffer

Transmit buffer

I/O-bus

87

4552C–4BMCU–01/04

Combination Mode 12:

Burst Modulation 2

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 2 output mode 2: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6: Timer 2 compare match toggles (TOG2) to the SSI

Timer 3 mode 7:

Carrier frequency burst modulation controlled by the internal

output (SO) of SSI

The Timer 3 counter is driven by an internal or external clock source. Its compare and

compare mode registers must be programmed to generate the carrier frequency with

the output toggle flip-flop (M3). The internal data output (SO) of the SSI is used to

enable and disable the Timer 3 output. The SSI can be supplied with the toggle signal of

Timer 2.

Figure 91. Burst Modulation 2

CL3

0 1 01 2 34 5 01 0 12 3 45 0 10 1 23 4 50 1 01

50 1 01

5 0 1 01

5 01 01

50 1 01

5 01 01

Counter 3

CM31

CM32

TOG3

M3

3

0

1

2

3

0

1

2

3

Counter 2/2

TOG2

SO

T3O

Combination Mode 13:

FSK Modulation

SSI mode 1:

8-bit shift register internal data output (SO) to the Timer 3

Timer 2 output mode 3: 8-bit compare counter and 4-bit prescaler

Timer 2 output mode 1/6: Timer 2 4-bit compare match signal (POUT) to the SSI

Timer 3 mode 8:

FSK modulation with shift register data output (SO)

The two compare registers are used to generate two different time intervals. The SSI

data output selects which compare register is used for the output frequency generation.

A "0" level at the SSI data output enables the compare register 1 and a "1" level enables

the compare register 2. The compare- and compare mode registers must be pro-

grammed to generate the two frequencies via the output toggle flip-flop. The SSI can be

supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter

is driven by an internal or external clock source.

88

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 92. FSK Modulation

T3R

0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0 1

Counter 3

CM31

CM32

SO

0

1

0

T3O

Microcontroller Block The microcontroller block is a multichip device which offers a combination of a MARC4-

based microcontroller and a serial E2PROM data memory in a single package. A micro-

controller is used and as serial E2PROM the U505M. Two internal lines can be used as

chip-to-chip link in a single package. The maximum internal data communication

frequency between the microcontroller block and the U505M over the chip link

(MCL_SC and MCL_SD) is f_{SC_MCL}= 500 kHz.

The microcontroller and the EEPROM portions of this multi-chip device are equivalent to

their respective individual component chips, except for the electrical specification.

Internal 2-wire Multi-chip Link Two additional on-chip pads (MCL_SC and MCL_SD) for the SC and the SD line can be

used as chip-to-chip link for multi-chip applications. These pads can be activated by

setting the MCL bit in the SISC register.

Figure 93. Link between the Microcontroller Block and U505M

U505M

SCL

SDA

Multi chip link

MCL_SC

MCL_SD

V _DD

V_SS

BP40/SC

BP43/SD

Microcontroller

BP10

BP13

U505M EEPROM

The U505M is a 512-bit EEPROM internally organized as 32 × 16-bits. The program-

ming voltage as well as the write-cycle timing is generated on-chip. The U505M features

a serial interface allowing operation on a simple two-wire bus with an MCL protocol. Its

low power consumption makes it well suited for battery applications.

89

4552C–4BMCU–01/04

Figure 94. Block Diagram EEPROM

Timing control

HV-generator

V_DD

Address

EEPROM

32 x 16

control

V_SS

Mode

control

16-bit read/write buffer

8-bit data register

SCL

I/O

control

SDA

Serial Interface

The U505M has a two-wire serial interface (TWI) to the microcontroller for read and

write accesses to the EEPROM. The U505M is considered to be a slave in all these

applications. That means, the controller has to be the master that initiates the data

transfer and provides the clock for transmit and receive operations.

The serial interface is controlled by the microcontroller block which generates the serial

clock and controls the access via the SCL line and SDA line. SCL is used to clock the

data into and out of the device. SDA is a bi-directional line that is used to transfer data

into and out of the device. The following protocol is used for the data transfers.

Serial Protocol

•

Data states on the SDA line changing only while SCL is low.

Changes on the SDA line while SCL is high are interpreted as START or STOP

condition.

•

A START condition is defined as high to low transition on the SDA line while the

SCL-line is high.

A STOP condition is defined as low to high transition on the SDA line while the SCL

line is high.

Each data transfer must be initialized with a START condition and terminated with a

STOP condition. The START condition wakes the device from standby mode and the

STOP condition returns the device to standby mode.

•

A receiving device generates an acknowledge (A) after the reception of each byte.

This requires an additional clock pulse, generated by the master. If the reception

was successful the receiving master or slave device pulls down the SDA line during

that clock cycle. If an acknowledge is not detected (N) by the interface in transmit

mode, it will terminate further data transmissions and go into receive mode. A

master device must finish its read operation by a non-acknowledge and then send a

stop condition to bring the device into a known state.

90

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Figure 95. MCL Protocol

SCL

SDA

Stand Start

by condition

Data

valid

Data

Data/

changeacknowledge

valid

Stop Stand-

condition by

•

Before the START condition and after the STOP condition the device is in standby

mode and the SDA line is switched as input with pull-up resistor.

The control byte that follows the START condition determines the following

operation. It consists of the 5-bit row address, 2 mode control bits and the

READ/NWRITE bit that is used to control the direction of the following transfer. A "0"

defines a write access and a "1" a read access.

Control Byte Format

EEPROM Address

Mode

Read/

Control Bits

NWrite

Start

A4

A3

A2

A1

A0

C1

C0

R/NW

Ackn

Control byte

Ackn

Data byte

Ackn

Data byte

Ackn

Stop

EEPROM

The EEPROM has a size of 512 bits and is organized as 32 × 16-bit matrix. To read and

write data to and from the EEPROM the serial interface must be used. The interface

supports one and two byte write accesses and one to n-byte read accesses to the

EEPROM.

EEPROM – Operating Modes

The operating modes of the EEPROM are defined via the control byte. The control byte

contains the row address, the mode control bits and the read/not-write bit that is used to

control the direction of the following transfer. A "0" defines a write access and a "1" a

read access. The five address bits select one of the 32 rows of the EEPROM memory to

be accessed. For all accesses the complete 16-bit word of the selected row is loaded

into a buffer. The buffer must be read or overwritten via the serial interface. The two

mode control bits C1 and C2 define in which order the accesses to the buffer are per-

formed: High byte – low byte or low byte – high byte. The EEPROM also supports

autoincrement and autodecrement read operations. After sending the start address with

the corresponding mode, consecutive memory cells can be read row by row without

transmission of the row addresses.

Two special control bytes enable the complete initialization of EEPROM with "0" or

with "1".

91

4552C–4BMCU–01/04

Write Operations

The EEPROM permits 8-bit and 16-bit write operations. A write access starts with the

START condition followed by a write control byte and one or two data bytes from the

master. It is completed via the STOP condition from the master after the acknowledge

cycle.

The programming cycle consists of an erase cycle (write "zeros") and the write cycle

(write "ones"). Both cycles together take about 10 ms.

Acknowledge Polling

If the EEPROM is busy with an internal write cycle, all inputs are disabled and the

EEPROM will not acknowledge until the write cycle is finished. This can be used to

detect the end of the write cycle. The master must perform acknowledge polling by

sending a start condition followed by the control byte. If the device is still busy with the

write cycle, it will not return an acknowledge and the master has to generate a stop con-

dition or perform further acknowledge polling sequences. If the cycle is complete, it

returns an acknowledge and the master can proceed with the next read or write cycle.

Write One Data Byte

Write Two Data Bytes

Write Control Byte Only

Write Control Bytes

Start

Control byte

A

Data byte 1

Stop

A

Stop

Data byte 2

A

Stop

MSB

LSB

R/NW

0

Write low byte first

Byte order

A4

A3

A2

A1

A0

C1

0

C0

1

Row address

LB(R)

HB(R)

MSB

A4 A3

LSB

R/NW

0

Write high byte first

Byte order

A2

A1

A0

C1

1

C0

0

Row address

HB(R)

LB(R)

A -> acknowledge; HB -> high byte; LB -> low byte; R -> row address

Read Operations

The EEPROM allows byte-, word- and current address read operations. The read oper-

ations are initiated in the same way as write operations. Every read access is initiated by

sending the START condition followed by the control byte which contains the address

and the read mode. When the device has received a read command, it returns an

acknowledge, loads the addressed word into the read/write buffer and sends the

selected data byte to the master. The master has to acknowledge the received byte if it

wants to proceed the read operation. If two bytes are read out from the buffer the device

increments respectively decrements the word address automatically and loads the

buffer with the next word.

92

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

The read mode bits determines if the low or high byte is read first from the buffer and if

the word address is incremented or decremented for the next read access. If the mem-

ory address limit is reached, the data word address will roll over and the sequential read

will continue. The master can terminate the read operation after every byte by not

responding with an acknowledge (N) and by issuing a stop condition.

Read One Data Byte

Read Two Data Bytes

Read n Data Bytes

Start

Control byte

A

Data byte 1

N

A

Stop

Data byte 2

N

Stop

Start Control byte

A

–

Data byte n

N Stop

Read Control Bytes

MSB

A4 A3

LSB

Read low byte first,

address increment

A2

A1

A0

C1

C0

1

R/NW

1

Row address

0

Byte order

LB(R)

HB(R)

LB(R+1) HB(R+1)

- - -

LB(R+n) HB(R+n)

MSB

A4 A3

Row address

LSB

Read high byte first,

address decrement

A2

A1

A0

C1

1

C0

0

R/NW

1

Byte order

HB(R)

LB(R)

HB(R-1)

LB(R-1)

- - -

HB(R-n)

LB(R-n)

A -> acknowledge, N -> no acknowledge; HB -> high byte; LB -> low byte,

R -> row address

Initialization After a

Reset Condition

The EEPROM with the serial interface has its own reset circuitry. In systems with micro-

controllers that have their own reset circuitry for power-on reset, watchdog reset or

brown-out reset, it may be necessary to bring the U505M into a known state indepen-

dent of its internal reset. This is performed by writing:

Start

Control byte

A

Data byte 1

N Stop

to the serial interface. If the U505M acknowledges this sequence it is in a defined state.

Maybe it is necessary to perform this sequence twice.

93

4552C–4BMCU–01/04

Absolute Maximum Ratings: Microcontroller Part

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of

electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an

appropriate logic voltage level (e.g., V_DD).

Voltages are given relative to V_SS

Parameters

Symbol

V_DD

Value

-0.3 to +4.0

V_SS-0.3 ≤V_IN≤V_DD+0.3

Indefinite

Unit

V

Supply voltage

Input voltage (on any pin)

Output short circuit duration

Operating temperature range

Storage temperature range

Soldering temperature (t ≤10 s)

V_IN

V

t_short

T_amb

T_stg

s

-40 to +125

-40 to +130

260

°C

T_sld

Thermal Resistance

Parameter

Symbol

Value

Unit

Thermal resistance

R_thJA

135

K/W

DC Operating Characteristics

V_SS= 0 V, T_amb= -40° C to +125° C unless otherwise specified.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Power Supply

Operating voltage at V_DD

V_DD

I_DD

V_POR

4.0

V

f

_SYSCL= 1 MHz

V_DD= 1.8 V

_DD= 3.0 V

Active current

CPU active

200

300

µA

V

450

Power down current (CPU sleep,

RC oscillator active,

4-MHz quartz oscillator active)

f_SYSCL= 1 MHz

V_DD= 1.8 V

V_DD= 3.0 V

I_PD

40

70

µA

180

2.3

Sleep current (CPU sleep,

32-kHz quartz oscillator active

4-MHz quartz oscillator inactive)

V_DD= 1.8 V

0.4

0.6

µA

I_Sleep

V_DD= 3.0 V

Sleep current (CPU sleep,

32-kHz quartz oscillator inactive

4-MHz quartz oscillator inactive)

V

_DD= 1.8 V

_DD= 3.0 V

0.1

0.3

µA

I_Sleep

C_L

1.5

10

Pin capacitance

Any pin to V_SS

7

pF

94

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

DC Operating Characteristics (Continued)

V_SS= 0 V, T_amb= -40° C to +125° C unless otherwise specified.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Power-on Reset Threshold Voltage

POR threshold voltage

POR hysteresis

BOT = 1

BOT = 0

V_POR

1.6

1.7

2.0

50

1.8

V

1.85

2.15

mV

Voltage Monitor Threshold Voltage

VM high threshold voltage

VM middle threshold voltage

VM low threshold voltage

External Input Voltage

VMI

V_DD> VM, VMS = 1

V_MThh

V_MThm

V_MThl

3.0

2.6

2.2

3.25

2.8

V

V_DD< VM, VMS = 0

V_DD> VM, VMS = 1

V_DD< VM, VMS = 0

V_DD> VM, VMS = 1

V_DD< VM, VMS = 0

2.75

2.36

1.97

2.4

V_MThl

V_DD= 3 V, VMS = 1

_DD= 3 V, VMS = 0

V_VMI

1.3

1.4

V

VMI

V

1.2

All Bi-directional Ports

0.2 ×

V_DD

Input voltage LOW

Input voltage HIGH

V_DD= 1.8 to 6.5 V

V_IL

V_IH

I_IL

V_SS

V

0.8 ×

V_DD

V

_DD= 1.8 to 6.5 V

_DD= 2.0 V,

V_DD

Input LOW current

(switched pull-up)

V

-1.4

-7

-4

-20

-12

-40

µA

V_DD= 3.0 V, V_IL= V_SS

Input HIGH current

(switched pull-down)

V

_DD= 2.0 V,

1.4

7

4

20

12

40

µA

I_IH

I_IL

V_DD= 3.0 V, V_IH= V_DD

Input LOW current

(static pull-up)

V_DD= 2.0 V

-14

-60

-50

-160

-100

-320

µA

V_DD= 3.0 V, V_IL= V_SS

Input LOW current

(static pull-down)

V

_DD= 2.0 V

14

60

50

160

100

320

µA

I_IH

V_DD= 3.0 V, V_IH= V_DD

Input leakage current

V_IL= V_SS

I_IL

100

nA

V_IH= V_DD

I_IH

V_OL= 0.2 × V_DD

V_DD= 2.0 V

V_DD= 3.0 V

Output LOW current

Output HIGH current

I_OL

0.5

2

1.2

5

2.5

8

mA

V

_OH= 0.8 × V_DD

V_DD= 2.0 V

_DD= 3.0 V

I_OH

-0.5

-2

-1.2

-5

-2.5

-8

mA

V

Note:

The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller.

95

4552C–4BMCU–01/04

AC Characteristics

Supply Voltage V_DD= 1.8 V to 4.0 V, V_SS= 0 V, T_amb= 25° C unless otherwise specified.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Operation Cycle Time

V

_DD= 1.8 V to 4.0 V

t_SYSCL

500

250

4000

ns

T_amb= -40°C to +125°C

System clock cycle

V_DD= 2.4 V to 4.0 V

T_amb= -40°C to +125°C

Timer 2 input Timing Pin T2I

Timer 2 input clock

f_T2I

t_T2IL

t_T2IH

5

MHz

ns

Timer 2 input LOW time

Timer 2 input HIGH time

Timer 3 Input Timing Pin T3I

Timer 3 input clock

Rise/fall time < 10 ns

100

ns

f_T3I

t_T3IL

t_T3IH

SYSCL/2

MHz

ns

Timer 3 input LOW time

Timer 3 input HIGH time

Interrupt Request Input Timing

Interrupt request LOW time

Interrupt request HIGH time

External System Clock

EXSCL at OSC1, ECM = EN

EXSCL at OSC1, ECM = DI

Input HIGH time

Rise/fall time < 10 ns

2 t_SYSCL

ns

Rise/fall time < 10 ns

t_IRL

t_IRH

100

ns

Rise/fall time < 10 ns

f_EXSCL

t_IH

0.5

0.02

0.1

4

MHz

µs

Reset Timing

Power-on reset time

V_DD> V_POR

t_POR

1.5

3.8

5

ms

RC Oscillator 1

Frequency

f_RcOut1

MHz

%

V_DD= 2.0 V to 4.0 V

Stability

∆f/f

±50

T_amb= -40°C to +105°C

RC Oscillator 2 – External Resistor

Frequency

R_ext= 170 kΩ

f_RcOut2

∆f/f

4

MHz

%

V_DD= 2.0 V to 4.0 V

Stability

±15

10

T_amb= -40°C to +105°C

Stabilization time

t_S

µs

4-MHz Crystal Oscillator (Operating Range V_DD= 2.2 V to 4.0 V)

Frequency

f_X

4

5

MHz

ms

Start-up time

t_SQ

∆f/f

Stability

-10

10

ppm

Integrated input/output capacitances C_IN/C_OUTprogrammable in steps of

C_IN

C_OUT

0

20

pF

(mask programmable)

2 pF

96

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

AC Characteristics (Continued)

Supply Voltage V_DD= 1.8 V to 4.0 V, V_SS= 0 V, T_amb= 25° C unless otherwise specified.

Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

32-kHz Crystal Oscillator (Operating Range V_DD= 2.0 V to 4.0 V)

Frequency

f_X

32.768

0.5

kHz

s

Start-up time

t_SQ

∆f/f

Stability

-10

10

ppm

Integrated input/output capacitances C_IN/C_OUTprogrammable in steps of

C_IN

C_OUT

0

20

pF

(mask programmable)

External 32-kHz Crystal Parameters

Crystal frequency

2 pF

f_X

32.768

30

kHz

kΩ

pF

fF

Serial resistance

RS

C0

C1

50

Static capacitance

1.5

3

Dynamic capacitance

External 4-MHz Crystal Parameters

Crystal frequency

f_X

4.0

40

1.4

3

MHz

W

Serial resistance

RS

C0

C1

150

3

Static capacitance

pF

fF

Dynamic capacitance

EEPROM

Operating current during erase/write

cycle

I_WR

600

1300

12

µA

500000

50000

1000000

100000

Erase-/write cycles

For 16-bit access

E_D

Cycles

Endurance

T

_amb= 105°C

Data erase/write cycle time

Data retention time

t_DEW

9

ms

t_DR

100

1

Years

T_amb= 105°C

Power-up to read operation

Power-up to write operation

Serial Interface

t_PUR

0.2

ms

t_PUW

SCL clock frequency

f_{SC_MCL}

100

500

kHz

Crystal

Figure 96. Crystal Equivalent Circuit

Characteristics

C1

L

RS

Equivalent

circuit

OSCIN

SCLIN

OSCOUT

SCLOUT

C0

97

4552C–4BMCU–01/04

Emulation

The basic function of emulation is to test and evaluate the customer's program and

hardware in real time. This therefore enables the analysis of any timing, hardware or

software problem. For emulation purposes, all MARC4 controllers include a special

emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are

available via Port 0 and Port 1 to allow an external access to the on-chip peripherals.

The MARC4 emulator uses this mode to control the peripherals of any MARC4

controller (target chip) and emulates the lost ports for the application.

The MARC4 emulator can stop and restart a program at specified points during execu-

tion, making it possible for the applications engineer to view the memory contents and

those of various registers during program execution. The designer also gains the ability

to analyze the executed instruction sequences and all the I/O activities.

Figure 97. MARC4 Emulation

Emulator target board

MARC4 emulator

MARC4

emulation-CPU

Program

memory

MARC4 target chip

I/O bus

CORE

Trace

(inactive)

memory

I/O control

Peripherals

Emulation control

Port 0

Port 1

Control

logic

SYSCL/

TCL,

TE, NRST

Application-specific hardware

Personal computer

98

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Option Settings for Ordering

Please select the option settings from the list below and insert ROM CRC.

Output

Input

Output

Input

Port 1

Port 5

BP10 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

BP50 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

BP13 [

]

CMOS

BP51 [

]

CMOS

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

Port 2

BP52 [

]

CMOS

BP20 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

BP53 [

]

CMOS

BP21 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

Port 6

BP22 [

]

CMOS

BP60 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

BP23 [

]

CMOS

BP63 [

]

CMOS

[

Open drain [N]

Open drain [P]

[

Open drain [N]

Open drain [P]

Static pull-down

Port 4

BP40 [

]

CMOS

[

]

Switched pull-up

Switched pull-down

Static pull-up

OSC1

OSC2

[

Open drain [N]

Open drain [P]

[

]

No integrated capacitance

Internal capacitance (0 to 20 pF) [ _____pF]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

BP41 [

]

CMOS

[

]

No integrated capacitance

[

Open drain [N]

Open drain [P]

Internal capacitance (0 to 20 pF) [ _____pF]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

Clock Used

BP42 [

]

CMOS

[

]

External resistor

External clock

32-kHz crystal

4-MHz crystal

[

Open drain [N]

Open drain [P]

Static pull-down

Switched pull-up

Switched pull-down

Static pull-up

BP43 [

]

CMOS

[

Open drain [N]

Open drain [P]

ECM (External Clock Monitor)

[

]

Enable

Disable

Static pull-down

Please attach this page to the approval form.

Date: ____________

Signature: _________________________Company: _________________________

99

4552C–4BMCU–01/04

Ordering Information

Extended Type Number⁽¹⁾

ATAR862x-yyy-TNQzf

ATAR862x-yyy-TNSzf

Program Memory

4 kB ROM

Data-EEPROM

512 bit

Package

SSO24

Delivery

Taped and reeled

Tubes

4 kB ROM

512 bit

Note:

1. x = Hardware revision

yyy = Customer specific ROM-version

z

= Operating temperature range

= -- (-40°C to +85°C)

= C (-40° C to +105° C)

= D (-40° C to +125° C)

= RF frequency range

= 3 (315 MHz)

f

= 4 (433 MHz)

= 8 (868 MHz/915 MHz)

Package Information

5.7

5.3

Package SSO24

Dimensions in mm

8.05

7.80

4.5

4.3

1.30

0.15

0.05

0.25

0.65

6.6

6.3

7.15

24

13

technical drawings

according to DIN

specifications

1

12

100

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Table of Contents

Features................................................................................................. 1

Description............................................................................................ 1

Pin Configuration.................................................................................. 2

Pin Description: RF Part ...................................................................... 2

Pin Description: Microcontroller Part................................................. 3

UHF ASK/FSK Transmitter Block........................................................ 4

Features................................................................................................. 4

Description............................................................................................ 4

General Description.............................................................................. 6

Functional Description......................................................................... 6

ASK Transmission ................................................................................................ 6

FSK Transmission ................................................................................................ 6

CLK Output........................................................................................................... 7

Clock Pulse Take Over ...................................................................................7

Output Matching and Power Setting ...............................................................7

Application Circuit................................................................................................. 8

Absolute Maximum Ratings: RF Part................................................ 11

Thermal Resistance............................................................................ 11

Electrical Characteristics................................................................... 11

Microcontroller Block......................................................................... 13

Features............................................................................................... 13

Description.......................................................................................... 13

Introduction......................................................................................... 14

MARC4 Architecture General Description........................................ 14

Components of MARC4 Core ............................................................ 14

ROM ................................................................................................................... 15

RAM.................................................................................................................... 15

Expression Stack ..........................................................................................15

101

4552C–4BMCU–01/04

Return Stack .................................................................................................15

Registers............................................................................................................. 16

Program Counter (PC) ..................................................................................16

RAM Address Registers ................................................................................17

Expression Stack Pointer (SP) ......................................................................17

Return Stack Pointer (RP) ............................................................................17

RAM Address Registers (X and Y) ...............................................................17

Top of Stack (TOS) .......................................................................................17

Condition Code Register (CCR) ....................................................................17

Carry/Borrow (C) ...........................................................................................17

Branch (B) .....................................................................................................17

Interrupt Enable (I) ........................................................................................17

ALU..................................................................................................................... 18

I/O Bus................................................................................................................ 18

Instruction Set..................................................................................................... 18

Interrupt Structure............................................................................................... 18

Interrupt Processing ......................................................................................19

Interrupt Latency ...........................................................................................19

Software Interrupts ............................................................................................. 20

Hardware Interrupts............................................................................................ 20

Master Reset ....................................................................................... 21

Power-on Reset and Brown-out Detection ......................................................... 21

Watchdog Reset ...........................................................................................22

External Clock Supervisor .............................................................................22

Voltage Monitor................................................................................... 22

Voltage Monitor Control/ Status Register ......................................................23

Clock Generation................................................................................ 24

Clock Module...................................................................................................... 24

Oscillator Circuits and External Clock Input Stage ............................................. 25

RC-oscillator 1 Fully Integrated .....................................................................25

External Input Clock ......................................................................................26

RC-oscillator 2 with External Trimming Resistor ...........................................26

4-MHz Oscillator ...........................................................................................27

32-kHz Oscillator ...........................................................................................27

Clock Management............................................................................................. 28

Clock Management Register (CM) ................................................................28

System Configuration Register (SC) .............................................................29

Power-down Modes............................................................................ 29

Peripheral Modules............................................................................. 30

Addressing Peripherals....................................................................................... 30

102

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Bi-directional Ports............................................................................. 33

Bi-directional Port 1 ............................................................................................ 33

Bi-directional Port 2 ............................................................................................ 34

Port 2 Data Register (P2DAT) ......................................................................35

Port 2 Control Register (P2CR) ....................................................................35

Bi-directional Port 5 ............................................................................................ 35

Port 5 Data Register (P5DAT) ......................................................................36

Port 5 Control Register (P5CR) Byte Write ...................................................36

Bi-directional Port 4 ............................................................................................ 37

Port 4 Data Register (P4DAT) ......................................................................38

Port 4 Control Register (P4CR) Byte Write ...................................................38

Bi-directional Port 6 ............................................................................................ 38

Port 6 Data Register (P6DAT) ......................................................................39

Port 6 Control Register (P6CR) ....................................................................39

Universal Timer/Counter/ Communication Module (UTCM) ............................... 39

Timer 1................................................................................................................ 40

Timer 1 Control Register 1 (T1C1) ................................................................42

Timer 1 Control Register 2 (T1C2) ................................................................43

Watchdog Control Register (WDC) ...............................................................43

Timer 2................................................................................................................ 44

Timer 2 Modes.................................................................................................... 45

Mode 1: 12-bit Compare Counter .................................................................45

Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler ...........45

Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler .........46

Timer 2 Output Modes........................................................................................ 46

Timer 2 Output Signals....................................................................................... 47

Timer 2 Output Mode 1 .................................................................................47

Timer 2 Output Mode 2 .................................................................................48

Timer 2 Output Mode 3 .................................................................................48

Timer 2 Output Mode 4 .................................................................................49

Timer 2 Output Mode 5 .................................................................................49

Timer 2 Output Mode 7 .................................................................................49

Timer 2 Registers ............................................................................................... 50

Timer 2 Control Register (T2C) .....................................................................50

Timer 2 Mode Register 1 (T2M1) ..................................................................50

Duty Cycle Generator ...................................................................................51

Timer 2 Mode Register 2 (T2M2) ..................................................................52

Timer 2 Compare and Compare Mode Registers .........................................52

Timer 2 Compare Mode Register (T2CM) ....................................................53

Timer 2 COmpare Register 1 (T2CO1) .........................................................53

Timer 2 COmpare Register 2 (T2CO2) Byte Write .......................................53

Timer 3................................................................................................. 54

Features ........................................................................................................54

Timer/Counter Modes......................................................................................... 55

Timer 3 – Mode 1: Timer/Counter .................................................................56

103

4552C–4BMCU–01/04

Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External

Capture (with T3I Input) ...............................................57

Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal

Capture (with TOG2) ...................................................58

Timer 3 – Mode 4: Timer/Counter .................................................................58

Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External

Capture (with T3I Input) ...............................................58

Timer 3 Modulator/Demodulator Modes ............................................................. 58

Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by

Timer 2 Output Toggle Flip-Flop (M2) .........................58

Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by

SSI Internal Output (SO) .............................................59

Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO) ...............59

Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register ...............59

Timer 3 – Mode 10: Manchester Demodulation/ Pulse-width Demodulation 60

Timer 3 – Mode 11: Biphase Demodulation ..................................................60

Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I) .........61

Timer 3 Modulator for Carrier Frequency Burst Modulation ............................... 61

Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated

Signals................................................................................................. 61

Timer 3 Registers ............................................................................................... 62

Timer 3 Mode Register (T3M) .......................................................................62

Timer 3 Control Register 1 (T3C) Write ........................................................63

Timer 3 Status Register 1 (T3ST) Read .......................................................63

Timer 3 Clock Select Register (T3CS) ..........................................................64

Timer 3 Compare- and Compare-mode Register .........................................64

Timer 3 Compare-Mode Register 1 (T3CM1) ...............................................65

Timer 3 Compare Mode Register 2 (T3CM2) ...............................................65

Timer 3 COmpare Register 1 (T3CO1) Byte Write .......................................66

Timer 3 COmpare Register 2 (T3CO2) Byte Write .......................................66

Timer 3 Capture Register ................................................................................... 66

Timer 3 CaPture Register (T3CP) Byte Read ...............................................66

Synchronous Serial Interface (SSI) .................................................................... 67

SSI Peripheral Configuration ........................................................................67

General SSI Operation ..................................................................................68

8-bit Synchronous Mode ...............................................................................69

9-bit Shift Mode (MCL) ..................................................................................71

8-bit Pseudo MCL Mode ...............................................................................72

MCL Bus Protocol .........................................................................................72

SSI Interrupt ..................................................................................................74

Modulation and Demodulation ......................................................................74

Internal 2-wire Multi-chip Link .......................................................................74

Serial Interface Registers ................................................................................... 75

Serial Interface Control Register 1 (SIC1) ....................................................75

Serial Interface Control Register 2 (SIC2) ....................................................76

Serial Interface Status and Control Register (SISC) .....................................77

Serial Transmit Buffer (STB) – Byte Write ....................................................77

104

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

ATAR862-4 [Preliminary]

Serial Receive Buffer (SRB) – Byte Read .....................................................78

Combination Modes ........................................................................... 78

Combination Mode Timer 2 and SSI................................................................... 78

Combination Mode 1: Burst Modulation ........................................................79

Combination Mode 2: Biphase Modulation 1 ................................................79

Combination Mode 3: Manchester Modulation 1 ..........................................80

Combination Mode 4: Manchester Modulation 2 ..........................................80

Combination Mode 5: Biphase Modulation 2 ................................................81

Combination Mode Timer 3 and SSI................................................................... 82

Combination Mode 6: FSK Modulation .........................................................82

Combination Mode 7: Pulse-width Modulation (PWM) .................................83

Combination Mode 8: Manchester Demodulation/

Pulse-width Demodulation ......................................83

Combination Mode 9: Biphase Demodulation ...............................................84

Combination Mode Timer 2 and Timer 3 ............................................................ 85

Combination Mode 10: Frequency Measurement or Event Counter with

Time Gate .............................................................85

Combination Mode 11: Burst Modulation 1 ...................................................86

Combination Mode Timer 2, Timer 3 and SSI .................................................... 87

Combination Mode 12: Burst Modulation 2 ...................................................88

Combination Mode 13: FSK Modulation .......................................................88

Microcontroller Block......................................................................... 89

Internal 2-wire Multi-chip Link .......................................................................89

U505M EEPROM................................................................................................ 89

Serial Interface.................................................................................................... 90

Serial Protocol ...............................................................................................90

Control Byte Format ......................................................................................91

EEPROM ............................................................................................................ 91

EEPROM – Operating Modes .......................................................................91

Write Operations ...........................................................................................92

Acknowledge Polling .....................................................................................92

Write One Data Byte .....................................................................................92

Write Two Data Bytes ...................................................................................92

Write Control Byte Only ................................................................................92

Write Control Bytes .......................................................................................92

Read Operations ...........................................................................................92

Read One Data Byte .....................................................................................93

Read Two Data Bytes ...................................................................................93

Read n Data Bytes ........................................................................................93

Read Control Bytes .......................................................................................93

Initialization After a Reset Condition................................................................... 93

Absolute Maximum Ratings: Microcontroller Part .......................... 94

105

4552C–4BMCU–01/04

Thermal Resistance............................................................................ 94

DC Operating Characteristics............................................................ 94

AC Characteristics.............................................................................. 96

Crystal Characteristics....................................................................... 97

Emulation............................................................................................................ 98

Option Settings for Ordering............................................................. 99

Ordering Information........................................................................ 100

Package Information ....................................................................... 100

Table of Contents ............................................................................. 101

106

ATAR862-4 [Preliminary]

4552C–4BMCU–01/04

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

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Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

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Biometrics/Imaging/Hi-Rel MPU/

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Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

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38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

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Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

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Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Atmel^®and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4552C–4BMCU–01/04


型号：	ATAR862X-YYY-TNQD4
厂家：	ATMEL
描述：	Microcontroller, 4-Bit, MROM, 4MHz, CMOS, PDSO24, SSOP-24 微控制器光电二极管
文件：	总107页 (文件大小：1292K)
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ATAR862X-YYY-TNQD4 [ATMEL]

相关型号：

ATAR862X-YYY-TNQY3

ATAR862X-YYY-TNQYF

ATAR862X-YYY-TNQYJ3

ATAR862X-YYY-TNSD4

ATAR862X-YYY-TNSYJ3

ATAR890

ATAR890-C

ATAR890-XXX-TKQ

ATAR890-XXX-TKQY

ATAR890-XXX-TKQYC

ATAR890-XXX-TKS

ATAR890-XXX-TKSY