ATF1508AS-10QU100 [ATMEL]
Highperformance EE PLD; 高性能EE PLD
| 型号： | ATF1508AS-10QU100 |
| 厂家： | 
ATMEL |
| 描述： | Highperformance EE PLD |
| 文件： | 总31页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
• Flexible Logic Macrocell
– D/T/Latch Configured Flip-flops
High-
performance
EE PLD
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
• Advanced Power Management Features
– Automatic 10 µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages
• Advanced EE Technology
ATF1508AS
ATF1508ASL
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• 3.3 or 5.0V I/O Pins
• Security Fuse Feature
• Green (Pb/Halide-free/RoHS Compliant) Package Options
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent-latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 0784P–PLD–7/05
100-lead PQFP
Top View
84-lead PLCC
Top View
I/O
I/O
1
2
3
4
5
6
7
8
9
80 I/O
79 I/O
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 I/O
73 I/O
72 I/O
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 I/O
56 I/O
55 I/O
54 I/O
53 VCCIO
52 I/O
51 I/O
I/O/PD1 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
73 I/O
I/O/PD1
I/O
72 GND
71 I/O/TDO
70 I/O
VCCIO
I/O/TDI
I/O
I/O 16
I/O 17
69 I/O
I/O 18
68 I/O
I/O
GND 19
I/O 20
67 I/O
I/O
66 VCCIO
65 I/O
I/O 10
I/O 11
I/O 21
I/O 12
I/O 22
64 I/O
GND 13
I/O 14
I/O/TMS 23
I/O 24
63 I/O
62 I/O/TCK
61 I/O
I/O 15
I/O 25
I/O 16
VCCIO 26
I/O 27
60 I/O
I/O/TMS 17
I/O 18
59 GND
58 I/O
I/O 28
I/O 19
I/O 29
57 I/O
VCCIO 20
I/O 21
I/O 30
56 I/O
I/O 22
I/O 31
55 I/O
I/O 23
GND 32
54 I/O
I/O 24
I/O 25
I/O 26
I/O 27
GND 28
I/O 29
I/O 30
160-lead PQFP
Top View
100-lead TQFP
Top View
N/C
N/C
1
2
3
4
5
6
7
8
9
120 N/C
119 N/C
118 N/C
117 N/C
116 N/C
115 N/C
114 N/C
113 GND
112 I/O/TDO
111 I/O
110 I/O
109 I/O
108 I/O
107 I/O
106 I/O
105 I/O
104 VCCIO
103 I/O
102 I/O
101 I/O
100 I/O
99 I/O/TCK
98 I/O
N/C
N/C
N/C
I/O/PD1
1
2
3
4
5
6
7
8
9
75 I/O
N/C
I/O
VCCIO
I/O/TDI
I/O
74 GND
73 I/O/TDO
72 I/O
N/C
VCCIO
I/O/TDI
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
GND 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O/TMS 22
I/O 23
I/O 24
I/O 25
VCCIO 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
N/C 34
N/C 35
N/C 36
N/C 37
N/C 38
N/C 39
N/C 40
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
64 I/O
I/O 13
63 I/O
I/O 14
62 I/O/TCK
61 I/O
97 I/O
I/O/TMS 15
I/O 16
96 I/O
60 I/O
95 GND
94 I/O
I/O 17
59 GND
58 I/O
93 I/O
VCCIO 18
I/O 19
92 I/O
57 I/O
91 I/O
I/O 20
56 I/O
90 I/O
89 I/O
I/O 21
55 I/O
88 I/O
I/O 22
54 I/O
87 N/C
86 N/C
85 N/C
84 N/C
83 N/C
82 N/C
81 N/C
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
2
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Block Diagram
8 to 12
16
3
0784P–PLD–7/05
Description
The ATF1508AS is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells
and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and
increase odds of successful pin-locked design modifications.
The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending
on the type of device package selected. Each dedicated pin can also serve as a global control
signal, register clock, register reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each
input and I/O pin also feeds into the global bus. The switch matrix in each logic block then
selects 40 individual signals from the global bus. Each macrocell also generates a foldback
logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS
allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight
such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product
terms.
The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is accessible regardless of the state
of the security fuse.
The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-
dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-
scan Description Language (BSDL). ISP allows the device to be programmed without remov-
ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also
allows design modifications to be made in the field via software.
Product Terms and
Select Mux
Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with a little small additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
4
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Flip-flop
The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The
flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock,
one of the macrocell product terms can be selected as a clock enable. When the clock enable
function is active and the enable signal (product term) is low, all clock edges are ignored. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
I/O Control
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The 16 foldback terms in each region allows generation of high fan-in sum
terms (up to 21 product terms) with a little additional delay.
3.3V or 5.0V I/O
Operation
The ATF1508AS device has two sets of VCC pins viz, VCCINT and VCCIO. VCCINT pins must
always be connected to a 5.0V power supply. VCCINT pins are for input buffers and are “com-
patible” with both 3.3V and 5.0V inputs. VCCIO pins are for I/O output drives and can be
connected for 3.3/5.0V power supply.
Open-collector
Output Option
This option enables the device output to provide control signals such as an interrupt that can
be asserted by any of the several devices.
5
0784P–PLD–7/05
Figure 1. ATF1508AS Macrocell
Programmable
Pin-keeper
Option for
The ATF1508AS offers the option of programming all input and I/O pins so that “pin-keeper”
circuits can be utilized. When any pin is driven high or low and then subsequently left floating,
it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Inputs and I/Os
Input Diagram
6
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Speed/Power
Management
The ATF1508AS has several built-in speed and power management features. The
ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power-savings for most applications
running at system speeds below 5 MHz.
To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
I/O Diagram
All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10
mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to
power down the part. The power-down option is selected in the design source file. When
enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down
mode, all internal logic signals are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s
macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins,
with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power
bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which
include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching, and may be specified as fast switching in the design file.
7
0784P–PLD–7/05
Design
Software
Support
ATF1508AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high level description languages and formats.
Power-up Reset
The ATF1508AS is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and
the state of each output will depend on the polarity of its buffer. However, due to the asynchro-
nous nature of reset and uncertainty of how VCC actually rises in the system, the following
conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF1508AS has two options for the hysteresis about the reset level, VRST, Small and
Large. During the fitting process users may configure the device with the Power-up Reset hys-
teresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred microamps as
well.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns.
Once programmed, fuse verify is inhibited. However, User Signature and device ID remains
accessible.
Programming
ATF1508AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-
tocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the
PC. ISP is performed by using either a download cable or a comparable board tester or a sim-
ple microprocessor interface.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP Software. Conversion to other ATE
tester format beside SVF is also possible
ATF1508AS devices can also be programmed using standard third-party programmers. With
third-party programmer, the JTAG ISP port can be disabled thereby allowing four additional
I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
8
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ISP
The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O
default to high-Z state during such a condition. In addition the pin-keeper option preserves the
former state during device programming.
Programming
Protection
All ATF1508AS devices are initially shipped in the erased state thereby making them ready to
use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
JTAG-BST
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508AS. The boundary-scan technique involves the inclusion of a shift-register stage
(contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The
ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP con-
troller is automatically reset at power-up. The six JTAG BST modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508AS is imple-
mented using the Boundary-scan Definition Language (BSDL) described in the JTAG
specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can
be used to perform BST on the ATF1508AS.
The ATF1508AS also has the option of using four JTAG-standard I/O pins for In-System pro-
gramming (ISP). The ATF1508AS is programmable through the four JTAG pins using
programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
JTAG
The ATF1508AS contains up to 96 I/O pins and four input pins, depending on the device type
and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)
in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A
typical BSC consists of three capture registers or scan registers and up to two update regis-
ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the (BST) capture registers. Input to the cap-
ture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by
the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are
shown below.
Boundary-scan
Cell (BSC)
Testing
9
0784P–PLD–7/05
BSC
Configuration
Pins and
Macrocells
(Except JTAG
TAP Pins)
Note:
The ATF1508AS has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
BSC
Configuration
for Macrocell
TDO
OEJ
0
1
0
D Q
D Q
1
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
Boundary Scan
Definition
Language
These are now available in all package types via the Atmel Web Site. These models can be
used for Boundary-scan Test Operation in the ATF1508AS and have been scheduled to con-
form to the IEEE 1149.1 standard.
(BSDL) Models
for the ATF1508
10
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
PCI Compliance
The ATF1508AS also supports the growing need in the industry to support the new Peripheral
Component Interconnect (PCI) interface standard in PCI-based designs and specifications.
The PCI interface calls for high current drivers, which are much larger than the traditional TTL
drivers.
PCI Voltage-to-
current Curves
for +5V
Pull Up
VCC
Test Point
Signaling in
Pull-up Mode
2.4
DC
drive point
1.4
AC drive
point
Current (mA)
-44
-178
-2
PCI Voltage-to-
current Curves
for +5V
Signaling in
Pull-down Mode
Pull Down
VCC
2.2
AC drive
point
DC
drive point
0.55
Test Point
Current (mA)
95
380
3,6
11
0784P–PLD–7/05
PCI DC Characteristics
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
5.25
Units
V
Supply Voltage
Input High Voltage
VCC + 0.5
0.8
V
VIL
Input Low Voltage
-0.5
V
IIH
Input High Leakage Current(1)
Input Low Leakage Current(1)
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
VIN = 2.7V
VIN = 0.5V
70
µA
µA
V
IIL
-70
VOH
VOL
IOUT = -2 mA
2.4
IOUT = 3 mA, 6 mA
0.55
10
12
8
V
CIN
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
1. Leakage current is without pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
mA
mA
mA
µA
IOH(AC)
Switching
0 < VOUT ≤ 1.4
-44
Current High
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
VOUT = 3.1V
-44+(VOUT - 1.4)/0.024
Equation A(1)
-142
(Test High)
Switching
IOL(AC)
VOUT > 2.2V
95
mA
mA
mA
mA
mA
V/ns
V/ns
Current Low
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT = 0.71
VOUT/0.023
Equation B(2)
206
(Test Point)
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
SLEWR
SLEWF
0.4V to 2.4V load
2.4V to 0.4V load
0.5
0.5
3.0
3.0
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
12
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Power-down
Mode
The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high,
the device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched and held. Therefore, all registered and combinatorial out-
put data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-
Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O
hold latches remain active to ensure that pins do not float to indeterminate levels, further
reducing system power. The power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD pin logic array input. However, bur-
ied logic resources in this macrocell may still be used.
Power-down AC Characteristics(1)(2)
-7
-10
-15
-20
-25
Symbol
tIVDH
Parameter
Min Max Min Max Min Max Min Max Min Max Units
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
7
7
7
10
10
10
15
15
15
20
20
20
25
25
25
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
tGVDH
tCVDH
tDHIX
12
12
12
1
15
15
15
1
25
25
25
1
30
30
30
1
35
35
35
1
tDHGX
tDHCX
tDLIV
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
13
0784P–PLD–7/05
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V ± 5%
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Ambient)
VCCINT or VCCIO (5V) Power Supply
VCCIO (3.3V) Power Supply
2.7V - 3.6V
2.7V - 3.6V
DC Characteristics(1)
Symbol Parameter
Condition
Min
Typ
Max
Units
IIL
Input or I/O Low
Leakage Current
VIN = VCC
-2
-10
µA
IIH
Input or I/O High
Leakage Current
2
10
40
µA
µA
IOZ
ICC1
Tri-state Output
Off-state Current
VO = VCC or GND
-40
Power Supply
Current, Standby
VCC = Max
Std Mode
Com.
Ind.
160
180
10
10
mA
mA
µA
VIN = 0, VCC
“L” Mode
Com.
Ind.
µA
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
Std Mode
1
10
mA
(2)
ICC3
VCC = Max
VIN = 0, VCC
Com.
Ind.
65
85
mA
mA
V
Reduced-power Mode
Supply Current
VCCIO
5.0V Device Output
Com.
Ind.
4.75
4.5
5.25
5.5
Supply Voltage
V
VCCIO
VIL
Supply Voltage
3.3V Device Output
3.0
3.6
V
Input Low Voltage
Input High Voltage
-0.3
2.0
0.8
V
VIH
VCCIO + 0.3
0.45
0.45
V
VOL
VIN = VIH or VIL
VCCIO = MIN, IOL = 12 mA
Com.
Ind.
V
Output Low Voltage (TTL)
V
VIN = VIH or VIL
VCC = MIN, IOL = 0.1 mA
Com.
Ind.
0.2
V
Output Low Voltage (CMOS)
Output High Voltage (TTL)
0.2
V
VOH
VIN = VIH or VIL
VCCIO = MIN, IOH = -4.0 mA
2.4
V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
14
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
Pin Capacitance(1)
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
10
pF
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Timing Model
U
Input Test Waveforms and Measurement Levels
rR, tF = 1.5 ns typical
Output AC Test Loads
(3.0V)*
(703 )*
(8060 )*
Note:
*Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
15
0784P–PLD–7/05
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
200.0
150.0
100.0
50.0
250.0
200.0
150.0
100.0
50.0
STANDARD POWER
STANDARD POWER
REDUCED POWER MODE
REDUCED POWER MODE
0.0
0.00
5.00
10.00
FREQUENCY (MHz)
15.00
20.00
4.50
4.75
5.00
CC (V)
5.25
5.50
V
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW-POWER ("L") VERSION
(TA = 25°C, F = 0)
0
-10
-20
-30
-40
-50
-60
30.0
20.0
10.0
0.0
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
VCC (V)
5.25
5.50
SUPPLY VOLTAGE (V)
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER
0
-20
(TA = 25°C, F = 0)
300.0
250.0
200.0
150.0
100.0
50.0
-40
-60
STANDARD POWER
-80
-100
-120
-140
-160
REDUCED POWER MODE
0.0
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.00
20.00
40.00
FREQUENCY (MHz)
60.00
80.00
100.00
INPUT VOLTAGE (V)
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
43
42
41
40
39
38
37
36
1100.0
1000.0
900.0
800.0
700.0
STANDARD POWER
REDUCED POWER MODE
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
VCC (V)
5.25
5.50
SUPPLY VOLTAGE (V)
16
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
OUTPUT SOURCE CURRENT
NORMALIZED TCO
VS. SUPPLY VOLTAGE (TA = 25°C)
VS. SUPPLY VOLTAGE (VCC = 5V, TA = 25°C)
1.20
1.10
1.00
0.90
0.80
-10
-30
-50
-70
-90
-110
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
4.5
4.5
5.0
5.0
5.0
4.50
4.75
5.00
5.25
5.50
5.50
75
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT CURRENT
NORMALIZED TSU
VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C)
VS. SUPPLY VOLTAGE (TA = 25°C)
40
30
20
10
0
1.20
1.10
1.00
0.90
0.80
-10
-20
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.50
4.75
5.00
5.25
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
NORMALIZED TPD
VS. TEMPERATURE (VCC = 5.0V)
140
120
100
80
1.20
1.10
1.00
0.90
0.80
60
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-40
0
25
OUTPUT VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO
VS. TEMPERATURE (VCC = 5.0V)
NORMALIZED TPD
VS. SUPPLY VOLTAGE (TA = 25°C)
1.20
1.10
1.00
0.90
0.80
1.20
1.10
1.00
0.90
0.80
-40
0
25
75
4.50
4.75
5.00
5.25
5.50
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
17
0784P–PLD–7/05
NORMALIZED TSU
VS. TEMPERATURE (VCC = 5.0V)
1.20
1.10
1.00
0.90
0.80
-40
0
25
75
TEMPERATURE (C)
18
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
AC Characteristics (1)
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
tPD1
Input or Feedback to
Non-registered Output
7.5
10
3
15
20
25
ns
tPD2
I/O Input or Feedback to
Non-registered Feedback
7
9
3
12
16
20
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
6
0
3
7
0
3
11
0
16
0
20
0
ns
ns
ns
tFSU
Global Clock Setup Time of
Fast Input
3
3
3
tFH
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
2
MHz
tCOP
tCH
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
4.5
7.5
5
8
10
20
13
25
ns
ns
3
3
3
2
4
4
3
3
5
5
4
4
6
6
4
5
7
7
5
6
tCL
ns
tASU
tAH
ns
ns
tACOP
tACH
tACL
tCNT
fCNT
10
15
ns
3
3
4
4
6
6
8
8
10
10
ns
ns
Minimum Clock Global Period
8
8
10
10
13
13
17
17
22
22
ns
Maximum Internal Global
Clock Frequency
125
100
76.9
66
50
MHz
tACNT
fACNT
Minimum Array Clock Period
ns
Maximum Internal Array
Clock Frequency
125
100
125
76.9
100
66
50
MHz
fMAX
tIN
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
166.7
41.7
33.3
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5
0.5
1
0.5
0.5
1
2
2
2
8
1
6
6
3
4
2
2
2
2
tIO
tFIN
2
2
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
4
5
10
1
12
1.2
8
Cascade Logic Delay
Logic Array Delay
0.8
3
0.8
5
7
Logic Control Delay
3
5
7
8
Internal Output Enable Delay
2
2
3
4
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCCIO = 5V; CL = 35 pF)
2
1.5
5
6
19
0784P–PLD–7/05
AC Characteristics (Continued)(1)
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
tOD2
Output Buffer and Pad Delay
(Slow slew rate = OFF;
2.5
2.0
5
6
7
ns
VCCIO = 3.3V; CL = 35 pF)
tOD3
tZX1
tZX2
tZX3
tXZ
Output Buffer and Pad Delay
(Slow slew rate = ON;
VCCIO = 5V or 3.3V; CL = 35 pF)
5
4.0
4.5
9
5.5
5.0
5.5
9
8
7
10
9
12
10
10
12
8
ns
ns
ns
ns
ns
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
7
9
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; CL = 35 pF)
10
6
11
7
Output Buffer Disable Delay
(CL = 5 pF)
4
5
tSU
tH
Register Setup Time
Register Hold Time
3
2
3
2
3
3
4
4
2
5
5
2
6
6
3
ns
ns
ns
tFSU
Register Setup Time of Fast
Input
tFH
Register Hold Time of Fast
Input
0.5
0.5
2
2
2.5
ns
tRD
Register Delay
1
1
2
2
1
1
2
2
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
3
5
6
7
8
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
Reduced-power Adder(2)
3
5
6
7
8
tGLOB
tPRE
tCLR
tUIM
tRPA
1
1
1
1
1
2
3
4
5
6
2
3
4
5
6
1
1
2
2
2
10
11
13
14
15
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
20
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508AS Dedicated Pinouts
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
84-lead J-lead
100-lead PQFP
100-lead TQFP
160-lead PQFP
2
1
92
91
90
89
87
3,43
6
90
89
88
87
85
1,41
4
142
141
140
139
137
63,159
9
84
INPUT/GCLK1
I/O /GCLK3
83
81
I/O / PD (1, 2)
I/O / TDI(JTAG)
I/O / TMS(JTAG)
I/O / TCK(JTAG)
I/O / TDO(JTAG)
GND
12,45
14
23
17
64
75
15
62
73
22
62
99
71
112
7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
VCCINT
VCCIO
3,43
41,93
39,91
61,143
13,26,38,
53,66,78
5,20,36,53,68,84
3,18,34,51,66,82
8,26,55,79,104,133
N/C
–
–
–
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
# of SIGNAL PINS
68
84
80
84
80
100
96
# USER I/O PINS
OE (1, 2)
64
Global OE Pins
Global Clear Pin
Global Clock Pins
Power-down pins
GCLR
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for boundary scan testing or in-system programming
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
21
0784P–PLD–7/05
ATF1508AS I/O Pinouts
84-lead
J-lead
100-lead 100-lead 160-lead
84-lead
J-lead
100-lead 100-lead 160-lead
MC
1
PLB
A
PQFP
TQFP
PQFP
160
–
MC
33
PLB
C
PQFP
TQFP
PQFP
–
–
4
–
2
–
–
–
27
25
41
2
A
34
C
–
–
–
A/
PD1
3
12
3
1
159
35
C
31
26
24
33
4
5
A
A
A
A
A
A
A
A
A
A
A
A
–
11
10
–
–
2
–
100
99
–
158
153
152
–
36
37
38
39
40
41
42
43
44
45
46
47
C
C
C
C
C
C
C
C
C
C
C
C
–
30
29
–
–
25
24
–
–
23
22
–
32
31
30
–
6
1
7
–
8
9
100
99
–
98
97
–
151
150
–
28
–
23
22
–
21
20
–
29
28
–
9
–
10
11
12
13
14
15
–
–
8
98
–
96
–
149
147
146
145
–
27
–
21
–
19
–
27
25
24
23
–
–
6
96
95
–
94
93
–
25
24
–
19
18
–
17
16
–
5
–
C/
TMS
16
A
4
94
92
144
48
23
17
15
22
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
22
–
16
–
14
–
21
–
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
41
–
39
–
37
–
59
–
21
–
15
–
13
–
20
19
18
16
–
40
–
38
–
36
–
58
57
56
54
–
20
–
14
12
–
12
10
–
39
–
37
35
–
35
33
–
–
–
18
17
–
11
10
–
9
15
14
–
37
36
–
34
33
–
32
31
–
53
52
–
8
–
16
–
9
7
13
12
11
10
–
35
–
32
–
30
–
51
50
49
48
–
–
–
15
–
8
6
34
–
31
30
–
29
28
–
7
5
–
–
–
–
B/
TDI
32
65
14
44
6
4
9
64
97
D
G
33
63
29
65
27
63
43
E
42
40
62
100
22
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508AS I/O Pinouts (Continued)
84-lead
J-lead
100-lead 100-lead 160-lead
84-lead
J-lead
100-lead 100-lead 160-lead
MC
PLB
PQFP
TQFP
PQFP
MC
PLB
PQFP
TQFP
PQFP
66
E
–
–
–
–
98
G
–
–
–
–
E/
PD2
67
45
43
41
63
99
G
64
66
64
101
68
69
70
71
72
73
74
75
76
77
78
79
E
E
E
E
E
E
E
E
E
E
E
E
–
46
–
–
44
46
–
–
42
44
–
64
65
67
–
100
101
102
103
104
105
106
107
108
109
110
111
G
G
G
G
G
G
G
G
G
G
G
G
–
65
–
–
67
69
–
–
65
67
–
102
103
105
–
–
–
48
49
–
47
48
–
45
46
–
68
69
–
67
68
–
70
71
–
68
69
–
106
107
–
50
–
49
–
47
–
70
71
72
73
–
69
–
72
–
70
–
108
109
110
111
–
51
–
50
51
–
48
49
–
70
–
73
74
–
71
72
–
–
–
G/
TDO
80
E
52
52
50
78
112
71
75
73
112
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
–
–
54
–
52
–
80
–
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
–
–
77
–
75
–
121
–
54
–
55
–
53
–
88
89
90
91
–
73
–
78
–
76
–
122
123
128
129
–
55
56
–
56
57
–
54
55
–
74
75
–
79
80
–
77
78
–
57
–
58
59
–
56
57
–
92
93
–
76
–
81
82
–
79
80
–
130
131
–
–
–
58
–
60
–
58
–
94
96
97
98
–
77
–
83
–
81
–
132
134
135
136
–
60
61
–
62
63
–
60
61
–
79
80
–
85
86
–
83
84
–
F/
TCK
H/
GCLK3
96
62
64
62
99
128
81
87
85
137
23
0784P–PLD–7/05
Ordering Information
ATF1508AS Standard Package Options
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
ATF1508AS-7 JC84
ATF1508AS-7 QC100
ATF1508AS-7 AC100
ATF1508AS-7 QC160
ATF1508AS-10 JC84
ATF1508AS-10 QC100
ATF1508AS-10 AC100
ATF1508AS-10 QC160
84J
100Q1
100A
160Q1
84J
Commercial
7.5
4.5
166.7
(0°C to 70°C)
100Q1
100A
160Q1
Commercial
10
10
15
5
5
5
125
125
100
(0°C to 70°C)
ATF1508AS-10 Jl84
ATF1508AS-10 Ql100
ATF1508AS-10 Al100
ATF1508AS-10 Ql160
84J
Industrial
100Q1
100A
160Q1
(-40°C to +85°C)
ATF1508AS-15 JC84
ATF1508AS-15 QC100
ATF1508AS-15 AC100
ATF1508AS-15 QC160
84J
100Q1
100A
160Q1
Commercial
(0°C to 70°C)
ATF1508AS-15 JI84
ATF1508AS-15 QI100
84J
100Q1
Industrial
15
8
100
ATF1508AS-15 AI100
ATF1508AS-15 QI160
100A
(-40°C to +85°C)
160Q1
Notes: 1. The last time buy is Sept. 30, 2005 for shaded parts.
2. The recommended replacement package for QC160 is the AU100.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF1508AS Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
Commercial
ATF1508AS-7 JX84
ATF1508AS-7 AX100
84J
100A
7.5
10
4.5
5
166.7
125
(0°C to 70°C)
ATF1508AS-10 JU84
ATF1508AS-10 QU100
ATF1508AS-10 AU100
84J
100Q1
100A
Industrial
(-40°C to +85°C)
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100-lead, Plastic Quad Pin Flat Package (PQFP)
100Q1
100A
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160-lead, Plastic Quad Pin Flat Package (PQFP)
160Q1
24
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
ATF1508ASL Standard Package Options
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
ATF1508ASL-20 JC84
ATF1508ASL-20 QC100
ATF1508ASL-20 AC100
ATF1508ASL-20 QC160
ATF1508ASL-25 JI84
ATF1508ASL-25 QI100
ATF1508ASL-25 AI100
ATF1508ASL-25 QI160
84J
100Q1
100A
160Q1
84J
Commercial
20
25
12
15
83.3
70
(0°C to 70°C)
100Q1
100A
160Q1
Industrial
(-40°C to +85°C)
Note:
1. The last time buy is Sept. 30, 2005 for shaded parts.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
ATF1508ASL Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
Ordering Code
Package
Operation Range
Industrial
ATF1508ASL-25 JU84
ATF1508ASL-25 AU100
84J
100A
25
15
70
(-40°C to +85°C)
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100-lead, Plastic Quad Pin Flat Package (PQFP)
100Q1
100A
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160-lead, Plastic Quad Pin Flat Package (PQFP)
160Q1
25
0784P–PLD–7/05
Package Information
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
B
R
26
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
100Q1 – PQFP
E
PIN 1 ID
PIN 1
e
D1
B
D
E1
COMMON DIMENSIONS
(Unit of Measure = mm)
JEDEC STANDARD MS-022, GC-1
A
0º~7º
C
MIN
–
MAX
3.4
NOM
3.04
NOTE
SYMBOL
A
L
A1
D
0.25
0.33
0.5
A1
23.20 BSC
17.20 BSC
14.00 BSC
–
E
E1
B
0.22
0.11
0.40
0.23
C
–
D1
L
20 BSC
–
0.73
1.03
e
0.65 BSC
07/6/2005
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
Plastic Quad Flat Package (PQFP)
100Q1
C
R
27
0784P–PLD–7/05
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
28
ATF1508AS(L)
0784P–PLD–7/05
ATF1508AS(L)
160Q1 – PQFP
D1
D
E
E1
Top View
Bottom View
A2
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
e
b
L1
MIN
0.25
3.20
MAX
0.50
SYMBOL
NOM
–
NOTE
Side View
A1
A2
D
5
3.40
3.60
31.20 BSC
28.00 BSC
31.20 BSC
28.00 BSC
0.65 BSC
–
2
3
2
3
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing
MS-022, Variation DD-1, for additional information.
D1
E
2. To be determined at seating plane.
3. Regardless of the relative size of the upper and lower body sections,
dimensions D1 and E1 are determined at the largest feature of the body
exclusive of mold Flash and gate burrs, but including any mismatch
between the upper and lower sections of the molded body.
4. Dimension b does not include Dambar protrusion. The Dambar
protrusion(s) shall not cause the lead width to exceed b maximum by more
than 0.08 mm. Dambar cannot be located on the lower radius or the lead
foot.
E1
e
b
0.22
0.40
4
L1
1.60 REF
5. A1 is defined as the distance from the seating plane to the lowest point of
the package body.
3/28/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt.,
Plastic Quad Flat Pack (PQFP)
160Q1
A
R
29
0784P–PLD–7/05
Revision History
Revision
Comments
Green package options added.
0784P
The ATF1508ASL-25 commercial speed offering was obsoleted in 2002
and replaced by the ATF1508ASL-20 commercial speed grade.
0784O
30
ATF1508AS(L)
0784P–PLD–7/05
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trade-
marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
0784P–PLD–7/05
xM
相关型号：
ATF1508AS-15AJ100
EE PLD, 15ns, PQFP100, 14 X 14 MM, 1 MM THICKNESS, 0.50 MM PITCH, PLASTIC, TQFP-100
ATMEL
ATF1508AS-15AL100
EE PLD, 15ns, PQFP100, 14 X 14 MM, 1 MM THICKNESS, 0.50 MM PITCH, PLASTIC, TQFP-100
ATMEL
©2020 ICPDF网 联系我们和版权申明