ATF1508BE-5CX132 [ATMEL]
Highperformance CPLD; 高性能CPLD
| 型号： | ATF1508BE-5CX132 |
| 厂家： | 
ATMEL |
| 描述： | Highperformance CPLD |
| 文件： | 总30页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance Fully CMOS, Electrically-erasable Complex
Programmable Logic Device
– 128 Macrocells
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
– SSTL2 and SSTL3 I/O Standards
• In-System Programming (ISP) Supported
– ISP Using IEEE 1532 (JTAG) Interface
– IEEE 1149.1 JTAG Boundary Scan Test
• Flexible Logic Macrocell
High-
performance
CPLD
– D/T/Latch Configurable Flip-flops
– 5 Product Terms per Macrocell, Expandable up to 40
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a Combinatorial Output and
Vice Versa
ATF1508BE
• Fully Green (RoHS Compliant)
• As Low As 10 µA Standby Current
• Power Saving Option During Operation Using PD1 and PD2 Pins
• Programmable Pin-keeper Option on Inputs and I/Os
• Programmable Schmitt Trigger Input Option on Input and I/O Pins
• Programmable Input and I/O Pull-up Option
• Unused I/O Pins Can Be Configured as Ground (Optional)
• Available in Commercial and Industrial Temperature Ranges
• Available in 100-lead TQFP and 132-ball CBGA
• Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• Security Fuse Feature
• Hot-Socketing Supported
3663A–PLD–1/08
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Outputs Can Be Configured for High or Low Drive
• Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell
• Three Global Clock Pins
• Fast Registered Input from Product Term
• Pull-up Option on TMS and TDI JTAG Pins
• OTF (On-the-Fly) Reconfiguration Mode
• DRA (Direct Reconfiguration Access)
1. Description
The ATF1508BE is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 128 logic
macrocells and up to 84 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508BE’s enhanced routing switch matrices increase usable gate count
and the odds of successful pin-locked design modifications.
The ATF1508BE has up to 80 bi-directional I/O pins and four dedicated input pins. Each dedi-
cated input pin can also serve as a global control signal, register clock, register reset or output
enable. Each of these control signals can be selected for use individually within each macrocell.
Figures 1-1 and 1-2 show the pin assignments for the 100-lead TQFP and 132-ball CBGA pack-
ages, respectively.
2
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Figure 1-1. 100-lead TQFP Top View
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIOA
I/O/TDI
I/O
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
VREFA / I/O 12
I/O 13
66 VCCIOB
65 I/O
64 I/O
63 I/O
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O / VREFB
59 GND
58 I/O
I/O 17
VCCIOA 18
I/O 19
57 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIOB
3
3663A–PLD–1/08
Figure 1-2. 132-CBGA Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
I/O
I/O
VCCINT I/GCLR
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
VCCIOB
NC
NC
NC
NC
GND
I/O/TDO
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIOB
GND
NC
I/O
GND
I/O
I/OE1 I/OE2/ VCCIOB
GCLK2
NC
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O/PD1
I/O
I/O
I/O
G
H
J
I/O
I/O/PD2
I/O
VCCIOA
GND
GND
I/O
I/O/VREFA I/O
I/O
I/O
I/O
I/O
GND
I/GCLK1
NC
VCCIOA
I/O
I/O
K
L
VCCNT
NC
NC
I/O I/O/VREFB I/O
M
N
P
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
I/O
NC
NC
I/O/TDI I/O/TCK
GND I/O/TMS
I/O
I/O
I/O
NC
GND
I/O
NC
I/O
NC
I/O
I/O
GND
VCCINT
NC
I/O
I/O
I/O
GND
VCCIOA
I/O
I/O
VCCIOA
Note:
1. The 132-ball CBGA package is 8 x 8 x 1.2 mm in size with 0.5 mm ball spacing.
4
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Figure 1-3. Block Diagram
10
16
10
5
3663A–PLD–1/08
Each of the 128 macrocells generates a buried feedback signal that goes to the global bus (see
Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1508BE allows fast, efficient generation of complex logic functions. The ATF1508BE con-
tains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1508BE macrocell, shown in Figure 1-4, is highly flexible and capable of supporting
complex logic functions operating at high speed. The macrocell consists of five sections: product
terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1508BE. Two bytes
(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Electronic Signature is accessible regard-
less of the state of the security fuse.
The ATF1508BE device supports In-System Programming (ISP) via the industry-standard 4-pin
JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary
Scan Test. ISP allows the device to be programmed without removing it from the printed circuit
board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to
be made in the field via software.
Figure 1-4. ATF1508BE Macrocell
BURIED FEEDBACK
SCHMITT
TRIGGER
SSTL
6
ATF1508BE
3663A–PLD–1/08
ATF1508BE
1.1
1.2
Product Terms and Select Mux
Each ATF1508BE macrocell has five product terms. Each product term receives as its inputs all
signals from the switch matrix and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX configuration is determined by the design
compiler, which selects the optimum macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1508BE’s logic structure is designed to efficiently support all types of logic. Within a sin-
gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with minimal additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-
tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
1.3
Flip-flop
The ATF1508BE’s flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial out-
put macrocell. (This feature is automatically implemented by the fitter software). In addition to D,
T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and is latched when the clock is low.
The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-
uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always off.
1.4
1.5
Extra Feedback
The ATF1508BE macrocell output can be selected as registered or combinatorial. The extra bur-
ied feedback signal can be either combinatorial or a registered signal regardless of whether the
output is combinatorial or registered. (This enhancement function is automatically implemented
by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second
latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-
ually configured as an input, output or bi-directional pin. The output enable for each macrocell
can be selected from the true or complement of the two output enable pins, a subset of the I/O
pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software
when the I/O is configured as an input or bi-directional pin.
7
3663A–PLD–1/08
1.6
1.7
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
2. Input and I/O Pins
2.1
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1508BE offers the option of individually programming each of its input or I/O pin so that
pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left
floating, it will stay at that previous high or low level. This circuitry prevents undriven input and
I/O lines from floating to intermediate voltage levels, which causes unnecessary power con-
sumption and system noise. The keeper circuits eliminate the need for external pull-up resistors
and eliminate their DC power consumption.
Figure 2-1 shows the pin-keeper circuit for an Input Pin and Figure 2-2 shows the same for an
I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is
approximately 50 kΩ.
Figure 2-1. Input with Programmable Pin-keeper
VCCINT
50K
8
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Figure 2-2. I/O with Programmable Pin-keeper
VCCIO
VCCINT
50K
2.2
2.3
Schmitt Trigger
The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt
trigger option can be used to buffer inputs with slow rise times.
Output Drive Capability
Each output has a high/low drive option. The low drive option (slow slew rate) can be used to
reduce system noise by slowing down outputs that do not need to operate at maximum speed or
drive strength. Outputs default to high drive strength by Atmel software and can be set to low
drive strength through the slew rate option.
2.4
2.5
I/O Bank
The I/O pins of the ATF1508BE are grouped into two banks, Bank A and Bank B. Bank A com-
prises of I/O pins for macrocells 1 to 64 (Logic Block A, B, C, and D), and it is powered by
V
CCIOA. Bank B comprises of I/O pins for macrocells 65 to 128 (Logic Block E, F, G, and H), and
it is powered by VCCIOB
.
I/O Standard
The ATF1508BE supports a wide range of I/O standards which include LVTTL, LVCMOS33,
LVCMOS25, LVCMOS18 and LVCMOS15. The I/O pins of the ATF1508BE can also be individ-
ually configured to support SSTL-2 (Class I) and SSTL-3 (Class I) advanced I/O standards.
This and the two I/O banks, together, allow the ATF1508BE to be used for voltage level
translation.
9
3663A–PLD–1/08
3. Power Management
Unlike conventional CPLDs with sense amplifiers, the ATF1508BE is designed using low-power
full CMOS design techniques. This enables the ATF1508BE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1508BE also has an optional power-down mode. In this mode, current drops to below
100 µA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-
rocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
4. Security Feature
A fuse is provided to prevent unauthorized copying of the ATF1508BE fuse patterns. Once
enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature
remains accessible. To reset this feature, the entire memory array in the device must be erased.
5. Programming Methods
The ATF1508BE devices are In-System Programmable (ISP) or In-System Configurable (ISC)
devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally
required for programming and facilitates rapid design iterations and field changes.
When using the ISP hardware or software to program the ATF1508BE devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for buried logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities. ATF1508BE devices can
also be programmed using standard third-party programmers. With a third-party programmer,
the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
The ATF1508BE device supports several configuration modes which gives designers several
unique options for programming.
The different modes of programming are:
• ISC – In-System Configuration
• OTF – On-the-Fly Reconfiguration
• DRA – Direct Reconfiguration Access
10
ATF1508BE
3663A–PLD–1/08
ATF1508BE
5.1
In-System Configuration – ISC (Also Referred to as ISP)
This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The
term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP elim-
inates the need for an external device programmer, and the devices can be soldered to a PCB
without being preprogrammed.
In the ISC mode, the logic operation of the ATF1508BE is halted and the embedded configura-
tion memory is programmed. The device is programmed by first erasing the configuration
memory in the CPLD and then loading the new configuration data into the memory, which in-turn
configures the PLD for functional mode. When the device is in the ISC programming mode, all
user I/Os are held in the high impedance state.
The ISC mode is best suited for working with the ATF1508BE device in a design development or
production environment. Configuration of the ATF1508BE device done via a Download Cable
(see Figure 5-1 on page 11) is the default mode used to program the device in the ISC mode. In
this mode, the PC is typically the controlling device that communicates with the CPLD.
Figure 5-1. Configuration of ATF1508BE Device Using a Download Cable
Connect
ISP Download
Cable to 10-pin
ATF1508BE
CPLD Device
JTAG Header
TCK
VCC
TDO
2
1
3
5
7
9
4
6
TMS
TDI
8
10
JTAG
Connector
5.2
On-the-Fly Reconfiguration – OTF
In this mode, the CPLD design pattern stored in the internal configuration memory can be modi-
fied while the previously-programmed design pattern is operating with minimal disturbance to
the programming operation of the new design. The new configuration will take affect after the
OTF programming process is completed and the OTF mode is exited.
The configuration data for any design is stored in the internal configuration memory. Once the
configuration data is transferred to the internal static registers of the CPLD, the CPLD operates
with the design pattern and the configuration memory is free to be re-loaded with a new set of
configuration data. The design pattern due to the new configuration content is activated through
an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence.
Figure 5-2 shows the electrical interface for configuration of the ATF1508BE device in the OTF
mode. The processor is the controlling device that communicates with the CPLD and uses con-
figuration data stored in the external memory to configure the CPLD.
11
3663A–PLD–1/08
Figure 5-2. Configuration of ATF1508BE Device Using a Processor and Memory
ATF1508BE
CPLD Device
TCK
TDO
Processor
TMS
TDI
Serial Data
Data
Address
Memory
5.3
Direct Reconfiguration Access – DRA
This reconfiguration mode allows the user to directly modify the internal static registers of the
CPLD without affecting the configuration data stored in the embedded memory. It is more useful
in cases where immediate and temporary context change in the function of the hardware is
desired.
The embedded configuration memory in the ATF1508BE does not change when a new set of
configuration data is passed to the ATF1508BE using the DRA mode. Instead, the internal static
registers of the CPLD are directly written with the data entering the device via the JTAG port. In
other words, it's a temporary change in the function performed by the CPLD since a power
sequence results in the device being configured again by the data stored in the embedded
memory.
5.4
ISP Programming Protection
The ATF1508BE has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The I/O pins default to
high-Z state during such a condition.
All ATF1508BE devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
12
ATF1508BE
3663A–PLD–1/08
ATF1508BE
6. JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1508BE. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRE-
LOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1508BE’s BSC can be fully described
using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1508BE testing to be
described and implemented using any one of the third-party development tools supporting this
standard.
The ATF1508BE also has the option of using the four JTAG-standard I/O pins for ISP. The
ATF1508BE is programmable through the four JTAG pins using the IEEE standard JTAG pro-
gramming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level
programming signals from the ISP interface for in-system programming. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
6.1
JTAG Boundary-scan Cell (BSC) Testing
The ATF1508BE contains 80 I/O pins and four dedicated input pins. Each input pin and I/O pin
has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in
detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one
for the macrocells. The BSCs in the device are chained together through the capture registers.
Input to the capture register chain is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active device data signals, to shift data in and
out of the device and to load data into the update registers. Control signals are generated inter-
nally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 6-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note:
The ATF1508BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
13
3663A–PLD–1/08
Figure 6-2. BSC Configuration for Macrocell
TDO
0
1
D
Q
TDI
CLOCK
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
BSC for I/O Pins and Macrocells
7. Design Software Support
ATF1508BE designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages such as VHDL® and Verilog®. Third
party synthesis and simulation tools from Mentor Graphics® are integrated into Atmel’s software
tools.
14
ATF1508BE
3663A–PLD–1/08
ATF1508BE
8. Electrical Specifications
Table 8-1.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature...................................–40°C to +85° C
Storage Temperature....................................–65°C to +150° C
Supply Voltage (VCCINT) ....................................–0.5V to +2.5V
Supply Voltage for Output Drivers (VCCIO) ........–0.5V to +4.5V
Junction Temperature ...................................–55°C to +155° C
Table 8-2.
Operating Temperature Range
Commercial
0° C - 70° C
Industrial
Operating Temperature (Ambient)
-40°C - 85°C
Table 8-3.
Pin Capacitance(1)
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
10
pF
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
15
3663A–PLD–1/08
Table 8-4.
Symbol
DC Characteristics
Parameter
Condition
Min
Typ
Max
Units
Supply Voltage for internal
logic and input buffers
VCCINT
VCCIO
VCCIO
VCCIO
VCCIO
1.7
1.8
1.9
V
Supply Voltage for output
drivers at 3.3V
3.0
2.3
1.7
1.4
3.3
2.5
1.8
1.5
3.6
2.7
1.9
1.6
V
V
V
V
Supply Voltage for output
drivers at 2.5V
Supply Voltage for output
drivers at 1.8V
Supply Voltage for Output
Drivers at 1.5V
ISB_IO
Standby Current, VCCIO
VCCIO = 3.3V, VCCINT = 1.8V
VCCINT = 1.9V, VCCIO = 3.6V
1
µA
µA
ISB_INT
Standby Current, VCC Core(1)
20
Operating Current(1)
for VCCINT (supply voltage)
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
ICC_INT(HD)
ICC_IO(HD)
ICC_INT(LD)
ICC_IO(LD)
315
330
145
60
µA
µA
µA
µA
Operating Current(1)
for VCCIO (supply voltage for
output drivers), per LAB
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
Operating Current(1)
for VCCINT (low drive)
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
Operating Current(1)
for VCCIO (supply voltage for
output drivers), per LAB
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
IIL, IIH
Input Leakage
VCCINT = 1.8V, VIN = 0V or VCCINT
1
1
µA
µA
VCCINT = 1.8V, VCCIO = 3.6V,
IOZH, IOH
Output or IO Leakage
VIN = 0V or VCCIO
LVCMOS 3.3V & LVTTL (HD: High Drive, LD: Low Drive)
VIL
VIH
Input Low-voltage
Input High-voltage
-0.3
2
0.8
3.9
0.4
0.4
V
V
V
V
V
V
HD: IOL = 8 mA, VCCIO = 3V
LD: IOL = 1 mA, VCCIO = 3V
HD: IOH = -8 mA, VCCIO = 3V
LD: IOH = -1 mA, VCCIO = 3V
VOL
Output Low-voltage
Output High-voltage
VCCIO - 0.4V
VCCIO - 0.4V
VOH
LVCMOS 2.5V
VIL
VIH
Input Low-voltage
Input High-voltage
-0.3
1.7
0.7
3.9
0.4
0.4
V
V
V
V
V
V
HD: IOL = 8 mA, VCCIO = 2.3V
LD: IOL = 1 mA, VCCIO = 2.3V
HD: IOH = -8 mA, VCCIO = 2.3V
LD: IOH = -1 mA, VCCIO = 2.3V
VOL
Output Low-voltage
Output High-voltage
VCCIO - 0.4V
VCCIO - 0.4V
VOH
16
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Table 8-4.
Symbol
LVCMOS 1.8V
VIL
DC Characteristics (Continued)
Parameter
Condition
Min
Typ
Max
Units
Input Low-voltage
Input High-voltage
-0.3
1.2
0.35 x VCCIO
V
V
V
V
V
V
VIH
3.9
0.45
0.2
HD: IOL = 2 mA, VCCIO = 1.7V
LD: IOL = 1 mA, VCCIO = 1.7V
HD: IOH = -2 mA, VCCIO = 1.7V
LD: IOH = -1 mA, VCCIO = 1.7V
VOL
Output Low-voltage
Output High-voltage
VCCIO - 0.45V
VCCIO - 0.45V
VOH
LVCMOS 1.5V
VIL
VIH
Input Low-voltage
Input High-voltage
-0.3
1.2
0.35 x VCCIO
V
V
V
V
V
V
3.9
0.45
0.2
HD: IOL = 2 mA, VCCIO = 1.4V
LD: IOL = 1 mA, VCCIO = 1.4V
HD: IOH = -2 mA, VCCIO = 1.4V
LD: IOH = -1 mA, VCCIO = 1.4V
VOL
Output Low-voltage
Output High-voltage
VCCIO - 0.45V
VCCIO - 0.45V
VOH
Note:
1. 16-bit up/down counter used in each LAB.
Table 8-5.
Schmitt Trigger Input Threshold Voltage
VTHL
VTLH
VCCINT
Min
0.68
0.81
Max
0.73
0.88
Min
1.05
1.18
Max
1.08
1.22
1.70
1.95
Table 8-6.
Symbol
VCCIO
SSTL2-1 DC Voltage Specifications
Parameter
Conditions
Min
2.3
Typ
2.5
Max
2.7
Units
V
Input Source Voltage
Input Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
(1)
VREF
1.15
1.25
1.25
1.35
V
(2)
VTT
VREF - 0.05
VREF + 0.45
-0.3
VREF + 0.04
3.9
V
VIH
V
VIL
VREF - 0.6
V
VOH
IOH = -8 mA, VCCIO = 2.3V
IOL = 8 mA, VCCIO = 2.3V
VCCIO - 0.6
V
VOL
0.54
V
VIH(DC)
VIL(DC)
VREF + 0.15
-0.3
VCCIO + 0.3
VREF - 0.15
V
V
Notes: 1. Peak-to-peak noise on VREF may not exceed 2% VREF, VREF should track the variations in VCCIO
.
2. VTT of transmitting device must track VREF of receiving devices.
17
3663A–PLD–1/08
Table 8-7.
Symbol
VCCIO
SSTL3-1 DC Voltage Specifications
Parameter
Conditions
Min
3.0
Typ
3.3
1.5
1.5
Max
3.6
Units
V
Input Source Voltage
Input Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
(1)
VREF
1.3
1.7
V
(2)
VTT
VREF - 0.05
VREF + 0.4
-0.3
VREF + 0.05
VCCIO + 0.3
VREF - 0.6
V
VIH
V
VIL
V
VOH
IOH = -8 mA, VCCIO = 3V
IOL = 8 mA, VCCIO = 2.3V
VCCIO - 1.1
V
VOL
0.7
V
VIH(DC)
VIL(DC)
VREF + 0.18
-0.3
VCCIO + 0.3
VREF - 0.18
V
V
Notes: 1. Peak-to-peak noise on VREF may not exceed 2% VREF, VREF should track the variations in VCCIO
.
2. VTT of transmitting device must track VREF of receiving devices.
9. Timing Model
Internal Output
Enable Delay
tIOE
Global Control
Delay
Input
Delay
tIN
Register/
Combinatorial
tGLOB
Cascade Logic
Delay
Delays
tSUI
tHI
tPRE
tCLR
tRD
tCOMB
tFSUI
tFHI
Output
Delay
tOD1
(+tSCH
)
Logic Array
Delay
tPEXP
Switch
Matrix
tUIM
tLAD
(+tSSO
)
Register
Control
Delay
tXZ
tZX1
tZX2
Fast Input
Delay
tFIN
tLAC tIC tEN
(+SSTL2-1_OAD)
(+SSTL3-1_OAD)
I/O
Delay
tIO
Foldback Term
Delay
tSEXP
(+tSCH
)
(+SSTL2-1_IAD)
(+SSTL3-1_IAD)
18
ATF1508BE
3663A–PLD–1/08
ATF1508BE
10. Output AC Test Loads
VCCIO
R1
R2
Device
Under Test
Test Point
CL
R1
R2
CL
LVTTL
350 Ohm
300 Ohm
200 Ohm
150 Ohm
350 Ohm
300 Ohm
200 Ohm
150 Ohm
35 pF
35 pF
35 pF
35 pF
LVCMOS33
LVCMOS25
LVCMOS18
Note:
CL includes test fixtures and probe capacitance.
19
3663A–PLD–1/08
11. AC Characteristics
Table 11-1. AC Characteristics (1)
-5
-7
Symbol
tPD1_INP
tPD1
Parameter
Min
Max
5.0
7
Min
Max
6
Units
ns
Delay for Single Input to Non-registered Output
Input or Feedback to Non-registered Output
Input or Feedback to Non-registered Feedback
Global Clock Setup Time
7.5
4.7
ns
tPD2
4.2
ns
tSU
2.2
0
2.8
0
ns
tH
Global Clock Hold Time
ns
tFSU
Global Clock Setup Time of Fast Input
Global Clock Hold Time of Fast Input
Global Clock to Output Delay
Global Clock High Time
1
2
ns
tFH
0.5
0.75
ns
tCOP
6
6.9
7.5
ns
tCH
1.25
1.25
1.7
2
2
ns
tCL
Global Clock Low Time
ns
tASU
Array Clock Setup Time
2.2
0.60
ns
tAH
Array Clock Hold Time
0.50
ns
tACOP
tACH
Array Clock to Output Delay
Array Clock High Time
6.5
ns
1.75
1.75
2.5
2.5
ns
tACL
Array Clock Low Time
ns
tCNT
Minimum Global Clock Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
3
4
4.75
5.5
ns
fCNT
333
250
210
181
MHz
ns
tACNT
fACNT
fMAX_EXT_SYNC
fMAX_EXT_ASYNC
tIN
MHz
MHz
MHz
ns
Maximum External Frequency
Maximum External Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
VCCIO = 3.3V
VCCIO = 3.3V
122
122
103
103
0.9
0.9
1
0.7
0.7
tIO
ns
tFIN
1
2
ns
tSEXP
tPEXP
tLAD
Foldback Term Delay
3
ns
Cascade Logic Delay
0.5
1.8
1.5
2
1.0
1.8
2
ns
Logic Array Delay
ns
tLAC
Logic Control Delay
ns
tIOE
Internal Output Enable Delay
2
ns
V
CCIO = 1.5V
4.5
4.0
3.5
2.8
4.5
4.0
3.5
2.8
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
Output Buffer Delay (HD)
(High Drive; CL = 35 pF)
tOD1
ns
20
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Table 11-1. AC Characteristics (Continued)(1)
-5
-7
Symbol
Parameter
Min
Max
Min
Max
Units
V
CCIO = 1.5V
5.0
4.5
3.5
3.0
6.0
5.5
4.5
4.0
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
Output Buffer Enable Delay
(High Drive; CL = 35 pF)
tZX1
ns
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
6.0
5.5
4.5
4.0
7.0
6.5
5.5
5.0
Output Buffer Enable Delay
(Low Drive; CL = 35 pF)
tZX2
ns
tXZ
Output Buffer Disable Delay (CL = 5 pF)
Register Setup Time
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUI
tHI
tFSUI
tFHI
1.7
0.5
0.5
0.5
2.2
0.6
0.6
0.6
Register Hold Time
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
0.7
1.2
1.2
1.2
1.8
3
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
1.8
tEN
Register Enable Time
Global Control Delay
2.5
tGLOB
tPRE
tCLR
tUIM
tSCH
1.8
2
Register Preset Time
1.75
1.75
0.5
2
Register Clear Time
2
Switch Matrix Delay
0.8
2
Schmitt Trigger Added Delay
1.5
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
6.5
5.5
5.25
5
8.5
7.5
7.25
7
Output Added Delay for VCCIO Level
(LD)
tSSO
ns
SSTL2-1_IAD(2)
SSTL3-1_IAD(2)
V
CCIO = 2.5V
VCCIO = 3.3V
CCIO = 2.5V
VCCIO = 3.3V
1.5
1.5
1.5
1.5
SSTL Input Delay Adder (HD)
SSTL Output Delay Adder (HD)
ns
ns
SSTL2-1_OAD(2)
SSTL3-1_OAD(2)
V
1
1
1
1
Note:
1. See ordering information for valid part numbers.
2. SSTL is not supported for low drive output (LD).
21
3663A–PLD–1/08
12. Power-down Mode
The ATF1508BE includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 100 µA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file or through Atmel software. Designs using the
power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
Table 12-1. Power-down AC Characteristics(1)(2)
-5/-7
Symbol
tIVDH
Parameter
Min
10
Max
Units
ns
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
tGVDH
tCVDH
tDHIX
10
ns
10
ns
5
5
5
2
2
2
2
ns
tDHGX
tDHCX
tDLIV
ns
ns
µs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
µs
µs
µs
Notes: 1. For low-drive outputs, add tSSO
.
2. Pin or product term.
22
ATF1508BE
3663A–PLD–1/08
ATF1508BE
13. ATF1508BE Dedicated Pinouts
Table 13-1. ATF1508BE Dedicated Pinouts
Dedicated Pin
INPUT / OE2 / GCLK2
INPUT / GCLR
INPUT / OE1
132-ball CBGA
100-lead TQFP
C3
A3
90
89
88
87
85
1, 41
12
60
4
C2
INPUT / GCLK1
I/O / GCLK3
L2
M8
I/O / PD (1,2)
F1, G12
H1
I/O / VREFA
I/O / VREFB
L13
M9
I/O / TDI (JTAG)
I/O / TMS (JTAG)
I/O / TCK (JTAG)
I/O / TDO (JTAG)
N10
M10
B9
15
62
73
A9, B14, B3, E14, H14, J14, K2, N1, N9,
N12, P4
GND
11, 26, 38, 43, 59, 74, 86, 95
VCCINT
VCCIOA
VCCIOB
A2, K12, P1
J3, P7, P13, G14
A7, A14, C4
39, 91
3, 18, 34
51, 66, 82
L1, L3, M1, N4, C13, B10, D3, P6, P8, N2,
N7, N8, M7, M2, M12, M13, M14, C7, C8,
C14, B6, B7, B8, B13, A6, A8, A13
N/C
# of Signal Pins
# User I/O Pins
OE (1, 2)
84
80
84
80
Global OE pins
GCLR
Global Clear pin
Global Clock pins
Power-down pins
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan testing or in-system
programming
GND
Ground pins
VCCINT
VCCIOA
VCC pins for the device (+1.8V)
LAB A and B – VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or
3.3V)
VCCIOB
LAB C and D – VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or
3.3V)
VREFA
VREFB
Reference voltage pin for SSTL inputs in bank A
Reference voltage pin for SSTL inputs in bank B
23
3663A–PLD–1/08
Table 13-2. ATF1508BE I/O Pinouts
Logic
Block
100-lead
TQFP
132-ball
CBGA
Logic
Block
100-lead
TQFP
132-ball
CBGA
MC
1
MC
33
A
A
2
-
G1
-
C
C
25
-
B1
-
2
34
A/
PD1
3
1
F1
35
C
24
B2
4
5
A
A
A
A
A
A
A
A
A
A
A
A
-
100
99
-
-
36
37
38
39
40
41
42
43
44
45
46
47
C
C
C
C
C
C
C
C
C
C
C
C
-
-
F2
F3
-
23
22
-
A1
B4
-
6
7
8
98
97
-
E1
E2
-
21
20
-
A4
C5
-
9
10
11
12
13
14
15
96
-
E3
-
19
-
B5
-
94
93
-
D1
D2
-
17
16
-
A5
C6
-
C/
TMS
16
A
92
C1
48
15
N10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
14
-
C2
-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
37
-
P2
-
B
B
13
-
G3
-
36
-
M3
-
B
B/VREFA
12
10
-
H1
H2
-
35
33
-
N3
P3
-
B
B
B
B
B
B
B
B
B
B
9
H3
J1
-
32
31
-
M4
M5
-
8
-
7
J2
-
30
-
N5
-
-
6
K1
K3
-
29
28
-
P5
M6
-
5
-
B/
TDI
32
4
M9
64
D
27
N6
24
ATF1508BE
3663A–PLD–1/08
ATF1508BE
Table 13-2. ATF1508BE I/O Pinouts (Continued)
Logic
Block
100-lead
TQFP
132-ball
CBGA
Logic
Block
100-lead
TQFP
132-ball
CBGA
MC
65
MC
97
E
E
40
-
G13
-
G
G
63
-
C12
-
66
98
E/
PD2
67
41
G12
99
G
64
B12
68
69
70
71
72
73
74
75
76
77
78
79
E
E
E
E
E
E
E
E
E
E
E
E
-
-
100
101
102
103
104
105
106
107
108
109
110
111
G
G
G
G
G
G
G
G
G
G
G
G
-
-
42
44
-
F14
F13
-
65
67
-
A12
C11
-
45
46
-
F12
E13
-
68
69
-
B11
A11
-
47
-
E12
-
70
-
C10
-
48
49
-
D14
D13
-
71
72
-
A10
C9
-
G/
TDO
80
E
50
D12
112
73
B9
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
F
52
-
H12
-
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
75
-
N14
-
F
F
53
-
H13
-
76
-
N13
-
F
F
54
55
-
J13
J12
-
77
78
-
P14
P12
-
F
F
F
56
57
-
K14
K13
-
79
80
-
M11
N11
-
F
F
F
58
-
L14
-
81
-
P11
-
F
F/VREFB
60
61
-
L13
L12
-
83
84
-
P10
P9
-
F
F
F/
TCK
H/
GCLK3
96
62
M10
128
85
M8
25
3663A–PLD–1/08
14. Typical DC and AC Characteristic Graphs
ICCINT & ICCIO PER LAB @
ICCINT & ICCIO PER LAB @
VCCINT = 1.8V (HD) OVER FREQUENCY
VCCINT = 1.8V (HD) OVER FREQUENCY
35
30
25
20
15
10
5
800
700
600
500
400
300
200
100
0
Iccio_Vccio_1.5V
Iccio_Vccio_1.8V
Iccio_Vccio_2.5V
Iccio_Vccio_3.3V
Iccint_vccio_3.3V
Iccio_Vccio_1.5V
Iccio_Vccio_1.8V
Iccio_Vccio_2.5V
Iccio_Vccio_3.3V
Iccint_vccio_3.3V
0
0.025
0.1
0.2
0.5
1
2
1
2
5
10
20
50
75
100
FREQUENCY (MHz)
FREQUENCY (MHZ)
ICCINT & ICCIO (LD) @
VCCINT = 1.8V OVER FREQUENCY
ICCINT & ICCIO (LD)@
VCCINT = 1.8V OVER FREQUENCY
700
600
500
400
300
200
100
0
30
25
20
15
10
5
Iccio_Vccio_1.5V
Iccio_Vccio_1.8V
Iccio_Vccio_2.5V
Iccio_Vccio_3.3V
Iccint_Vccio_3.3V
Iccio_Vccio_1.5V
Iccio_Vccio_1.8V
Iccio_Vccio_2.5V
Iccio_Vccio_3.3V
Iccint_Vccio_3.3V
0
0.025
0.1
0.2
0.5
1
2
1
2
5
10
20
50
75
100
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE
OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), High Drive
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), High Drive
0
-20
160
120
80
40
0
-40
1.5V
1.8V
2.5V
3.3V
1.5V
1.8V
2.5V
3.3V
-60
-80
-100
-120
OUTPUT VOLTAGE ( V )
OUTPUT VOLTAGE ( V )
26
ATF1508BE
3663A–PLD–1/08
ATF1508BE
OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE
OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), Low Drive
(VCCINT = 1.8V, VCCIO =1.5-3.3V, TA = 25C), Low Drive
25
20
15
10
5
0
-5
1.5V
1.8V
2.5V
3.3V
1.5V
1.8V
2.5V
3.3V
-10
-15
-20
-25
0
OUTPUT VOLTAGE ( V )
OUTPUT VOLTAGE ( V )
INPUT & I/O CURRENT VS. INPUT VOLTAGE
INPUT CURRENT VS. INPUT VOLTAGE
INPUT PIN (VCCINT = 1.8V, TA = 25C)
(PIN-KEEPER ON)
V
CCINT = 1.8V, VCCIO = 1.8V (TA = 25°C)
(Pull-Up On)
0.0
80
60
40
20
0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
-20
-40
0
0.5
1
1.5
1.8
INPUT VOLTAGE ( V )
INPUT VOLTAGE (V)
TPD VS. # MC SWITCHING
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C)
I/O PIN CURRENT VS. I/O PIN VOLTAGE
I/O PIN (VCCINT = 1.8V, VCCIO = 1.5V-3.3V, TA = 25C)
(PIN KEEPER ON)
7.2
7.0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
5.4
5.2
5.0
4.8
200
150
100
50
1.5V
1.8V
2.5V
3.3V
1.5V
1.8V
2.5V
3.3V
0
-50
-100
-150
I/O PIN VOLTAGE ( V )
# MC SWITCHING
27
3663A–PLD–1/08
15. Ordering Information
15.1 Lead-free Package Options (RoHS Compliant)
tPD
tCO
(ns)
(ns)
Ordering Code
Package
Operation Range
Commercial
5
7
5
7
6
ATF1508BE-5AX100
100A
(0° C to +70°C)
Industrial
6.5
6
ATF1508BE-7AU100
ATF1508BE-5CX132
ATF1508BE-7CU132
100A
(-40°C to +85°C)
Commercial
132C1
132C1
(0° C to +70°C)
Industrial
6.5
(-40°C to +85°C)
Note:
For shaded devices, contact marketing for availability.
Package Type
100A
132C1
100-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
132-ball, Plastic Chip-Size Ball Grid Array Package (CBGA)
28
ATF1508BE
3663A–PLD–1/08
ATF1508BE
16. Packaging Information
16.1 100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3.
Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
29
3663A–PLD–1/08
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3663A–PLD–1/08
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