ATF1516AEL-15QC208 [ATMEL]
EE PLD, 15ns, PQFP208, PLASTIC, QFP-208;型号: | ATF1516AEL-15QC208 |
厂家: | ATMEL |
描述: | EE PLD, 15ns, PQFP208, PLASTIC, QFP-208 |
文件: | 总76页 (文件大小:617K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• 2nd Generation EE Complex Programmable Logic Devices
– 3.0V to 3.6V Operating Range with 5V Tolerant I/Os
– 32 - 512 Macrocells with Enhanced Features
– Pin-compatible with Industry-standard Devices
– Speeds to 4.5 ns Maximum Pin-to-pin Delay
– Registered Operation to 225 MHz
• Enhanced Macrocells with Logic Doubling™ Features
– Bury Either Register or COM while Using the Other for Output
– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell
– 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade
Logic, Plus 15 More with Foldback Logic
– D/T/Latch Configurable Flip-flops plus Transparent Latches
– Global and/or per Macrocell Register Control Signals
– Global and/or per Macrocell Output Enable
– Programmable Output Slew Rate per Macrocell
– Programmable Output Open Collector Option per Macrocell
– Fast Registered Input from Product Term
• Enhanced Connectivity
ATF15xxAE
Family
Datasheet
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
– Single Level Switch Matrix for Maximum Routing Options
– Up to 40 Inputs per Logic Block
• Advanced Power Management Features
– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and
I/O for µA Level Standby Current on “L” versions
– Pin-controlled 1 mA Standby Mode
– Reduced-power Option per Macrocell
– Automatic Power Down of Unused Macrocells
– Programmable Pin-keeper Inputs and I/Os
• Available in Commercial and Industrial Temperature Ranges
• Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA
• EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
Preliminary
– 10 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993
– Pull-up Option on JTAG Pins TMS and TDI
• IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG
• PCI-compliant
• Security Fuse Feature
Rev. 2398H–PLD–8/03
General
Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells
in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability.
Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel
ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling archi-
tecture consists of wider fan-in, additional routing and clock options, combined with
sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel
enhanced macrocell includes double independent buried feedback that allows designers to
pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for
later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with
no additional design effort and is highly cost effective.
The Atmel ATF15xx Family includes all popular configurations and speeds.
Table 1. ATF15xxAE Family Device Features
Feature
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
12000
512
Usable Gates
Macrocells
750
1500
3000
128
6000
256
32
64
Logic Blocks
Max. # Pins
Max. User I/Os
TPD Grades (ns)
2
44
4
100
8
16
32
256
256
256
36
68
100
164
212
4, 7, 10(15)
4, 7, 10(15)
5, 7, 10(15)
5, 7, 10(15)
5, 7, 12(15)
The Atmel ATF15xxAE Family includes pin-compatible products in all popular packages.
Table 2. ATF15xxAE Family Device Packages and Number of Signal Pins(1)(2)
Packages
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
44-pin PLCC
44-pin TQFP
49-ball BGA
84-pin PLCC
100-pin TQFP
100-ball BGA
144-pin LQFP
169-ball BGA
208-pin PQFP
256-ball BGA
36
36
36
36
41
68
84
68
68
84
84
84
100
100
120
120
164
164
176
212
100
Notes: 1. Contact Atmel for up-to-date information on device and package availability.
2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing
(BST), the four associated pins become JTAG pins and are unavailable for user I/O.
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
Functional
Description
The ATF15xxAE Family of 3.3 Volt supply, high-performance, high-density complex program-
mable logic devices (CPLDs) utilizes Atmel’s proven electrically-erasable technology. With up
to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF15xxAE Family’s enhanced macrocell architecture, switch matrices and routing
increase usable gate count for new designs and increase odds of successful pin-locked
design modifications while maintaining pin-compatibility with industry-standard CPLDs.
The ATF15xxAE Family devices have four dedicated input pins and depending on the type of
device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these control
signals can be selected for use individually within each macrocell. Each input and I/O pin also
feeds into the global bus.
The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in
each logic block selects 40 individual signals from the global bus. Macrocells within a given
logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic
between macrocells in the Logic Block allows fast, efficient generation of complex logic func-
tions. All macrocells are capable of being I/Os; however, the actual number of I/O pins
depends on the device and package type. The ATF15xxAE Family members contain two, four,
eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a
fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.
Unused macrocells are automatically disabled by the fitter software to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the other fuses. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF15xxAE Family devices are In-System Programmable (ISP) devices. They use the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via software.
Global Bus/Switch
Matrix
The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback
signals from all macrocells. The switch matrix in each logic block receives as its inputs all sig-
nals from the global bus. Up to 40 of these signals can be selected as inputs to the individual
logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch
matrix signal distribution structure, where each logic block input has access to the same num-
ber of global bus inputs, maximizing the number of possible ways to route a global bus signal.
This single level structure is in contrast with split switch matrix structures used by others in
which routing a particular global bus input to a particular logic block input makes that signal
unavailable to some other logic blocks, thus greatly limiting the available opportunities to
route.
The ATF15xxAE Family macrocell, shown in Figure 2, consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and
output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can
generate a foldback logic term from the product term mux and a buried feedback with extra
routing that go to the global bus.
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2398H–PLD–8/03
Figure 1. ATF15xxAE Family Typical Block Diagram
2 to 16
N
2 to 16
N-1
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
Figure 2. ATF15xxAE Family Macrocell with Enhanced Features In Red
Product Terms and
Select Mux
Within each macrocell are five product terms. Each product term may receive as its inputs any
combination of the signals from the switch matrix or regional foldback bus. The product term
select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic
gates and control signals. The PTMUX programming is determined by the fitter software,
which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can
be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input
allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-
tion of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JK-
type flip-flops, or fed to the buried feedback to synthesize an extra latch.
Foldback Bus
Each macrocell can also generate a foldback product term. This signal goes to the regional
bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse
polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred
method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms
in each region can also generate additional fan-in sum terms with nominal additional delay.
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2398H–PLD–8/03
Flip-flop
The ATF15xxAE Family’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output or vice-versa. (This enhanced function is automatically implemented by
the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes
state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode,
data passes through when the clock is high and is latched when the clock is low.
When a GCK signal is used as the clock, one of the macrocell product terms can be selected
as a clock enable. When the clock enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The
flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product
term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-
nous preset (AP) can be a product term or always off.
Extra Feedback
I/O Control
The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered. (This enhanced function is automatically
implemented by the fitter software) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Programmable
Pin-keeper Option
for Inputs and I/Os
The ATF15xxAE Family offers the option of programming all input and I/O pins with pin-keeper
circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin
keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input
and I/O lines from floating to intermediate voltage levels, which causes unnecessary power
consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up
resistors and eliminate their DC power consumption.
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
Input Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
I/O Diagram
PROGRAMMABLE
OPTION (PIN KEEPER)
Speed/Power
Management
The ATF15xxAE Family has several speed and power management features.
Multiple Power
Supplies, Power
Sequencing and
Hot-Socketing
Because the ATF15xxAE Family can be used in a system with mixture of power supply volt-
ages, it has been designed to function with the VCCINT and VCCIO power supplies applied in any
sequence. Also, until the power up sequence completes, the input/output buffers are kept in a
high impedance state, and so may be driven but do not drive power out.
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2398H–PLD–8/03
Power-on Reset
The ATF15xx Family devices are designed with a power-on reset, a feature critical for state
machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be
initialized, and the state of each output will depend on the polarity of its buffer. However, due
to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system,
the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3. The clock must remain stable during TD.
The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and
Large. To ensure a robust operating environment in applications where the device is operated
near 3.0V, Atmel recommends that during the fitting process users configure the device with
the Power-on Reset hysteresis set to Large.
Power Down of
Unused
To conserve power, Atmel fitters automatically power down all unused macrocells.
Macrocells
Input Transition
Detection/
Automatic Power
Down
The ATF15xxAEL versions provide automatic power down to µA level standby power (the “L”
suffix indicates “low” power) through Atmel’s patented Input Transition Detection (ITD) circuitry
on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a low-
power standby mode when no logic transitions are occurring. This reduces power consump-
tion during inactive periods, and so provides proportional power-savings for most applications
running at system speeds below fcritical (~5 MHz).
In clocked applications where the device is operated at a frequency high enough to keep the
device from going into standby (above fcritical), the device will perform at the faster speeds
given in the next faster speed column. These higher speeds can be achieved in combinatorial
designs as well, as long as, once activated by an initial input transition, the device continues to
receive input transitions often enough to keep the device from going into standby mode again.
That is, the time between input transitions is less than 1/fcritical
.
Reduced-Power
per Macrocell
To further reduce power, each ATF15xx Family macrocell has a reduced-power bit feature.
With this feature the designer can reduce power by 50% or more for logic that does not need
to operate at the maximum switching speed. The reduced-power bit may be activated by
changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power
mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down
AC characteristic parameters are computed from external input or I/O pins, with the reduced-
power bit turned on.
Slew Rate Control
Each output also has individual slew rate control. This may be used to reduce system noise by
slowing down outputs that do not need to operate at maximum speed. Outputs default to slow
switching. The slew rate option is selected in the design source file.
Pin Controlled
Power-down
All ATF15xx Family devices also have an optional pin-controlled power-down mode. When
activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device
goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply
current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as
are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.
Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
latches remain active to ensure that pins do not float to indeterminate levels, further reducing
system power. All pin transitions are ignored until the PD pin is brought low. When the power-
down feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output.
However, the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals. The power-down option is selected in the design source file.
Power
Consumption
Estimates
An estimate of power consumption can be made based on typical designs and operation con-
ditions, but because it is sensitive to these factors, power consumption must be verified with
actual pattern and operation conditions. The equations given below are based on a pattern of
16-bit up/down counters in each logic block and may be used to estimate power consumption
for both operating modes.
Standby Power
1. Pstandby = Iccstandby x Vsupply
Where:
Iccstandby = the standby current given for the particular device and standby mode (e.g., pin con-
trolled Power Down)
Vsupply= the power supply voltage
Active Power
2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload
Where:
Iccinternal = the internal current estimated from equation 3 below
Vsupply= the power supply voltage
Pload = depends on the device output load capacitance and switching frequency on each out-
put pin.
Pload and additional power savings at low frequencies using Atmel Input Transition Detection
(“L” versions) can be estimated according to the methods discussed in the Atmel Application
Note “Saving Power with Atmel PLDs”
3.
I
ccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop
x
NS)
Where:
MCreducedpower = the number of macrocells operating at reduced power (from fitter report file)
MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are pow-
ered down.)
NS = the proportion of logic nodes switching (typically 10-20%)
fop = the switching frequency
K1, K2,and K3 = device constants given in the table below.
Device
K1
0.6
0.6
0.6
0.6
0.6
K2
0.3
0.3
0.3
0.3
0.3
K3
ATF1502AE
ATF1504AE
ATF1508AE
ATF1516AE
ATF1532AE
0.015
0.015
0.015
0.015
0.015
Note:
Shaded data is preliminary and subject to change without notice.
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2398H–PLD–8/03
Design
Software
Atmel ATF15xx Family fitters allow logic synthesis using a variety of high-level description lan-
guages and formats. ATF15xx Family designs are supported by Atmel specific design tools as
well as by several third-party tools. Free conversion software is also offered for industry stan-
dard devices. Check the Atmel web site or contact your authorized Atmel sales representative
for up-to-date design software information.
Programming
ATF15xx Family devices can be programmed using standard third-party programmers. With
third-party programmers, the JTAG ISP port can be disabled thereby allowing four additional
I/O pins to be used for logic. Check the Atmel web site, contact your authorized Atmel sales
representative or Atmel PLD Applications for details of third-party programmers.
ATF15xx Family devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG
protocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes. Atmel provides ISP hardware and soft-
ware to allow programming of the ATF15xx Family via the PC. ISP is performed by using
either a download cable, a compatible board tester or a simple microprocessor interface.
It is most common to devote the JTAG pins to ISP, but it is possible to use ISP to program the
part through the JTAG pins, and set these four pins I/O pins. However, this will effectively dis-
able further ISP and the device will need to be erased on a programmer to re-enable ISP.
Contact Atmel PLD Applications by e-mail at pld@atmel.com or call our Hotline at (408) 436-
4333 for details.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE
tester formats is also possible. Check the Atmel web site for up-to-date programming and soft-
ware support information.
ISP
The ATF15xx Family also incorporates a protection feature that locks the device and prevents
the inputs and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option
preserves the former state during device programming.
Programming
Protection
All ATF15xx Family devices are initially shipped in the erased state thereby making them
ready to use for ISP.
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF15xx Family fuse pat-
terns. Once programmed, fuse verify is inhibited. However, the User Signature and device ID
remain accessible.
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
JTAG-BST
Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP)
controller. The boundary-scan technique involves the inclusion of a shift-register stage (con-
tained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing principles. Each input pin and
I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The
ATF15xxAE Family does not currently include a Test Reset (TRST) input pin because the TAP
controller is automatically reset at power-up. The ATF15xx Family implements six BST instruc-
tions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx
Family BST and ISP instructions have a length of 10 bits.
JTAG BST Instructions
Description
SAMPLE/PRELOAD
Captures signals at the device pins for later examination,
or loads a data pattern prior to an EXTEST instruction.
EXTEST
Allows testing of off-chip circuitry and interconnections
by forcing a pattern on the output pins or capturing
signals from the input pins.
BYPASS
Places a single shift register stage between TDI and
TDO, allowing test BST data to pass through a particular
device in a chain of devices.
IDCODE
Places the 32-bit IDCODE register between TDI and
TDO, allowing the IDCODE data to be shifted out of
TDO.
UESCODE
HIGHZ
Places the 16-bit user electronic signature register
between TDI and TDO, allowing the UESCODE data to
be shifted out of TDO.
Places the BYPASS register between TDI and TDO in a
high impedance mode, protecting the device from
damage from externally applied test signals.
7 ISP instructions
These seven instructions allow in-system programming
via the four JTAG pins.
The ATF15xx Family BST implementation complies with the Boundary-scan Definition Lan-
guage (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party
tool that supports the BSDL format can be used to perform BST on the ATF15xx Family.
The ATF15xx Family also has the option of using four JTAG-standard I/O pins for in-system
programming (ISP). The ATF15xx Family is programmable through the four JTAG pins using
programming-compatible with the IEEE JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins. Refer to Atmel Application Note “Designing for In-System Programmabil-
ity with Atmel CPLDs for more details.
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2398H–PLD–8/03
JTAG
The ATF15xx Family has four dedicated input pins and a number of I/O pins depending on the
device type and package type selected. Each input pin and I/O pin has a boundary-scan cell
(BSC) which supports boundary-scan testing as described in detail by IEEE Standard 1149.1.
A typical BSC consists of three capture registers or scan registers and up to two update regis-
ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The
BSCs in the device are chained together through the (BST) capture registers. Input to the cap-
ture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by
the JTAG TAP controller.
Boundary-scan
Cell (BSC)
Testing
IDCODE
Boundary-Scan
Register Length
Device
MSB
LSB
ATF1502AE
ATF1504AE
ATF1508AE
ATF1516AE
ATF1532AE
96
192
352
672
1232
0000,0001,0101,0100,0010,0000,0011,1111
0000,0001,0101,0100,0100,0000,0011,1111
0000,0001,0101,0100,1000,0000,0011,1111
0000,0001,0101,0101,0000,0000,0011,1111
0000,0001,0101,0110,0000,0000,0011,1111
Note:
Shaded data is preliminary and subject to change without notice.
Boundary-scan
Definition
Language
These are now available in all package types via the Atmel web site. These models conform to
the IEEE 1149.1 standard and can be used for Boundary-scan Test Operation of the ATF15xx
Family.
(BSDL) Models
The BSC configuration for the input and I/O pins and macrocells are shown below.
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
BSC
Configuration
for Pins (Except
JTAG TAP Pins)
.
BSC
Configuration
for Macrocell
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
Register
Update
Register
Mode
TDI
Clock
Shift
Macrocell BSC
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2398H–PLD–8/03
PCI Compliance
The ATF15xx Family also supports peripheral component interconnect (PCI) interface stan-
dard in PCI-based designs and specifications. The PCI interface calls for high current drivers,
which are much larger than the traditional TTL drivers.
PCI Voltage-to-
current Curves for
+5V Signaling in
Pull-up Mode
Pull Up
VCC
Test Point
2.4
DC
drive point
1.4
AC drive
point
Current (mA)
-44
-2
-178
PCI Voltage-to-
current Curves for
+5V Signaling in
Pull-down Mode
Pull Down
VCC
2.2
AC drive
point
DC
drive point
0.55
Test Point
Current (mA)
95
3,6
380
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ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
Timing Model
U
Pin Capacitance
Typ(1)
Max
8
Units
pF
Condition
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
pF
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Input Test Waveforms and Measurement Levels
Output AC Test Loads
3.3V
(2.5V)
703
(521
)
C = C
L
8060
(481 )
15
2398H–PLD–8/03
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Ambient Temperature Under Bias.................. -65°C to +135°C
Storage Temperature..................................... -65°C to +150°C
Junction Temperature ..............................................150°C(MAX)
Voltage on Any Pin with
Respect to Ground .......................................-2.0V to +5.75V(1)
Voltage on Input Pins
Note:
1. For currents less than 100 mA, minimum voltage
is -0.6 VDC and maximum voltage is VCC
with Respect to Ground
+
During Programming.....................................-2.0V to +14.0V(1)
0.75 VDC. Pulses of less than 20µs may under-
shoot to -2.0V or overshoot to 5.75V.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC Output Current per Pin ................................ -25 to +25 mA
DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
–
Operating Temperature (Ambient), TA
0°C - 70°C
–
(1)
Junction Temperature, TJ
V
CCINT (3.3V) Power Supply
VCCIO (3.3V) Power Supply
CCIO (2.5V) Power Supply
3.0V - 3.6V
3.0V - 3.6V
2.3V - 2.7V
3.0V - 3.6V
3.0V - 3.6V
2.3V - 2.7V
-0.5V - 5.75V
0 - VCCIO
V
VI Input Voltage
-0.5V - 5.75V
0 - VCCIO
VO Output Voltage
tR Input Rise Time
tF Input Fall Time
40 ns Max
40 ns Max
40 ns Max
40 ns Max
Note:
1. Junction temperature is package and device dependant and can be calculated as follows: TJ(MAX) = TA(MAX) + (θJA|Air Flow =
0*P(MAX)). For more information, see “Thermal Characteristic’s of Atmel Packages”
16
ATF15xxAE Family [Preliminary]
2398H–PLD–8/03
ATF15xxAE Family [Preliminary]
DC Characteristics(1)
Symbol Parameter
Condition
Min
-10
-10
Typ
Min
10
Unit
µA
II
Input Leakage Current
VIN = VCCINT or Ground
VO = VCCINT or GND
IOZ
ICC1
Tri-State Output Off-State Current
Power Supply Current, Standby
10
µA
VCCINT = Max
IN = 0, VCCINT
Std Mode
Com.
Ind.
Note 3
Note 3
1
mA
mA
mA
mA
mA
V
“ITD”
Mode
Com.
Ind.
1
ICC2
Power Supply Current,
Power-down Mode
VCCINT = Max
IN = 0, VCCINT
PD Mode
0.1
1
V
(2)
ICC3
Reduced-power Mode Supply
Current, Standby
VCCINT = Max
IN = 0, VCCINT
Std Mode
Com.
Ind.
Note 3
Note 3
mA
mA
V
V
VIL
VIH
VOL
Input Low Voltage
-0.5
1.7
0.8
5.75
0.45
0.45
0.2
0.2
.2
Input High Voltage
V
3.3V Output Low Voltage (TTL)
VCCIO = 3.0V, IOL = 8 mA
Com.
Ind.
V
V
3.3V Output Low Voltage (CMOS)
2.5V Low Voltage
V
CCIO = 3.0V, IOL = 0.1 mA
Com.
Ind.
V
V
IOL = 100 µA, VCCIO = 2.3V
OL = 1 mA, VCCIO = 2.3V
V
I
.4
V
IOL = 2 mA, VCCIO = 2.3V
VCCIO = 3.0V, IOH = -2.0 mA
.7
V
VOH
Output High Voltage -3.3V (TTL)
Output High Voltage -3.3V (CMOS)
2.4
V
V
IN = VIH or VIL
VCCIO
-0.2
V
VCCIO = 3.0V, IOH = -0.1 mA
2.5V High Voltage
IOH = -100 µA, VCCIO = 2.3V
2.1
2.0
1.7
V
V
V
I
OH = -1 mA, VCCIO = 2.3V
I
OH = -2 mA, VCCIO = 2.3V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
3. See Characterization Curves for each device.
Power-down AC Characteristics(1)
-4, -5
-7
-10
-12
-15
Symbol Parameter
Min
Max
Min
7.5
7.5
7.5
Max
Min
10
Max
Min
12
Max
Min
15
Max
Unit
ns
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
Valid 1, I/O before PD High
4.5
4.5
4.5
Valid 1, OE(2) before PD High
Valid 1, Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
10
12
15
ns
10
12
15
ns
9.0
9.0
9.0
1.0
15
15
15
1.0
20
20
20
1.0
22
22
22
1.0
25
25
25
1.0
ns
ns
ns
µs
17
2398H–PLD–8/03
Power-down AC Characteristics(1)
-4, -5
-7
-10
-12
-15
Symbol Parameter
Min Max
Min
Max
1.0
Min
Max
1.0
Min
Max
1.0
Min
Max
1.0
Unit
µs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE, (Pin or Term)
1.0
1.0
1.0
PD Low to Valid Clock, (Pin or Term)
1.0
1.0
1.0
1.0
µs
PD Low to Valid Output
1.0
1.0
1.0
1.0
µs
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
AC Characteristics ATF1502AE(L)(1)
AE -4
AE -7
AE -10
AEL-15(6)
Min Max
Symbol
tPD1
Parameter
Min
Max
4.5
Min
Max
Min
Max
Unit
ns
Input or Feedback to Non-registered Output
7.5
7.5
10
10
15
12
tPD2
I/O Input or Feedback to Non-registered
Feedback
4.5
ns
tSU
tH
tFSU
tFH
tCOP
tCH
Global Clock Setup Time
Global Clock Hold Time
2.9
0.0
2.5
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
4.7
0.0
3.0
0.0
1.0
3.0
3.0
2.5
0.5
1.0
3.0
3.0
6.3
0.0
3.0
0.0
1.0
4.0
4.0
3.6
0.5
1.0
4.0
4.1
11
0.0
3.0
1.0
1.0
5.0
5.0
4.0
4.0
1.0
6.0
6.0
ns
ns
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
ns
MHz
ns
3.0
4.3
5.0
7.2
6.7
9.4
8.0
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
Array Clock Output Delay
Array Clock High Time
15
ns
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
4.4
4.4
7.2
7.2
9.7
9.7
13
13
ns
(3)
fCNT
225
133
100
77
MHz
ns
tACNT
(4)
fACNT
225
230
133
140
100
100
77
77
MHz
MHz
ns
(5)
fMAX
tIN
tIO
0.7
0.7
2.3
1.9
0.5
1.5
0.6
0.0
1.2
1.2
2.8
3.1
0.8
2.5
1.0
0.0
1.5
1.5
3.4
4.0
1.0
3.3
1.2
00
2.0
2.0
2.0
8.0
1.0
6.0
3.5
3.0
ns
tFIN
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
Foldback Term Delay
ns
Cascade Logic Delay
ns
Logic Array Delay
ns
Logic Control Delay
ns
Internal Output Enable Delay
ns
18
ATF1502AE(L)
2398H–PLD–8/03
ATF1502AE(L)
AC Characteristics ATF1502AE(L)(1) (Continued)
AE -4
AE -7
AE -10
AEL-15(6)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tOD1
Output Buffer and Pad Delay
0.8
1.3
1.8
3.0
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V;
CL= 35pF)
1.3
5.8
1.8
2.3
6.8
3.0
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
6.3
5.0
tZX1
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
4.0
4.5
4.0
4.5
5.0
5.5
7.0
7.0
ns
ns
tZX2
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 3.3V;
CL= 35pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
9.0
4.0
9.0
4.0
10.0
5.0
10
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5pF)
Register Setup Time
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
0.6
1.0
1.5
2.0
1.0
1.5
1.5
2.8
1.3
1.5
1.5
4.0
4.0
2.0
2.0
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
0.7
0.6
1.2
0.6
0.8
1.2
1.2
0.9
2.5
1.2
1.0
2.0
1.0
1.3
1.9
1.9
1.5
4.0
1.5
1.3
2.5
1.2
1.9
2.6
2.6
2.1
5.0
2.0
2.0
7.0
7.0
1.0
5.0
5.0
2.0
14
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
tEN
Register Enable Time
Global Control Delay
tGLOB
tPRE
tCLR
tUIM
Register Preset Time
Register Clear Time
Switch Matrix Delay
(2)
tRPA
Reduced Power Adder
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipeline data.
6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical
the device will achieve the speeds of the -10 column. (See “ITD/automatic power down.”)
,
19
2398H–PLD–8/03
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-10
-20
-30
-40
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
20
ATF1502AE(L)
2398H–PLD–8/03
ATF1502AE(L)
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-20
40
30
20
10
0
-40
TBD
-60
TBD
-80
-100
-120
-10
-20
-30
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
INPUT VOLTAGE (V)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
21
2398H–PLD–8/03
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
22
ATF1502AE(L)
2398H–PLD–8/03
ATF1502AE(L)
ATF1502AE(L) Pinouts
44-lead PLCC
TDI/I/O
I/O
7
8
9
39 I/O
38 I/O/TDO
37 I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
35 VCC
34 I/O
ATF1502AE(L)
ATF1504AE(L)
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
VCC 15
I/O 16
30 GND
29 I/O
I/O 17
44-lead TQFP
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
32 I/O/TDO
31 I/O
30 I/O
29 VCC
28 I/O
27 I/O
26 I/O/TCK
25 I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
ATF1502AE(L)
ATF1504AE(L)
VCC
I/O 10
I/O 11
24 GND
23 I/O
23
2398H–PLD–8/03
ATF1502AE(L) Dedicated Pinouts
44-lead
J-lead
44-lead
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
2
1
40
39
44
38
INPUT/GCLK1
I/O/GCLK3
43
37
41
35
I/O/PD (1,2)
I/O/TDI (JTAG)
I/O/TMS (JTAG)
I/O/TCK (JTAG)
I/O/TDO (JTAG)
GNDINT
11, 25
7
5, 19
1
13
7
32
26
38
32
22, 42
10, 30
3, 23
15, 35
36
16, 36
4, 24
17, 41
9, 29
36
GNDIO
VCCINT
VCCIO
# of Signal Pins
# User I/O Pins
32
32
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O drivers
VCCINT VCC pins for the internal device logic (+3.3V)
VCCIO VCC for the I/O drivers
24
ATF1502AE(L)
2398H–PLD–8/03
ATF1502AE(L)
ATF1502AE(L) I/O Pinouts
MC
PLC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
44-lead PLCC
44-lead TQFP
1
4
42
43
44
1
2
5
3
6
4/TDI
5
7
8
2
6
9
3
7/PD1
8
11
12
13
14
16
17
18
19
20
21
41
40
39
38
37
36
34
33
32
31
29
28
27
26
25
24
5
6
9/TMS
10
7
8
11
10
11
12
13
14
15
35
34
33
32
31
30
28
27
26
25
23
22
21
20
19
18
12
13
14
15
16
17
18
19
20/TDO
21
22
23
24
25/TCK
26
27
28
29
30
31/PD2
32
25
2398H–PLD–8/03
ATF1502AE(L) Ordering Information
tPD
tCO1
(ns)
FMAX
(ns)
(MHz)
Ordering Code
Package
Operation Range
4.5
7.5
3.0
230
140
ATF1502AE-4 AC44
ATF1502AE-4 JC44
44A
44J
Commercial
(0°C to 70°C)
5.0
ATF1502AE-7 AC44
ATF1502AE-7 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502AE-7 AI44
ATF1502AE-7 JI44
44A
44J
Industrial
(-40°C to +85°C)
10.0
15.0
6.7
8.0
100
77
ATF1502AE-10 AC44
ATF1502AE-10 JC44
44A
44J
Commercial
(0°C to 70°C)
ATF1502AE-10 AI44
ATF1502AE-10 JI44
44A
44J
Industrial
(-40°C to +85°C)
ATF1502AEL-15 AC44
ATF1502AEL-15 JC44
44A
44J
Commercial
(0°C to 70°C)
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
44A
44J
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
26
ATF1502AE(L)
2398H–PLD–8/03
ATF1504AE(L)
AC Characteristics ATF1504AE(L) (1)
AE -4
Min Max
4.5
AE -7
AE -10
AEL -15(6)
Symbol Parameter
Min
Max
Min
Max
10
Min Max
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
7.5
7.5
15
4.5
10
12
ns
2.8
4.7
0.0
3.0
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
6.2
0.0
3.0
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
11
0.0
3.0
1.0
ns
tH
Global Clock Hold Time
0.0
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
2.5
ns
0.0
MHz
ns
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
3.1
4.3
5.1
7.2
7.0
9.6
1.0
5.0
5.0
5.0
4.0
1.0
6.0
6.0
9.0
ns
tCL
Global Clock Low Time
ns
tASU
tAH
Array Clock Setup Time
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
Array Clock Output Delay
15
ns
Array Clock High Time
ns
Array Clock Low Time
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
4.5
4.5
7.4
7.4
10
10
13
13
ns
(3)
fCNT
225
133
100
77
MHz
ns
tACNT
(4)
fACNT
225
230
133
140
100
100
77
77
MHz
MHz
ns
(5)
fMAX
tIN
0.6
0.6
2.5
1.8
0.4
1.5
0.6
0.0
0.8
1.1
1.1
3.0
3.0
0.7
2.5
1.0
0.0
1.3
1.4
1.4
3.7
3.9
0.9
3.2
1.2
00
2.0
2.0
2.0
8.0
1.0
6.0
3.5
3.0
3.0
tIO
ns
tFIN
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
ns
Cascade Logic Delay
ns
Logic Array Delay
ns
Logic Control Delay
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
1.8
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
1.3
5.8
1.8
6.3
2.3
6.8
3.0
5.0
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V; CL=
35pF)
tZX1
Output Buffer Enable Delay
4.0
4.0
5.0
7.0
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
27
2398H–PLD–8/03
AC Characteristics ATF1504AE(L) (Continued)(1)
AE -4
AE -7
AE -10
AEL -15(6)
Min Max
7.0
Symbol Parameter
tZX2 Output Buffer Enable Delay
Min Max
Min
Max
Min
Max
Unit
4.5
4.5
5.5
ns
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V; CL=
35pF)
9.0
9.0
10.0
10
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5pF)
Register Setup Time
4.0
1.3
4.0
5.0
6.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
1.0
1.5
1.5
2.9
1.3
1.5
1.5
tH
Register Hold Time
0.6
4.0
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
1.0
2.0
1.5
2.0
tRD
0.7
1.2
0.9
1.9
1.0
1.5
2.1
2.1
1.7
4.0
1.6
1.3
2.5
1.2
2.2
2.9
2.9
2.3
5.0
2.0
tCOMB
tIC
Combinatorial Delay
0.6
2.0
Array Clock Delay
1.2
6.0
tEN
Register Enable Time
Global Control Delay
0.6
6.0
tGLOB
tPRE
tCLR
tUIM
1.0
2.0
Register Preset Time
Register Clear Time
1.3
4.0
1.3
4.0
Switch Matrix Delay
1.0
2.0
(2)
tRPA
Reduced Power Adder
3.5
10
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipeline data.
6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical
the device will achieve the speeds of the -10 column. (See “ITD/automatic power down.”)
,
28
ATF1504AE(L)
2398H–PLD–8/03
ATF1504AE(L)
NORMALIZED ICC VS. TEMP
STAND-BY ICC VS.
1.4
1.2
1.0
0.8
0.6
0.4
SUPPLY VOLTAGE (TA = 25°C)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
0
-10
-20
-30
-40
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
48
46
44
42
40
38
36
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
29
2398H–PLD–8/03
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
30
ATF1504AE(L)
2398H–PLD–8/03
ATF1504AE(L)
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
31
2398H–PLD–8/03
ATF1504AE(L) Pinouts
44-lead PLCC – Top View
44-lead TQFP – Top View
TDI/I/O
I/O
7
8
9
39 I/O
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
32 I/O/TDO
31 I/O
30 I/O
29 VCC
28 I/O
27 I/O
26 I/O/TCK
25 I/O
24 GND
23 I/O
38 I/O/TDO
37 I/O
I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
35 VCC
34 I/O
ATF1502AE(L)
ATF1504AE(L)
ATF1502AE(L)
ATF1504AE(L)
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
VCC 15
I/O 16
VCC
I/O 10
I/O 11
30 GND
29 I/O
I/O 17
100-lead TQFP
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIO
I/O/TDI
I/O
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
64 I/O
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
I/O 13
63 I/O
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 17
59 GND
58 I/O
VCCIO 18
I/O 19
57 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
32
ATF1504AE(L)
2398H–PLD–8/03
ATF1504AE(L)
ATF1504AE(L)
49-ball 0.8 mm Pitch
Bottom View
A
B
C
D
E
F
G
7
6
5
4
3
2
1
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
100-ball 1.0 mm Pitch
Bottom View
A
B
C
D
E
F
G
H
J
K
10
9
8
7
6
5
4
3
2
1
33
2398H–PLD–8/03
ATF1504AE(L) Dedicated Pinouts
44-lead
TQFP
44-lead
49-ball
BGA
100-ball
BGA
100-lead
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
J-lead
40
39
2
B4
A3
A5
B5
90
89
1
38
44
A4
B6
88
INPUT/GCLK1
I/O /GCLK3
37
43
A5
A6
87
35
41
C4
C6
85
I/O/PD (1,2)
5, 19
1
11, 25
7
D1, G5
B1
E1, H6
A1
12, 42
4
I/O/TDI (JTAG)
I/O/TMS (JTAG)
I/O/TCK (JTAG)
I/O/TDO (JTAG)
GNDINT
7
13
F1
F3
15
26
32
F7
F8
62
32
38
B7
A10
73
16, 36
22, 44
C2, E6
C3, D6, D7, E5,
F6, G4, G5, H8
38, 86
GNDIO
4, 24
10, 30
B5, F4
–
11, 26, 43,
59, 74, 95
VCCINT
VCCIO
17, 41
9, 29
3, 23
B3, E4
C6, E2
D5, G6
39, 91
15, 35
C8, D4, E6,
F5, G7, H3
3, 18, 34,
51, 66, 82
N/C
-
-
-
B1, B10, C1, C9,
C10, D8, E3, E4,
H1, H9, H10, J1,
J2, J10, K1, K9
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
# of Signal Pins
# User I/O Pins
36
32
36
32
41
37
68
64
68
64
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GNDINT Ground pins for the internal device logic
GNDIO Ground pins for the I/O pins
VCCINT VCC pins for the internal device logic
VCCIO VCC for the I/O drivers
34
ATF1504AE(L)
2398H–PLD–8/03
ATF1504AE(L)
ATF1504AE(L) I/O Pinouts
100-
ball
100-
lead
100-
ball
100-
lead
44-lead 44-lead 49-ball 84-lead
44-lead 44-lead 49-ball 84-lead
MC
1
PLC
A
PLCC
TQFP
BGA
D2
-
PLCC
BGA
TQFP
MC
33
PLC
C
PLCC
TQFP
BGA
E5
-
PLCC
BGA
TQFP
12
-
6
-
22
F4
E2
14
13
24
-
18
-
44
K6
J6
40
41
2
A
21
34
C
45
A/
PD1
C/
PD2
3
11
5
D1
20
E1
12
35
25
19
G5
46
H6
42
4
5
6
7
A
A
A
A
9
8
-
3
2
-
D4
C1
-
18
17
16
15
D2
D1
D3
C2
10
9
36
37
38
39
C
C
C
C
26
27
-
20
21
-
F5
G6
-
48
49
50
51
K7
J7
44
45
46
47
8
H7
J8
-
-
-
6
-
-
G7
8/
TDI
A
7
1
B1
14
A1
4
40
C
28
22
F6
52
K8
48
9
A
A
A
A
A
A
A
-
-
-
-
B2
-
12
11
10
9
B2
A2
A3
B3
A4
B4
C4
100
99
98
97
96
94
93
41
42
43
44
45
46
47
C
C
C
C
C
C
C
29
-
23
-
D5
54
55
56
57
58
60
61
K10
J9
52
54
56
57
58
60
61
10
11
12
13
14
15
-
-
6
-
44
-
A1
-
-
-
G9
G10
G8
F9
-
-
-
-
-
-
8
-
-
-
5
-
43
-
A2
-
6
31
-
25
-
E7
-
5
F10
48/
TCK
16
A
4
42
C3
4
C5
92
C
32
26
F7
62
F8
62
17
18
19
20
21
22
23
B
B
B
B
B
B
B
21
-
15
-
G4
E3
G3
F3
G2
G1
-
41
40
39
37
36
35
34
K5
J5
37
36
35
33
32
31
30
49
50
51
52
53
54
55
D
D
D
D
D
D
D
33
-
27
-
D7
-
63
64
65
67
68
69
70
F7
E9
63
64
65
67
68
69
71
20
19
18
-
14
13
12
-
H5
K4
J4
34
36
37
-
28
30
31
-
D6
C7
B6
-
E10
E8
E7
H4
J3
D9
-
-
-
-
-
D10
56/
TDO
24
B
17
11
F2
33
K3
29
D
38
32
B7
71
A10
73
25
26
27
28
29
30
31
B
B
B
B
B
B
B
16
-
10
-
D3
31
30
29
28
27
25
24
K2
H2
G2
G1
G3
F2
F1
25
23
21
20
19
17
16
57
58
59
60
61
62
63
D
D
D
D
D
D
D
39
-
33
-
A7
-
73
74
75
76
77
79
80
B9
A9
A8
B8
A7
B7
C7
75
76
79
80
81
83
84
-
-
-
-
-
-
A6
-
-
-
-
-
-
-
-
-
-
-
-
14
-
8
-
E1
-
40
-
34
-
C5
-
32/
TMS
D/
GCLK3
B
13
7
F1
23
F3
15
64
41
35
C4
81
C6
85
35
2398H–PLD–8/03
ATF1504AE(L) Ordering Information
tPD
tCO1
(ns)
fMAX
(ns)
(MHz)
Ordering Code
Package
Operation Range
4.5
3.1
225
ATF1504AE-4 AC44
ATF1504AE-4 JC44
ATF1504AE-4 CC49
ATF1504AE-4 AC100
ATF1504AE-4 CTC100
44A
Commercial
44J
(0°C to 70°C)
49C1
100A
100CT1
7.5
5.1
133
ATF1504AE-7 AC44
ATF1504AE-7 JC44
ATF1504AE-7 CC49
ATF1504AE-7 AC100
ATF1504AE-7 CTC100
44A
Commercial
44J
(0°C to 70°C)
49C1
100A
100CT1
ATF1504AE-7 AI44
ATF1504AE-7 JI44
ATF1504AE-7 CI49
ATF1504AE-7 AI100
ATF1504AE-7 CTI100
44A
Industrial
44J
(-40°C to +85°C)
49C1
100A
100CT1
10.0
7.0
100
ATF1504AE-10 AC44
ATF1504AE-10 JC44
ATF1504AE-10 CC49
ATF1504AE-10 AC100
ATF1504AE-10 CTC100
44A
Commercial
44J
(0°C to 70°C)
49C1
100A
100CT1
ATF1504AE-10 AI44
ATF1504AE-10 JI44
ATF1504AE-10 CI49
ATF1504AE-10 AI100
ATF1504AE-10 CTI100
44A
Industrial
44J
(-40°C to +85°C)
49C1
100A
100CT1
15.0
9.0
77
ATF1504AEL-15 AC44
ATF1504AEL-15 JC44
ATF1504AEL-15 CC49
ATF1504AEL-15 AC100
ATF1504AEL-15CTC100
44A
Commercial
44J
(0°C to 70°C)
49C1
100A
100CT1
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are the
same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use com-
mercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
49C1
100A
100CT1
49-lead, Chip Scale Ball Grid Array (CBGA) 0.8 mm pitch
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
100-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
36
ATF1504AE(L)
2398H–PLD–8/03
ATF1508AE(L)
AC Characteristics ATF1508AE(L) (1)
AE -5
AE -7
AE -10
AEL -15(6)
Symbol Parameter
Min
Max
Min
Max
Min
Max
10
Min
3
Max
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
5
5
7.5
7.5
10
3
ns
3.3
0
4.9
0
6.6
0
11
0
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
2.5
0
3
3
3
ns
0
0
1
MHz
ns
1
3.4
4.9
1
5
1
6.6
9.4
9
2
3
4
5
5
5
4
ns
tCL
Global Clock Low Time
2
3
4
ns
tASU
tAH
Array Clock Setup Time
1.8
0.2
1
2.8
0.3
1
3.8
0.3
1
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
Array Clock Output Delay
7.1
15
ns
Array Clock High Time
2
3
4
6
6
ns
Array Clock Low Time
2
3
4
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
5.2
5.2
7.7
7.7
10.2
10.2
13
13
ns
(3)
fCNT
193
130
100
77
MHz
ns
tACNT
(4)
fACNT
193
200
130
133
100
100
77
77
MHz
MHz
ns
(5)
fMAX
tIN
0.7
0.7
2.5
2
1
1
1.4
1.4
3.4
3.8
0.9
3.1
1.3
0
2
2
tIO
ns
tFIN
3
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
2.9
0.7
2.4
1
8
ns
Cascade Logic Delay
0.4
1.6
0.7
0
1
ns
Logic Array Delay
6
ns
Logic Control Delay
3.5
3
ns
Internal Output Enable Delay
0
ns
Output Buffer and Pad Delay
0.8
1.2
1.6
3
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
1.3
5.8
1.7
6.2
2.1
6.6
3
5
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
tZX1
Output Buffer Enable Delay
4
4
5
7
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
37
2398H–PLD–8/03
AC Characteristics ATF1508AE(L) (Continued)(1)
AE -5
AE -7
AE -10
AEL -15(6)
Symbol Parameter
tZX2 Output Buffer Enable Delay
Min
Max
Min
Max
Min
Max
Min
Max
Unit
4.5
4.5
5.5
7
ns
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
9
4
9
10
10
6
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5pF)
Register Setup Time
4
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.4
0.6
1.1
1.4
2.1
1
2.9
1.3
1.6
1.4
5
4
2
2
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
1.6
1.4
tRD
0.8
0.5
1.2
0.7
1.1
1.4
1.4
1.4
4.0
1.2
0.9
1.7
1
1.6
1.3
2.2
1.3
2
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
6
tEN
Register Enable Time
Global Control Delay
6
tGLOB
tPRE
tCLR
tUIM
1.6
2
2
Register Preset Time
Register Clear Time
2.7
2.7
2.6
5
4
2
4
Switch Matrix Delay
2
2
(2)
tRPA
Reduced Power Adder
4.0
10
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipeline data.
6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical
the device will achieve the speeds of the -10 column. (See “ITD/automatic power down.”)
,
38
ATF1508AE(L)
2398H–PLD–8/03
ATF1508AE(L)
STAND-BY ICC VS.
NORMALIZED ICC VS. TEMP
SUPPLY VOLTAGE (TA = 25°C)
1.4
1.2
1.0
0.8
0.6
0.4
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0
-10
-20
-30
-40
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
39
2398H–PLD–8/03
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
40
ATF1508AE(L)
2398H–PLD–8/03
ATF1508AE(L)
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
41
2398H–PLD–8/03
ATF1508AE(L) Pinouts
84-lead PLCC – Top View
100-lead TQFP – Top View
I/O/PD1 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
73 I/O
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
72 GND
71 I/O/TDO
70 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIO
I/O/TDI
I/O
I/O 16
I/O 17
69 I/O
71 I/O
I/O 18
68 I/O
I/O
70 I/O
GND 19
I/O 20
67 I/O
I/O
69 I/O
66 VCCIO
65 I/O
I/O
68 I/O
I/O 21
I/O
67 I/O
I/O 22
64 I/O
ATF1508AE(L)
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
I/O/TMS 23
I/O 24
63 I/O
62 I/O/TCK
61 I/O
64 I/O
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
I/O 25
I/O 13
63 I/O
VCCIO 26
I/O 27
60 I/O
I/O 14
62 I/O/TCK
61 I/O
59 GND
58 I/O
I/O/TMS 15
I/O 16
I/O 28
60 I/O
I/O 29
57 I/O
I/O 17
59 GND
58 I/O
I/O 30
56 I/O
VCCIO 18
I/O 19
I/O 31
55 I/O
57 I/O
GND 32
54 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
144-lead LQFP – Top View
1
108
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
19
90
36
42
ATF1508AE(L)
2398H–PLD–8/03
ATF1508AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
100-ball 1.0 mm Pitch
Bottom View
A
B
C
D
E
F
G
H
J
K
10
9
8
7
6
5
4
3
2
1
ATF1508AE(L)
169-ball 0.8 mm Pitch
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
13 12 11 10
9
8
7
6
5
4
3
2
1
43
2398H–PLD–8/03
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
256-ball 1.0 mm Pitch
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
44
ATF1508AE(L)
2398H–PLD–8/03
ATF1508AE(L)
ATF1508AE(L) Dedicated Pinouts
84-pin
J-Lead
100-pin
TQFP
100-ball
BGA
144-pin
LQFP
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
INPUT/OE2/GCK2
I/O/GCLK3
169-ball BGA
256-ball BGA
83
1
87
89
A6
B5
125
127
126
128
119
142, 61
4
D8
D9
D6
E8
84
88
B6
D7
E9
2
90
A5
E7
D8
81
85
C6
A8
F9
I/O PD (1,2)
TDI (JTAG)
12, 45
14
1,41
4
B1, J6
A1
D4, H8
E4, M9
E4
D4
TMS (JTAG)
TCK (JTAG)
TDO (JTAG)
GNDINT
23
15
F3
20
J4
J10
J6
62
62
F8
89
J11
D13
71
73
A10
D6, G5
104
E10
42, 82
38,86
52, 57,
A7, E8, J7, N7
A8, C9, G9, K8, P9
124, 129
GNDIO
7, 19,
32, 47,
59, 72
11, 26,
43, 59,
74, 95
C3, D7,
E5, F6,
G4, H8
3, 13, 17,
33, 59, 64,
85, 105,
135
A3, A12, E1, F5,
F13, H1, H9, J13,
N2, N11
A3, B10, C2, D14, F6, G10, H8, J9,
K7, L11, M3, P6, P10, R2, R3, T1,
T15
VCCINT
VCCIO
3, 43
39, 91
D5, G6
51, 58,
123, 130
B7, E6, H7, M7
B9, C8, G8, K9, P8
13, 26,
38, 53,
66, 78
3, 18,
34, 51,
66, 82
C8, D4,
E6, F5,
G7, H3
24, 50, 73,
76, 95,
115, 144
A2, A11, E13, F1,
F9, H5, H13, J1,
N3, N12
B3, B5, C14, E15, F11, G3, G7, G15,
H9, J8, K10, L3, L6, M15, P14, T2,
T3
No Connect
-
-
-
1, 2, 12,
19, 34, 35,
36, 43, 46,
47, 48, 49,
66, 75, 90,
103, 108,
120, 121,
122
B5, B6, B8, B9, C5,
C6, C7, C8, C9,
C10, E2, E3, E11,
E12, F2, F3, F11,
F12, G1, G3, G11,
G12, H2, H3, H11,
H12, J2, J3, J11,
J12, L4, L5, L6, L7,
L8, L9, M5, M6,
M8, M9
A1, A2, A4, A5, A6, A7, A9, A10,
A11, A12, A13, A14, A15, A16, B1,
B2, B4, B6, B7, B8, B11, B12, B13,
B14, B15, B16, C1, C3, C4, C6, C11,
C13, C15, C16, D1, D2, D3, D15,
D16, E1, E2, E3, E14, E16, F1, F2,
F15, F16, G1, G2, G14, G16, H1, H2,
H15, H16, J1, J2, J15, J16, K1, K2,
K3, K14, K15, K16, L1, L2, L15, L16,
M1, M14, M16, N1, N2, N3, N14,
N15, N16, P1, P2, P3, P4, P12, P13,
P15, P16, R1, R4, R5, R6, R7, R8,
R9, R11, R12, R13, R14, R15, R16,
T4, T5, T6, T8, T9, T10, T11, T12,
T13, T14, T16
# of Signal pins
68
64
84
80
84
80
100
96
100
96
100
96
# of User I/O pins
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
45
2398H–PLD–8/03
ATF1508AE(L) I/O Pinouts
84-pin 100-pin 100-ball 144-pin 169-ball 256-ball
84-pin 100-pin 100-ball 144-pin 169-ball 256-ball
MC
1
PLB J-Lead TQFP
BGA
C1
-
LQFP
143
-
BGA
E5
-
BGA
F4
-
MC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
PLB J-Lead TQFP
BGA
K1
-
LQFP
32
-
BGA
K4
-
BGA
N4
-
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-
-
2
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
-
-
25
-
2
3/PD1
4
12
-
1
B1
-
142
141
140
139
-
D4
B2
B3
C3
-
E4
C5
E5
D5
-
31
-
24
-
J1
-
31
30
29
28
-
J5
N1
M1
L1
-
M4
M2
L4
L5
-
-
5
11
10
-
100
99
-
B2
A2
-
30
29
-
23
22
-
H1
H2
-
6
7
8
9
-
98
97
-
A3
B3
-
138
137
-
C4
B4
-
D6
E6
-
28
-
21
20
-
G2
G1
-
27
26
-
L2
K3
-
K5
K4
-
9
10
11
12
13
14
15
-
-
8
-
96
-
A4
-
136
134
133
132
-
A4
D5
A5
F6
-
D7
C7
E7
F7
-
27
-
19
-
G3
-
25
23
22
21
-
G6
K2
H4
K1
-
K6
J3
J5
J4
-
6
5
-
94
93
-
B4
C4
-
25
24
-
17
16
-
F2
F1
-
48/
TMS
16
A
4
92
C5
131
A6
F8
C
23
15
F3
20
J4
J6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
22
-
14
-
F4
-
18
-
D1
-
J7
-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
41
-
37
-
K5
-
56
-
N6
-
N8
-
21
-
13
-
E2
-
16
15
14
11
-
G5
D2
G4
D3
-
H5
H3
H4
H6
-
40
-
36
-
J5
-
55
54
53
45
-
K7
N5
H6
N4
-
M8
P7
L8
N7
-
20
-
12
10
-
E1
E3
-
39
-
35
33
-
H5
K4
-
-
-
18
17
-
9
E4
D2
-
10
9
C1
C2
-
H7
G5
-
37
36
-
32
31
-
J4
H4
-
44
42
-
K6
M4
-
M7
L7
-
8
-
-
16
-
7
D1
-
8
G7
B1
F4
A1
-
G4
F3
G6
F5
-
35
-
30
-
J3
-
41
40
39
38
-
J6
M3
L3
M2
-
M6
P5
N6
M5
-
-
7
15
-
6
D3
C2
-
6
34
-
29
28
-
K3
J2
-
5
5
-
-
-
-
32/
TDI
B
14
4
A1
4
E4
D4
64
D
33
27
K2
37
K5
N5
46
ATF1508AE(L)
2398H–PLD–8/03
ATF1508AE(L)
ATF1508AE(L) I/O Pinouts
84-pin 100-pin 100-ball 144-pin 169-ball 256-ball
84-pin 100-pin 100-ball 144-pin 169-ball 256-ball
MC
65
PLB J-Lead TQFP
BGA
K6
-
LQFP
BGA
L10
-
BGA
N9
-
MC
97
PLB J-Lead TQFP
BGA
F7
-
LQFP
BGA
G13
-
BGA
J10
-
E
E
44
-
40
-
60
-
G
G
63
-
63
-
91
-
66
98
67/
PD2
E
45
41
J6
61
H8
M9
99
G
64
64
E9
92
G10
H12
68
69
70
71
72
73
74
75
76
77
78
79
E
E
E
E
E
E
E
E
E
E
E
E
-
46
-
-
-
62
63
65
-
N8
K8
N9
-
R10
L9
100
101
102
103
104
105
106
107
108
109
110
111
G
G
G
G
G
G
G
G
G
G
G
G
-
65
-
-
-
E10
E8
-
93
94
96
-
D13
G9
D12
-
H14
H13
H11
-
42
44
-
H6
K7
-
65
67
-
N10
-
-
-
48
49
-
45
46
-
J7
H7
-
67
68
-
J8
M10
L10
-
67
68
-
68
69
-
E7
D9
-
97
98
-
D11
C13
-
H10
G12
-
M10
-
50
-
47
-
J8
-
69
70
71
72
-
K9
N10
K10
L11
-
M11
P11
N11
N12
-
69
-
70
-
D10
-
99
100
101
102
-
F10
C12
E9
G13
F14
G11
F12
-
51
-
48
49
-
K8
K9
-
70
-
71
72
-
D8
C9
-
B13
-
-
-
112/
TDO
80
E
52
50
K10
74
M11
N13
G
71
73
A10
104
E10
D13
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
-
-
52
-
J10
-
77
-
M12
-
M13
-
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
-
75
-
C10
-
106
-
A13
-
F13
-
54
-
53
-
H10
-
78
79
80
81
-
J9
L13
L14
L12
M12
-
73
-
76
-
B10
-
107
109
110
111
-
D10
B12
D9
C11
-
E13
C12
E12
D12
-
N13
M13
L13
-
55
56
-
54
55
-
H9
J9
-
74
75
-
77
78
-
B9
A9
-
57
-
56
57
-
G9
G10
-
82
83
-
L12
K13
-
K12
K13
-
76
-
79
80
-
A8
B8
-
112
113
-
B11
B10
-
D11
E11
-
-
-
58
-
58
-
G8
-
84
86
87
88
-
G8
K12
H10
K11
-
K11
J14
J12
J13
-
77
-
81
-
A7
-
114
116
117
118
-
F8
A10
F7
A9
-
D10
C10
E10
F10
-
60
61
-
60
61
-
F9
F10
-
79
80
-
83
84
-
B7
C7
-
96/
TCK
128/
GCLK3
F
62
62
F8
89
J10
J11
H
81
85
C6
119
A8
F9
47
2398H–PLD–8/03
ATF1508AE(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
5.0
3.4
200
ATF1508AE-5 JC84
84J
Commercial
ATF1508AE-5 AC100
ATF1508AE-5 CTC100
ATF1508AE-5 AAC144
ATF1508AE-5 CC169
ATF1508AE-5 CTC256
100A
(0°C to 70°C)
100CT1
144AA
169C1
256CT1
7.5
5.0
133
ATF1508AE-7 JC84
84J
Commercial
ATF1508AE-7 AC100
ATF1508AE-7 CTC100
ATF1508AE-7 AAC144
ATF1508AE-7 CC169
ATF1508AE-7 CTC256
100A
(0°C to 70°C)
100CT1
144AA
169C1
256CT1
ATF1508AE-7 JI84
84J
Industrial
ATF1508AE-7 AI100
ATF1508AE-7 CTI100
ATF1508AE-7 AAI144
ATF1508AE-7 CI169
ATF1508AE-7 CTI256
100A
(-40°C to +85°C)
100CT1
144AA
169C1
256CT1
10.0
6.6
100
ATF1508AE-10 JC84
ATF1508AE-10 AC100
ATF1508AE-10 CTC100
ATF1508AE-10 AAC144
ATF1508AE-15 CC169
ATF1508AE-10 CTC256
84J
Commercial
100A
(0°C to 70°C)
100CT1
144AA
169C1
256CT1
ATF1508AE-10 JI84
84J
Industrial
ATF1508AE-10 AI100
ATF1508AE-10 CTI100
ATF1508AE-10 AAI144
ATF1508AE-10 CI169
ATF1508AE-10 CTI256
100A
(-40°C to +85°C)
100CT1
144AA
169C1
256CT1
15.0
9.0
77
ATF1508AEL-15 JC84
ATF1508AEL-15 AC100
ATF1508AEL-15 CTC100
ATF1508AEL-15 AAC144
ATF1508AEL-15 CC169
ATF1508AEL-15 CTC256
84J
Commercial
100A
(0°C to 70°C)
100CT1
144AA
169C1
256CT1
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are the
same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use com-
mercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
100-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
144-lead, Low Profile Plastic Gull Wing Quad Flatpack (LQFP)
169-lead, Chip Scale Ball Grid Array (CBGA) 0.8 mm pitch
256-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
100CT1
144AA
169C1
256CT1
48
ATF1508AE(L)
2398H–PLD–8/03
ATF1516AE(L)
AC Characteristics ATF1516AE(L) (1)
AE -5
AE -7
AE -10
AEL -15(6)
Symbol Parameter
Min
Max
Min
Max
Min
Max
10
Min
Max
15
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
5.5
5.5
7.5
7.5
10
12
ns
3.9
0
5.2
0
6.9
0
11
0
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
2.5
0
3
3
3
ns
0
0
1
MHz
ns
1
3.5
5.4
1
4.8
7.3
1
6.4
9.7
9
2
3
4
5
5
5
4
ns
tCL
Global Clock Low Time
2
3
4
ns
tASU
tAH
Array Clock Setup Time
2.0
0.2
1
2.7
0.3
1
3.6
0.5
1
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
Array Clock Output Delay
15
ns
Array Clock High Time
2
3
4
6
6
ns
Array Clock Low Time
2
3
4
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
5.8
5.8
7.9
7.9
10.5
10.5
13
13
ns
(3)
fCNT
175
125
100
77
MHz
ns
tACNT
(4)
fACNT
175
200
125
133
100
100
77
77
MHz
MHz
ns
(5)
fMAX
tIN
0.7
0.7
2.4
2.1
0.3
1.7
0.8
0
0.9
0.9
2.9
2.8
0.5
2.2
1.0
0
1.2
1.2
3.4
3.7
0.6
2.8
1.3
0
2
2
tIO
ns
tFIN
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
8
ns
Cascade Logic Delay
1
ns
Logic Array Delay
6
ns
Logic Control Delay
3.5
3
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
0.9
1.2
1.6
3
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
1.4
5.9
1.7
6.2
2.1
6.6
3
5
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
49
2398H–PLD–8/03
AC Characteristics ATF1516AE(L) (Continued)(1)
AE -5
AE -7
AE -10
AEL -15(6)
Symbol Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Unit
tZX1
tZX2
tZX3
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
4.0
4.0
4.5
9
5.0
5.5
10
7
ns
Output Buffer Enable Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
4.5
9
7
ns
ns
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
10
tXZ
tSU
Output Buffer Disable Delay (CL= 5pF)
Register Setup Time
4
4
5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
0.7
1.1
1.4
2.1
0.9
1.6
1.4
2.9
1.2
1.6
1.4
5
4
2
2
|
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
0.9
0.5
1.2
0.8
1.0
1.6
1.6
1.7
4.0
1.2
0.8
1.6
1.0
1.5
2.3
2.3
2.4
4.0
1.6
1.2
2.1
1.3
2.1
3.0
3.0
3.2
5.0
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
6
tEN
Register Enable Time
Global Control Delay
6
tGLOB
tPRE
tCLR
tUIM
tRPA
2
Register Preset Time
Register Clear Time
4
4
Switch Matrix Delay
2
Reduced Power Adder(2)
10
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipeline data.
6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical
the device will achieve the speeds of the -10 column. (See “ITD/automatic power down.”)
,
50
ATF1516AE(L)
2398H–PLD–8/03
ATF1516AE(L)
NORMALIZED ICC VS. TEMP
STAND-BY ICC VS.
1.4
1.2
1.0
0.8
0.6
0.4
SUPPLY VOLTAGE (TA = 25°C)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT VS.
SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
INPUT FREQUENCY (VCC = 5.0V, TA = 25°C)
1.000
0.800
0.600
0.400
0.200
0.000
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
TBD
TBD
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
OUTPUT SOURCE CURRENT VS.
OUTPUT SOURCE CURRENT VS.
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
0
-10
-20
-30
-40
TBD
TBD
-50
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
VOH (V)
OUTPUT SINK CURRENT VS.
OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
48
46
44
42
40
38
36
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
TBD
TBD
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
51
2398H–PLD–8/03
INPUT CLAMP CURRENT VS.
INPUT CURRENT VS.
INPUT VOLTAGE (VCC = 5.0V, TA = 35°C)
INPUT VOLTAGE (VCC = 5.0V, TA = 25°C)
40
30
20
10
0
0
-20
-40
TBD
-60
TBD
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD VS. VCC
NORMALIZED TPD VS. TEMP
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
NORMALIZED TCO VS. VCC
NORMALIZED TCO VS. TEMP
1.3
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (V)
NORMALIZED TSU VS. VCC
NORMALIZED TSU VS. TEMP
1.2
1.2
1.1
1.0
0.9
0.8
1.1
1.0
0.9
0.8
TBD
TBD
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
52
ATF1516AE(L)
2398H–PLD–8/03
ATF1516AE(L)
DELTA TPD VS.
DELTA TCO VS.
OUTPUT LOADING
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
TBD
TBD
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TCO VS. # OF OUTPUT SWITCHING
DELTA TPD VS. # OF OUTPUT SWITCHING
0.0
-0.1
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
TBD
TBD
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
53
2398H–PLD–8/03
ATF1516AE(L) Pinouts
100-lead TQFP – Top View
144-lead LQFP – Top View
1
108
I/O/PD1
I/O
1
2
3
4
5
6
7
8
9
75 I/O
74 GND
73 I/O/TDO
72 I/O
VCCIO
I/O/TDI
I/O
71 I/O
I/O
70 I/O
I/O
69 I/O
I/O
68 I/O
I/O
67 I/O
I/O 10
GND 11
I/O 12
66 VCCIO
65 I/O
64 I/O
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
I/O 13
63 I/O
I/O 14
62 I/O/TCK
61 I/O
19
90
I/O/TMS 15
I/O 16
60 I/O
I/O 17
59 GND
58 I/O
VCCIO 18
I/O 19
57 I/O
I/O 20
56 I/O
I/O 21
55 I/O
I/O 22
54 I/O
I/O 23
53 I/O
I/O 24
52 I/O
I/O 25
51 VCCIO
36
208-lead PQFP – Top View
1
156
ATF1516AE(L)
ATF1532AE(L)
26
131
54
ATF1516AE(L)
2398H–PLD–8/03
ATF1516AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
100-ball 1.0 mm Pitch – Bottom View
A
B
C
D
E
F
G
H
J
K
10
9
8
7
6
5
4
3
2
1
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
256-ball 1.0 mm Pitch – Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
55
2398H–PLD–8/03
ATF1516AE(L) Dedicated Pinouts
100-pin
TQFP
100-ball
BGA
144-pin
LQFP
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
INPUT/OE2/GCK2
I/O/GCLK3
208-pin PQFP
256-ball BGA
87
89
A6
B5
125
127
126
128
TBD
TBD
4
184
D9
182
E8
88
B6
183
E9
90
A5
181
D8
TBD
TBD
4
TBD
TBD
A1
TBD
TBD
I/O PD (1,2)
TDI (JTAG)
TBD
TBD
176
D4
TMS (JTAG)
TCK (JTAG)
TDO (JTAG)
GNDINT
15
F3
20
127
J6
62
F8
89
30
189
J11
D13
73
A10
D6, G5
104
38, 86
52, 57, 124,
129
75, 82, 180, 185
A8, C9, G9, K8, P9
GNDIO
11, 26,
43, 59,
74, 95
C3, D7,
E5, F6,
G4, H8
3, 13, 17,
33, 59, 64,
85, 105,
135
14, 32, 50, 72, 94,
116, 134, 152, 174,
200
A3, B10, C2, D14, F6, G10, H8, J9, K7,
L11, M3, P6, P10, R2, R3, T1, T15
VCCINT
VCCIO
39, 91
D5, G6,
51, 58, 123,
130
74, 83, 179, 186
B9, C8, G8, K9, P8
3, 18, 34,
51, 66, 82
C8, D4,
E6, F5,
G7, H3
24, 50, 73,
76, 95, 115,
144
5, 23, 41, 63, 85, 107,
125, 143, 165, 191
B3, B5, C14, E15, F11, G3, G7, G15,
H9, J8, K10, L3, L6, M15, P14, T2, T3
No Connect
-
-
-
1,2, 51, 52, 53, 54,
103, 104, 105, 106,
155, 156, 157, 158,
207, 208
A1, A2, A6, A12, A13, A14, A15, A16,
B1, B2, B15, B16, C1, C15, C16, D1,
D3, D15, D16, G1, G16, H15, H16, J1,
K1, L1, L2, M1, M16, N1, N16, P1, P2,
P15, P16, R1, R14, R15, R16, T7, T8,
T10, T11, T14, T16
# of Signal pins
84
80
84
80
120
116
164
160
164
160
# of User I/O pins
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
56
ATF1516AE(L)
2398H–PLD–8/03
ATF1516AE(L)
ATF1516AE(L) I/O Pinouts
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
MC
1
PLB
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
BGA
LQFP
PQFP
153
-
BGA
C3
-
MC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PLB
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
BGA
LQFP
PQFP
108
-
BGA
N4
-
-
-
C1
-
-
-
-
36
-
2
-
-
-
3
-
-
2
154
-
C4
-
-
-
-
35
-
109
-
P3
-
4
-
-
-
-
5
-
B1
1
159
160
-
E5
D5
-
-
-
34
-
110
111
-
N3
M4
-
6
-
-
143
-
-
7
-
-
-
-
-
-
8
2
1
-
-
-
161
162
-
C5
B4
-
25
24
-
K1
J1
-
32
31
-
112
113
-
M2
L4
-
9
-
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
B2
-
-
100
-
142
163
-
A4
-
23
-
H1
-
30
-
114
-
L5
-
-
-
-
141
164
166
-
A5
D6
-
22
-
H2
-
29
-
115
117
-
K6
K5
-
99
-
A2
-
140
-
139
-
-
-
-
98
-
A3
-
167
141
-
C6
F5
-
21
31
-
G2
H4
-
28
44
-
118
92
-
K4
N6
-
-
-
-
-
-
10
-
142
-
F2
-
30
-
J3
-
43
-
93
-
T5
-
-
-
-
-
9
-
144
145
-
E1
F4
-
29
28
-
K3
J2
-
42
41
-
95
96
-
M6
R5
-
-
-
-
-
-
8
7
-
D2
D1
-
8
7
-
146
147
-
F3
E2
-
-
-
40
-
97
98
-
M5
P5
-
-
-
-
-
-
6
-
D3
-
6
-
148
-
D2
-
-
-
39
-
99
-
N5
-
-
-
5
-
C2
-
5
-
149
150
-
E3
E4
-
-
-
38
-
100
101
-
T4
R4
-
-
-
-
-
-
-
-
-
4
A1
4
151
D4
27
K2
37
102
P4
57
2398H–PLD–8/03
ATF1516AE(L) I/O Pinouts
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
MC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PLB
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
BGA
LQFP
PQFP
168
-
BGA
B6
-
MC
97
PLB
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
BGA
LQFP
PQFP
119
-
BGA
K3
-
-
-
-
-
-
-
-
-
-
-
-
98
-
-
-
-
169
-
E6
-
99
-
-
-
27
-
120
-
K2
-
-
-
-
-
138
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
-
-
170
171
-
F7
E7
-
-
-
26
-
121
122
-
J7
H7
-
-
-
-
-
-
-
-
-
-
-
97
96
-
B3
A4
-
137
136
-
172
173
-
D7
C7
-
20
19
-
G1
G3
-
25
23
-
123
124
-
J5
J2
-
94
-
B4
-
134
-
175
-
B7
-
17
-
F2
-
22
-
126
-
J3
-
93
-
C4
-
133
132
-
176
177
-
A7
F8
-
16
-
F1
-
21
-
127
128
-
J4
H6
-
-
-
-
-
-
92
-
C5
-
131
-
178
130
-
B8
H5
-
15
37
-
F3
K5
-
20
-
129
79
-
J6
M8
-
F
-
-
-
-
F
-
-
19
-
131
-
H1
-
36
-
J5
-
54
-
80
-
N8
-
F
-
-
F
-
-
18
-
132
133
-
H2
H3
-
-
-
53
-
81
84
-
L8
R7
-
F
-
-
35
-
H5
-
F
-
-
-
-
F
14
13
-
F4
E2
-
16
15
-
135
136
-
H4
G6
-
-
-
49
48
-
86
87
-
P7
N7
-
F
-
-
F
-
-
F
12
-
E1
-
14
-
137
-
G5
-
-
-
47
-
88
-
M7
-
F
-
-
F
10
-
E3
-
12
-
138
139
-
G2
G4
-
33
-
K4
-
46
-
89
90
-
L7
T6
-
F
F
-
-
-
-
-
-
F
9
E4
11
140
F1
32
J4
45
91
R6
58
ATF1516AE(L)
2398H–8/03
ATF1516AE(L) I/O Pinouts
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
100-ball 100-pin
144-pin
LQFP
208-pin 256-ball
MC
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PLB
BGA
LQFP
PQFP
197
-
BGA
C11
-
MC
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
PLB
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
L
TQFP
BGA
PQFP
38
-
BGA
K11
-
I
I
80
-
B8
114
-
-
-
-
-
-
-
-
I
81
-
A7
116
196
-
B11
-
57
-
G10
82
-
37
-
K12
-
I
-
-
-
I
-
-
117
195
194
-
A11
F10
-
-
-
83
-
36
35
-
K14
K13
-
I
-
-
-
-
-
I
-
-
-
118
119
-
-
-
-
I
-
-
193
192
-
E10
A10
-
58
-
G8
84
86
-
34
33
-
K15
K16
-
I
-
-
-
I
-
-
-
-
I
83
-
B7
120
-
190
-
C10
-
60
-
F9
87
-
31
-
J13
-
I
-
-
I
84
-
C7
121
-
189
188
-
D10
F9
-
61
-
F10
88
-
30
29
-
J14
J12
-
I
-
-
-
I
-
-
-
-
-
I
85
63
-
C6
122
-
187
27
-
A9
J15
-
62
-
F8
-
89
-
28
78
-
J11
R8
-
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
F7
-
-
L
-
-
-
64
-
E9
90
-
26
-
J16
-
L
-
-
55
-
77
-
T9
-
-
L
-
-
65
-
E10
91
-
25
24
-
J10
H14
-
L
-
-
56
-
76
73
-
R9
N9
-
-
L
-
-
-
-
-
-
L
-
-
-
-
92
93
-
22
21
-
H13
H12
-
L
40
41
-
K6
J6
-
60
61
-
71
70
-
M9
L9
-
-
-
L
-
-
L
67
-
E8
-
94
-
20
-
H11
-
L
42
-
H6
-
62
-
69
-
R10
-
L
-
-
96
-
19
18
-
H10
G11
-
L
44
-
K7
-
63
-
68
67
-
N10
M10
-
-
-
L
-
-
-
L
-
-
-
68
E7
97
17
G14
L
45
J7
65
66
L10
59
ATF1516AE(L)
2398H–8/03
ATF1516AE(L) I/O Pinouts
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
100-pin
TQFP
100-ball 144-pin
208-pin 256-ball
MC
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
PLB
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
N
BGA
LQFP
PQFP
BGA
B14
-
MC
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
PLB
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
BGA
LQFP
PQFP
49
-
BGA
R13
-
-
-
-
106
4
-
-
-
-
-
-
-
-
-
75
-
C10
107
3
C13
-
-
-
74
-
48
-
P13
-
-
-
-
-
-
-
-
108
206
205
-
B13
F12
-
-
-
75
-
47
46
-
N13
M14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
109
204
203
-
E12
D12
-
52
53
-
J10
77
78
-
45
44
-
M13
L13
-
76
-
B10
110
H10
-
-
-
77
-
B9
111
202
-
C12
-
54
-
H9
79
-
43
-
L14
-
-
-
-
-
-
-
201
199
-
B12
E11
-
55
-
J9
80
-
42
40
-
L12
L15
-
78
-
A9
112
-
-
-
-
-
-
79
-
A8
113
198
16
-
D11
G13
-
56
46
-
G9
81
66
-
39
65
-
L16
R11
-
-
-
H7
N
-
-
-
98
-
P
-
N
69
-
D9
15
-
G12
-
P
47
-
J8
67
-
64
-
P11
-
N
-
P
-
N
-
-
99
-
13
12
-
F16
F15
-
P
48
49
-
K8
68
69
-
62
61
-
N11
M11
-
N
-
-
P
K9
N
-
-
-
P
-
N
70
-
D10
100
101
-
11
10
-
F13
F14
-
P
-
-
-
60
59
-
T12
R12
-
N
-
-
P
-
-
70
-
N
-
P
-
-
N
71
-
D8
-
102
-
9
E16
-
P
-
-
-
58
-
M12
-
N
-
P
-
-
-
N
72
-
C9
-
103
-
8
E14
E13
-
P
-
-
71
-
57
56
-
P12
N12
-
N
7
P
-
-
-
N
-
-
-
-
P
-
-
N
73
A10
104
6
D13
P
50
K10
72
55
T13
60
ATF1516AE(L)
2398H–PLD–8/03
ATF1516AE(L)
ATF1516AE(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
5.5
3.5
200
ATF1516AE-5 AC100
ATF1516AE-5 CTC100
ATF1516AE-5 AAC144
ATF1516AE-5 QC208
ATF1516AE-5 CTC256
100A
Commercial
100CT1
144AA
208Q1
256CT1
(0°C to 70°C)
7.5
4.8
133
ATF1516AE-7 AC100
ATF1516AE-7 CTC100
ATF1516AE-7 AAC144
ATF1516AE-7 QC208
ATF1516AE-7 CTC256
100A
Commercial
100CT1
144AA
208Q1
256CT1
(0°C to 70°C)
ATF1516AE-7 AI100
ATF1516AE-7 CTI100
ATF1516AE-7 AAI144
ATF1516AE-7 QI208
ATF1516AE-7 CTI256
100A
Industrial
100CT1
144AA
208Q1
256CT1
(-40°C to +85°C)
10.0
6.4
100
ATF1516AE-10 AC100
ATF1516AE-10 CTC100
ATF1516AE-10 AAC144
ATF1516AE-10 QC208
ATF1516AE-10 CTC256
100A
Commercial
100CT1
144AA
208Q1
256CT1
(0°C to 70°C)
ATF1516AE-10 AI100
ATF1516AE-10 CTI100
ATF1516AE-10 AAI144
ATF1516AE-10 QI208
ATF1516AE-10 CTI256
100A
Industrial
100CT1
144AA
208Q1
256CT1
(-40°C to +85°C)
15.0
9.0
77
ATF1508AEL-15 AC100
ATF1508AEL-15 CTC100
ATF1508AEL-15 AAC144
ATF1508AEL-15 QC208
ATF1508AEL-15 CTC256
100A
Commercial
100CT1
144AA
208Q1
256CT1
(0°C to 70°C)
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are the
same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use com-
mercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
100A
100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP)
100-ball, Tape Ball Grid Array (TBGA) 1.0 mm pitch
144-lead, Low Profile Plastic Gull Wing Quad Flatpack (LQFP)
208-lead, Plastic Quad Flatpack (PQFP)
100CT1
144AA
208Q1
256CT1
256-ball, Tape Ball Grid Array (TBGA) 1.0 mm pitch
61
2398H–PLD–8/03
AC Characteristics ATF1532AE(L) (1)
AE -7
AE -10
AE -12
AEL -15(6)
Symbol Parameter
Min
Max
Min
Max
Min
Max
Min
Max
15
Unit
ns
tPD1
tPD2
tSU
Input or Feedback to Non-registered Output
I/O Input or Feedback to Non-registered Feedback
Global Clock Setup Time
7.5
7.5
10
10
12
12
12
ns
5.6
0
7.6
0
9.1
0
11
0
ns
tH
Global Clock Hold Time
ns
tFSU
tFH
tCOP
tCH
Global Clock Setup Time of Fast Input
Global Clock Hold of Fast Input
Global Clock to Output Delay
Global Clock High Time
3
3
3
3
ns
0
0
0
1
MHz
ns
1
4.7
7.8
1
6.3
1
7.5
9
3
4
5
5
5
5
4
ns
tCL
Global Clock Low Time
3
4
5
ns
tASU
tAH
Array Clock Setup Time
2.5
0.2
1
3.5
0.3
1
4.1
0.4
1
ns
Array Clock Hold Time
ns
tACOP
tACH
tACL
tCNT
Array Clock Output Delay
10.4
12.5
15
ns
Array Clock High Time
3
4
5
6
6
ns
Array Clock Low Time
3
4
5
ns
Minimum Clock Global Period
Maximum Internal Global Clock Frequency
Minimum Array Clock Period
Maximum Internal Array Clock Frequency
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
8.6
8.6
11.5
11.5
13.9
13.9
13
13
ns
(3)
fCNT
120
90
75
70
MHz
ns
tACNT
(4)
fACNT
120
133
90
75
80
70
66
MHz
MHz
ns
(5)
fMAX
tIN
100
0.7
0.7
3.1
2.7
0.4
2.2
1.0
0
0.9
0.9
3.6
3.5
0.5
2.8
1.3
0
1.0
1.0
4.1
4.4
0.6
3.5
3.5
0
2
2
tIO
ns
tFIN
2
ns
tSEXP
tPEXP
tLAD
tLAC
tIOE
tOD1
Foldback Term Delay
8
ns
Cascade Logic Delay
1
ns
Logic Array Delay
6
ns
Logic Control Delay
3.5
3
ns
Internal Output Enable Delay
ns
Output Buffer and Pad Delay
1.0
1.5
1.7
3
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
tOD2
Output Buffer and Pad Delay
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
1.5
6.0
2.0
6.5
2.2
6.7
3
5
ns
ns
tOD3
Output Buffer and Pad Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
tZX1
Output Buffer Enable Delay
4
5
5
7
ns
(slow slew rate = OFF; VCCIO = 5V; CL= 35pF)
62
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
AC Characteristics ATF1532AE(L) (Continued)(1)
AE -7
AE -10
AE -12
AEL -15(6)
Symbol Parameter
tZX2 Output Buffer Enable Delay
Min
Max
Min
Max
Min
Max
Min
Max
Unit
4.5
5.5
5.5
7
ns
(slow slew rate = OFF; VCCIO = 3.3V; CL= 35pF)
tZX3
Output Buffer Enable Delay
(slow slew rate = ON; VCCIO = 5V or 3.3V;
CL= 35pF)
9
4
10
10
5
10
6
ns
tXZ
tSU
Output Buffer Disable Delay (CL= 5pF)
Register Setup Time
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.1
0.6
1.6
1.4
3.0
0.8
1.6
1.4
3.5
1.0
1.6
1.4
5
4
2
2
tH
Register Hold Time
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
tRD
1.3
0.6
1.8
1.0
1.7
1.0
1.0
3.0
4.5
1.7
0.8
2.3
1.3
2.2
1.4
1.4
4.0
5.0
2.1
1.0
2.9
1.7
2.7
1.7
4.8
4.8
5.0
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
6
tEN
Register Enable Time
Global Control Delay
6
tGLOB
tPRE
tCLR
tUIM
2
Register Preset Time
Register Clear Time
4
4
Switch Matrix Delay
2
(2)
tRPA
Reduced Power Adder
10
Notes: 1. See ordering Information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reduced-
power mode.
3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one
logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG
.
4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable, and a
PIA fan-out of one logic block (16 macrocells).
5. fMAX is the fastest available frequency for pipeline data.
6. For clocked applications and frequencies above fcritical, OR, non-clocked applications with dormant times less that 1/fcritical
the device will achieve the speeds of the -10 column. (See “ITD/automatic power down.”)
,
63
2398H–PLD–8/03
ATF1532AE(L) Pinouts
144-lead LQFP – Top View
1
108
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
19
90
36
208-lead PQFP – Top View
1
156
ATF1516AE(L)
ATF1532AE(L)
26
131
64
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L)
256-ball 1.0 mm Pitch
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
65
2398H–PLD–8/03
ATF1532AE(L) Dedicated Pinouts
Dedicated Pin
INPUT/GCLK1
INPUT/GCLR
INPUT/OE1
INPUT/OE2/GCK2
I/O/GCLK3
144-pin LQFP
208-pin PQFP
256-ball BGA
125
184
D9
127
182
E8
126
183
E9
128
181
D8
TBD
TBD
TBD
I/O PD (1,2)
TDI (JTAG)
TBD
TBD
TBD
4
176
D4
TMS (JTAG)
TCK (JTAG)
TDO (JTAG)
GNDINT
20
127
J6
89
104
30
189
J11
D13
52, 57, 124, 129
75, 82, 180, 185
A8, C9, G9, K8, P9
GNDIO
3, 13, 17, 33, 59, 64, 85,
105, 135
14, 32, 50, 51, 94, 116, 134,
152, 158, 200
A3, B10, C2, D14, F6, G10, H8, J9, K7, L11,
M3, P6, P10, R2, R3, T1, T15
VCCINT
VCCIO
51, 58, 123, 130
74, 83, 179, 186
B9, C8, G8, K9, P8
24, 50, 73, 76, 95, 115,
144
5, 23, 41, 63, 85, 105, 107,
125, 143, 165, 191, 207
B3, B5, C14, E15, F11, G3, G7, G15, H9,
J8, K10, L3, L6, M15, P14, T2, T3
No Connect
-
-
-
# of Signal pins
# of User I/O pins
120
116
176
172
212
206
OE (1,2) Global OE pins.
GCLR Global Clear pin.
GCLK (1,2,3) Global Clock pins.
TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing.
GNDINT Ground pins for the internal device logic.
GNDIO Ground pins for the I/O drivers.
VCCINT VCC pins for the internal device logic.
VCCIO VCC pins for the I/O drivers.
66
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
1
PLB
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
MC
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PLB
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
134
173
D7
142
163
E4
2
-
-
-
-
-
-
-
-
3
-
-
-
-
4
-
-
-
-
-
-
5
-
-
C7
-
141
164
C5
-
6
-
-
-
-
7
-
-
-
-
-
-
8
-
-
-
-
-
-
9
-
175
B7
-
140
166
A5
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
-
-
-
133
176
A7
-
-
167
D5
-
-
-
-
-
-
-
-
-
-
-
132
177
F8
-
139
168
E5
-
-
-
-
-
131
178
B8
D6
-
-
-
E6
B2
-
-
169
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
138
170
C6
-
1
-
A2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
159
-
-
137
171
B6
-
-
B4
-
-
-
-
136
172
A6
-
-
160
-
A4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F7
-
-
-
161
-
C4
-
E7
143
162
C3
67
2398H–PLD–8/03
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
PLB
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
F
MC
97
PLB
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
-
-
-
E3
-
-
-
-
H6
-
-
98
-
7
-
153
C1
-
99
15
-
141
G5
-
-
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
-
-
-
B1
-
14
-
142
G4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
154
A1
-
-
144
G4
-
-
-
-
-
6
-
155
D2
-
-
145
G1
-
-
-
-
-
-
-
-
-
-
5
-
156
D3
-
12
-
146
G6
-
-
-
4
-
157
D4
F2
-
-
-
F5
J1
-
147
19
-
135
F
-
-
-
F
-
148
F3
-
-
136
H7
-
F
-
-
-
-
F
11
-
149
F1
-
18
-
137
H5
-
F
-
-
F
-
-
-
-
-
-
F
-
-
-
-
-
-
F
-
-
F4
-
-
-
H2
-
F
-
-
-
-
138
-
F
10
-
150
E1
-
-
H3
-
F
-
-
F
-
-
-
-
-
-
F
9
-
151
D1
-
-
139
-
H1
-
F
-
-
-
F
8
E2
16
140
H4
68
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
PLB
MC
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
PLB
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
L
I
I
-
-
-
K1
-
29
115
N4
-
-
-
-
-
M2
-
I
-
129
J7
-
117
I
-
-
-
-
I
20
-
130
J6
-
-
118
M1
-
I
-
-
-
I
-
-
-
-
-
-
I
-
-
-
-
-
-
I
-
131
J5
-
28
-
119
M4
-
I
-
-
-
I
-
-
J4
-
-
-
M5
-
I
-
-
-
-
I
-
-
-
-
-
-
I
-
132
J3
-
-
120
L5
-
I
-
-
-
-
I
-
133
J2
L2
-
27
34
-
121
L4
R1
-
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
-
122
109
-
-
L
-
-
-
L1
-
L
-
-
-
-
-
L
-
-
-
26
-
123
K6
-
L
32
-
110
P2
-
-
L
-
-
-
-
L
-
-
-
-
-
124
-
-
L
-
-
111
-
-
25
-
K5
-
L
-
N3
-
L
-
23
-
126
-
K4
-
L
-
112
-
N2
-
L
-
-
-
-
L
-
-
-
22
-
127
-
K3
-
L
31
-
113
-
P1
-
L
21
128
K2
L
30
114
N1
69
2398H–PLD–8/03
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
PLB
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
N
MC
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
PLB
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
-
-
101
P5
47
-
88
-
R7
-
-
-
-
-
-
46
-
89
-
P7
-
-
-
-
-
102
N5
-
45
-
90
-
T7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
37
-
103
T4
-
-
91
-
L8
-
-
-
-
104
R4
-
44
-
92
-
N7
-
-
-
-
-
-
-
-
-
36
-
106
P4
-
-
-
M7
-
-
-
-
35
42
-
108
P3
R6
-
43
54
-
93
79
-
L7
M9
-
95
N
-
P
N
-
-
-
-
P
-
-
-
N
-
-
P
-
-
-
N
41
-
96
-
T6
-
P
-
80
-
L9
-
N
P
-
N
-
-
-
P
-
-
-
N
-
-
-
P
-
-
-
N
40
-
97
-
N6
-
P
53
-
81
-
R8
-
N
P
N
39
-
98
-
M6
-
P
-
84
-
T8
-
N
P
-
N
-
-
-
P
-
-
-
N
-
99
-
R5
-
P
49
-
86
-
N8
-
N
-
P
N
38
100
T5
P
48
87
M8
70
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
PLB
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
MC
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
PLB
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
T
55
78
-
N9
66
-
62
-
K11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
77
-
T9
67
-
61
-
M12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
56
-
76
-
R9
68
-
60
-
N12
-
-
-
73
-
L10
69
-
59
-
T12
-
-
-
-
-
-
-
-
-
60
-
71
-
M10
-
58
-
R12
-
-
-
61
62
-
70
69
-
N10
70
-
57
56
-
T13
R10
P12
-
T
-
-
63
-
68
-
T10
T
-
-
-
-
T
-
-
-
-
67
-
M11
T
-
55
-
T14
-
-
T
-
-
-
-
-
T
-
-
-
-
-
-
N11
-
T
-
-
-
P13
-
-
66
-
T
71
-
54
-
-
T
65
-
65
-
P11
-
T
72
-
53
-
R13
-
T
-
-
-
T
-
-
-
-
-
R11
-
T
-
52
-
R14
-
-
-
T
-
-
64
T11
T
74
49
R15
71
2398H–PLD–8/03
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
PLB
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
V
MC
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
PLB
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
X
75
-
48
-
P15
82
-
35
-
L16
-
-
-
-
-
-
-
L13
-
-
-
-
-
-
-
47
-
N15
83
-
34
-
L12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
46
-
T16
84
-
33
-
K12
-
-
-
-
45
-
R16
86
-
31
-
K14
-
-
-
-
-
-
-
-
-
77
-
44
-
P16
87
-
30
-
K15
-
-
78
79
-
43
42
-
N14
88
89
-
29
K16
N16
J11
V
-
X
-
28
-
-
V
80
-
40
-
M14
X
-
J12
V
-
X
-
-
V
-
39
-
N13
X
-
27
-
J13
V
-
-
X
-
-
V
-
-
-
X
-
-
-
V
-
-
-
X
-
-
-
J14
-
V
81
-
38
-
M16
X
-
26
-
V
-
M13
-
X
-
V
-
-
X
-
-
J15
-
V
-
-
X
-
-
V
-
-
-
X
-
-
-
V
-
37
-
L14
-
X
-
25
-
K13
-
V
-
X
-
V
-
36
L15
X
90
24
J16
72
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
PLB
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Z
MC
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
PLB
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB
91
-
22
-
H10
-
10
-
F14
-
-
-
-
21
-
H11
-
9
-
F15
-
-
-
-
92
-
20
-
H12
98
8
-
F16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H15
-
-
E12
-
-
-
-
-
-
-
19
-
H16
99
7
-
E13
-
-
-
-
-
-
-
-
-
-
-
18
-
H14
100
6
-
E14
-
-
-
-
93
-
17
-
H13
101
-
E16
G12
-
-
D16
Z
-
-
-
-
-
-
Z
-
16
-
G13
102
4
-
C16
Z
-
-
-
-
Z
94
-
15
-
G14
-
-
B16
Z
-
-
-
-
Z
-
-
-
-
-
-
Z
-
-
-
G16
-
-
-
-
A16
-
Z
96
-
13
-
-
3
-
Z
-
103
-
Z
-
12
-
G11
-
2
-
D15
-
Z
-
Z
-
-
-
-
-
-
Z
97
-
11
-
F12
-
104
-
1
-
D13
-
Z
Z
-
-
F13
106
208
C15
73
2398H–PLD–8/03
ATF1532AE(L) I/O Pinouts
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
144-pin
LQFP
208-pin
PQFP
256-ball
BGA
MC
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
PLB
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
MC
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
PLB
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
EE
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
-
-
B15
-
196
D11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
107
-
A15
113
195
C11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
108
206
B14
114
194
A11
-
-
-
-
-
-
-
205
A14
116
193
B11
-
-
-
-
-
-
-
-
-
-
-
-
-
204
B13
117
-
F10
-
-
-
-
-
-
109
203
A13
-
-
E10
-
202
C13
118
192
D10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
110
201
D12
-
-
C10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C12
-
-
119
-
-
190
-
-
A10
-
111
199
-
-
-
198
B12
-
120
-
189
-
J10
-
-
-
-
-
-
-
-
-
112
197
A12
-
121
-
188
-
F9
-
-
-
-
-
E11
122
187
A9
74
ATF1532AE(L)
2398H–PLD–8/03
ATF1532AE(L)
ATF1532AE(L) Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
7.5
4.7
6.3
133
ATF1532AE-7 AAC144
ATF1532AE-7 QC208
ATF1532AE-7 CTC256
144AA
208Q1
256CT1
Commercial
(0°C to 70°C)
10.0
100
ATF1532AE-10 AAC144
ATF1532AE-10 QC208
ATF1532AE-10 CTC256
144AA
208Q1
256CT1
Commercial
(0°C to 70°C)
ATF1532AE-10 AAI144
ATF1532AE-10 QI208
ATF1532AE-10 CTI256
144AA
208Q1
256CT1
Industrial
(-40°C to +85°C)
12.0
15.0
7.5
9.0
80
ATF1532AE-12 AAC144
ATF1532AE-12 QC208
ATF1532AE-12 CTC256
144AA
208Q1
256CT1
Commercial
(0°C to 70°C)
ATF1532AE-12 AAI144
ATF1532AE-12 QI208
ATF1532AE-12 CTI256
144AA
208Q1
256CT1
Industrial
(-40°C to +85°C)
66
ATF1508AEL-15 AAC144
ATF1508AEL-15 CC208
ATF1508AEL-15 CTC256
144AA
169Q1
256CT1
Commercial
(0°C to 70°C)
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
144AA
208Q1
256CT1
144-lead, Very Thin Plastic Gull Wing Quad Flatpack (LQFP)
208-ball, Plastic Quad Flatpack (PQFP)
256-lead, Tape Ball Grid Array (TBGA) 1.0 mm pitch
75
2398H–PLD–8/03
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
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Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
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Fax: 1(408) 436-4314
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Fax: (49) 71-31-67-2340
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Tel: 1(719) 576-3300
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Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, are the registered trademarks, and Logic Doubling™ is the
trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2398H–PLD–8/03
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