ATF20V8BQL-15PI [ATMEL]
Flash PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, DIP-24;
| 型号： | ATF20V8BQL-15PI |
| 厂家： | 
ATMEL |
| 描述： | Flash PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, MS-001AF, DIP-24 时钟 ATM 异步传输模式 输入元件 光电二极管 可编程逻辑 |
| 文件： | 总22页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Industry-standard Architecture
– Emulates Many 24-pin PALs®
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
• Several Power Saving Options
Device
ICC, Standby
50 mA
ICC, Active
55 mA
ATF20V8B
ATF20V8BQ
ATF20V8BQL
High-
35 mA
40 mA
5 mA
20 mA
performance
EE PLD
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
ATF20V8B
• High-reliability CMOS Process
– 20 Year Data Retention
ATF20V8BQ
ATF20V8BQL
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-Compliant
• Green Package Options (Pb/Halide-free/RoHS Complant) Available
Block Diagram
TSSOP
Pin Configurations
All Pinouts Top View
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
2
IN
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
4
Pin Name Function
IN
5
IN
6
CLK
I
Clock
IN
7
IN
8
IN
9
Logic Inputs
IN
10
11
12
IN
I/O
OE
*
Bi-directional Buffers
Output Enable
No Internal Connection
+5V Supply
GND
OE/IN
DIP/SOIC
PLCC
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 IN
VCC
IN
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 IN
IN
IN
IN
*
5
6
7
8
9
25 I/O
24 I/O
23 I/O
IN
IN
IN
22
*
IN
IN
21 I/O
20 I/O
19 I/O
IN
IN 10
IN 11
IN
Rev. 0407J–07/06
IN 10
IN 11
GND 12
13 OE/IN
Description
The ATF20V8B is a high-performance CMOS (electrically-
erasable) programmable logic device (PLD) that utilizes
Atmel’s proven electrically-erasable Flash memory technol-
ogy. Speeds down to 7.5 ns and power dissipation as low
as 10 mA are offered. All speed ranges are specified over
the full 5V 10% range for industrial temperature ranges,
and 5V 5% for commercial temperature ranges.
these options significantly reduces total system power and
enhances system reliability.
The ATF20V8Bs incorporate a superset of the generic
architectures, which allows direct replacement of the 20R8
family and most 24-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
modes of operation, configured automatically with soft-
ware, allow highly complex logic functions to be realized.
Several low-power options allow selection of the best solu-
tion for various types of power-limited applications. Each of
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is VCC + 0.75V DC which
may overshoot to 7.0V for pulses of less than 20
ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V 5%
Industrial
-40°C - 85°C
5V 10%
Operating Temperature (Ambient)
VCC Power Supply
ATF20V8B(Q)(L)
2
ATF20V8B(Q)(L)
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
0 ≤ VIN ≤ VIL(Max)
-35
-100
µA
Input or I/O High
Leakage Current
IIH
3.5 ≤ VIN ≤ VCC
10
µA
Com.
Ind.
60
60
60
60
60
60
35
5
90
100
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
B-7, -10
B-15
Com.
Ind.
B-15
90
B-25
Com.
Ind.
80
VCC = Max,
VIN = Max,
Outputs Open
Power Supply
ICC
B-25
90
Current, Standby
BQ-10
BQL-15
BQL-15
BQL-25
BQL-25
Com.
Com.
Ind.
55
10
5
15
Com.
Ind.
5
10
5
15
Com.
Ind.
80
80
60
60
60
60
40
20
20
20
20
110
125
90
B-7, -10
B-15
Com.
Ind.
B-15
105
90
B-25
Com.
Ind.
VCC = Max,
Outputs Open,
f = 15 MHz
Clocked Power
ICC2
B-25
105
55
Supply Current
BQ-10
BQL-15
BQL-15
BQL-25
BQL-25
Com.
Com.
Ind.
35
40
Com.
Ind.
35
40
Output Short
IOS(1)
VOUT = 0.5V
-130
mA
Circuit Current
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
VCC + 0.75
Com.,
Ind.
IOL = 24 mA
IOL = 16 mA
0.5
0.5
V
V
V
VIN = VIH or VIL,
VCC = Min
VOL
Output Low Voltage
VIN = VIH or VIL,
VCC = Min
VOH
Output High Voltage
I
OH = -4.0 mA
2.4
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. Shaded parts are obsolete with a last time buy date of 19 August 1999.
3
AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics(1)
-7
-10
-15
-25
Symbol
Parameter
Min
Max
7.5
7
Min
Max
Min
Max
Min
Max
Units
ns
8 outputs switching
1 output switching
3
3
10
3
15
3
25
Input or Feedback to
Non-Registered Output
tPD
ns
tCF
tCO
Clock to Feedback
Clock to Output
3
6
7
8
10
12
ns
2
5
5
2
2
10
2
ns
Input or Feedback
Setup Time
tS
7.5
12
15
ns
tH
tP
Hold Time
0
8
4
0
12
6
0
16
8
0
ns
ns
Clock Period
24
12
tW
Clock Width
ns
External Feedback 1/(tS + tCO
)
100
125
125
9
68
74
83
10
10
10
10
45
50
62
15
15
15
15
37
40
41
20
20
20
20
MHz
MHz
MHz
ns
fMAX
Internal Feedback 1/(tS + tCF
)
No Feedback 1/(tP)
tEA
Input to Output Enable — Product Term
Input to Output Disable —Product Term
OE pin to Output Enable
3
2
3
2
3
2
3
2
tER
9
ns
tPZX
tPXZ
2
6
2
2
2
ns
OE pin to Output Disable
1.5
6
1.5
1.5
1.5
ns
Note:
1. See ordering information for valid part numbers and speed grades.
2. Shaded -25 parts are obsolete with a last-time buy date of August 19, 1999.
3. Shaded -7 and -15 parts are obsolete with a last-time buy date of September 30, 2006.
ATF20V8B(Q)(L)
4
ATF20V8B(Q)(L)
Input Test Waveforms and
Measurement Levels
Output Test Loads
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
Note:
5
6
8
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
Parameter Description
Typ
600 1,000
3.8 4.5
Max
Units
ns
3. The clock must remain stable during tPR
.
tPR
Power-up Reset Time
Power-up Reset Voltage
VRST
V
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
5
Input and I/O Pull-ups
All ATF20V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to VCC. This
ensures that all logic array inputs are at known states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible drivers (see input and I/O
diagrams below).
Input Diagram
I/O Diagram
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF20V8B architecture. Eight configurable macrocells can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.
subsets can be found in each of the configuration modes
described in the following pages. The user can download
the listed subset device JEDEC programming file to the
PLD programmer, and the ATF20V8B can be configured to
act like the chosen device. Check with your programmer
manufacturer for this capability.
The ATF20V8B can be configured in one of three different
modes. Each mode makes the ATF20V8B look like a dif-
ferent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter-
mining factors would be the usage of register versus com-
binatorial outputs and dedicated outputs versus outputs
with output enable control.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the content of the ATF20V8B.
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessi-
ble regardless of the state of the security fuse.
The ATF20V8B universal architecture can be programmed
to emulate many 24-pin PAL devices. These architectural
ATF20V8B(Q)(L)
6
ATF20V8B(Q)(L)
Compiler Mode Selection
Registered
Complex
P20V8C
Simple
P20V8
G20V8
Auto Select
P20V8
ABEL, Atmel-ABEL
CUPL
P20V8R
G20V8MS
GAL20V8_R(1)
“Registered”
P20V8
G20V8MA
GAL20V8_C7(1)
“Complex”
P20V8
G20V8A
LOG/iC
GAL20V8_C8(1)
GAL20V8
GAL20V8
P20V8
OrCAD-PLD
PLDesigner
Tango-PLD
“Simple”
P20V8
G20V8
G20V8
G20V8
G20V8
Note:
1. Only applicable for version 3.4 or lower.
ATF20V8B Registered Mode
PAL Device Emulation/PAL Replacement. The registered
mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or com-
binatorial output or I/O, or as an input. For a registered out-
put or I/O, the output is enabled by the OE pin, and the
register is clocked by the CLK pin. Eight product terms are
allocated to the sum term. For a combinatorial output or
I/O, the output enable is controlled by a product term, and
seven product terms are allocated to the sum term. When
the macrocell is configured as an input, the output enable is
permanently disabled.
Any register usage will make the compiler select this mode.
The following registered devices can be emulated using
this mode:
20R8
20R6
20R4
20RP8
20RP6
20RP4
Registered Mode Operation
7
Registered Mode Logic Diagram
ATF20V8B(Q)(L)
8
ATF20V8B(Q)(L)
ATF20V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex
Mode, combinatorial output and I/O functions are possible.
Pins 1 and 11 are regular inputs to the array. Pins 13
through 18 have pin feedback paths back to the AND-array,
which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have
input capability. In this mode, each macrocell has seven
product terms going to the sum term and one product term
enabling the output.
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
20L8
20H8
20P8
Complex Mode Operation
The compiler selects this mode when all outputs are combi-
natorial without OE control. The following simple PALs can
be emulated using this mode:
ATF20V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple
Mode, 8 product terms are allocated to the sum term. Pins
15 and 16 (center macrocells) are permanently configured
as combinatorial outputs. Other macrocells can be either
inputs or combinatorial outputs with pin feedback to the
AND-array. Pins 1 and 11 are regular inputs.
14L8 14H8 14P8
16L6 18H6 16P6
18L4 18H4 18P4
20L2 20H2 20P2
Simple Mode Option
9
Complex Mode Logic Diagram
ATF20V8B(Q)(L)
10
ATF20V8B(Q)(L)
Simple Mode Logic Diagram
11
ATF20V8B(Q)(L)
12
ATF20V8B(Q)(L)
13
ATF20V8B(Q)(L)
14
ATF20V8B(Q)(L)
ATF20V8B Ordering Information
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
7.5
5
5
ATF20V8B-7JC
ATF20V8B-7PC
ATF20V8B-7SC
ATF20V8B-7XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
10
7.5
7
ATF20V8B-10JC
ATF20V8B-10PC
ATF20V8B-10SC
ATF20V8B-10XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8B-10JI
ATF20V8B-10PI
ATF20V8B-10SI
ATF20V8B-10XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
15
12
10
ATF20V8B-15JC
ATF20V8B-15PC
ATF20V8B-15SC
ATF20V8B-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8B-15JI
ATF20V8B-15PI
ATF20V8B-15SI
ATF20V8B-15XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
Note:
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
ATF20V8B Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
10
7.5
7
ATF20V8B-10JU
ATF20V8B-10PU
28J
Industrial
24P3
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
15
ATF20V8BQ and ATF20V8BQL Ordering Information
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
10
7.5
7
ATF20V8BQ-10JC
ATF20V8BQ-10PC
ATF20V8BQ-10XC
28J
Commercial
24P3
24X
(0°C to 70°C)
15
15
12
12
10
10
ATF20V8BQL-15JC
ATF20V8BQL-15PC
ATF20V8BQL-15SC
ATF20V8BQL-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF20V8BQL-15JI
ATF20V8BQL-15PI
ATF20V8BQL-15SI
ATF20V8BQL-15XI
28J
Industrial
24P3
24S
24X
(-40°C to 85°C))
Note:
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
ATF20V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD (ns)
tS (ns)
tCO (ns)
Ordering Code
Package
Operation Range
15
12
10
ATF20V8BQL-15JU
ATF20V8BQL-15PU
28J
Industrial
24P3
(-40°C to 85°C))
Note:
1. Shaded parts are obsolete with a last-time buy date of September 30, 2006.
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
ATF20V8B(Q)(L)
16
ATF20V8B(Q)(L)
Packaging Information
28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
12.319
11.430
12.319
11.430
9.906
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
12.573
D1
E
–
11.582 Note 2
12.573
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
11.582 Note 2
10.922
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
28J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
17
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
31.623
7.620
6.096
0.356
1.270
2.921
0.203
–
32.131 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1
L
1.651
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
6/1/04
DRAWING NO. REV.
24P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
D
R
ATF20V8B(Q)(L)
18
ATF20V8B(Q)(L)
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
2.65
0.30
10.65
7.60
15.60
0.51
1.27
0.32
NOM
NOTE
SYMBOL
A
–
A1
A1
D
0.10
10.00
7.40
15.20
0.33
0.40
0.23
–
–
D1
E
–
0º ~ 8º
–
L1
B
–
L
–
–
L
L1
e
1.27 BSC
06/17/2002
TITLE
DRAWING NO. REV.
24S
2325 Orchard Parkway
San Jose, CA 95131
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
B
R
19
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
1.20(0.047)MAX
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0º ~ 8º
0.75(0.030)
0.45(0.018)
04/11/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
24X
A
R
ATF20V8B(Q)(L)
20
ATF20V8B(Q)(L)
Revision History
Revision Level – Release Date
History
J – July 2006
Ordering Information tables updated to reflect obsolete parts.
21
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0407J–07/06
相关型号：
ATF20V8BQL-15PU
Flash PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, GREEN, PLASTIC, MS-001AF, DIP-24
ATMEL
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