ATF22LV10C-15JI [ATMEL]
High Performance E2 PLD; 高性能可编程逻辑器件E2
| 型号： | ATF22LV10C-15JI |
| 厂家： | 
ATMEL |
| 描述： | High Performance E2 PLD |
| 文件： | 总9页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
3.0V to 5.5V Operating Range
Advanced Low Voltage Electricaly Erasable Programmable Logic Device
User Controlled Power Down Pin Option
Pin-Controlled Standby Power (10 µA Typical)
Well-Suited for Battery Powered Systems
10 ns Maximum Propagation Delay
CMOS and TTL Compatible Inputs and Outputs
Latch Feature Hold Inputs to Previous Logic States
•
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•
•
•
•
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Advanced Electrically Erasable Technology
•
High
Reprogrammable
100% Tested
Performance
E2 PLD
High Reliability CMOS Process
•
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
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ATF22LV10C
Block Diagram
TSSOP Top View
Pin Configurations
Pin Name
CLK
IN
Function
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Clock
2
ATF22LV10C
IN
3
Logic Inputs
Bidirectional Buffers
(3V to 5.5V) Supply
IN/PD
IN
4
5
I/O
IN
6
IN
7
VCC
IN
8
IN
9
IN
10
11
12
Programmable
Power Down
PD
IN
GND
(1)
DIP/SOIC
PLCC
Top view
Note: 1. For PLCC, pin 1, 8, 15, and 22 can be left unconnected. For superior
performance, connect VCC to pin 1 and GND to 8, 15, and 22.
Rev. 0780E/LV10C-E–05/98
Description
The ATF22LV10C is a high performance CMOS (Electri-
cally Erasable) Programmable Logic Device (PLD) which
utilizes Atmel’s proven electrically erasable Flash memory
technology. Speeds down to 10 ns and power dissipation
as low as 10 µA are offered. All speed ranges are speci-
fied over the 3.0V to 5.5V range for industrial and commer-
cial temperature ranges.
The ATF22LV10C is capable of operating at supply volt-
ages down to 3.0V. When the power down pin is active,
the device is placed into a zero standby power down
mode. When the power down pin is not used or active, the
device operates in a full power low voltage mode. Pin
“keeper” circuits on input and output pins hold pins to their
previous logic levels when idle, which eliminate static
power consumed by pull-up resistors.
The ATF22LV10C provides a low voltage and user con-
trolled “zero” power CMOS PLD solution. A user-control-
led power down feature offers “zero” (5 µA typical)
standby power. This feature allows the user to manage
total system power to meet specific application require-
ments and enhance reliability, all without sacrificing
speed. (The ATF22LV10CZ provides edge-sensing “zero”
standby power (10 µA typical), as well as low voltage op-
eration. See the ATF22LV10CZ Data Sheet.)
The ATF22LV10C macrocell incorporates a variable prod-
uct term architecture. Each output is allocated from 8 to
16 product terms which allows highly complex logic func-
tions to be realized. Two additional product terms are in-
cluded to provide synchronous reset and asynchronous
reset. These additional product terms are common to all
10 registers and are automatically cleared upon power up.
Register Preload simplifies testing. A Security Fuse pre-
vents unauthorized copying of programmed fuse patterns.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................... -40°C to +85°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
(1)
Respect to Ground.........................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming....................-2.0V to +14.0V
Note: 1. Minimum voltage is -0.6V dc, which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum out-
put pin voltage is Vcc + 0.75V dc, which may over-
shoot to 7.0V for pulses of less than 20 ns.
(1)
Programming Voltage with
Respect to Ground.......................-2.0V to +14.0V
(1)
DC and AC Operating Conditions
Commercial
0°C - 70°C
3.0V - 5.5V
Industrial
-40°C - 85°C
3.0V - 5.5V
Operating Temperature (Case)
Power Supply
V
CC
2
ATF22LV10C
ATF22LV10C
Functional Logic Diagram Description
The Functional Logic Diagram describes the
ATF22LV10C architecture.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the contents of the
ATF22LV10C. Eight bytes (64 fuses) of User Signature
are accessible to the user for purposes such as storing
project name, part number, revision or date. The User
Signature is accessible regardless of the state of the Se-
curity Fuse.
The ATF22LV10C has 12 inputs and 10 I/O macrocells.
Each macrocell can be configured into one of four output
configurations: active high/low, registered/combinatorial
output. The universal architecture of the ATF22LV10C
can be programmed to emulate most 24-pin PAL devices.
DC Characteristics
Symbol Parameter
Condition
0 ≤ V ≤ V (max)
Min
Typ
Max
Units
Input or I/O Low
I
I
I
I
I
I
I
-10
µA
IL
IN
IL
Leakage Current
Input or I/O High
Leakage Current
(V - 0.2)V ≤ V ≤ V
CC
10
µA
IH
CC
IN
Power Supply
Current, Standby
V
= MAX, V = MAX,
Com.
Ind.
55
60
85
90
mA
mA
CC
IN
CC
CC2
CC3
PD
Outputs Open
Clocked Power
Supply Current
V
= MAX,
Com.
Ind.
1
1
mA/MHz
mA/MHz
CC
Outputs Open
Clocked Power
Supply Current
V
= MAX,
Com.
Ind.
100
105
mA
mA
CC
Outputs Open, f = 15 MHz
Power Supply
Current, PD Mode
V
V
= MAX,
= MAX, Outputs Open
Com.
Ind.
10
10
100
100
µA
µA
CC
IN
Output Short
Circuit Current
(1)
V
= 0.5V
-130
mA
OS
OUT
V
V
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
IL
V
+ 0.75
CC
IH
V
V
= V or V
IH IL
IN
0.5
V
V
Output Low Voltage
= MIN,
OL
CC
I
OL
= 8 mA
V
V
= V or V ,
2.4
V
IN
IH
IL
Output High Voltage
V
= MIN,
OH
CC
I
= -4.0 mA
OH
Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
AC Waveforms
AC Characteristics (1)
-10
-15
Symbol Parameter
Min
Max
10
5
Min
Max
15
8
Units
ns
t
t
t
t
t
t
t
Input to Feedback to Non-Registered Output
Clock to Feedback
3
3
PD
CF
CO
S
ns
Clock to Output
2
7.5
0
6.5
2
12
0
10
ns
Input or Feedback Setup Time
Input Hold Time
ns
ns
H
Clock Period
12
6
16
8
ns
P
Clock Width
ns
W
External Feedback 1/(t + t
)
71.4
80
83.3
45.5
50
62.5
MHz
MHz
MHz
S
CO
)
F
MAX
Internal Feedback 1/(t + t
S
CF
No Feedback 1/(t )
P
t
t
t
t
t
t
t
Input to Output Enable
Input to Output Disable
3
2
12
12
13
3
2
15
15
15
ns
ns
ns
ns
ns
ns
ns
EA
ER
AP
Input or I/O to Asynchronous Reset of Register
Setup Time, Synchronous Preset
3
3
10
8
10
8
SP
Asynchronous Reset Width
AW
AR
SPR
Asynchronous Reset Recovery Time
Synchronous Preset to Clock Recovery Time
6
6
10
10
Note: 1. See ordering information for valid part numbers.
4
ATF22LV10C
ATF22LV10C
Power Down AC Characteristics
-10
-15
Symbol
Parameter
MIn
10
0
Max
Min
15
0
Max
Units
ns
t
t
t
t
t
t
t
t
t
t
Valid Input Before PD High
Valid OE Before PD High
Valid Clock Before PD High
Input Don’t Care After PD High
OE Don’t Care After PD High
Clock Don’t Care After PD High
PD Low to Valid Input
IVDH
ns
GVDH
CVDH
DHIX
0
0
ns
10
10
10
5
15
15
15
7.5
3
ns
ns
DHGX
DHCX
DLIV
ns
ns
PD Low to Valid OE
3
ns
DLGV
DLCV
DLOV
PD Low to Valid Clock
PD Low to Valid Output
10
7.5
10
7.5
ns
ns
Input Test Waveforms and
Measurement Levels
Output Test Loads
Note: Similar competitors’ devices are specified
with slightly different loads. These load differ-
ences may affect output signals’ delay and slew
rate. Atmel devices are tested with sufficient
margins to meet compatible device specification
conditions.
Pin Capacitance (f = 1 MHz, T = 25°C)
Typ
Max
8
Units
pF
Conditions
C
C
5
6
V
V
= 0V
IN
IN
8
pF
= 0V
OUT
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
file preload sequence will be done automatically by most
of the approved programmers after the programming.
Power Up Reset
The registers in the ATF22LV10C are designed to reset
during power up. At a point delayed slightly from V
CC
Electronic Signature Word
There are 64 bits of programmable memory that are al-
ways available to the user, even if the device is secured.
These bits can be used for user-specific data.
crossing V
, all registers will be reset to the low state.
RST
The output state will depend on the polarity of the buffer.
This feature is critical for state machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
actually rises in the system, the
CC
following conditions are required:
Security Fuse Usage
1. The V
0.7V.
rise must be monotonic and start below
CC
A single fuse is provided to prevent unauthorized copying
of the ATF22LV10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit
User Signature remains accessible.
2. The clock must remain stable during T
.
PR
3. After T , all input and feedback setup times must be
PR
The security fuse should be programmed last, as its effect
is immediate.
met before driving the clock pin high.
Preload of Register Outputs
Programming/Erasing
The ATF22LV10C’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
Programming/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware
& Software Support for information on software/program-
ming.
Parameter
Description
Typ
Max
Units
Power-Up
Reset Time
T
PR
600
1,000
ns
Power-Up
Reset Voltage
V
RST
2.5
3.0
V
6
ATF22LV10C
ATF22LV10C
Input and I/O Pin Keeper
All ATF22V10C family members have internal input and
I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their
last driven state. This ensures that all logic array inputs
and device outputs are at known states. These are rela-
tively weak active circuits that can be easily overridden by
TTL-compatible drivers (see input and I/O diagrams be-
low).
of power down will remain at the same state. During
power down, all input signals except the power down pin
are blocked. Input and I/O hold latches remain active to
insure that pins do not float to indeterminate levels, further
reducing system power. The power down pin feature is
enabled in the logic design file. Designs using the power
down pin may not use the PD pin logic array input. How-
ever, all other PD pin macrocell resources may still be
used, including the buried feedback and foldback product
term array inputs.
Power Down Mode
PD pin configuration is controlled by the design file, and
appears as a separate fuse bit in the JEDEC file. When
the power down feature is not specified in the design file,
the IN/PD pin will be configured as a regular logic input.
The ATF22LV10C includes an optional pin controlled
power down feature. When this mode is enabled, the PD
pin acts as the power down pin (Pin 4 on the DIP/SOIC
packages and Pin 5 on the PLCC package). When the PD
pin is high, the device supply current is reduced to less
than 100 µA. During power down, all output data and in-
ternal logic states are latched and held. Therefore, all reg-
istered and combinatorial output data remain valid. Any
outputs which were in an undetermined state at the onset
Note: Some programmers list the 22V10 JEDEC
compatible 22V10C (no PD used) separately from the
non-22V10 JEDEC compatible 22V10CEX (with PD
used).
Input Diagram
I/O Diagram
7
Functional Logic Diagram ATF22LV10C
* Input not available if the power down (PD) option is utilized.
8
ATF22LV10C
ATF22LV10C
t
t
t
CO
(ns)
PD
S
Ordering Code
Package
Operation Range
(ns)
(ns)
10
7.5
6.5
ATF22LV10C-10JC
ATF22LV10C-10PC
ATF22LV10C-10SC
ATF22LV10C-10XC
28J
Commercial
(0°C to 70°C)
24P3
24S
24X
15
12
12
10
10
ATF22LV10C-15JC
ATF22LV10C-15PC
ATF22LV10C-15SC
ATF22LV10C-15XC
28J
Commercial
(0°C to 70°C)
24P3
24S
24X
ATF22LV10C-15JI
ATF22LV10C-15PI
ATF22LV10C-15SI
ATF22LV10C-15XI
28J
Industrial
(-40°C to +85°C)
24P3
24S
24X
Package Type
28J
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24P3
24S
24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP)
24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC)
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline TSSOP
24X
9
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