ATF22V10C-10SI [ATMEL]
High Performance E2 PLD; 高性能可编程逻辑器件E2
| 型号： | ATF22V10C-10SI |
| 厂家： | 
ATMEL |
| 描述： | High Performance E2 PLD |
| 文件： | 总8页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
Industry Standard Architecture
•
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
•
5 ns Maximum Pin-to-Pin Delay
CMOS and TTL Compatible Inputs and Outputs
•
Latch Feature Holds Inputs to Previous Logic States
Advanced Flash Technology
•
Reprogrammable
100% Tested
High
Performance
E2 PLD
High Reliability CMOS Process
•
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Dual-in-Line and Surface Mount Packages in Standard Pinouts
•
ATF22V10C
Logic Diagram
Pin Configurations
Pin Name
Function
TSSOP Top View
CLK
IN
Clock
Logic Inputs
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
I/O
*
Bidirectional Buffers
No Internal Connection
+5V Supply
IN/PD
IN
IN
IN
VCC
PD
IN
IN
Power Down
IN
10
11
12
IN
ATF22V10C
GND
PLCC
DIP/SOIC
Top view
Note:
For PLCC, pins 1, 8, 15 and 22 can be left uncon-
nected. For superior performance, connect VCC
to pin 1 and ground to 8, 15, 22.
Rev. 0735C/22V10C-D–04/98
Description
Several low power options allow selection of the best so-
lution for various types of power-limited applications. Each
of these options significantly reduces total system power
and enhances system reliability.
The ATF22V10C is a high performance CMOS (Elec-
trically Erasable) Programmable Logic Device (PLD)
which utilizes Atmel’s proven electrically erasable
Flash memory technology. Speeds down to 5 ns and
power dissipation as low as 100 µA are offered. All
speed ranges are specified over the full 5V ± 10%
range for industrial temperature ranges, and 5V ± 5%
for commercial temperature ranges.
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Temperature Under Bias................... -40°C to +85°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
(1)
Respect to Ground........................-2.0V to +7.0V
Voltage on Input Pins
with Respect to Ground
During Programming................... -2.0V to +14.0V
(1)
Note:
1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V
for pulses of less than 20 ns. Maximum output pin voltage is
VCC + 0.75V dc, which may overshoot to 7.0V for pulses of
less than 20 ns.
Programming Voltage with
Respect to Ground...................... -2.0V to +14.0V
(1)
DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
5V ± 10%
Operating Temperature (Case)
Power Supply
0°C - 70°C
V
5V ± 5%
CC
2
ATF22V10C
ATF22V10C
DC Characteristics
Symbol Parameter
Condition
0 ≤ V
V (MAX)
IL
Min Typ
Max
Units
Input or I/O Low
Leakage Current
≤
IN
I
IL
-35
-10
µA
µA
Input or I/O High
Leakage Current
I
IH
3.5 ≤ V ≤ V
CC
10
IN
V
V
= MAX,
= MAX,
C-5, 7, 10
C-10
Com.
Ind.
85
90
130
140
mA
mA
CC
Power Supply Current,
Standby
I
I
I
CC
IN
Outputs Open
(2)
(2)
C-5, 7, 10
C-10
Com.
Ind.
1
1
mA/MHz
mA/MHz
mA
Clocked Power Supply V = MAX,
CC
CC2
CC3
PD
Current
Outputs Open
V
= MAX,
C-5, 7, 10
Com.
150
160
CC
Clocked Power Supply
Current
Outputs Open,
f = 15 MHz
C-10
Ind.
mA
V
V
= MAX
Com.
Ind.
10
10
100
100
µA
µA
CC
Power Supply Current,
PD Mode
I
I
= 0, MAX
IN
Output Short Circuit
Current
(1)
OS
V
= 0.5V
-130
mA
OUT
V
V
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
V
V
IL
V
+0.75
CC
IH
I
I
= 16 mA
= 12 mA
Com., Ind.
Mil.
0.5
0.5
OL
V
V
= V or V ,
IN
IH
IL
V
V
Output Low Voltage
Output High Voltage
OL
= MIN
CC
OL
V
V
= V or V ,
IN
IH
IL
I
= -4.0 mA
2.4
V
OH
OH
= MIN
CC
Notes: 1. Not more than one output at a time should be shorted.
Duration of short circuit test should not exceed 30 sec.
2. Low frequency only. See Supply Current versus Input Frequency curves.
3
AC Waveforms (1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics (1)
-5
-7
-10
Symbol Parameter
Min
1
Max
Min
3
Max
Min
3
Max Units
t
t
Input or Feedback to Combinatorial Output
Clock to Output
5
4
3
7.5
10
6.5
4
ns
ns
PD
CO
(2)
1
2
4.5
3.5
2
tCF
tS
Clock to Feedback
ns
Input or Feedback Setup Time
Hold Time
3
0
3.5
0
4.5
0
ns
t
H
ns
External Feedback 1/(t + t
)
142
166
166
125 (3)
142
90
MHz
MHz
MHz
ns
S
CO
F
MAX
Internal Feedback 1/(t + t
)
117
125
S
CF
No Feedback
Clock Period
Clock Width
166
t
t
t
t
t
t
t
t
t
6
3
6
3
8
3
3
3
3
8
6
6
8
P
ns
W
Input or I/O to Output Enable
Input or I/O to Output Disable
2
6
5
7
3
7.5
7.5
10
10
9
ns
EA
ER
AP
AW
AR
SP
SPR
2
3
ns
Input or I/O to Asynchronous Reset of Register
Asynchronous Reset Width
3
3
12
ns
5.5
4
7
ns
Asynchronous Reset Recovery Time
Setup Time, Synchronous Preset
5
ns
4
4.5
5
ns
Synchronous Preset to Clock Recovery Time
4
ns
Notes: 1. See ordering information for valid part numbers.
2. 5.5 ns for DIP package devices.
3. 111 MHz for DIP package devices.
4
ATF22V10C
ATF22V10C
Power Down AC Characteristics (1, 2, 3)
-5
-7
-10
Symbol Parameter
Min
5
Max
Min
7.5
0
Max
Min
10
0
Max
Units
ns
t
t
t
t
t
t
t
t
t
t
Valid Input Before PD High
Valid OE Before PD High
Valid Clock Before PD High
Input Don’t Care After PD High
OE Don’t Care After PD High
Clock Don’t Care After PD High
PD Low to Valid Input
IVDH
0
ns
GVDH
CVDH
DHIX
0
0
0
ns
5
5
7
7
10
10
10
10
25
25
30
ns
ns
DHGX
DHCX
DLIV
5
7
ns
5
7.5
20
20
25
ns
PD Low to Valid OE
15
15
20
ns
DLGV
DLCV
DLOV
PD Low to Valid Clock
ns
PD Low to Valid Output
ns
3. Clock and input transitions are ignored.
Notes: 1. Output data is latched and held.
2. HI-Z outputs remain HI-Z.
Output Test Loads:
Input Test Waveforms and
Measurement Levels
Commercial
tR, tF < 3 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
pF
Conditions
C
C
5
6
8
8
V
V
= 0V
IN
IN
pF
= 0V
OUT
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the ATF22V10Cs are designed to reset
1. The V rise must be monotonic, and starts below
CC
during power up. At a point delayed slightly from V
0.7V,
CC
crossing V
, all registers will be reset to the low state.
RST
2. After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
The output state will depend on the polarity of the output
buffer.
3. The clock must remain stable during t
.
PR
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the un-
certainty of how V actually rises in the system, the fol-
CC
lowing conditions are required:
5
V
R
ST
Parameter Description
Typ
Max
Units
POWER
Power-Up
Reset Time
t
PR
t
600
1,000
ns
PR
REGISTERED
OUTPUTS
Power-Up
Reset
t
S
V
RST
3.8
4.5
V
Voltage
t
W
CLOCK
Preload of Registered Outputs
Security Fuse Usage
The ATF22V10C’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most
of the approved programmers after the programming.
A single fuse is provided to prevent unauthorized copying
of the ATF22V10C fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Electronic Signature Word
Programming/erasing is performed using standard PLD
programmers. See CMOS PLD Programming Hardware &
Software Support for information on software/program-
ming.
There are 64 bits of programmable memory that are al-
ways available to the user, even if the device is secured.
These bits can be used for user-specific data.
Input and I/O Pin Keeper Circuits
The ATF16V8C contains internal input and I/O pin keeper
circuits. These circuits allow each ATF16V8C pin to hold
its previous value even when it is not being driven by an
external source or by the device’s output buffer. This helps
insure that all logic array inputs are at known, valid logic
levels. This reduces system power by preventing pins
from floating to indeterminate levels. By using pin keeper
circuits rather than pull-up resistors, there is no DC current
required to hold the pins in either logic state (high or low).
These pin keeper circuits are implemented as weak feed-
back inverters, as shown in the Input Diagram below.
These keeper circuits can easily be overdriven by stand-
ard TTL- or CMOS-compatible drivers. The typical over-
drive current required is 40 µA.
Input Diagram
I/O Diagram
6
ATF22V10C
ATF22V10C
Functional Logic Diagram ATF22V10C
7
Ordering Information
t
t
t
CO
(ns)
PD
S
Ordering Code
Package
Operation Range
(ns)
(ns)
5
3
4
ATF22V10C-5JC
28J
Commercial
(0°C to 70°C)
7.5
10
3.5
4.5
4.5
6.5
ATF22V10C-7JC
ATF22V10C-7PC
ATF22V10C-7SC
ATF22V10C-7XC
28J
Commercial
(0°C to 70°C)
24P3
24S
24X
ATF22V10C-10JC
ATF22V10C-10PC
ATF22V10C-10SC
ATF22V10C-10XC
28J
Commercial
(0°C to 70°C)
24P3
24S
24X
ATF22V10C-10JI
ATF22V10C-10PI
ATF22V10C-10SI
ATF22V10C-10XI
28J
Industrial
(-40°C to 85°C)
24P3
24S
24X
Package Type
28J
28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
24P3
24S
24-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
24X
8
ATF22V10C
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