ATF22V10CZ-15SI [ATMEL]
Highperformance EE PLD; 高性能EE PLD
| 型号： | ATF22V10CZ-15SI |
| 厂家： | 
ATMEL |
| 描述： | Highperformance EE PLD |
| 文件： | 总13页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Industry-standard Architecture
• 12 ns Maximum Pin-to-pin Delay
• Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)
• CMOS and TTL Compatible Inputs and Outputs
• Advanced Electrically-erasableTechnology
– Reprogrammable
– 100% Tested
• Latch Feature Holds Inputs to Previous Logic State
• High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
High-
performance
EE PLD
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Standard Pinouts
• PCI Compliant
Block Diagram
ATF22V10CZ
ATF22V10CQZ
Description
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable
(continued)
Pin Configurations
All Pinouts Top View
TSSOP
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Pin Name Function
2
IN
3
CLK
IN
Clock
IN
4
IN
5
Logic Inputs
Bi-directional Buffers
+5V Supply
IN
6
IN
7
I/O
IN
8
IN
9
VCC
IN
10
11
12
IN
PLCC
GND
DIP/SOIC
IN
IN
IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
GND*
IN
IN
IN
IN 10
IN 11
IN
IN
IN
IN
IN
Rev. 0778H–03/01
IN 10
IN 11
Note:
For PLCC, P1, P8, P15 and P22 can be left
unconnected. For superior performance, con-
nect VCC to pin 1 and GND to 8, 15, and 22.
GND 12
Flash memory technology. Speeds down to 12 ns with zero
standby power dissipation are offered. All speed ranges
are specified over the full 5V 10% range for industrial tem-
perature ranges; 5V 5% for commercial range 5-volt
devices. The ATF22V10CZ/CQZ provides a low voltage
and edge-sensing “zero” power CMOS PLD solution with
“zero” standby power (5 µA typical). The
ATF22V10CZ/CQZ provides a “zero” power CMOS PLD
solution with 5V operating voltages, powering down auto-
matically to the zero power-mode through Atmel’s patented
Input Transition Detection (ITD) circuitry when the device is
idle, offering “zero” (25 µA worst case) standby power. This
feature allows the user to manage total system power to
meet specific application requirements and enhance reli-
ability. Pin “keeper” circuits on input and output pins elimi-
nate static power consumed by pull-up resistors. The
“CQZ” combines the low high-frequency ICC of the “Q”
design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the
generic architectures, which allows direct replacement of
the 22V10 family and most 24-pin combinatorial PLDs. Ten
outputs are each allocated 8 to 16 product terms. Three
different modes of operation, configured automatically
with software, allow highly complex logic functions to be
realized.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
Commercial
Industrial
-40°C - 85°C
5V 10%
Operating Temperature (Ambient)
CC Power Supply
0°C - 70°C
V
5V 5%
Compiler Mode Selection
PAL Mode
GAL Mode
(5828 Fuses)
(5892 Fuses)
Synario
ATF22V10C (DIP)
ATF22V10C (PLCC)
ATF22V10C DIP (UES)
ATF22V10C PLCC (UES)
WINCUPL
P22V10
G22V10
P22V10LCC
G22V10LCC
ATF22V10C(Q)Z
2
ATF22V10C(Q)Z
Functional Logic Diagram Description
The Functional Logic Diagram describes the
ATF22V10CZ/CQZ architecture.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the
ATF22V10CZ/CQZ. Eight bytes (64 fuses) of User Signa-
ture are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Sig-
nature is accessible regardless of the state of the security
fuse.
The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macro-
cells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combina-
torial output.The universal architecture of the
ATF22V10CZ/CQZ can be programmed to emulate most
24-pin PAL devices.
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
Input or I/O Low
Leakage Current
IIL
-10
µA
0 ≤ VIN ≤ VIL (Max)
3.5 ≤ VIN ≤ VCC
Input or I/O High
Leakage Current
IIH
10
µA
CZ-12, 15
CZ-15
Com
Ind
90
90
40
40
5
150
180
60
mA
mA
mA
mA
µA
µA
µA
µA
VCC = Max
Outputs Open,
f = 15 MHz
Clocked Power
Supply Current
ICC
CQZ-20
CQZ-20
CZ-12, 15
CZ-15
Com
Ind
80
Com
Ind
25
VCC = Max
5
50
Power Supply Current,
Standby
ISB
VIN = MAX
Outputs Open
CQZ-20
CQZ-20
Com
Ind
5
25
5
50
Output Short Circuit
Current
(1)
IOS
VOUT = 0.5V
-130
mA
VIL
VIH
Input Low Voltage
Input High Voltage
-0.5
2.0
0.8
V
V
VCC + 0.75
VIN = VIH or VIL
VCC = Min,
IOL = 16 mA
VOL
Output Low Voltage
Output High Voltage
0.5
V
V
VIN = VIH or VIL
VCCIO = Min,
VOH
2.4
IOH = -4.0 mA
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
3
AC Waveforms
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
tS
tH
tW
tW
CP
tP
tAW
tAR
ASYNCH. RESET
tCO
tPD
tAP
tER
VALID
tER
tEA
REGISTERED
OUTPUTS
OUTPUT
VALID
VALID
VALID
DISABLED
tEA
COMBINATORIAL
OUTPUTS
OUTPUT
VALID
VALID
DISABLED
AC Characteristics(1)
-12
-15
-20
Symbol Parameter
Min
Max
12
6
Min
Max
15
Min
Max
20
8
Units
ns
tPD
tCF
tCO
tS
Input or Feedback to Non-registered Output
Clock to Feedback
3
3
3
4.5
8
ns
Clock to Output
2
10
0
8
2
10
0
2
14
0
12
ns
Input or Feedback Setup Time
Input Hold Time
ns
tH
ns
tW
Clock Width
6
6
10
ns
External Feedback 1/(tS + tCO
)
55.5
62
83.3
55.5
69
83.3
38.5
45.5
50.0
MHz
MHz
MHz
fMAX
Internal Feedback 1/(tS + tCF
No Feedback 1/(tP)
)
tEA
Input to Output Enable - Product Term
Input to Output Disable - Product Term
OE Pin to Output Enable
3
2
2
2
12
15
12
15
3
3
2
2
15
15
15
15
3
3
2
2
20
20
20
20
ns
ns
ns
ns
tER
tPZX
tPXZ
OE Pin to Output Disable
Input or I/O to Asynchronous Reset of
Register
tAP
3
10
3
15
3
22
ns
tSP
tAW
tAR
Setup Time, Synchronous Preset
Asynchronous Reset Width
10
7
10
8
14
20
20
ns
ns
ns
Asynchronous Reset Recovery Time
5
6
Synchronous Preset to Clock Recovery
Time
tSPR
10
10
14
ns
Note:
1. See ordering information for valid part numbers.
ATF22V10C(Q)Z
4
ATF22V10C(Q)Z
Input Test Waveforms and
Measurement Levels
Output Test Loads
Note:
Similar competitors devices are specified with slightly
different loads. These load differences may affect output
signals’ delay and slew rate. Atmel devices are tested
with sufficient margins to meet compatible device specifi-
cation conditions.
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ
Max
10
Units
Conditions
CIN
8
8
pF
pF
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
10
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
Security Fuse Usage
The registers in the ATF22V10CZ/CQZ are designed to
reset during power-up. At a point delayed slightly from VCC
crossing VRST, all registers will be reset to the low state.
The output state will depend on the polarity of the buffer.
A single fuse is provided to prevent unauthorized copying
of the ATF22V10CZ/CQZ fuse patterns. Once pro-
grammed, fuse verify and preload are inhibited. However,
the 64-bit User Signature remains accessible. The security
fuse should be programmed last, as its effect is immediate.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the
following conditions are required:
Programming/Erasing
Programming/erasing is performed using standard
PLD programmers. See CMOS PLD Programming Hard-
ware & Software Support for information on software/pro-
gramming.
1. The VCC rise must be monotonic and start
below 0.7V.
2. The clock must remain stable during TPR
.
3. After TPR occurs, all input and feedback setup times
must be met before driving the clock pin high.
V
R
ST
POWER
t
PR
Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with cir-
cuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can
be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
REGISTERED
OUTPUTS
t
S
t
W
CLOCK
Parameter Description
Typ
Max
Units
Electronic Signature Word
TPR
Power-up
600
1000
ns
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Reset Time
VRST
Power-up
Reset Voltage
3.8
4.5
V
5
Input and I/O Pull-ups
All ATF22V10CZ/CQZ family members have internal input
and I/O pin-keeper circuits. Therefore, whenever inputs or
I/Os are not being driven externally, they will maintain their
last driven state. This ensures that all logic array inputs and
device outputs are at known states. These are relatively
weak active circuits that can be easily overridden by TTL-
compatible drivers (see input and I/O diagrams below).
Input Diagram
VCC
100K
INPUT
ESD
PROTECTION
CIRCUIT
I/O Diagram
V
CC
OE
DATA
I/O
V
CC
INPUT
100K
ATF22V10C(Q)Z
6
ATF22V10C(Q)Z
Functional Logic Diagram ATF22V10CZ/CQZ
7
NORMALIZED ICC VS. TEMP
ATF22V10CZ/CQZ STAND-BY ICC vs.
1.4
1.2
1.0
0.8
0.6
0.4
SUPPLY VOLTAGE (TA = 25°C)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.8
5.0
5.3
5.5
-40.0
0.0
25.0
75.0
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
ATF22V10CZ SUPPLY CURRENT vs. INPUT
FREQUENCY (VCC = 5.0V, TA = 25°C)
ATF22V10CQZ SUPPLY CURRENT VS.
INPUT FREQUENCY (VCC = 5V, TA = 25°C)
140.000
120.000
100.000
80.000
60.000
40.000
20.000
0.000
50.000
40.000
30.000
20.000
10.000
0.000
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
0.0
0.5
2.5
5.0
7.5
10.0
25.0
37.5
50.0
FREQUENCY (MHz)
ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT
VS.
ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT VS
SUPPLY VOLTAGE (VOH = 2.4V)
OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
0
-10
-20
-30
-40
-50
4.0
4.5
5.0
5.5
6.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00
OH (V)
SUPPLY VOLTAGE (V)
V
ATF22V10CZ/CQZ OUTPUT SINK CURRENT VS.
SUPPLY VOLTAGE (VOL = 0.5V)
ATF22V10CZ/CQZ OUTPUT SINK CURRENT vs.
SUPPLY VOLTAGE (VOL = 0.5V)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
48
46
44
42
40
38
36
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
ATF22V10C(Q)Z
8
ATF22V10C(Q)Z
ATF22V10CZ/CQZ INPUT CURRENT VS
INPUT VOLTAGE (VCC = 5V, TA = 25°C)
ATF22V10CZ/CQZ INPUT CLAMP CURRENT VS
INPUT VOLTAGE (VCC = 5V, TA = 35°C)
40
30
20
10
0
0
-20
-40
-60
-80
-10
-20
-30
-100
-120
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NORMALIZED TPD vs. TEMP
NORMALIZED TPD vs. VCC
1.1
1.0
0.9
0.8
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
4.5
4.8
5.0
5.3
5.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZED TCO VS TEMP
1.1
1.0
0.9
0.8
NORMALIZED TCO vs. VCC
1.3
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
TEMPERATURE (V)
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
NORMALIZED TSU VS VCC
NORMALIZED TSU vs. TEMP
1.2
1.1
1.0
0.9
0.8
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
TEMPERATURE (C)
25.0
75.0
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
9
ATF22V10C DELTA TPD vs.
OUTPUT LOADING
ATF22V10C DELTA TCO VS.
OUTPUT LOADING
8
6
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
4
2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
OUTPUT LOADING (PF)
NUMBER OF OUTPUTS LOADING
DELTA TPD vs. # OF OUTPUT SWITCHING
DELTA TCO vs. # OF OUTPUT SWITCHING
0.0
-0.1
-0.1
-0.2
-0.2
-0.3
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
ATF22V10C(Q)Z
10
ATF22V10C(Q)Z
ATF22V10CZ/CQZ Ordering Information
tPD
tS
tCO
(ns)
(ns)
(ns)
Ordering Code
Package
Operation Range
12
10
8
ATF22V10CZ-12JC
ATF22V10CZ-12PC
ATF22V10CZ-12SC
ATF22V10CZ-12XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
15
4.5
8
ATF22V10CZ-15JC
ATF22V10CZ-15PC
ATF22V10CZ-15SC
ATF22V10CZ-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF22V10CZ-15JI
ATF22V10CZ-15PI
ATF22V10CZ-15SI
ATF22V10CZ-15XI
28J
Industrial
24P3
24S
24X
(-40°C to +85°C)
20
14
12
ATF22V10CQZ-20JC
ATF22V10CQZ-20PC
ATF22V10CQZ-20SC
ATF22V10CQZ-20XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF22V10CQZ-20JI
ATF22V10CQZ-20PI
ATF22V10CQZ-20SI
ATF22V10CQZ-20XI
28J
Industrial
24P3
24S
24X
(-40°C to +85°C)
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-pin, 0.300", Plastic Dual Inline Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)
24-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
11
Packaging Information
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3, 24-pin, 0.300" Wide,
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
.045(1.14) X 30° - 45°
1.27(32.3)
1.25(31.7)
.045(1.14) X 45° PIN NO. 1
.012(.305)
.008(.203)
PIN
1
IDENTIFY
.430(10.9)
.390(9.91)
.021(.533)
.013(.330)
.266(6.76)
.250(6.35)
SQ
.456(11.6)
.450(11.4)
SQ
.032(.813)
.026(.660)
.495(12.6)
.485(12.3)
.090(2.29)
SQ
MAX
1.100(27.94) REF
.200(5.06)
MAX
.050(1.27) TYP
.043(1.09)
.005(.127)
MIN
.300(7.62) REF SQ
.020(.508)
.120(3.05)
.090(2.29)
SEATING
PLANE
.180(4.57)
.165(4.19)
.070(1.78)
.020(.508)
.023(.584)
.014(.356)
.151(3.84)
.125(3.18)
.065(1.65)
.040(1.02)
.022(.559) X 45° MAX (3X)
.110(2.79)
.090(2.29)
.325(8.26)
.300(7.62)
0
15
REF
.012(.305)
.008(.203)
.400(10.2) MAX
24S, 24-lead, 0.300" Wide,
Plastic Gull-Wing Small Outline (SOIC)
24X, 24-lead, 4.4 mm Wide, Plastic Thin Shrink
Small Outline (TSSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
.020(.508)
.013(.330)
.299(7.60) .420(10.7)
.291(7.39) .393(9.98)
PIN 1 ID
.050(1.27) BSC
.616(15.6)
.598(15.2)
.105(2.67)
.092(2.34)
.012(.305)
.003(.076)
.013(.330)
.009(.229)
.050(1.27)
.015(.381)
0
8
REF
ATF22V10C(Q)Z
12
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相关型号：
ATF22V10CZ/CQZ
ATF22V10CZ/CQZ [Updated 3/01. 13 Pages] 500 gate high-speed. zero power electrically erasable PLD. 24 pins
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