ATF280E [ATMEL]
Rad Hard Reprogrammable FPGA; 抗辐射FPGA的可再编程
| 型号： | ATF280E |
| 厂家： | 
ATMEL |
| 描述： | Rad Hard Reprogrammable FPGA |
| 文件： | 总45页 (文件大小：1465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
SRAM based FPGA designed for Space use
– 280K equivalent ASIC gates
– Unlimited reprogrammability
– SEE hardened cells (Configuration RAM, FreeRAMTM, DFF, JTAG, I/O buffers)
– No need for Triple Modular Redundancy (TMR)
FreeRAM™:
•
– 115200 Bits of Distributed RAM
– 32x4 RAM blocks organization
– Independent of Logic Cells
– Single/Dual Port capability
– Synchronous/Asynchronous capability
Global Reset Option
Rad Hard
Reprogrammable
FPGA
•
•
•
•
8 Global Clocks and 4 Fast Clocks
8 LVDS transceivers and 8 LVDS receivers
Cold sparing and PCI Compliant I/Os
– 308 for 472pins MCGA package
– 150 for 256pins MQFPF package
Flexible Configuration modes
– Master/Slave Capability
ATF280E
•
– Serial/Parallel Capability
– Check of the data during FPGA configuration
Self Integrity Check (SIC) of the configuration during FPGA operation
Performance
•
•
Advance
– 100 MHz Internal Performance
– 50MHz System Performance
– 10ns 32X4 FreeRAM™ access time
Operating range
Information
•
– Voltages
• 1.65V to 1.95V (Core)
• 3V to 3.6V (Clustered I/Os)
– Temperature
• - 55°C to +125°C
•
Radiation Performance
– Total Dose tested up to 300 krads (Si)
– No single event latch-up below a LET of 80 MeV/mg/cm2
ESD better than 2000V
•
•
Quality Grades
– QML-Q or V
– ESCC
•
•
Ceramic packages
– 256pins MQFPF (150 I/Os, 8 LVDS Tx and 8 LVDS Rx)
– 472pins MCGA (308 I/Os, 8 LVDS Tx and 8 LVDS Rx)
Design Kit including
– ATF280E and Configurator Samples
– Evaluation Board
– Software Design Tools
– ISP Cable/Dongle
7750A–AERO–07/07
1. Description
The ATF280E is a radiation hardened SRAM-based reprogrammable FPGA. It has been espe-
cially designed for space application by implementing hardened cells and permanent self-
integrity check mechanism.
The ATF280E is manufactured using the ATMEL 0.18µ rad-hard AT58KRHA CMOS technology.
The Atmel architecture is developed to provide the highest levels of performance, functional
density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can
implement any pair of Boolean functions of (the same) three inputs or any single Boolean func-
tion of four inputs. The cell’s small size leads to arrays with large numbers of cells, greatly
multiplying the functionality in each cell. A simple, high-speed busing network provides fast, effi-
cient communication over medium and long distances.
The ATF280E FPGA offers a patented distributed 10 ns SEU hardened SRAM capability where
the RAM can be used without losing logic resources. Multiple independent, synchronous or
asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created
using Atmel’s macro generator tool. They are organized by blocks of 32x4 bits. The ATF280E
also embeds 8 global clocks, 4 high speed clocks, 8 LVDS Transmit channels, 8 LVDS Receive
channels and a complete set of cold sparing programmable I/Os. The ATF280E I/Os are fully
PCI-compliant.
The ATF280E is available in two space qualified packages. The MCGA472 package offers up to
324 I/Os for user application. The MQFP256 package is also proposed for application requiring
less than 166 I/Os.
2
ATF280E
7750A–AERO–07/07
ATF280E
2. Pin Configuration
Table 2-1.
ATF280E MCGA472 pin assignment
LEAD
A3
Signal
VDD
VSS
IO
Cluster
1
LEAD
C7
Signal
IO/D2
IO/CHECKN
IO
Cluster
12
12
12
11
11
11
11
10
10
10
10
10
10
4
LEAD
E7
Signal
IO/FCK4
IO
Cluster
12
12
12
12
12
11
10
10
10
10
10
10
9
A4
1
C8
E8
A5
12
12
12
12
12
12
11
10
10
10
10
10
10
10
1
C9
E9
IO
A6
VCC
IO
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
OLVDS6N
OLVDS6
ILVDS5N
ILVDS5
IO
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
VCC
IO
A7
A8
VCC
IO
REFEast
IO
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B2
IO/D3
VCCB
IO
IO
VCC
IO
VCC
IO/FCK3
IO/D5
IO/D6
IO
IO
VCC
IO
VCC
IO
IO
IO
VSS
VDD
VDD
VSS
IO/A2/CS1N
IO
IO
9
IO
5
IO
9
VCC
VSS
VDD
VSS
VDD
VCC
IO
6
IO
9
6
VCC
IO
1
3
D2
1
F2
1
3
D3
1
F3
IO
1
B3
3
D4
VCC
IO
12
12
12
12
12
12
12
12
10
10
10
10
10
10
10
9
F4
IO/A0
IO
1
B4
12
12
12
12
12
12
11
11
11
11
10
10
10
10
10
10
D5
F5
1
B5
D6
CCLK
IO
F6
IO
12
B6
IO
D7
F7
IO/GCK6/CSOUTN
12
12
12
12
12
10
10
10
10
10
9
B7
IO
D8
IO
F8
IO/D0
IO
B8
IO
D9
VCC
IO
F9
B9
IO
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
IO
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
OLVDS5N
OLVDS5
ILVDS6N
ILVDS6
IO
IO
IO
IO/D4
VCC
IO
VCC
IO
IO
IO
IO/D7
DIODE
IO
IO/CS0
VCC
IO
IO
IO
IO
VCC
CON
VCC
9
IO
VCC
IO/D8
9
IO
9
9
3
7750A–AERO–07/07
LEAD
B20
B21
C1
Signal
VDD
VSS
VDD
VDD
VSS
IO
Cluster
LEAD
D21
D22
E1
Signal
VCC
VSS
VCC
IO
Cluster
LEAD
F21
F22
G1
Signal
IO/D9
IO
Cluster
4
3
9
6
9
9
1
1
1
1
1
1
4
1
IO
C2
4
E2
1
G2
VCC
C3
4
E3
IO
1
G3
IO
C4
12
12
12
E4
IO
1
G4
IO/A3
IO
C5
IO
E5
IO
1
G5
C6
IO
E6
VCC
12
G6
IO/GCK7/A1
4
ATF280E
7750A–AERO–07/07
ATF280E
Table 2-2.
ATF280E MCGA472 pin assignment
LEAD
G7
Signal
IO
Cluster
12
12
12
12
12
10
10
10
10
9
LEAD
J8
Signal
VCC
IO
Cluster
LEAD
L9
Signal
IO
Cluster
1
1
3
1
G8
VCC
IO/D1
IO
J9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
M1
IO/A6
IO
G9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
IO
12
12
12
10
10
9
1
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO
IO
10
9
VCC
IO
IO
IO
IO
IO
9
IO
IO/GCK5
VCC
IO
VCC
IO
9
IO
9
IO
9
IO
9
IO
IO
9
IO
9
IO/GCK4
IO/D10
IO
9
IO
9
IO
9
9
VCC
IO/D11
IO
9
OLVDS4
OLVDS3
IO
8
8
7
1
2
2
2
3
3
3
3
3
3
4
7
7
9
8
7
7
8
7
8
8
7
3
2
9
9
IO
9
9
IO
9
IO
9
IO
IO
9
IO
1
M2
OLVDS7
OLVDS8
VCCB
IO
IO/A4
IO
1
K2
ILVDS8
ILVDS7
VCC
IO
2
M3
H2
1
K3
2
M4
H3
IO
1
K4
1
M5
H4
IO
1
K5
1
M6
IO
H5
VCC
IO
1
K6
VCC
IO
1
M7
IO
H6
1
K7
1
M8
IO
H7
IO
1
K8
IO
1
M9
IO
H8
VCC
VCC
IO
1
K9
IO
1
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
N1
IO
H9
12
12
12
12
10
10
10
9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
TCK
IO
1
IO
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
12
10
10
9
IO/D14
IO
IO
IO
IO
RESETN
IO
IO/D12
VCCB
IO/D13
IO
IO
VCC
VCC
VCC
IO
IO
9
VCC
IO
9
9
REFSouth
VCC
9
VCC
IO
9
IO
9
9
ILVDS3N
ILVDS4N
IO
IO
9
OLVDS4N
OLVDS3N
IO
8
IO
9
8
IO
9
9
IO
IO
9
IO/A7
1
N2
OLVDS7N
5
7750A–AERO–07/07
LEAD
J1
Signal
IO
Cluster
LEAD
L2
Signal
ILVDS8N
ILVDS7N
VCC
Cluster
LEAD
N3
Signal
OLVDS8N
IO
Cluster
1
1
1
1
1
1
1
2
2
1
2
1
1
3
2
3
3
3
3
3
3
J2
IO
L3
N4
J3
IO
L4
N5
IO/A9
IO
J4
IO/A5
IO
L5
REFNorth
IO
N6
J5
L6
N7
VCC
J6
VCC
IO
L7
IO
N8
IO/A12
IO
J7
L8
IO/A8
N9
6
ATF280E
7750A–AERO–07/07
ATF280E
Table 2-3.
Cluster
ATF280E MCGA472 pin assignment
LEAD
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
Signal
LEAD
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
Signal
IO
Cluster
LEAD
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
Signal
Cluster
TMS
4
4
6
7
7
7
7
7
7
7
8
8
7
3
3
3
3
3
3
3
3
4
4
6
6
6
7
7
7
7
7
7
7
7
7
3
3
3
4
5
6
6
6
7
7
7
7
7
7
7
7
3
3
3
3
3
3
3
4
4
4
4
6
6
6
6
6
7
7
7
7
7
7
3
3
3
VCC
IO
4
4
6
6
6
6
6
6
7
7
7
7
7
3
3
3
3
4
4
4
4
4
4
5
6
6
6
6
6
6
7
7
7
7
7
7
3
3
IO
IO
VCCB
VCC
IO
IO
M1
IO
IO
VCC
VCC
IO
IO
IO
IO
IO
IO/GCK2
IO
VCC
IO
IO
VCC
IO
IO
VCC
ILVDS3
ILVDS4
IO
IO
IO
IO
IO
IO/D15
VCC
IO
IO
VCC
IO
IO/A11
IO
P2
T2
V2
IO
P3
IO
T3
IO
V3
IO
P4
VCC
VCC
IO
T4
IO
V4
IO
P5
T5
IO
V5
IO
P6
T6
TDO
IO/A14
IO
V6
IO
P7
IO/A13
VCC
IO/GCK1/A16
IO
T7
V7
IO/A19
VCC
VCC
IO
P8
T8
V8
P9
T9
IO
V9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
IO
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO
IO/A20
IO
REFWest
IO
IO
IO
VCC
IO
IO
IO/GCK3
VCC
IO
VCC
IO
VCC
IO
IO/A22
VCC
IO
VCC
IO
M2
IO/INIT
IO
IO
IO
IO
IO
IO
IO
VCC
IO
IO
IO
VCC
VSS
VCC
IO
IO
IO
R2
IO
U2
IO
W2
R3
IO
U3
VCC
W3
7
7750A–AERO–07/07
LEAD
R4
Signal
IO
Cluster
LEAD
U4
Signal
TDI
Cluster
LEAD
W4
Signal
VCC
IO
Cluster
3
3
3
3
4
4
3
3
3
4
4
4
3
4
4
4
4
4
R5
IO/A10
IO
U5
VCC
W5
R6
U6
IO/GCK8/A15
TRST
W6
IO
R7
VCC
VCC
VCC
U7
W7
IO
R8
U8
IO
W8
IO
R9
U9
VCC
W9
IO
8
ATF280E
7750A–AERO–07/07
ATF280E
Table 2-4.
ATF280E MCGA472 pin assignment
LEAD
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
Signal
IO
Cluster
LEAD
AA4
Signal
IO/A17
IO
Cluster
4
4
6
6
6
6
6
6
6
6
7
7
7
7
7
9
4
4
4
4
4
4
5
5
5
5
6
6
6
6
6
6
9
7
9
10
9
4
4
VCC
IO
AA5
AA6
IO/A18
VCC
IO
4
IO
AA7
4
VCC
IO
AA8
4
AA9
IO
4
IO
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AB3
ILVDS2
ILVDS2N
OLVDS1
OLVDS1N
IO
5
M0
5
IO
5
VCC
IO
5
6
IO/LDC
VSS
VDD
VDD
VSS
IO
IO
6
IO
6
IO/A23
IO
6
Y2
6
Y3
VCC
VDD
VSS
VDD
VSS
VCC
VCC
IO
6
Y4
10
10
12
12
4
Y5
IO
Y6
IO
Y7
IO
AB4
Y8
IO
AB5
Y9
IO
AB6
4
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA2
AA3
ILVDS1
ILVDS1N
OLVDS2
OLVDS2N
IO
AB7
4
AB8
IO/FCK1
IO
4
AB9
4
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
IO
4
IO
4
IO
IO/A21
IO
6
IO
6
VCC
IO
IO
6
IO
6
IO/OTSN
VSS
VDD
VDD
VSS
VDD
IO/FCK2
IO
6
6
IO
6
VSS
VDD
12
12
9
7750A–AERO–07/07
3. Pin Description
Clock
GCK1:GCK8 - Global Clock (Input)
FCK1:FCK4 - Fast Clock (Input)
I/O
I/Oy_x - Programmable I/O (Input/Output)
The programmable I/Os are dedicated to user’s application. Each programmable I/O can inde-
pendently be configured as input, output or bidirectional I/O. Each I/O is part of an I/O cluster.
This leads to the following naming: I/Oy_x where ‘y’ is the cluster number (1 < y < 8) and ‘x’ is
the I/O number in the cluster.
OLVDSx - LVDS Driver (Output)
OLVDSx where ‘x’ is the LVDS channel number (1 < x < 8).
OLVDSxN - Complimentary LVDS Driver (Output)
OLVDSxN where ‘x’ is the LVDS channel number (1 < x < 8).
ILVDSx - LVDS Receiver (Input)
ILVDSx where ‘x’ is the LVDS channel number (1 < x < 8).
ILVDSxN - Complimentary LVDS Receiver(Input)
ILVDSxN where ‘x’ is the LVDS channel number (1 < x < 8).
FPGA Configuration
M0, M1, M2 (Input)
The mode pins are dedicated TTL threshold inputs that determine the configuration mode to be
used. Table 1 lists the states for each configuration mode. The mode pins should not be
changed during power-on-reset, manual reset, or configuration download. The user may change
the mode pins during configuration idle. These pins have no pull-up resistors to VCC, so they
need to be driven by the user or tied off.
CCLK (Input/Output)
CCLK is the configuration clock pin. It is an input or output depending on the mode of operation.
During power-on-reset or manual reset, it is a tri-stated output. During configuration download
and in Mode 0, it is an output with a typical frequency of 1 MHz. During configuration download
and in all other modes, it is a Schmitt trigger input with approximately 1V of hysteresis for noise
immunity. It is an input during configuration idle, but is ignored. It is pulled to VCC with a nominal
50K internal resistor.
RESETn - Reset (Input)
RESETn is the FPGA configuration manual reset pin. It is available during all configuration
states. It initiates a configuration clear cycle and, if operating in Mode 0, an auto configuration. It
is a dedicated Schmitt trigger input with approximately 1V of hysteresis for noise immunity. It is
pulled to VCC with a nominal 50K internal resistor.
INIT - (Input/Output)
10
ATF280E
7750A–AERO–07/07
ATF280E
INIT is a multi-function pin. During power-on-reset and manual reset, the pin functions as an
open drain bi-directional I/O which releases High when the configuration clear cycle is complete,
but can be held Low to hold the configuration in a reset state. Once released, the FPGA will pro-
ceed to either configuration download or idle, as appropriate. During configuration download, the
INIT pin is again an open drain bi-directional pin which signals if an error is encountered during
the download of a configuration bitstream. In addition, during the Check Function, the INIT pin
drives Low for any configuration SRAM mismatch (see the description of the Check Function on
page 16 for more details). While in open drain mode, the pin is pulled to VDD with a nominal 20K
internal resistor. When not configuring, the INIT pin becomes a fully functional user I/O.
CON - Configuration Status (Input/Output)
CON is the FPGA configuration start and status pin. It is a dedicated open drain bi-directional
pin. During power-on-reset or manual reset, CON is driven Low by the FPGA. In Modes 2, 6, or
7, when the FPGA has finished the configuration clear cycle, CON is released to indicate the
device is ready for the user to initiate configuration download. The user may then drive CON
Low to initiate a configuration download. After three clock cycles, CON is then driven Low by the
FPGA until it finishes the download, and it is then released. In Mode 0, CON is not released by
the FPGA at the end of power-on-reset or manual reset. Instead, CON is controlled by the FPGA
until the end of the auto-configuration process. CON is released at the end of configuration
download in Mode 0, and the user may then initiate a manual configuration download by driving
CON Low. While in open drain mode, the pin is pulled to VDD with a nominal 10K internal
resistor.
HDC - High During Configuration (output)
HDC(1) is driven High by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
LDC - Low During Configuration (output)
HDC(1) is driven Low by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
D0 - Configuration Data Bus - LSB (Input/Output)
D0 is the lsb of the FPGA configuration data bus used to download configuration data to the
device. During power-on-reset or manual reset, D0 is controlled by the configuration SRAM. The
D0 pin will transition from the user programmed state to a CMOS input with a nominal 20K inter-
nal pull-up resistor as the SRAM at that location is cleared by the configuration clear cycle. D0
becomes an input during configuration download.
D1:D15 - Configuration Data Bus - Upper bits (Input/Output)
D1:D15 are the upper bits of the 8/16-bit parallel data bus used to download configuration data
to the device. During power-on-reset or manual reset, D1:D15 are controlled by the configura-
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tion SRAM. The D1:D15 pins will transition from the user programmed state to CMOS inputs
with nominal 20K internal pull-up resistors as the SRAM at those locations is cleared by the con-
figuration clear cycle.
When in Modes 2 or 6, D1:D7 become inputs during configuration download. D1:D7 are not
used in the serial Modes 0, 1 and 7.
When in Modes 2 or 6, D8:D15 become optional inputs during configuration download. They
become available as soon as the appropriate bit in the configuration control register is set.
D8:D15 are not used in the serial Modes 0, 1 and 7.
A0:A19 - Configuration Address Bus (Input/Output)
A0:A19(1) are used to control external addressing of memories during downloads. During
power-on-reset or manual reset, A0:A19 are controlled by the configuration SRAM. The A0:A19
pins will transition from the user programmed state to CMOS inputs with nominal 20K internal
pull-up resistors as the SRAM at those locations is cleared by the configuration clear cycle.
When in Mode 6, A0:A19 become outputs during configuration download. A0:A19 are used only
in Mode 6.
Note: 1. Pin A2 is also pin CS1, which is available only for Mode 2. See the description for CS1
on page 5 for more details.
CS0/CS1 - Configuration Chip Select (Input/Output)
CS0 is an FPGA configuration chip select. It is active Low. During power-on-reset or manual
reset, CS0 is controlled by the configuration SRAM. The CS0 pin will transition from the user
programmed state to a CMOS input with a nominal 20K internal pull-up resistor as the SRAM at
that location is cleared by the configuration clear cycle. In Mode 1, it is used as a chip select to
enable configuration to begin. It is most often used as the chip select of the downstream device
in a cascade chain, and is usually driven by CSOUT of the upstream device. Releasing CS0 dur-
ing configuration causes the Mode 1 FPGA to abort the download and release CON.
CS0 is used only in Mode 1. CS1 is used only in Mode 2
Note: 1. Pin CS1 is also pin A2, which is active only for Mode 6. See the description for A0:A19,
on page 5 for more details.
CSOUT - Configuration Cascade Output (Output)
CSOUT is the configuration pin used to enable the downstream device in a cascade chain. Dur-
ing power-on-reset or manual reset, CSOUT is controlled by the configuration SRAM. The
CSOUT pin will transition from the user programmed state to a CMOS input with a nominal 20K
internal pull-up resistor as the SRAM at that location is cleared by the configuration clear cycle.
During configuration download, CSOUT becomes an optional output. It is enabled by default
after reset, and may be enabled or disabled via the configuration control register. If the user has
disabled the cascade function, the pin remains a user I/O. If the cascade function is enabled, the
CSOUT pin is driven High at the start of configuration download. At the end of the device’s por-
tion of the cascade bitstream, the CSOUT pin is driven Low (and into the CS0 or CS1 of the
downstream device) to enable the downstream device. CSOUT is released by the device at the
end of the cascade bitstream and becomes a fully functional user I/O.
CHECK - Configuration Check (Input/Output)
CHECK is a configuration control pin used to control the Check Function. The Check Function
takes a bitstream and compares it to the contents of a previously loaded bitstream and notifies
the user of any differences. Any differences causes the INIT pin to go Low. During power-on-
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ATF280E
reset or manual reset, CHECK is controlled by the configuration SRAM. The CHECK pin will
transition from the user programmed state to a CMOS input with a nominal 20K internal pull-up
resistor as the SRAM at that location is cleared by the configuration clear cycle. During configu-
ration download, CHECK becomes an optional input. It is enabled by default after reset, and
may be enabled or disabled via the configuration control register. If the user has disabled the
Check Function, the pin remains a user I/O.
OTS - Dual Use Tri State (Input)
OTS is an input pin used to immediately tri-state all user I/O. It is enabled by a bit in the configu-
ration control register. Once activated, it is always an input. The OTS tri-state control of Dual-use
pins is superseded by the configuration logic’s claim on those pins. If the user has disabled the
OTS function, the pin remains as User I/O.
JTAG
TCK - Test Clock (input)
Used to clock serial data into boundary scan latches and control sequence of the test
state machine. TCK can be asynchronous with CLK.
TMS - Test Mode select (input)
Primary control signal for the state machine. Synchronous with TCK. A sequence of values on
TMS adjusts the current state of the TAP.
TDI - Test data input (input)
Serial input data to the boundary scan latches. Synchronous with TCK
TDO - Test data output (output)
Serial output data from the boundary scan latches. Synchronous with TCK
TRST - Test Reset (input)
Resets the test state machine. Can be asynchronous with TCK. Shall be grounded for end
application.
Power Supply
VDD - Core Power Supply
VDD is the power supply input for the ATF280E core. VDD = 1.8V 0.2V
VCCy - I/O Power Supply
VCC is the power supply input for the programmable I/Os. Each I/O cluster has dedicated VCCy
sources where ‘y’ is the cluster number (1 < y < 8). VCC can be independently configured to
either 1.8V 0.2V or 3.3V 0.3V for each cluster.
VCCB - LVDS I/O Power Supply
VCCB is the power supply input for the LVDS I/Os. Each pair of LVDS channels has a dedicated
VCCB sources. VCCB = 3.3V 0.3V
VREF - LVDS reference voltage
VREF is the reference voltage for LVDS buffer operations. Each LVDS cluster has dedicated
VREF source. VREF = 1.25V 0.1V
VSS - Ground
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4. ATF280E FPGA Architecture
4.1
The Symmetrical Array
At the heart of the Atmel ATF280E architecture is a symmetrical array of identical cells. The
array is continuous from one edge to the other, except for bus repeaters spaced every four cells.
At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adja-
cent buses. The RAM can be configured as either a single-ported or dual-ported RAM (1), with
either synchronous or asynchronous operation
Figure 4-1. Core device overview
Note:
1. the right-most column can only be used as single-port RAM.
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ATF280E
Figure 4-2. Floor-plan for a 12x12 cells array(1).
Note:
1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are
legal) on the same plane. Each repeater has connections to two adjacent local-bus segments
and two express-bus segments. This is done automatically using the integrated development
system (IDS) tool.
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4.2
The Core Cell
The following figure depicts the ATF280E cell which is a highly configurable logic block based
around two 3-input LUTs (8 x 1 ROM), and which can be combined to produce one 4-input LUT.
This means that any cell can implement two functions of 3 inputs or one function of 4 inputs.
Figure 4-3. ATF280E Core Cell
Every cell includes a register element, a D-type flip-flop, with programmable clock and reset
polarities. The initialization of the register is also programmable. It can be either SET or RESET.
The flip-flop can be used to register the output of one of the LUT. It can also be exploited in con-
junction with the feedback path element to implement a complete ripple counter stage in a single
cell. The registered or unregistered output of each LUT can be feedback within the cell and
treated as another input (Feedback signal in Figure 3). This allows, for example, a single counter
stage to be implemented within one cell without using external routing resources for the feed-
back connection.
There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the “front end” of
the cell. This AND gate is an important feature in the implementation of efficient array multipliers
as the product and carry terms can both be generated within a single logic cell.
The cell flexibility makes the ATF280E architecture well suited for most of the digital design
application areas.
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ATF280E
4.2.1
Synthesis Mode
This mode is particularly important for the use of VHDL design. VHDL Synthesis tools generally
will produce as their output large amounts of random logic functions. Having a 4-input LUT struc-
ture gives efficient random logic optimization without the delays associated with larger LUT
structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell.
Figure 4-4. Synthesis Modes
4.2.2
Arithmetic Mode
This mode is frequently used in many designs. As can be seen in the figure, the ATF280E core
cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core
cell. Note that the sum output in this diagram is registered. This output could then be tri-stated
and/or fed back into the cell.
Figure 4-5. Arithmetic Mode
4.2.3
DSP/Multiplier Mode
This mode is used to efficiently implement array multipliers. An array multiplier is an array of bit-
wise multipliers, each implemented as a full adder with an upstream AND gate. Using this AND
gate and the diagonal interconnects between cells, the array multiplier structure fits very well
into the ATF280E architecture.
Figure 4-6. DSP/Multiplier Mode
4.2.4
Counter Mode
Counters are fundamental to almost all digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an
adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit
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counter can be implemented in one core cell. Again, the output can be registered, tri-stated
and/or fed back.
Figure 4-7.
Counter Mode
4.2.5
Tri-state/Mux Mode
This mode is used in many telecommunications applications, where data needs to be routed
through more than one possible path. The output of the core cell is very often tri-statable for
many inputs to many outputs data switching.
Figure 4-8. Tri-state/Mux Mode
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ATF280E
4.3
The Busing Network
The following figure depicts one of five identical busing planes. Each plane has three bus
resources:
• a local-bus resource (the middle bus)
• two express-bus (both sides) resources
Figure 4-9. Busing Plane
The bus resources are connected via repeaters. Each repeater has connections to two adjacent
local-bus segments and two express-bus segments.
Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-
bus segment spans eight cells and “leapfrogs” or bypasses a repeater. Repeaters regenerate
signals and can connect any bus to any other bus (all pathways are legal) on the same plane.
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Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing
long on-chip tri-state buses to be created. Local/Local turns are implemented through pass
gates in the cell-bus interface (see following page).
Express/Express turns are implemented through separate pass gates distributed throughout the
array.
4.3.1
Dual Function Bus Resource
Some of the bus resource on the ATF280E are used as a dual-function resource. The table
hereafter shows which buses are used in a dual-function mode and which bus plane is used.
Table 4-1.
Dual-function Buses
Function
Type
Plane(s)
Direction
Comments
Horizontal and
Vertical
Cell Output Enable
RAM Output Enable
RAM Write Enable
RAM Address
Local
5
2
Bus full length at array edge
Express
Express
Express
Vertical
Vertical
Vertical
Bus in first column to left of RAM block
Bus full length at array edge
1
Bus in first column to left of RAM block
Buses full length at array edge
1 - 5
Buses in second column to left of RAM block
RAM Data In
RAM Data Out
Clocking
Local
Local
1
2
4
5
Horizontal
Horizontal
Vertical
Express
Express
Bus half length at array edge
Bus half length at array edge
Set/Reset
Vertical
The ATF280E software tools are designed to accommodate dual-function buses in an efficient
manner
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ATF280E
4.4
Cell Connections
The following figure presents the direct connections between a cell and its eight nearest neigh-
bors. It also summarizes the connections between a cell and five horizontal local buses (1 per
busing plane) and five vertical local buses (1 per busing plane).
Figure 4-10. Cell Connections
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5. FreeRAMTM
The ATF280E offers 115Kbits of dual-port RAM called FreeRAMTM. The FreeRAMTM is made of
32 x 4 dual-ported RAM blocks and dispersed throughout the array as shown in the figure here-
after. This FreeRAMTM is SEU hardened.
A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four
sector rows (plane 2). A 5-bit Input Address Bus connects to five vertical express buses in same
column. A 5-bit Output Address Bus connects to five vertical express buses in same column. Ain
(input address) and Aout (output address) alternate positions in horizontally aligned RAM
blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-
most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single
port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional)
data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to
the vertical express buses in the same column.
Figure 5-1. RAM Connections (One RAM Block)
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ATF280E
Reading and writing of the 10ns 32 x 4 dual-port FreeRAM are independent of each other. Read-
ing the 32 x 4 dual-port RAM is completely asynchronous.
Latches on Write Address, Write Enable and Data In are transparent: when Load is logic 1, data
flows through, when Load is logic 0, data is latched. These latches are used to synchronize
Write Address, Write Enable Not, and Din signals for a synchronous RAM.
Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the
memory latch together form an edge-triggered flip flop. When a nibble is (Write) addressed and
LOAD is logic 1 and WE is logic 0, data flows through the bit. When a nibble is not (Write)
addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble.
The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous
RAM) or they both select “1” (for an asynchronous RAM). CLOCK is obtained from the clock for
the sector-column immediately to the left and immediately above the RAM block.
Writing any value to the RAM clear byte during configuration clears the RAM (see the
“AT40K/40KAL Configuration Series” application note at www.atmel.com).
Figure 5-2. RAM Logic
Note:
Ain and Aout are 5 bits wide, and the memory block is 32x4.
Here is an example of a RAM macro constructed using ATF280E’s FreeRAM cells. The macro
shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic
required to complete the address decoding for the macro. Most of the logic cells in the sectors
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occupied by the RAM will be unused: they can be used for other logic in the design. This logic
can be automatically generated using the macro generators.
Figure 5-3. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous)
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ATF280E
6. Clocking Scheme
The entire ATF280E clocking scheme (including clock trees and muxes) is SET hardened.
There are eight differential Global Clock buses (GCK1 - GCK8) on the ATF280E FPGA. In addi-
tion to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4).
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column
Clock mux is at the top of every column of an array and the Sector Clock mux is at every four
cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock
provided to each sector column of four cells is inverted, non-inverted or tied off to “0”, using the
Sector Clock mux to minimize the power consumption in a sector that has no clocks.
The clock can either come from the Column Clock or from the Plane 4 express bus. The
extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast
clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well,
FCK3 and FCK4, to provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configuration at
power-up, constant “0” is provided to each register’s clock pins. After configuration at power-up,
the registers either set or reset, depending on the user’s choice. The clocking scheme is
designed to allow efficient use of multiple clocks with low clock skew, both within a column and
across the core cell array.
Figure 6-1. Clocking (for One Column of Cells)
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6.1
Global Clocks
Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global
Clock pins. Any clocks used in the design should use global clocks where possible. These sig-
nals are distributed across the top edge of the FPGA along special high-speed buses. Global
Clock signals can be distributed throughout the FPGA with less than 1 ns skew.
This can be done by using Assign Pin Locks command in the IDS software to lock the clocks to
the Global Clock locations.
6.2
Fast Clocks
There are four Fast Clocks (FCK1 - FCK4) on the ATF280E, two per edge column of the array
for PCI specification. Even the derived clocks can be routed through the Global network. Access
points are provided in the corners of the array to route the derived clocks into the global clock
network.
The IDS software tools handle derived clocks to global clock connections automatically if used.
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ATF280E
7. Set/Reset Scheme
The ATF280E reset scheme is essentially the same as the clock scheme except that there is
only one differential Global Reset. A dedicated Global Set/Reset bus can be driven by any User
I/O, except those used for clocking (Global Clocks or Fast Clocks). Like the clocking scheme,
set/reset scheme is SET hardened.
The automatic placement tool will choose the reset net with the most connections to use the glo-
bal resources. You can change this by using an RSBUF component in your design to indicate
the global reset. Additional resets will use the express bus network.
The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is
Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane
5 express bus or Global Set/Reset using the Sector Set/Reset mux (Figure 10). The set/reset
provided to each sector column of four cells is either inverted or non-inverted using the Sector
Reset mux.
The function of the Set/Reset input of a register is determined by a configuration bit in each cell.
The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a regis-
ter is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each
register (i.e., all registers are set at power-up).
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Figure 7-1. Set/Reset (for One Column of Cells)
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ATF280E
8. I/O Specifications
The ATF280E provides 2 types of I/O which are all cold sparing:
• programmable I/Os (PCI compatible)
• LVDS I/Os
The ATF280E periphery is divided into 12 clusters. Height clusters are dedicated to programma-
ble I/Os and four clusters are dedicated to LVDS. Each cluster consists in a set of I/O together
with its dedicated power supply source.
8.1
Programmable I/Os
Each Programmable I/O cluster has its dedicated power supply source. Programmable I/Os are
powered through VCC pads. VDD and VSS power lines are common to all clusters.
Programmable I/O clusters accept 2 different voltages. This feature provides the possibility to
use some programmable I/O clusters at either 1.8V or 3.3V.
Each programmable I/O can be configured as input, output or bi-directional. When configured as
input an optional Schmitt trigger can be enabled on the I/O. When configured as output optional
PCI compatibility can be enabled. In addition it is possible to select the buffer drive to optimize
speed of the application.
In addition, the ATF280E provides pull-up and pull-down capability on each I/O. The following
section presents all the configuration available on the programmable I/Os
8.1.1
8.1.2
Pull-up/Pull-down
Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak “1” or
“0” level to the pad pin. When all other drivers are off, this control will dictate the signal level of
the pad pin.
JTAG
All programmable I/Os (including LVDS buffers) are 1149.1 compliant. Each I/O may be included
or excluded from boundary scan chain during the configuration of the FPGA.
8.1.3
8.1.4
CMOS
The threshold level of the I/O is CMOS-compatible.
Schmitt
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative com-
parator circuit that adds 0.8V hysteresis to the input. This effectively improves the rise and fall
times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise.
8.1.5
8.1.6
Delays
Drive
The input buffer can be programmed to include four different intrinsic delays as specified in the
AC timing characteristics. This feature is useful for meeting data hold requirements for the input
signal.
The output drive capabilities of each I/O are programmable. They can be set to FAST, MEDIUM
or SLOW. The FAST setting has the highest drive capability (PCI compatible) buffer and the
fastest slew rate. MEDIUM produces a medium drive buffer, while SLOW yields a standard
buffer.
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Drive capability is dependent upon setting FAST, MEDIUM and SLOW performance and sup-
plies voltage.
Table 8-1.
Drive Capability for VCC = 3.3V
VCC = 3.3V
config.
Slow
IOh(mA)
IOl(mA)
Worst case
typical
Worst case
typical
30
13
5
20
8
17
5
Medium
Fast
10
18.5
29
23
40
Table 8-2.
Drive Capability for VCC = 1.8V
VCC =1.8V
config.
Slow
IOh(mA)
IOl(mA)
Worst case
typical
Worst case
typical
6
2
8
10
4
7
2
15
5
Medium
Fast
15
10
21
When no modification is performed by the user on the IDS software, the default configuration of
the drive for the I/Os is SLOW.
8.1.7
8.1.8
Tri-State
The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open drain (0 or
Z) by programming an I/O’s Source Selection mux. Of course, the output can be normal (0 or 1),
as well.
Dual-use I/O
Any pin which functions as user I/O and configuration I/O is a dual-use I/O pin. INIT, HDC, LDC,
D0:D15, A0:A19, CS0, CS1, CSOUT, CHECK, and OTS are all dual-use I/O pins.
It must be noted that while the configuration logic controls dual-use I/O pins during a particular
mode of operation, the configuration logic does not control the pull-up, pull-down, CMOS/TTL
threshold select, or Schmitt trigger selects.
The user must be cautioned to avoid possible system problems with the use of dual-use I/O
pins. For example, turning off the internal pull-up resistor for the open drain INIT pin would not
apply the weak High required of an open drain driver. Conversely, disabling the pull-up and
enabling the pull-down of the HDC pin might be a good idea, since the user may then actually
see the pin go Low at the end of configuration.
Dual-use pins share input buffers. It should be noted that even when the configuration has
claimed a pin for its own purposes, the user input buffer is still fully functional. This implies that
any user logic tied to the input buffers of the pins in question will remain operational.
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ATF280E
Figure 8-1. Dual Use I/O principle
8.2
LVDS I/Os
Each LVDS cluster has its dedicated power supply source. LVDS I/Os are powered through
VCCB pads. VDD and VSS power lines are common to all clusters.
The LVDS I/Os are composed of 8 LVDS transceiver (Tx) pairs, 8 receivers (Rx) pairs together
with 4 reference voltages (Vref). The reference voltage must be connected to an accurate 1.25V
voltage to give references to the transceivers and to the receivers.
The LVDS specification complies with the EIA-644 standard requirements.
8.2.1
JTAG
All LVDS I/Os are 1149.1 compliant. Each I/O may be included or excluded from boundary scan
chain during the configuration of the FPGA.
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9. ATF280E Configuration
Configuration is the process by which a design is loaded into an ATF280E FPGA. The ATF280E
device is a SRAM based FPGA. this lead to an unlimited reprogrammability capability.
It is possible to configure either the entire device or only a portions of the device. Sections can
be configured while others continue to operate undisturbed. The architecture of the ATF280E
leads to a maximum bitstream size of 3M bits. It is possible to store configuration bit-streams of
the ATF280E in one single 4Mbit EEPROM.
Full configuration takes only milliseconds. Partial configuration takes even less time and is a
function of design density.
Configuration data is transferred to the device in one of the six modes supported by the
ATF280E. Three dedicated input pins, M0, M1, and M2 are used to determine the configuration
mode.
9.1
9.2
Entering Configuration Modes
Configuration Modes
The ATF280E supports an auto-configuring Master mode, four Slave modes, and a Synchro-
nous RAM Mode for accessing the SRAM-based configuration memory directly from a parallel
microprocessor port.
The following table summarizes the ATF280E configuration modes.
Table 9-1.
Configuration Modes
Mode
Description
M2
M1
M0
CCLK
Data
Notes
Auto-Configuration Serial
EEPROM
0
Master Serial
Slave Serial
0
0
0
Output
Serial
Microprocessor or
Serial EEPROM
1
7
2
6
4
0
0
1
1
1
0
1
1
0
0
0
Input
Input
Input
Input
Input
Serial
Microprocessor or
Serial EEPROM
Slave Serial
Serial
Microprocessor or
parallel EEPROM
Slave Parallel
Slave Parallel
Synchronous RAM
0
1
1
8 or 16 bit word
8 or 16 bit word
8 or 16 bit word
20-bit address out, Parallel
EPROM
24-bit Address In,
Parallel Port of Microprocessor
In order to keep the maximum number of pins assigned to signals, it is recommended to use a
serial configuration interface. Here is an example of ATF280E serial configuration architecture.
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ATF280E
Figure 9-1. Mode 0 Configuration Architecture
ATF280E
AT69170E
For complete description of all the ATF280E configuration modes please refer to the “AT40K
Series Configuration” application note on the ATMEL web site www.atmel.com.
9.3
Configuration Check
The download of the bit-stream from the EEPROM to the FPGA is checked (CRC). Once config-
ured the FPGA will also self check the integrity of the configuration and generate a warning as
soon as a difference is detected.
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10. Development Software
The ATF280E is designed to quickly implement high performance, large gate count designs
through the use of combined Atmel and industry standard tools used on Windows/Linux
platform.
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ATF280E
11. Power-On Supply Requirements
Atmel FPGAs require a minimum rated power supply current capacity to ensure proper initializa-
tion. The power supply ramp-up time affects the current required. A fast ramp-up time requires
more current than a slow ramp-up time.
Moreover, the supply voltage must respect a sequence as described below:
The peripheral power up must be done before the core power up. No ramp up is required on
VCC power supply.
Table 11-1. Power-on Supply Requirements
Description
Maximum Current(1)(2)
3 A
Maximum Current Supply
Notes: 1. Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A
larger capacity power supply may result in a larger initialization current.
2. 2. Ramp-up time is measured from 0V DC to 1.8V DC. Peak current required lasts less than 2
ms, and occurs near the internal power on reset threshold voltage.
35
7750A–AERO–07/07
12. Electrical Characteristics
12.1 Absolute Maximum Ratings(1)
Supply Voltage 1.8V I/Os (VCC buffers)............................-0.3V to +2V
*NOTICE:
Stresses at or above those listed under "Abso-
lute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification is not implied. Exposure to abso-
lute maximum rating conditions for extended
periods may affect device reliability.
Supply Voltage 3.3V I/Os (VCC buffers)........................... -0.3V to +4V
Supply Voltage Core (VDD array)..............………….........-0.3V to +2V
Storage Temperature..................................................-65°C to +150°C
All Output Voltages with respect to Ground........................ -0.3V to 4V
ESD......................................................................................…..3000V
12.2 Operating Range
Table 12-1. Operating Range
Operating Temperature
-55°C to +125°C
3.3V 0.3V
VCC - I/O Power Supply
1.8V 0.15V
3.3V 0.3V
VCCB - LVDS I/O Power Supply
VREF - LVDS Reference Voltage
VDD - Core Power Supply
1.25 0.1V
1.8V 0.15V
36
ATF280E
7750A–AERO–07/07
ATF280E
12.3 DC Characteristics
Table 12-2. DC Characteristics
Symbol
Parameter
Conditions
CMOS
Min
Typ
Max
Units
70% Vcc
-0.3
V
V
V
V
IH
IL
High-level Input Voltage
Low-level Input Voltage
CMOS
30% Vcc
I
OH = -4 mA
CC = 3.0V
OH = -12 mA
CC = 3.0V
OH = -16 mA
CC = 3.0V
OL = +4 mA
CC = 3.0V
OL = +12 mA
CC = 3.0V
OL = +16 mA
2.4
2.4
2.4
V
V
V
V
V
V
V
I
V
OH
High-level Input Voltage
V
I
V
I
0.4
0.4
0.4
V
I
V
OL
Low-level Input Voltage
V
I
V
V
CC = 3.0V
IN = VCC max
-5
5
µA
µA
µA
µA
µA
µA
µA
µA
High-level Input Current
Low-level Input Current
I
I
I
IH
With pull-down, VIN = VCC
20
-5
75
300
5
V
IN = VSS
IL
With pull-up, VIN = VSS
-300
-5
-50
-20
5
Without pull-down, VOUT =VCC max
With pull-down, VOUT = VCC max
Without pull-up, VOUT = VSS
With pull-up, VOUT = VSS for CON
High-level Tri-state Output
Leakage Current
OZH
20
-5
300
Low-level Tri-state Output
Leakage Current
I
I
OZL
CC
-500
-150
1
-110
5
Standby Current
Consumption
Standby, un-programmed
All pins
mA
pF
C
IN
Input Capacitance
10
2
Cold sparing leakage
Input current
Vdd = Vss = 0V
I
I
ICS
-2
-2
µA
Vin = 0 to VDD Max
Vdd = Vss = 0V
Cold sparing leakage
output current
OCS
2
µA
V
Vin = 0 to VDD Max
Supply threshold of cold
sparing buffers
V
CSTH
Iocs = 100 µA
0.5
37
7750A–AERO–07/07
Table 12-3. LVDS Driver DC/ AC Characteristics
Symbol
|VOD|
Vol
Parameter
Test Condition
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Min.
251.4
1071
804
Max.
452.2
1731
1323
1527
Units
mV
Comments
Output differential voltage
Output voltage low
Output voltage high
Output offset voltage
see Figure below
see Figure below
see Figure below
see Figure below
mV
Voh
mV
VOS
937
mV
Change in |VOD| between "0" and
"1"
|Delta VOD|
|Delta VOS|
ISA, ISB
Rload = 100Ω
Rload = 100Ω
0
50
mV
mV
mA
–
–
Change in |VOS| between "0" and
"1"
0
200
6.2
Drivers shorted to
ground or VDD
Output current
1.0
–
–
ISAB
Rbias
Ibias
Output current
Bias resistor
Drivers shorted together
2.6
16.3
7
4.8
mA
KΩ
mA
–
–
16.7
14.6
Bias static current
–
Maximum operating
frequency
F Max.
VDD = 3.3V 0.3V
–
200
MHz
Consumption 20.9 mA
Clock
Tfall
Trise
Tp
Clock signal duty cycle
Fall time 80-20%
Rise time 20-80%
Propagation delay
Duty cycle skew
Max. frequency
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
Rload = 100Ω
45
55
%
–
445
445
1120
0
838
841
2120
80
ps
ps
ps
ps
see Figure below
see Figure below
see Figure below
–
Tsk1
Channel to channel skew
(same edge)
Tsk2
Rload = 100Ω
0
50
ps
–
Figure 12-1. Test Termination Measurements
Figure 12-2. Rise and Fall times Measurements
38
ATF280E
7750A–AERO–07/07
ATF280E
Table 12-4. LVDS Receiver DC/ AC Characteristics
Symbol
Vi
Parameter
Test Condition
Min.
0
Max.
2400
+100
2.4
Units
mV
mV
ns
Comments
Input voltage range
Input differential voltage
Propagation delay
–
–
–
–
–
Vidth
Tp
–
-100
0.7
-
Cout = 50 pF, VDD = 3.3V 0.3V
Cout = 50 pF
Tskew
Duty cycle distortion
500
ps
12.4 AC Timing Characteristics - TBD
All input I/O characteristics measured from VIH of 50% of VDD at the pad (CMOS threshold) to the
internal VIH of 50% of VDD
.
All output I/O characteristics are measured as the average of TPDLH and TPDHL to the pad VIH of
50% of VDD
.
Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal
IH of 50% of VCC
V
.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays
only.
Table 12-5. AC Characteristics
Cell Function
IO
Parameter
Path
Value Units Notes
Input
t
t
t
t
t
t
t
t
t
t
t
t
t
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
pad -> x/y
pad -> x/y
pad -> x/y
pad -> x/y
Output, fast
Output, fast
Output, fast
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
oe -> pad
Path
ns
ns
no extra delay
Input
1 extra delay
2 extra delays
3 extra delays
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
40 pF load
Input
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input
Output, slow
Output, medium
Output, fast
Output, slow
Output, slow
Output, medium
Output, medium
Output, fast
Output, fast
Cell Function
Parameter
Value Units Notes
Global Clocks and Set/Reset
GCK Input buffer
FCK Input buffer
Clock column driver
Clock sector driver
GSRN Input buffer
t
t
t
t
t
PD (max)
PD (max)
PD (max)
PD (max)
PD (max)
pad -> clock
ns
ns
ns
ns
ns
rising edge clock
pad -> clock
rising edge clock
clock -> colclk
colclk -> secclk
colclk -> secclk
rising edge clock
rising edge clock
from any pad to Global Set/Reset network
39
7750A–AERO–07/07
Cell Function
Parameter
Path
Value Units Notes
rising edge clock fully loaded clock tree rising
Global clock to output
t
t
PD (max)
PD (max)
clock pad -> out
ns
edge DFF 20 mA output buffer 40 pF pin load
rising edge clock fully loaded clock tree rising
edge DFF 20 mA output buffer 40 pF pin load
Fast clock to output
clock pad -> out
ns
Table 12-6. FreeRAM AC Characteristics
Async RAM
Write
t
WECYC (Minimum) cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
T
T
WEL (Minimum)
WEH (Minimum)
We
Pulse width low
Pulse width high
Write
We
Write
T
AWS (Minimum)
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
Write
TAWH (Minimum)
Write
T
T
T
DS (Minimum)
DH (Minimum)
DD (Maximum)
Write
Write /Read
Read
rd addr = wr addr
T
AD (Maximum)
rd addr -> dout
oe -> dout
Read
T
OZX (Maximum)
OXZ (Maximum)
Read
T
oe -> dout
Sync RAM
Write
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC (Minimum)
CLKL (Minimum)
CLKH (Minimum)
WCS (Minimum)
WCH (Minimum)
ACS (Minimum)
ACH (Minimum)
DCS (Minimum)
DCH (Minimum)
CD (Maximum)
AD (Maximum)
OZX (Maximum)
OXZ (Maximum)
cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
Clk
Write
Clk
Write
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
Write
Write
Write
Write/Read
Read
rd addr -> dout
oe -> dout
Read
Read
oe -> dout
Notes: 1. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The
input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
40
ATF280E
7750A–AERO–07/07
ATF280E
12.4.1
FreeRAM Asynchronous Timing Characteristics
12.4.1.1
Single-port Write/Read
12.4.1.2
Dual-port Write with Read
12.4.1.3
Dual-port Read
41
7750A–AERO–07/07
12.4.2
FreeRAM Synchronous Timing Characteristics
12.4.2.1
Single-port Write/Read
12.4.2.2
Dual-port Write with Read
12.4.2.3
Dual-port Read
42
ATF280E
7750A–AERO–07/07
ATF280E
13. Packaging Information
MCGA 472
43
7750A–AERO–07/07
256-pin MQFPT
44
ATF280E
7750A–AERO–07/07
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