ATF750C-10JI [ATMEL]
High-speed Complex Programmable Logic Device; 高速复杂可编程逻辑器件
| 型号： | ATF750C-10JI |
| 厂家： | 
ATMEL |
| 描述： | High-speed Complex Programmable Logic Device |
| 文件： | 总16页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Advanced, High-speed, Electrically-erasable Programmable Logic Device
– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L
• Low-power Edge-sensing “L” Option with 1 mA Standby Current
• D- or T-type Flip-flop
• Product Term or Direct Input Pin Clocking
• 7.5 ns Maximum Pin-to-pin Delay with 5V Operation
• Highest Density Programmable Logic Available in 24-pin Package
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
• Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
• Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
• Programmable Pin-keeper Circuits
High-speed
Complex
Programmable
Logic Device
• Dual-in-line and Surface Mount Package in Standard Pinouts
• Commercial and Industrial Temperature Ranges
• 20-year Data Retention
ATF750C
ATF750CL
• 2000V ESD Protection
• 1000 Erase/Write Cycles
Block Diagram
(OE PRODUCT TERMS)
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
12
INPUT
PINS
LOGIC
OPTION
4 TO 8
PRODUCT
TERMS
10
I/O
PINS
OUTPUT
OPTION
(UP T0 20
FLIP-FLOPS)
(CLOCK PIN)
Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform, predictable delays
(continued)
DIP/SOIC/TSSOP
PLCC
Pin Configurations
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
Pin Name Function
IN
CLK
IN
Clock
IN
IN
IN
*
5
6
7
8
9
25 I/O
24 I/O
23 I/O
IN
IN
Logic Inputs
IN
22
*
IN
I/O
*
Bi-directional Buffers
No Internal Connection
+5V Supply
IN
21 I/O
20 I/O
19 I/O
IN
IN 10
IN 11
IN
IN 10
IN 11
VCC
GND 12
Rev. 0776F–01/00
guarantee fast in-system performance. The ATF750C(L) is
a high-performance CMOS (electrically-erasable) complex
programmable logic device (CPLD) that utilizes Atmel’s
proven electrically-erasable technology.
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu-
ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip-
flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.
Each of the ATF750C(L)’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi-
directional I/O pins. Each flip-flop is individually config-
urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
The ATF750C(L) is a low-power device with speeds
as fast as 15 ns. The ATF750C(L) provides the optimum
low-power CPLD solution. This device significantly
reduces total system power, thereby allowing battery-
powered operations.
There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to 3.6V, 5V 5% or 5V 10%.
Commercial
-7.5, -10, -15
Industrial
-10, -15
5V Operation
Operating Temperature (Ambient)
0°C - 70°C
-40°C - +85°C
VCC Power Supply
5V 5%
5V 10%
ATF750C(L)
2
ATF750C(L)
Logic Options
Combinatorial Output
Registered Output
Combined Terms
Separate Terms
Combined Terms
Separate Terms
Clock Mux
CKMUX
CKi
TO
LOGIC
CELL
CLK
PIN
CLOCK
PRODUCT
TERM
SELECT
Output Options
3
Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programma-
ble “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
Table 1. Software Compiler Mode Selection
Synario
ATF750C
WINCUPL
V750C
Pin-keeper Circuit
Disabled
ATF750C (PPK)
V750CPPK
Enabled
Input Diagram
VCC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE
OPTION
ATF750C(L)
4
ATF750C(L)
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
ILI
Input Load Current VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
VOUT = -0.1V to VCC + 0.1V
Current
ILO
10
µA
Com.
125
135
125
135
0.12
0.15
180
190
180
190
1
mA
mA
mA
mA
mA
mA
C-7, -10
Ind., Mil.
Com.
V
V
CC = Max,
IN = Max,
Power Supply
Current, Standby
ICC
C-15
Ind., Mil.
Com.
Outputs Open
CL-15
Ind., Mil.
2
Output Short
Circuit Current
(1)
IOS
VIL
VOUT = 0.5V
-120
mA
Input Low Voltage
Input High Voltage
4.5 ≤ VCC ≤ 5.5V
-0.6
2.0
0.8
VCC + 0.75
0.5
V
V
V
V
V
VIH
IOL = 16 mA
Com., Ind.
Mil.
Output Low
Voltage
VIN = VIH or VIL,
VOL
I
OL = 12 mA
0.5
VCC = Min
IOL = 24 mA
Com.
0.8
Output High
Voltage
VIN = VIH or VIL,
VCC = Min
VOH
IOH = -4.0 mA
2.4
V
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and
Measurement Levels
Output Test Load
VCC
300
(390 MIL.)
390
(750 MIL.)
tR, tF < 3 ns (10% to 90%)
5
AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
-7
-10
C/CL-15
Symbol Parameter
Min
Max
7.5
7.5
7.5
7.5
5
Min
Max
10
Min
Max
Units
ns
tPD
tEA
tER
tCO
tCF
tS
Input or Feedback to Non-registered Output
Input to Output Enable
Input to Output Disable
Clock to Output
15
15
15
12
9
10
ns
10
ns
3
1
4
4
10
5
5
ns
Clock to Feedback
Input Setup Time
7.5
ns
3
4
8/12
7
ns
tSF
tH
Feedback Setup Time
Hold Time
3
4
ns
1
2
5
ns
tP
Clock Period
7
11
5.5
14
7
ns
tW
Clock Width
3.5
ns
External Feedback 1/(tS + tCO
Internal Feedback 1/(tSF + tCF
No Feedback 1/(tP)
)
95
71
86
90
50/41
62
MHz
MHz
MHz
ns
FMAX
)
125
142
71
tAW
tAR
Asynchronous Reset Width
5
3
10
10
15
15
Asynchronous Reset Recovery Time
Asynchronous Reset to Registered Output Reset
Setup Time, Synchronous Preset
ns
tAP
8
12
15
ns
tSP
4
7
8
ns
Note:
1. See ordering information for valid part numbers.
ATF750C(L)
6
ATF750C(L)
AC Waveforms, Input Pin Clock(1)
Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
-7
-10
C/CL-15
Symbol Parameter
Min
Max
7.5
7.5
7.5
6.5
3.5
Min
Max
10
10
10
7
Min
Max
Units
ns
tPD
Input or Feedback to Non-registered Output
15
15
15
10
5.5
tEA
Input to Output Enable
Input to Output Disable
Clock to Output
ns
tER
ns
tCOS
tCFS
tSS
0
0
0
0
0
ns
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
5
0
ns
4
5
8/12.5
ns
tSFS
tHS
4
5
7
0
ns
0
0
ns
tPS
Clock Period
7
10
5
12
6
ns
tWS
Clock Width
3.5
ns
External Feedback 1/(tSS + tCOS
)
95
83
55/44
80
MHz
MHz
MHz
ns
FMAXS
Internal Feedback 1/(tSFS + tCFS
No Feedback 1/(tPS
Asynchronous Reset Width
)
133
142
100
100
)
83
tAW
tARS
tAP
5
5
10
10
15
15
Asynchronous Reset Recovery Time
Asynchronous Reset to Registered Output Reset
Setup Time, Synchronous Preset
ns
8
10
15
ns
tSPS
5
5/9
11
ns
7
Functional Logic Diagram ATF750C, Upper Half
ATF750C(L)
8
ATF750C(L)
Functional Logic Diagram ATF750C, Lower Half
9
Preload of Registered Outputs
The ATF750C(L)’s registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the I/O pin will force the register
high; a VIL will force it low, independent of the output polar-
ity. The PRELOAD state is entered by placing a 10.25V to
10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.
When the clock term is pulsed high, the data on the I/O
pins is placed into the register chosen by the select pin.
Level Forced on Registered
Output Pin during Preload Cycle
Select Pin State
Register #0 State after Cycle
Register #1 State after Cycle
VIH
VIL
VIH
VIL
Low
Low
High
High
High
Low
X
X
X
High
Low
X
Power-up Reset
The registers in the ATF750C(L)s are designed to reset
during power-up. At a point delayed slightly from VCC cross-
ing VRST, all registers will be reset to the low state. The out-
put state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock terms or
pin high, and
Parameter Description
Typ Max
Units
ns
tPR
Power-up Reset Time
600 1000
3. The clock pin, or signals from which clock terms are
derived, must remain stable during tPR.
VRST
Power-up Reset Voltage
3.8
4.5
V
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
Note:
6
8
pF
VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATF750C(L)
10
ATF750C(L)
Using the ATF750C’s Many Advanced
Features
Synchronous Preset and
Asynchronous Reset
The ATF750C(L)’s advanced flexibility packs more usable
gates into 24 pins than any other logic device. The
ATF750C(L)s start with the popular 22V10 architecture,
and add several enhanced features:
One synchronous preset line is provided for all 20 registers
in the ATF750C(L). The appropriate input signals to cause
the internal clocks to go to a high state must be received
during a synchronous preset. Appropriate setup and hold
times must be met, as shown in the switching waveform
diagram.
• Selectable D- and T-type Registers
Each ATF750C(L) flip-flop can be individually configured
as either D- or T-type. Using the T-type configuration, JK
and SR flip-flops are also easily created. These options
allow more efficient product term usage.
An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flip-
flops are reset when the input signals received force the
internal resets high.
• Selectable Asynchronous Clocks
Each of the ATF750C(L)’s flip-flops may be clocked by
its own clock product term or directly from Pin 1 (SMD
Lead 2). This removes the constraint that all registers
must use the same clock. Buried state machines,
counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF750C(L) fuse patterns. Once the security fuse
is programmed, all fuses will appear programmed during
verify.
The security fuse should be programmed last, as its effect
is immediate.
• A Full Bank of Ten More Registers
The ATF750C(L) provides two flip-flops per output logic
cell for a total of 20. Each register has its own sum term,
its own reset term and its own clock term.
• Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750C(L) has a dedicated input
path. Each of the 20 registers has its own feedback
terms into the array as well. This feature, combined with
individual product terms for each I/O’s output enable,
facilitates true bi-directional I/O design.
11
ATF750CL SUPPLY CURRENT
ATF750C SUPPLY CURRENT VS.
VS. SUPPLY VOLTAGE (TA = 25°C)
SUPPLY VOLTAGE (TA = 25°C)
160
140
120
100
80
140
120
100
80
60
60
40
40
20
20
0
4.50
4.75
5.00
5.25
5.50
0
SUPPLY VOLTAGE (V)
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION (TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
160
140
120
100
80
120
80
40
0
60
40
20
0
0
5
10
25
50
75
100
0
5
10
25
50
75
100
FREQUENCY (MHz)
FREQUENCY (MHz)
ATF750C/CL OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V)
ATF750C/CL OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
0.00
0
-5
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-10
-15
-20
-25
-30
-35
-40
-45
-50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V)
V
OH (V)
ATF750C(L)
12
ATF750C(L)
ATF750C/CL OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V)
ATF750C/CL OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
140
120
100
80
44
43
42
41
40
39
38
37
36
35
34
60
40
20
0
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOL (V)
SUPPLY VOLTAGE (V)
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
ATF750C/CL OUTPUT SINK CURRENT
(VCC = 5V,TA = 25°C)
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
0
-5
-10
-15
-20
-25
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
INPUT VOLTAGE (V)
VOL (V)
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V,TA = 25°C)
ATF750C/CL INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 5V,TA = 35°C)
WITHOUT PIN-KEEPER
0
1.8
1.6
1.4
1.2
1
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.8
0.6
0.4
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
13
ATF750C(L) Ordering Information
Ext.
tPD
(ns)
tCOS
(ns)
fMAXS
(MHz)
Ordering Code
Package
Operation Range
7.5
10
6.5
95
83
ATF750C-7JC
28J
Commercial
(0°C to 70°C)
7
ATF750C-10JC
ATF750C-10PC
ATF750C-10SC
ATF750C-10XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF750C-10JI
ATF750C-10PI
ATF750C-10SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
15
10
55
ATF750C-15JC
ATF750C-15PC
ATF750C-15SC
ATF750C-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF750C-15JI
ATF750C-15PI
ATF750C-15SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
15
10
44
ATF750CL-15JC
ATF750CL-15PC
ATF750CL-15SC
ATF750CL-15XC
28J
Commercial
24P3
24S
24X
(0°C to 70°C)
ATF750CL-15JI
ATF750CL-15PI
ATF750CL-15SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
Using “C” Product for Industrial
To use commercial product for industrial ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” =
10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24S
24X
24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP)
ATF750C(L)
14
Packaging Information
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
24P3, 24-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
.045(1.14) X 30° - 45°
1.27(32.3)
1.25(31.7)
.045(1.14) X 45° PIN NO. 1
.012(.305)
.008(.203)
IDENTIFY
PIN
1
.430(10.9)
.390(9.91)
.021(.533)
.013(.330)
.266(6.76)
.250(6.35)
SQ
.456(11.6)
.450(11.4)
SQ
.032(.813)
.026(.660)
.495(12.6)
.485(12.3)
SQ
.090(2.29)
MAX
1.100(27.94) REF
.050(1.27) TYP
.043(1.09)
.200(5.06)
MAX
.005(.127)
MIN
.300(7.62) REF SQ
.020(.508)
.120(3.05)
.090(2.29)
SEATING
PLANE
.180(4.57)
.165(4.19)
.070(1.78)
.020(.508)
.023(.584)
.014(.356)
.151(3.84)
.125(3.18)
.022(.559) X 45° MAX (3X)
.065(1.65)
.040(1.02)
.110(2.79)
.090(2.29)
.325(8.26)
.300(7.62)
0
15
REF
.012(.305)
.008(.203)
.400(10.2) MAX
24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline
(TSSOP)
Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)*
.020(.508)
.013(.330)
.299(7.60) .420(10.7)
.291(7.39) .393(9.98)
PIN 1 ID
.050(1.27) BSC
.616(15.6)
.105(2.67)
.598(15.2)
.092(2.34)
.012(.305)
.003(.076)
.013(.330)
.009(.229)
.050(1.27)
0
REF
.015(.381)
*Controlling dimension: millimeters
8
ATF750C(L)
15
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