ATF750LVC-15XJ [ATMEL]
EE PLD, 15ns, CMOS, PDSO24, 4.40 MM, PLASTIC, MO-153AD, TSSOP-24;
| 型号： | ATF750LVC-15XJ |
| 厂家： | 
ATMEL |
| 描述： | EE PLD, 15ns, CMOS, PDSO24, 4.40 MM, PLASTIC, MO-153AD, TSSOP-24 光电二极管 |
| 文件： | 总17页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 3.0V to 3.6V Operating Range
• Advanced, High-speed, Electrically-erasable Programmable Logic Device
– Superset of 22V10
– Enhanced Logic Flexibility
– Architecturally Compatible with ATV750B and ATV750 Software and Hardware
• D- or T-type Flip-flop
• Product Term or Direct Input Pin Clocking
• 15 ns Maximum Pin-to-pin Delay with 3V Operation
• Highest Density Programmable Logic Available in 24-pin Package
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
• Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
• Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
• Programmable Pin-keeper Circuits
• Dual-in-line and Surface Mount Package in Standard Pinouts
• Commercial and Industrial Temperature Ranges
• 20-year Data Retention
High-speed
Complex
Programmable
Logic Device
ATF750LVC
• 2000V ESD Protection
• 1000 Erase/Write Cycles
• Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Block Diagram
(OE PRODUCT TERMS)
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
12
INPUT
PINS
LOGIC
OPTION
4 TO 8
PRODUCT
TERMS
10
I/O
PINS
OUTPUT
OPTION
(UP T0 20
FLIP-FLOPS)
(CLOCK PIN)
Description
The Atmel “750” architecture is twice as powerful as most other 24-pin programmable
logic devices. Increased product terms, sum terms, flip-flops and output logic configu-
rations translate into more usable gates. High-speed logic and uniform, predictable
(continued)
Pin Configurations
Pin Name Function
DIP/SOIC/TSSOP
PLCC
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
CLK
IN
Clock
IN
IN
IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
22 GND *
21 I/O
20 I/O
19 I/O
Logic Inputs
Bi-directional Buffers
Ground
IN
IN
IN
I/O
IN
GND *
IN
IN
GND
IN
IN 10
IN 11
IN
IN 10
IN 11
VCC
3V Supply
Note:
For PLCC, pins 1, 8, 15, and 22
can be left unconnected. For
superior performance, connect
VCC to pin 1 and GND to pins
8, 15, and 22.
GND 12
Rev. 1447E–02/06
delays guarantee fast in-system performance. The
ATF750LVC is a high-performance CMOS (electrically-
erasable) complex programmable logic device (CPLD) that
utilizes Atmel’s proven electrically-erasable technology.
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Each of the ATF750LVC’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi-
directional I/O pins. Each flip-flop is individually config-
urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu-
ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip-
flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.
There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +4.6V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 4.6V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
DC and AC Operating Conditions
3.3V Operation
Commercial
0°C - 70°C
3.0 - 3.6V
Industrial
-40°C - +85°C
3.0 - 3.6V
Operating Temperature (Ambient)
VCC Power Supply
ATF750LVC
2
ATF750LVC
Clock Mux
CKMUX
CKi
TO
LOGIC
CELL
CLK
PIN
CLOCK
PRODUCT
TERM
SELECT
Output Options
Bus-friendly Pin-keeper Input and I/Os
Input Diagram
All input and I/O pins on the ATF750LVC(L) have program-
mable “pin-keeper” circuits. If activated, when any pin is
driven high or low and then subsequently left floating, it will
stay at that previous high or low level.
VCC
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.
I/O Diagram
VCC
OE
Table 1. Software Compiler Mode Selection
Synario
ATF750LVC
Wincupl
V750C
Pin-keeper Circuit
Disabled
DATA
I/O
VCC
ATF750LVC (PPK)
V750CPPK
Enabled
100K
PROGRAMMABLE
OPTION
3
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
ILI
Input Load Current VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
VOUT = -0.1V to VCC + 0.1V
Current
ILO
10
90
µA
VCC = Max,
Com.
Ind.
65
70
mA
VIN = Max,
Outputs Open
Power Supply
Current, Standby
ICC
C-15
100
mA
mA
Output Short
Circuit Current
(1)(2)
IOS
VOUT = 0.5V
-120
VIL
Input Low Voltage
Input High Voltage
3.0 ≤ VCC ≤ 3.6V
-0.6
2.0
0.8
VCC + 0.75
0.5
V
V
V
V
V
VIH
IOL = 16 mA
IOL = 12 mA
IOL = 24 mA
Com., Ind.
Mil.
Output Low
Voltage
VIN = VIH or VIL,
VCC = Min
VOL
0.5
Com.
0.8
Output High
Voltage
VIN = VIH or VIL,
VCC = Min
VOH
IOH = -2.0 mA
2.4
V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. This test is performed at initial characterisation only.
Input Test Waveforms and
Measurement Levels
Output Test Load
VCC
316 Ω
348 Ω
tR, tF < 3 ns (10% to 90%)
ATF750LVC
4
ATF750LVC
AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
-15
Symbol
tPD
tEA
tER
tCO
tCF
tS
Parameter
Min
Max
15
15
15
12
9
Units
ns
Input or Feedback to Non-registered Output
Input to Output Enable
Input to Output Disable
Clock to Output
ns
ns
5
5
ns
Clock to Feedback
Input Setup Time
ns
8
ns
tSF
Feedback Setup Time
Hold Time
7
ns
tH
5
ns
tP
Clock Period
14
7
ns
tW
Clock Width
ns
External Feedback 1/(tS + tCO
)
50
62
71
MHz
MHz
MHz
ns
fMAX
Internal Feedback 1/(tSF + tCF
)
No Feedback 1/(tP)
tAW
tAR
tAP
tSP
Asynchronous Reset Width
15
15
Asynchronous Reset Recovery Time
Asynchronous Reset to Registered Output Reset
Setup Time, Synchronous Preset
ns
15
ns
8
ns
Note:
1. See ordering information for valid part numbers.
5
AC Waveforms, Input Pin Clock(1)
Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
-15
Symbol
tPD
Parameter
Min
Max
15
Units
ns
Input or Feedback to Non-registered Output
Input to Output Enable
Input to Output Disable
Clock to Output
tEA
15
ns
tER
15
ns
tCOS
tCFS
tSS
0
0
10
ns
Clock to Feedback
Input Setup Time
5.5
ns
8
ns
tSFS
tHS
Feedback Setup Time
Hold Time
7
ns
0
ns
tPS
Clock Period
12
6
ns
tWS
Clock Width
ns
External Feedback 1/(tSS + tCOS
Internal Feedback 1/(tSFS + tCFS
No Feedback 1/(tPS
Asynchronous Reset Width
)
55
80
83
MHz
MHz
MHz
ns
fMAXS
)
)
tAW
tARS
tAP
15
15
Asynchronous Reset Recovery Time
Asynchronous Reset to Registered Output Reset
Setup Time, Synchronous Preset
ns
15
ns
tSPS
11
ns
ATF750LVC
6
ATF750LVC
Functional Logic Diagram ATF750LVC, Upper Half
7
Functional Logic Diagram ATF750LVC, Lower Half
ATF750LVC
8
ATF750LVC
Using the ATF750LVC’s Many
Advanced Features
The ATF750LVC’s advanced flexibility packs more usable
gates into 24-pins than any other logic device. The
ATF750LVCs start with the popular 22V10 architecture,
and add several enhanced features:
Synchronous Preset and
Asynchronous Reset
One synchronous preset line is provided for all 20 registers
in the ATF750LVC. The appropriate input signals to cause
the internal clocks to go to a high state must be received
during a synchronous preset. Appropriate setup and hold
times must be met, as shown in the switching waveform
diagram.
• Selectable D- and T-type Registers
Each ATF750LVC flip-flop can be individually configured
as either D- or T-type. Using the T-type configuration, JK
and SR flip-flops are also easily created. These options
allow more efficient product term usage.
An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flip-
flops are reset when the input signals received force the
internal resets high.
• Selectable Asynchronous Clocks
Each of the ATF750LVC’s flip-flops may be clocked by
its own clock product term or directly from Pin 1 (SMD
Lead 2). This removes the constraint that all registers
must use the same clock. Buried state machines,
counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF750LVC fuse patterns. Once the security fuse
is programmed, all fuses will appear programmed during
verify.
The security fuse should be programmed last, as its effect
is immediate.
• A Full Bank of Ten More Registers
The ATF750LVC provides two flip-flops per output logic
cell for a total of 20. Each register has its own sum term,
its own reset term and its own clock term.
• Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750LVC has a dedicated input
path. Each of the 20 registers has its own feedback
terms into the array as well. This feature, combined with
individual product terms for each I/O’s output enable,
facilitates true bi-directional I/O design.
9
OUTPUT SINK CURRENT
VS SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
OUTPUT SOURCE CURRENT
VS SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
24.0
23.0
22.0
21.0
20.0
19.0
18.0
17.0
16.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
3.00
3.25
3.30
3.50
3.60
3.00
3.25
3.30
3.50
3.60
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT CLAMP CURRENT VS
INPUT CURRENT VS
INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
0.0
15.0
10.0
5.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
0.0
-5.0
-10.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SUPPLY CURRENT
VS SUPPLY VOLTAGE (TA = 25°C)
70.0
60.0
50.0
40.0
30.0
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
ATF750LVC
10
ATF750LVC
OUTPUT SOURCE SINK CURRENT VS
OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
OUTPUT SOURCE CURRENT VS
OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.3
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.3
VOL (V)
VOH (V)
SUPPLY CURRENT VS INPUT FREQUENCY
(VCC = 5.00V, TA = 25°C)
80
40
0
0
5
10
15
20
50
75
100
FREQUENCY (MHz)
11
ATF750LVC Ordering Information
Ext.
tPD
tCOS
(ns)
fMAXS
(MHz)
(ns)
Ordering Code
Package
Operation Range
15
10
55
ATF750LVC-15JC
ATF750LVC-15PC
ATF750LVC-15SC
ATF750LVC-15XC(1)
28J
Commercial
24P3
(0°C to 70°C)
24S
24X(1)
ATF750LVC-15JI
ATF750LVC-15PI
ATF750LVC-15SI
ATF750LVC-15X(1)I
28J
Industrial
24P3
(-40°C to 85°C)
24S
24X(1)
Note:
1. Special order only; TSSOP package requires special thermal management.
ATF750LVC Green Package Options (Pb/Halide-free/RoHS Compliant)
Ext.
tPD
tCOS
(ns)
fMAXS
(MHz)
(ns)
Ordering Code
Package
Operation Range
15
10
55
ATF750LVC-15JU
ATF750LVC-15PU
ATF750LVC-15SU
ATF750LVC-15XU
28J
Industrial
24P3
24S
24X
(-40°C to 85°C)
Using “C” Product for Industrial
Because the VCC conditions are the same for commercial and industrial for 3.3V products, and there is only 15°C difference
at the high end of the temperature range, there is very little risk in using “C” devices for industrial applications. Just de-rate
ICC by 15%.
Package Type
28-Lead, Plastic J-leaded Chip Carrier (PLCC)
28J
24P3
24S
24-lead, 0.300’ Wide, Plastic Dual Inline Package (PDIP)
24-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC)
24-lead, 0.173” Wide, Thin Shrink Small Outline (TSSOP)
24X*
ATF750LVC
12
ATF750LVC
Package Information
28J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
12.319
11.430
12.319
11.430
9.906
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
12.573
D1
E
–
11.582 Note 2
12.573
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AB.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
11.582 Note 2
10.922
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
28J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
13
24P3 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
31.623
7.620
6.096
0.356
1.270
2.921
0.203
–
32.131 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AF.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1
L
1.651
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
6/1/04
DRAWING NO. REV.
24P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
24P3, 24-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
D
R
ATF750LVC
14
ATF750LVC
24S – SOIC
B
D1
D
PIN 1 ID
PIN 1
e
E
A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
2.65
0.30
10.65
7.60
15.60
0.51
1.27
0.32
NOM
NOTE
SYMBOL
A
–
A1
A1
D
0.10
10.00
7.40
15.20
0.33
0.40
0.23
–
–
D1
E
–
0º ~ 8º
–
L1
B
–
L
–
–
L
L1
e
1.27 BSC
06/17/2002
TITLE
DRAWING NO. REV.
24S
2325 Orchard Parkway
San Jose, CA 95131
24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC)
B
R
15
24X – TSSOP
Dimensions in Millimeter and (Inches)*
JEDEC STANDARD MO-153 AD
Controlling dimension: millimeters
0.30(0.012)
0.19(0.007)
4.48(0.176)
4.30(0.169)
6.50(0.256)
6.25(0.246)
PIN 1
0.65(0.0256)BSC
7.90(0.311)
7.70(0.303)
1.20(0.047)MAX
0.15(0.006)
0.05(0.002)
0.20(0.008)
0.09(0.004)
0º ~ 8º
0.75(0.030)
0.45(0.018)
04/11/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
24X, 24-lead (4.4 mm body width) Plastic Thin Shrink Small Outline
Package (TSSOP)
24X
A
R
ATF750LVC
16
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