ATMEGA128-16AL_技术文档

Features

• High-performance, Low-power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 128K Bytes of In-System Self-programmable Flash program memory

– 4K Bytes EEPROM

8-bit

– 4K Bytes Internal SRAM

– Write/Erase cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

– SPI Interface for In-System Programming

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and

Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

ATmega128

ATmega128L

– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits

– Output Compare Modulator

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

– Software Selectable Clock Frequency

– ATmega103 Compatibility Mode Selected by a Fuse

– Global Pull-up Disable

• I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega128L

– 4.5 - 5.5V for ATmega128

• Speed Grades

Rev. 2467P–AVR–08/07

– 0 - 8 MHz for ATmega128L

– 0 - 16 MHz for ATmega128

Figure 1. Pinout ATmega128

Configurations

PEN

RXD0/(PDI) PE0

(TXD0/PDO) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

1

2

3

4

5

6

7

8

9

48 PA3 (AD3)

47 PA4 (AD4)

46 PA5 (AD5)

45 PA6 (AD6)

44 PA7 (AD7)

43 PG2(ALE)

42 PC7 (A15)

41 PC6 (A14)

40 PC5 (A13)

39 PC4 (A12)

38 PC3 (A11)

37 PC2 (A10)

36 PC1 (A9)

35 PC0 (A8)

34 PG1(RD)

33 PG0(WR)

(ICP3/INT7) PE7

(SS) PB0 10

(SCK) PB1 11

(MOSI) PB2 12

(MISO) PB3 13

(OC0) PB4 14

(OC1A) PB5 15

(OC1B) PB6 16

Note:

The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF

package should be soldered to ground.

Overview

The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATmega128

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Block Diagram

Figure 2. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC

INTERNAL

OSCILLATOR

ADC

AGND

AREF

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

JTAG TAP

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

PEN

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

TWO-WIRE SERIAL

INTERFACE

SPI

USART0

USART1

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash

with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O

lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible

Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial

Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable

gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.

1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and

programming and six software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue function-

ing. The Power-down mode saves the register contents but freezes the Oscillator, disabling all

other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asyn-

chronous timer continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except

Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby

mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This

allows very fast start-up combined with low power consumption. In Extended Standby mode,

both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec-

tive solution to many embedded control applications.

The ATmega128 AVR is supported with a full suite of program and system development tools

including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,

and evaluation kits.

ATmega103 and

ATmega128

Compatibility

The ATmega128 is a highly complex microcontroller where the number of I/O locations super-

sedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility

with the ATmega103, all I/O locations present in ATmega103 have the same location in

ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60

to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using

LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relo-

cation of the internal RAM space may still be a problem for ATmega103 users. Also, the

increased number of interrupt vectors might be a problem if the code uses absolute addresses.

To solve these problems, an ATmega103 compatibility mode can be selected by programming

the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the

internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.

The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on

current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128”

describes what the user should be aware of replacing the ATmega103 by an ATmega128.

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ATmega128(L)

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ATmega128(L)

ATmega103

Compatibility Mode

By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103

regards to RAM, I/O pins and interrupt vectors as described above. However, some new fea-

tures in ATmega128 are not available in this compatibility mode, these features are listed below:

•

One USART instead of two, Asynchronous mode only. Only the eight least significant bits of

the Baud Rate Register is available.

•

One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters

with three compare registers.

•

Two-wire serial interface is not supported.

Port C is output only.

Port G serves alternate functions only (not a general I/O port).

Port F serves as digital input only in addition to analog input to the ADC.

Boot Loader capabilities is not supported.

It is not possible to adjust the frequency of the internal calibrated RC Oscillator.

The External Memory Interface can not release any Address pins for general I/O, neither

configure different wait-states to different External Memory Address sections.

In addition, there are some other minor differences to make it more compatible to ATmega103:

•

Only EXTRF and PORF exists in MCUCSR.

Timed sequence not required for Watchdog Time-out change.

External Interrupt pins 3 - 0 serve as level interrupt only.

USART has no FIFO buffer, so data overrun comes earlier.

Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128.

Pin Descriptions

VCC

Digital supply voltage.

Ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATmega128 as listed on page

73.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega128 as listed on page

74.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

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2467P–AVR–08/07

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the ATmega128 as listed on page 77. In

ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated

when a reset condition becomes active.

Note:

The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not

programmed before they are put on the PCB, PORTC will be output during first power up, and until

the ATmega103 compatibility mode is disabled.

Port D (PD7..PD0)

Port E (PE7..PE0)

Port F (PF7..PF0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega128 as listed on page

78.

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the ATmega128 as listed on page

81.

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a Reset occurs.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

Port F also serves the functions of the JTAG interface.

In ATmega103 compatibility mode, Port F is an input Port only.

Port G (PG4..PG0)

Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port G output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port G also serves the functions of various special features.

The port G pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

In ATmega103 compatibility mode, these pins only serves as strobes signals to the external

memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 =

1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not

running. PG3 and PG4 are oscillator pins.

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ATmega128(L)

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ATmega128(L)

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page

51. Shorter pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

AREF

PEN

AREF is the analog reference pin for the A/D Converter.

PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled

high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro-

gramming mode. PEN has no function during normal operation.

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2467P–AVR–08/07

Resources

A comprehensive set of development tools, application notes, and datasheets are available for

download on http://www.atmel.com/avr.

Note:

1.

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATmega128(L)

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ATmega128(L)

About Code

Examples

This datasheet contains simple code examples that briefly show how to use various parts of the

device. These code examples assume that the part specific header file is included before compi-

lation. Be aware that not all C compiler vendors include bit definitions in the header files and

interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation

for more details.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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2467P–AVR–08/07

AVR CPU Core

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals and handle interrupts.

Architectural

Overview

Figure 3. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register file contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register file, the operation is executed,

and the result is stored back in the Register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-register, Y-register and Z-register, described later in

this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash Memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack

Pointer – SP – is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global

interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the

interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi-

tion. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses which can be accessed directly, or as the Data

Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has

Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

ALU – Arithmetic

Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

The AVR status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in

software with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register file can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD

instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in

BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement over-

flow flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

General Purpose

Register File

The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the

required performance and flexibility, the following input/output schemes are supported by the

Register file:

•

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 4 on page 12 shows the structure of the 32 general purpose working registers in the

CPU.

Figure 4. AVR CPU General Purpose Working Registers

7

0

Addr.

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ATmega128(L)

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ATmega128(L)

R0

R1

$00

$01

$02

R2

…

R13

R14

R15

R16

R17

…

$0D

$0E

$0F

$10

$11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

$1A

$1B

$1C

$1D

$1E

$1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register file have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

X-register, Y-register,

and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect

address registers X, Y, and Z are described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

15

XH

XL

0

X - register

7

0

7

R27 ($1B)

R26 ($1A)

15

YH

ZH

YL

ZL

0

Y - register

Z - register

7

0

7

R29 ($1D)

R28 ($1C)

15

0

7

R31 ($1F)

R30 ($1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the Instruction Set Reference for details).

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Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

Bit

15

SP15

SP7

7

14

SP14

SP6

6

13

SP13

SP5

5

12

SP12

SP4

4

11

SP11

SP3

3

10

SP10

SP2

2

9

SP9

SP1

1

8

SP8

SP0

0

SPH

SPL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

RAM Page Z Select

Register – RAMPZ

Bit

7

–

6

––

R

5

–

4

–

3

–

2

–

1

–

0

RAMPZ0

R/W

RAMPZ

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7..1 – Res: Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer

The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-

pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is

used only to select which page in the program memory is accessed when the ELPM/SPM

instruction is used. The different settings of the RAMPZ0 bit have the following effects:

RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is

accessed by ELPM/SPM

RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is

accessed by ELPM/SPM

Note that LPM is not affected by the RAMPZ setting.

Instruction

Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

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ATmega128(L)

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register file concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register file. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 7. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Reset and

Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate reset

vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 286 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The interrupt vectors can be moved to the start of the boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information.

The Reset vector can also be moved to the start of the boot Flash section by programming the

BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page

273.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

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There are basically two types of interrupts. The first type is triggered by an event that sets the

interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector

in order to execute the interrupt handling routine, and hardware clears the corresponding inter-

rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be

cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,

the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared

by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable

bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMWE ; start EEPROM write

sbiEECR, EEWE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

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ATmega128(L)

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set global interrupt enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set global interrupt enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response

Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles, the program vector address for the actual interrupt handling routine

is executed. During this 4-clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in Sleep mode, the inter-

rupt execution response time is increased by four clock cycles. This increase comes in addition

to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles,

the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incre-

mented by two, and the I-bit in SREG is set.

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AVR

ATmega128

Memories

This section describes the different memories in the ATmega128. The AVR architecture has two

main memory spaces, the Data Memory and the Program Memory space. In addition, the

ATmega128 features an EEPROM Memory for data storage. All three memory spaces are linear

and regular.

In-System

The ATmega128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for

program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

64K x 16. For software security, the Flash Program memory space is divided into two sections,

Boot Program section and Application Program section.

Reprogrammable

Flash Program

Memory

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128

Program Counter (PC) is 16 bits wide, thus addressing the 64K program memory locations. The

operation of Boot Program section and associated Boot Lock bits for software protection are

described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page

273. “Memory Programming” on page 286 contains a detailed description on Flash programming

in SPI, JTAG, or Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory and ELPM – Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 14.

Figure 8. Program Memory Map

Program Memory

$0000

Application Flash Section

Boot Flash Section

$FFFF

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ATmega128(L)

SRAM Data

Memory

The ATmega128 supports two different configurations for the SRAM data memory as listed in

Table 1.

Table 1. Memory Configurations

Configuration

Internal SRAM Data Memory External SRAM Data Memory

Normal mode

4096

up to 64K

ATmega103 Compatibility

mode

4000

Figure 9 shows how the ATmega128 SRAM Memory is organized.

The ATmega128 is a complex microcontroller with more peripheral units than can be supported

within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended

I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be

used. The Extended I/O space does not exist when the ATmega128 is in the ATmega103 com-

patibility mode.

In normal mode, the first 4352 Data Memory locations address both the Register file, the I/O

Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the

Register file, the next 64 location the standard I/O memory, then 160 locations of Extended I/O

memory, and the next 4096 locations address the internal data SRAM.

In ATmega103 compatibility mode, the first 4096 Data Memory locations address both the Reg-

ister file, the I/O Memory and the internal data SRAM. The first 32 locations address the Register

file, the next 64 location the standard I/O memory, and the next 4000 locations address the inter-

nal data SRAM.

An optional external data SRAM can be used with the ATmega128. This SRAM will occupy an

area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM

occupies the lowest 4352 bytes in normal mode, and the lowest 4096 bytes in the ATmega103

compatibility mode (Extended I/O not present), so when using 64KB (65536 bytes) of External

Memory, 61184 Bytes of External Memory are available in normal mode, and 61440 Bytes in

ATmega103 compatibility mode. See “External Memory Interface” on page 26 for details on how

to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the two-byte program counter is pushed

and popped, and external memory access does not take advantage of the internal pipe-line

memory access. When external SRAM interface is used with wait-state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait-states

respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,

registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

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The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 4096 bytes of internal data

SRAM in the ATmega128 are all accessible through all these addressing modes. The Register

file is described in “General Purpose Register File” on page 12.

Figure 9. Data Memory Map

Memory Configuration A

Memory Configuration B

Data Memory

$0000 - $001F

$0020 - $005F

160 Ext I/O Reg. $0060 - $00FF

32 Registers

64 I/O Registers $0020 - $005F

$0060

$0000 - $001F

32 Registers

64 I/O Registers

Internal SRAM

(4000 x 8)

$0100

Internal SRAM

$0FFF

$1000

(4096 x 8)

$10FF

$1100

External SRAM

(0 - 64K x 8)

External SRAM

(0 - 64K x 8)

$FFFF

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ATmega128(L)

Data Memory Access

Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 10.

Figure 10. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory access instruction

Next instruction

EEPROM Data

Memory

The ATmega128 contains 4K bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register.

“Memory Programming” on page 286 contains a detailed description on EEPROM programming

in SPI, JTAG, or Parallel Programming mode

EEPROM Read/Write

Access

The EEPROM access registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets

the user software detect when the next byte can be written. If the user code contains instructions

that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V_CC

is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time

to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-

ing EEPROM Corruption” on page 25. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

EEPROM Address

Register – EEARH and

EEARL

Bit

15

14

13

12

11

EEAR11

EEAR3

3

10

EEAR10

EEAR2

2

9

EEAR9

EEAR1

1

8

EEAR8

EEAR0

0

–

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEARL

7

R

6

R

5

R

4

R

Read/Write

Initial Value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15..12 – Res: Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

• Bits 11..0 – EEAR11..0: EEPROM Address

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The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the

4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

4096. The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

EEPROM Data

Register – EEDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

0

LSB

R/W

0

EEDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

EEPROM Control

Register – EECR

Bit

7

–

6

–

5

–

4

–

3

EERIE

R/W

0

2

EEMWE

R/W

0

1

EEWE

R/W

X

0

EERE

R/W

0

EECR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega128 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is written to one, writing EEWE to one within four clock cycles will write data to

the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no

effect. When EEMWE has been written to one by software, hardware clears the bit to zero after

four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM.

The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM

write takes place. The following procedure should be followed when writing the EEPROM (the

order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the

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ATmega128(L)

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming” on page 273 for details about boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared

during the four last steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 2. EEPROM Programming Time

Number of Calibrated RC

Symbol

Oscillator Cycles⁽¹⁾

Typ Programming Time

EEPROM Write (from CPU)

8448

8.5 ms

Note:

1. Uses 1 MHz clock, independent of CKSEL-fuse settings.

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The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts glo-

bally) so that no interrupts will occur during execution of these functions. The examples also

assume that no flash boot loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

EEPROM Write During When entering Power-down sleep mode while an EEPROM write operation is active, the

Power-down Sleep

Mode

EEPROM write operation will continue, and will complete before the write access time has

passed. However, when the write operation is completed, the Oscillator continues running, and

as a consequence, the device does not enter Power-down entirely. It is therefore recommended

to verify that the EEPROM write operation is completed before entering Power-down.

Preventing EEPROM

Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCReset Protection circuit

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2467P–AVR–08/07

can be used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

I/O Memory

The I/O space definition of the ATmega128 is shown in “Register Summary” on page 361.

All ATmega128 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O registers within the address range $00

- $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value

of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction

set section for more details. When using the I/O specific commands IN and OUT, the I/O

addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and

ST instructions, $20 must be added to these addresses. The ATmega128 is a complex micro-

controller with more peripheral units than can be supported within the 64 location reserved in

Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM,

only the ST/STS/STD and LD/LDS/LDD instructions can be used. The Extended I/O space is

replaced with SRAM locations when the ATmega128 is in the ATmega103 compatibility mode.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will operate on all bits in the I/O register, writing a one back into any flag read as set,

thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and peripherals control registers are explained in later sections.

External Memory

Interface

With all the features the External Memory Interface provides, it is well suited to operate as an

interface to memory devices such as External SRAM and Flash, and peripherals such as LCD-

display, A/D, and D/A. The main features are:

• Four different wait-state settings (including no wait-state).

• Independent wait-state setting for different extErnal Memory sectors (configurable sector size).

• The number of bits dedicated to address high byte is selectable.

• Bus-keepers on data lines to minimize current consumption (optional).

Overview

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM

becomes available using the dedicated External Memory pins (see Figure 1 on page 2, Table 27

on page 73, Table 33 on page 77, and Table 45 on page 85). The memory configuration is

shown in Figure 11.

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ATmega128(L)

Figure 11. External Memory with Sector Select

Memory Configuration A

Memory Configuration B

0x0000

Internal memory

0x0FFF

0x1000

0x10FF

0x1100

Lower sector

SRW01

SRW00

SRW10

SRL[2..0]

External Memory

Upper sector

External Memory

(0-60K x 8)

SRW11

SRW10

0xFFFF

Note:

ATmega128 in non ATmega103 compatibility mode: Memory Configuration A is available (Memory

Configuration B N/A)

ATmega128 in ATmega103 compatibility mode: Memory Configuration B is available (Memory

Configuration A N/A)

ATmega103

Compatibility

Both External Memory Control Registers (XMCRA and XMCRB) are placed in Extended I/O

space. In ATmega103 compatibility mode, these registers are not available, and the features

selected by these registers are not available. The device is still ATmega103 compatible, as

these features did not exist in ATmega103. The limitations in ATmega103 compatibility mode

are:

•

Only two wait-states settings are available (SRW1n = 0b00 and SRW1n = 0b01).

The number of bits that are assigned to address high byte are fixed.

The External Memory section can not be divided into sectors with different wait-state

settings.

•

Bus-keeper is not available.

RD, WR and ALE pins are output only (Port G in ATmega128).

Using the External

Memory Interface

The interface consists of:

•

AD7:0: Multiplexed low-order address bus and data bus.

A15:8: High-order address bus (configurable number of bits).

ALE: Address latch enable.

RD: Read strobe.

WR: Write strobe.

27

2467P–AVR–08/07

The control bits for the External Memory Interface are located in three registers, the MCU Con-

trol Register – MCUCR, the External Memory Control Register A – XMCRA, and the External

Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the data

direction registers that corresponds to the ports dedicated to the XMEM interface. For details

about the port override, see the alternate functions in section “I/O Ports” on page 66. The XMEM

interface will auto-detect whether an access is internal or external. If the access is external, the

XMEM interface will output address, data, and the control signals on the ports according to Fig-

ure 13 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,

there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface

is enabled, also an internal access will cause activity on address, data and ALE ports, but the

RD and WR strobes will not toggle during internal access. When the External Memory Interface

is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter-

face is disabled, the address space above the internal SRAM boundary is not mapped into the

internal SRAM. Figure 12 illustrates how to connect an external SRAM to the AVR using an octal

latch (typically “74 x 573” or equivalent) which is transparent when G is high.

Address Latch

Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with

care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-

tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The

External Memory Interface is designed in compliance to the 74AHC series latch. However, most

latches can be used as long they comply with the main timing parameters. The main parameters

for the address latch are:

•

D to Q propagation delay (t_PD).

Data setup time before G low (t_SU).

Data (address) hold time after G low (_TH).

The External Memory Interface is designed to guaranty minimum address hold time after G is

asserted low of t_h= 5 ns. Refer to t_{LAXX_LD}/t_{LLAXX_ST}in “External Data Memory Timing” Tables

137 through Tables 144 on pages 327 - 329. The D-to-Q propagation delay (t_PD) must be taken

into consideration when calculating the access time requirement of the external component. The

data setup time before G low (t_SU) must not exceed address valid to ALE low (t_AVLLC) minus PCB

wiring delay (dependent on the capacitive load).

Figure 12. External SRAM Connected to the AVR

D[7:0]

AD7:0

ALE

D

G

Q

A[7:0]

SRAM

A[15:8]

AVR

A15:8

RD

WR

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Pull-up and Bus-

keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to

one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by

writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-

abled and enabled in software as described in “External Memory Control Register B – XMCRB”

on page 33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the

AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.

Timing

External Memory devices have different timing requirements. To meet these requirements, the

ATmega128 XMEM interface provides four different wait-states as shown in Table 4. It is impor-

tant to consider the timing specification of the External Memory device before selecting the wait-

state. The most important parameters are the access time for the external memory compared to

the set-up requirement of the ATmega128. The access time for the External Memory is defined

to be the time from receiving the chip select/address until the data of this address actually is

driven on the bus. The access time cannot exceed the time from the ALE pulse must be

asserted low until data is stable during a read sequence (See t_LLRL+ t_RLRH- t_DVRHin Tables 137

through Tables 144 on pages 327 - 329). The different wait-states are set up in software. As an

additional feature, it is possible to divide the external memory space in two sectors with individ-

ual wait-state settings. This makes it possible to connect two different memory devices with

different timing requirements to the same XMEM interface. For XMEM interface timing details,

please refer to Table 137 to Table 144 and Figure 156 to Figure 159 in the “External Data Mem-

ory Timing” on page 327.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-

quently, the XMEM interface is not suited for synchronous operation.

Figure 13. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)

T1

T2

T3

T4

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Address

Data

XXXXXXXX

XXXXX

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

accesses the RAM (internal or external).

29

2467P–AVR–08/07

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal

or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0⁽¹⁾

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal

or external).

30

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1⁽¹⁾

T1

T2

T3

T4

T5

T6

T7

System Clock (CLK_CPU

)

ALE

A15:8 Prev. addr.

DA7:0 Prev. data

WR

Address

Data

Address

XX

DA7:0 (XMBK = 0) Prev. data

DA7:0 (XMBK = 1) Prev. data

RD

Data

Address

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal

or external).

XMEM Register

Description

MCU Control Register

– MCUCR

Bit

7

6

SRW10

R/W

0

5

SE

R/W

0

4

3

2

1

IVSEL

R/W

0

IVCE

R/W

0

SRE

R/W

0

SM1

R/W

0

SM0

R/W

0

SM2

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,

ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin

direction settings in the respective data direction registers. Writing SRE to zero, disables the

External Memory Interface and the normal pin and data direction settings are used.

• Bit 6 – SRW10: Wait-state Select Bit

For a detailed description in non-ATmega103 compatibility mode, see common description for

the SRWn bits below (XMCRA description). In ATmega103 compatibility mode, writing SRW10

to one enables the wait-state and one extra cycle is added during read/write strobe as shown in

Figure 14.

External Memory

Control Register A –

XMCRA

Bit

7

–

6

SRL2

R/W

0

5

SRL1

R/W

0

4

SRL0

R/W

0

3

SRW01

R/W

0

2

SRW00

R/W

0

1

SRW11

R/W

0

–

XMCRA

Read/Write

Initial Value

R

0

R

0

• Bit 7 – Res: Reserved Bit

This is a reserved bit and will always read as zero. When writing to this address location, write

this bit to zero for compatibility with future devices.

• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit

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2467P–AVR–08/07

It is possible to configure different wait-states for different External Memory addresses. The

external memory address space can be divided in two sectors that have separate wait-state bits.

The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 3 and Figure 11. By

default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address

space is treated as one sector. When the entire SRAM address space is configured as one sec-

tor, the wait-states are configured by the SRW11 and SRW10 bits.

Table 3. Sector limits with different settings of SRL2..0

SRL2

SRL1

SRL0

Sector Limits

0

Lower sector = N/A

Upper sector = 0x1100 - 0xFFFF

0

1

0

1

0

1

0

1

0

1

0

1

Lower sector = 0x1100 - 0x1FFF

Upper sector = 0x2000 - 0xFFFF

Lower sector = 0x1100 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

Lower sector = 0x1100 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

Lower sector = 0x1100 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x1100 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x1100 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x1100 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-

nal memory address space, see Table 4.

• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-

nal memory address space, see Table 4.

Table 4. Wait States⁽¹⁾

SRWn1 SRWn0 Wait States

0

1

0

1

0

1

No wait-states

Wait one cycle during read/write strobe

Wait two cycles during read/write strobe

Wait two cycles during read/write and wait one cycle before driving out

new address

Note:

1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see Figures

13 through Figures 16 for how the setting of the SRW bits affects the timing.

• Bit 0 – Res: Reserved Bit

This is a reserved bit and will always read as zero. When writing to this address location, write

this bit to zero for compatibility with future devices.

32

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

External Memory

Control Register B –

XMCRB

Bit

7

XMBK

R/W

0

6

–

5

–

4

–

3

–

2

XMM2

R/W

0

1

XMM1

R/W

0

XMM0

R/W

0

XMCRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is

enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise

be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so

even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is

one.

• Bit 6..4 – Res: Reserved Bits

These are reserved bits and will always read as zero. When writing to this address location,

write these bits to zero for compatibility with future devices.

• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are default used for the high address byte.

If the full 60KB address space is not required to access the External Memory, some, or all, Port

C pins can be released for normal Port Pin function as described in Table 5. As described in

“Using all 64KB Locations of External Memory” on page 35, it is possible to use the XMMn bits to

access all 64KB locations of the External Memory.

Table 5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address

Released Port Pins

None

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8 (Full 60 KB space)

7

PC7

6

PC7 - PC6

PC7 - PC5

PC7 - PC4

PC7 - PC3

PC7 - PC2

Full Port C

5

4

3

2

No Address high bits

Using all Locations of Since the external memory is mapped after the internal memory as shown in Figure 11, the

External Memory

Smaller than 64 KB

external memory is not addressed when addressing the first 4,352 bytes of data space. It may

appear that the first 4,352 bytes of the external memory are inaccessible (external memory

addresses 0x0000 to 0x10FF). However, when connecting an external memory smaller than 64

KB, for example 32 KB, these locations are easily accessed simply by addressing from address

0x8000 to 0x90FF. Since the External Memory Address bit A15 is not connected to the external

memory, addresses 0x8000 to 0x90FF will appear as addresses 0x0000 to 0x10FF for the exter-

nal memory. Addressing above address 0x90FF is not recommended, since this will address an

external memory location that is already accessed by another (lower) address. To the Applica-

tion software, the external 32 KB memory will appear as one linear 32 KB address space from

0x1100 to 0x90FF. This is illustrated in Figure 17. Memory configuration B refers to the

ATmega103 compatibility mode, configuration A to the non-compatible mode.

When the device is set in ATmega103 compatibility mode, the internal address space is 4,096

bytes. This implies that the first 4,096 bytes of the external memory can be accessed at

33

2467P–AVR–08/07

addresses 0x8000 to 0x8FFF. To the Application software, the external 32 KB memory will

appear as one linear 32 KB address space from 0x1000 to 0x8FFF.

Figure 17. Address Map with 32 KB External Memory

Memory Configuration B

Memory Configuration A

AVR Memory Map

External 32K SRAM

AVR Memory Map

External 32K SRAM

0x0000

Internal Memory

0x0FFF

0x1000

0x0FFF

0x1000

0x10FF

0x1100

0x10FF

0x1100

External

Memory

External

Memory

0x7FFF

0x8000

0x7FFF

0x8000

0x7FFF

0x90FF

0x9100

0x8FFF

0x9000

(Unused)

0xFFFF

34

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Using all 64KB

Locations of External

Memory

Since the External Memory is mapped after the Internal Memory as shown in Figure 11, only

60KB of External Memory is available by default (address space 0x0000 to 0x10FF is reserved

for internal memory). However, it is possible to take advantage of the entire External Memory by

masking the higher address bits to zero. This can be done by using the XMMn bits and control

by software the most significant bits of the address. By setting Port C to output 0x00, and releas-

ing the most significant bits for normal Port Pin operation, the Memory Interface will address

0x0000 - 0x1FFF. See the following code examples.

Assembly Code Example⁽¹⁾

; OFFSET is defined to 0x2000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi r16, 0xFF

out DDRC, r16

ldi r16, 0x00

out PORTC, r16

; release PC7:5

ldi r16, (1<<XMM1)|(1<<XMM0)

sts XMCRB, r16

; write 0xAA to address 0x0001 of external

; memory

ldi r16, 0xaa

sts 0x0001+OFFSET, r16

; re-enable PC7:5 for external memory

ldi r16, (0<<XMM1)|(0<<XMM0)

sts XMCRB, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi r16, 0x55

sts 0x0001+OFFSET, r16

C Code Example⁽¹⁾

#define OFFSET 0x2000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

XMCRB = (1<<XMM1) | (1<<XMM0);

*p = 0xaa;

XMCRB = 0x00;

*p = 0x55;

}

Note:

1. See “About Code Examples” on page 9.

Care must be exercised using this option as most of the memory is masked away.

35

2467P–AVR–08/07

System Clock

and Clock

Options

Clock Systems

and their

Distribution

Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 45. The clock systems are detailed below.

Figure 18. Clock Distribution

Asynchronous

Timer/Counter

General I/O

modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_ADC

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_ASY

clk_FLASH

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Clock

Multiplexer

Watchdog

Oscillator

Timer/Counter

Oscillator

External RC

Oscillator

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

Calibrated RC

Oscillator

External clock

CPU Clock – clk_CPU

I/O Clock – clk_I/O

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that address recognition in the TWI module is carried out asynchro-

nously when clk_I/Ois halted, enabling TWI address reception in all sleep modes.

Flash Clock – clk_FLASHThe Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

36

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Asynchronous Timer

Clock – clk_ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external 32 kHz clock crystal. The dedicated clock domain allows using this

Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

XTAL Divide Control

Register – XDIV

The XTAL Divide Control Register is used to divide the Source clock frequency by a number in

the range 2 - 129. This feature can be used to decrease power consumption when the require-

ment for processing power is low.

Bit

7

XDIVEN

R/W

0

6

XDIV6

R/W

0

5

XDIV5

R/W

0

4

XDIV4

R/W

0

3

XDIV3

R/W

0

2

XDIV2

R/W

0

1

XDIV1

R/W

0

XDIV0

R/W

0

XDIV

Read/Write

Initial Value

• Bit 7 – XDIVEN: XTAL Divide Enable

When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk_I/O,

clk_ADC, clk_CPU, clk_FLASH) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit

can be written run-time to vary the clock frequency as suitable to the application.

• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0

These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of

these bits is denoted d, the following formula defines the resulting CPU and peripherals clock

frequency f_CLK

:

Source clock

f

= ---------------------------------

CLK

129 – d

The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is written to

one, the value written simultaneously into XDIV6..XDIV0 is taken as the division factor. When

XDIVEN is written to zero, the value written simultaneously into XDIV6..XDIV0 is rejected. As

the divider divides the master clock input to the MCU, the speed of all peripherals is reduced

when a division factor is used.

When the system clock is divided, Timer/Counter0 can be used with Asynchronous clock only. The fre-

quency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source

clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter0 registers may fail.

Clock Sources

The device has the following clock source options, selectable by Flash fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 6. Device Clocking Options Select

Device Clocking Option

CKSEL3..0⁽¹⁾

1111 - 1010

1001

External Crystal/Ceramic Resonator

External Low-frequency Crystal

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2467P–AVR–08/07

Table 6. Device Clocking Options Select

Device Clocking Option

CKSEL3..0⁽¹⁾

1000 - 0101

0100 - 0001

0000

External RC Oscillator

Calibrated Internal RC Oscillator

External Clock

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is as an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7.

The frequency of the Watchdog Oscillator is voltage dependent as shown in the “ATmega128

Typical Characteristics” on page 332.

Table 7. Number of Watchdog Oscillator Cycles

Typical Time-out (V_CC= 5.0V)

Typical Time-Out (V_CC= 3.0V)

Number of Cycles

4K (4,096)

4.1 ms

65 ms

4.3 ms

69 ms

64K (65,536)

Default Clock

Source

The device is shipped with CKSEL = “0001” and SUT = “10”. The default clock source setting is

therefore the Internal RC Oscillator with longest startup time. This default setting ensures that all

users can make their desired clock source setting using an In-System or Parallel Programmer.

38

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 19. Either a quartz crystal or a

ceramic resonator may be used. The CKOPT fuse selects between two different Oscillator

Amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate will a full rail-

to-rail swing on the output. This mode is suitable when operating in a very noisy environment or

when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency

range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces

power consumption considerably. This mode has a limited frequency range and it can not be

used to drive other clock buffers.

For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with

CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The

optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray

capacitance, and the electromagnetic noise of the environment. Some initial guidelines for

choosing capacitors for use with crystals are given in Table 8. For ceramic resonators, the

capacitor values given by the manufacturer should be used.

Figure 19. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8.

Table 8. Crystal Oscillator Operating Modes

Frequency Range

(MHz)

Recommended Range for Capacitors

C1 and C2 for Use with Crystals

CKOPT

CKSEL3..1

101⁽¹⁾

1

0

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

1.0 -

–

110

12 pF - 22 pF

111

101, 110, 111

Note:

1. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 fuse together with the SUT1..0 fuses select the start-up times as shown in Table 9.

39

2467P–AVR–08/07

Table 9. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

AdditionalDelay

from Reset (V_CC

= 5.0V)

CKSEL0 SUT1..0

Recommended Usage

00

01

10

11

00

01

10

11

258 CK⁽¹⁾

1K CK⁽²⁾

16K CK

4.1 ms

65 ms

–

Ceramic resonator, fast

rising power

0

1

Ceramic resonator,

slowly rising power

Ceramic resonator,

BOD enabled

4.1 ms

65 ms

–

Ceramic resonator, fast

rising power

Ceramic resonator,

slowly rising power

Crystal Oscillator, BOD

enabled

4.1 ms

65 ms

Crystal Oscillator, fast

rising power

Crystal Oscillator,

slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

Low-frequency

Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal

Oscillator must be selected by setting the CKSEL fuses to “1001”. The crystal should be con-

nected as shown in Figure 19. By programming the CKOPT fuse, the user can enable internal

capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The inter-

nal capacitors have a nominal value of 36 pF.

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 10.

Table 10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset (V_CC

5.0V)

=

SUT1..0

00

Recommended Usage

1K CK⁽¹⁾

32K CK

4.1 ms

65 ms

Fast rising power or BOD enabled

Slowly rising power

01

10

Stable frequency at start-up

11

Reserved

Note:

1. These options should only be used if frequency stability at start-up is not important for the

application.

External RC

Oscillator

For timing insensitive applications, the External RC configuration shown in Figure 20 can be

used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22

40

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

pF. By programming the CKOPT fuse, the user can enable an internal 36 pF capacitor between

XTAL1 and GND, thereby removing the need for an external capacitor. For more information on

Oscillator operation and details on how to choose R and C, refer to the External RC Oscillator

application note.

Figure 20. External RC Configuration

V

CC

NC

XTAL2

XTAL1

GND

R

C

The Oscillator can operate in four different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 11.

Table 11. External RC Oscillator Operating Modes

CKSEL3..0

0101

Frequency Range (MHz)

0.1 - 0.9

0110

0.9 - 3.0

0111

3.0 - 8.0

1000

8.0 - 12.0

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 12.

Table 12. Start-Up Times for the External RC Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

SUT1..0

00

(V_CC= 5.0V)

Recommended Usage

BOD enabled

18 CK

6 CK⁽¹⁾

–

01

4.1 ms

65 ms

4.1 ms

Fast rising power

10

Slowly rising power

11

Fast rising power or BOD enabled

Note:

1. This option should not be used when operating close to the maximum frequency of the device.

41

2467P–AVR–08/07

Calibrated Internal The Calibrated Internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All fre-

quencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by

RC Oscillator

programming the CKSEL fuses as shown in Table 13. If selected, it will operate with no external

components. The CKOPT fuse should always be unprogrammed when using this clock option.

During Reset, hardware loads the calibration byte for the 1MHz oscillator into the OSCCAL Reg-

ister and thereby automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator

frequency selected, this calibration gives a frequency within 3% of the nominal frequency.

Using calibration methods as described in application notes available at www.atmel.com/avr it is

possible to achieve 1% accuracy at any given V_CCand Temperature. When this Oscillator is

used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for

the Reset Time-out. For more information on the pre-programmed calibration value, see the sec-

tion “Calibration Byte” on page 289.

Table 13. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0

0001⁽¹⁾

0010

Nominal Frequency (MHz)

1.0

2.0

4.0

8.0

0011

0100

Note:

1. The device is shipped with this option selected.

When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 14. XTAL1 and XTAL2 should be left unconnected (NC).

Table 14. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

–

4.1 ms

01

Fast rising power

Slowly rising power

10⁽¹⁾

65 ms

11

Reserved

Notes: 1. The device is shipped with this option selected.

Oscillator Calibration

Register – OSCCAL

Bit

7

6

5

4

3

2

1

0

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

Note:

OSCCAL Register is not available in ATmega103 compatibility mode.

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the Internal Oscillator to remove process vari-

ations from the Oscillator frequency. During Reset, the 1 MHz calibration value which is located

in the signature row high byte (address 0x00) is automatically loaded into the OSCCAL Register.

If the internal RC is used at other frequencies, the calibration values must be loaded manually.

This can be done by first reading the signature row by a programmer, and then store the calibra-

tion values in the Flash or EEPROM. Then the value can be read by software and loaded into

the OSCCAL Register. When OSCCAL is zero, the lowest available frequency is chosen. Writing

non-zero values to this register will increase the frequency of the Internal Oscillator. Writing $FF

42

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

to the register gives the highest available frequency. The calibrated Oscillator is used to time

EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10%

above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the

Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not

guaranteed, as indicated in Table 15.

Table 15. Internal RC Oscillator Frequency Range.

Min Frequency in Percentage of

Nominal Frequency (%)

Max Frequency in Percentage of

Nominal Frequency (%)

OSCCAL Value

$00

$7F

$FF

50

75

100

150

200

100

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

21. To run the device on an external clock, the CKSEL fuses must be programmed to “0000”. By

programming the CKOPT fuse, the user can enable an internal 36 pF capacitor between XTAL1

and GND.

Figure 21. External Clock Drive Configuration

EXTERNAL

CLOCK

SIGNAL

When this clock source is selected, start-up times are determined by the SUT fuses as shown in

Table 16.

Table 16. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

–

4.1 ms

01

Fast rising power

Slowly rising power

10

65 ms

11

Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

43

2467P–AVR–08/07

Timer/Counter

Oscillator

For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is

connected directly between the pins. No external capacitors are needed. The Oscillator is opti-

mized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is

not recommended.

Note:

The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator

and the internal capacitors have the same nominal value of 36 pF.

44

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Power

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

Management

and Sleep

Modes

To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register

select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or

Extended Standby) will be activated by the SLEEP instruction. See Table 17 for a summary. If

an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is

then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the register file and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Figure 18 on page 36 presents the different clock systems in the ATmega128, and their distribu-

tion. The figure is helpful in selecting an appropriate sleep mode.

MCU Control Register The MCU Control Register contains control bits for power management.

– MCUCR

Bit

7

6

SRW10

R/W

0

5

SE

R/W

0

4

3

2

1

IVSEL

R/W

0

IVCE

R/W

0

SRE

R/W

0

SM1

R/W

0

SM0

R/W

0

SM2

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the Sleep mode when the

SLEEP instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-

grammers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the

execution of the SLEEP instruction and to clear it immediately after waking up.

• Bits 4..2 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the six available sleep modes as shown in Table 17.

Table 17. Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Power-save

Reserved

Standby⁽¹⁾

Extended Standby⁽¹⁾

Note:

1. Standby mode and Extended Standby mode are only available with external crystals or

resonators.

45

2467P–AVR–08/07

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial

Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

ADC Noise

Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the

Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog to continue

operating (if enabled). This sleep mode basically halts clk_I/O, clk_CPU, and clk_FLASH, while allowing

the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an

SPM/EEPROM ready interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on

INT3:0 can wake up the MCU from ADC Noise Reduction mode.

Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the

Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled).

Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface

address match interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on

INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing

operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 90

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 37.

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0

will run during sleep. The device can wake up from either Timer Overflow or Output Compare

event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in

TIMSK, and the global interrupt enable bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended

instead of Power-save mode because the contents of the registers in the asynchronous timer

should be considered undefined after wake-up in Power-save mode if AS0 is 0.

This sleep mode basically halts all clocks except clk_ASY, allowing operation only of asynchronous

modules, including Timer/Counter0 if clocked asynchronously.

46

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Standby Mode

When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in 6 clock cycles.

Extended Standby When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to

Power-save mode with the exception that the Oscillator is kept running. From Extended Standby

mode, the device wakes up in six clock cycles.

Mode

Table 18. Active Clock Domains and Wake Up Sources in the Different Sleep Modes

Active Clock Domains

Oscillators

Wake Up Sources

SPM/

MainClock

Source

clk_CPUclk_FLASHclk_IOclk_ADCclk_ASYEnabled

Timer

Osc

Enabled INT7:0

TWI

Address

Match

Sleep

Mode

EEPROM

Ready

Other

ADC I/O

Timer 0

X

Idle

X

X⁽²⁾

X

ADC

Noise

X

X⁽²⁾

X⁽³⁾

X

Reduction

Power-

down

X⁽³⁾

X

Power-

save

X⁽²⁾

X⁽³⁾

X

X⁽²⁾

Standby⁽¹⁾

X

Extended

Standby⁽¹⁾

X⁽²⁾

Notes: 1. External Crystal or resonator selected as clock source

2. If AS0 bit in ASSR is set

3. Only INT3:0 or level interrupt INT7:4

47

2467P–AVR–08/07

Minimizing Power There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

Consumption

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

Analog to Digital

Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 230

for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. Refer to “Analog Comparator” on page 227 for details on how to

configure the Analog Comparator.

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the

Brown-out Detector is enabled by the BODEN fuse, it will be enabled in all sleep modes, and

hence, always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Brown-out Detector” on page 48 for details on how to

configure the Brown-out Detector.

Internal Voltage

Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 54 for details on the start-up time.

Watchdog Timer

Port Pins

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 55 for details on how to configure the Watchdog Timer.

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

the both the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the

device will be disabled. This ensures that no power is consumed by the input logic when not

needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will

then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 70 for

details on which pins are enabled. If the input buffer is enabled and the input signal is left floating

or have an analog signal level close to V_CC/2, the input buffer will use excessive power.

48

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

JTAG Interface and

On-chip Debug

System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or

Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will

contribute significantly to the total current consumption. There are three alternative ways to

avoid this:

•

Disable OCDEN Fuse.

Disable JTAGEN Fuse.

Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or

leaving the JTAG fuse unprogrammed disables the JTAG interface.

49

2467P–AVR–08/07

System Control

and Reset

Resetting the AVR

During Reset, all I/O registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute

jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the interrupt vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the interrupt

vectors are in the Boot section or vice versa. The circuit diagram in Figure 22 shows the reset

logic. Table 19 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the CKSEL fuses. The different selec-

tions for the delay period are presented in “Clock Sources” on page 37.

Reset Sources

The ATmega128 has five sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the Brown-out Detector is enabled.

JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register,

one of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG)

Boundary-scan” on page 252 for details.

50

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 22. Reset Logic

DATA BUS

D

L

Q

MCU Control and Status

Register (MCUCSR)

PEN

Pull-up Resistor

Power-On Reset

Circuit

Brown-Out

Reset Circuit

BODEN

BODLEVEL

Pull-up Resistor

SPIKE

FILTER

Reset Circuit

RESET

JTAG Reset

Register

Watchdog

Timer

Watchdog

Oscillator

Delay Counters

Clock

CK

TIMEOUT

Generator

CKSEL[3:0]

SUT[1:0]

Table 19. Reset Characteristics

Symbol Parameter

Condition

Min

Typ

Max

Units

Power-on Reset

Threshold Voltage

1.4

2.3

V

(rising)

V_POT

Power-on Reset

Threshold Voltage

1.3

2.3

V

(falling)⁽¹⁾

RESET Pin Threshold

Voltage

V_RST

0.2 V_CC

1.5

0.85 V_CC

V

Pulse width on RESET

t_RST

µs

Brown-out Reset

BODLEVEL = 1

BODLEVEL = 0

BODLEVEL = 1

2.4

3.7

2.6

4.0

2

2.9

Threshold Voltage⁽²⁾

V_BOT

V

4.5

Minimum low voltage

period for Brown-out

Detection

µs

t_BOD

BODLEVEL = 0

2

Brown-out Detector

hysteresis

V_HYST

100

mV

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

2. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

51

2467P–AVR–08/07

antees that a Brown-out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL=1 for ATmega128L and BODLEVEL=0 for ATmega128. BODLEVEL=1 is not

applicable for ATmega128.

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 19. The POR is activated whenever V_CCis below the detection level. The

POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

Figure 23. MCU Start-up, RESET Tied to V_CC

.

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 24. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see Table 19) will generate a reset, even if the clock is not running.

Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage – V_RSTon its positive edge, the delay counter starts the MCU after the

Time-out period t_TOUThas expired.

52

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 25. External Reset During Operation

CC

Brown-out Detection

ATmega128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel dur-

ing operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL

programmed). The trigger level has a hysteresis to ensure spike free Brown-out Detection. The

hysteresis on the detection level should be interpreted as V_BOT+= V_BOT+ V_HYST/2 and V_BOT-

_BOT- V_HYST/2.

=

V

The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled

(BODEN programmed), and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

26), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 26), the delay counter starts the MCU after the time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in Table 19.

Figure 26. Brown-out Reset During Operation

V

BOT+

CC

V

BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

53

2467P–AVR–08/07

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the

falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to page

55 for details on operation of the Watchdog Timer.

Figure 27. Watchdog Reset During Operation

CC

CK

MCU Control and

Status Register –

MCUCSR

The MCU Control and Status Register provides information on which reset source caused an

MCU reset.

Bit

7

6

–

5

–

4

3

2

1

0

JTD

R/W

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUCSR

Read/Write

Initial Value

R

0

R

0

See Bit Description

Note that only EXTRF and PORF are available in ATmega103 compatibility mode.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-On Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the reset flags to identify a reset condition, the user should read and then reset

the MCUCSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the reset flags.

Internal Voltage

Reference

ATmega128 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V ref-

erence to the ADC is generated from the internal bandgap reference.

54

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Voltage Reference

Enable Signals and

Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 20. To save power, the reference is not always turned on. The ref-

erence is on during the following situations:

1. When the BOD is enabled (by programming the BODEN fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 20. Internal Voltage Reference Characteristics

Symbol

V_BG

Parameter

Min

Typ

1.23

40

Max

1.40

70

Units

V

Bandgap reference voltage

Bandgap reference start-up time

Bandgap reference current consumption

1.15

t_BG

µs

I_BG

10

µA

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz. This is

the typical value at V_CC= 5V. See characterization data for typical values at other V_CClevels. By

controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as

shown in Table 22 on page 57. The WDR – Watchdog Reset – instruction resets the Watchdog

Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the ATmega128 resets and executes from the

Reset Vector. For timing details on the Watchdog Reset, refer to page 54.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3

different safety levels are selected by the Fuses M103C and WDTON as shown in Table 21.

Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling the

WDT in any of the safety levels. Refer to “Timed Sequences for Changing the Configuration of

the Watchdog Timer” on page 58 for details.

55

2467P–AVR–08/07

Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.

How to

Safety WDTInitial How to Disable

Change

M103C

WDTON

Level

State

the WDT

Time-out

Unprogrammed Unprogrammed

1

Disabled

Timed

sequence

Unprogrammed Programmed

2

0

2

Enabled

Disabled

Enabled

Always enabled

Timed

sequence

Programmed

Unprogrammed

Programmed

Timed

sequence

No

restriction

Always enabled

Timed

sequence

Figure 28. Watchdog Timer

WATCHDOG

OSCILLATOR

Watchdog Timer

Control Register –

WDTCR

Bit

7

–

6

–

5

–

4

WDCE

R/W

0

3

WDE

R/W

0

2

1

WDP1

R/W

0

WDP2

R/W

0

WDP0

R/W

0

WDTCR

Read/Write

Initial Value

R

0

R

0

R

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATmega128 and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit

must also be set when changing the prescaler bits. See “Timed Sequences for Changing the

Configuration of the Watchdog Timer” on page 58.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

56

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See “Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 58.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-

dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods

are shown in Table 22.

Table 22. Watchdog Timer Prescale Select

Number of WDT

Oscillator Cycles

TypicalTime-out

at V_CC= 3.0V

Typical Time-out

at V_CC= 5.0V

WDP2 WDP1 WDP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K (16,384)

32K (32,768)

14.8 ms

29.6 ms

59.1 ms

0.12 s

0.24 s

0.47 s

0.95 s

1.9 s

14.0 ms

28.1 ms

56.2 ms

0.11 s

0.22 s

0.45 s

0.9 s

64K (65,536)

128K (131,072)

256K (262,144)

512K (524,288)

1,024K (1,048,576)

2,048K (2,097,152)

1.8 s

57

2467P–AVR–08/07

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

Assembly Code Example

WDT_off:

; Reset WDT

wdr

in r16, WDTCR

; Write logical one to WDCE and WDE

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

{

/* Reset WDT*/

__watchdog_reset();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the three safety levels. Sepa-

rate procedures are described for each level.

Safety Level 0

Safety Level 1

This mode is compatible with the Watchdog operation found in ATmega103. The Watchdog

Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.

The time-out period can be changed at any time without restriction. To disable an enabled

Watchdog Timer, the procedure described on page 56 (WDE bit description) must be followed.

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out

period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or

changing the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as

desired, but with the WDCE bit cleared.

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

58

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

59

2467P–AVR–08/07

Interrupts

This section describes the specifics of the interrupt handling as performed in ATmega128. For a

general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on

page 15.

Interrupt Vectors

in ATmega128

Table 23. Reset and Interrupt Vectors

Vector

No.

Program

Address⁽²⁾Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

1

$0000⁽¹⁾

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

$0012

$0014

$0016

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

$0030⁽³⁾

$0032⁽³⁾

$0034⁽³⁾

$0036⁽³⁾

$0038⁽³⁾

$003A⁽³⁾

RESET

INT0

2

External Interrupt Request 0

External Interrupt Request 1

External Interrupt Request 2

External Interrupt Request 3

External Interrupt Request 4

External Interrupt Request 5

External Interrupt Request 6

External Interrupt Request 7

Timer/Counter2 Compare Match

Timer/Counter2 Overflow

3

INT1

4

INT2

5

INT3

6

INT4

7

INT5

8

INT6

9

INT7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

TIMER2 COMP

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

TIMER1 COMPB Timer/Counter1 Compare Match B

TIMER1 OVF

TIMER0 COMP

TIMER0 OVF

SPI, STC

Timer/Counter1 Overflow

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART0, Rx Complete

USART0 Data Register Empty

USART0, Tx Complete

ADC Conversion Complete

EEPROM Ready

USART0, RX

USART0, UDRE

USART0, TX

ADC

EE READY

ANALOG COMP

Analog Comparator

TIMER1 COMPC Timer/Countre1 Compare Match C

TIMER3 CAPT

Timer/Counter3 Capture Event

TIMER3 COMPA

Timer/Counter3 Compare Match A

TIMER3 COMPB Timer/Counter3 Compare Match B

TIMER3 COMPC Timer/Counter3 Compare Match C

TIMER3 OVF

Timer/Counter3 Overflow

60

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 23. Reset and Interrupt Vectors (Continued)

Vector

No.

Program

Address⁽²⁾Source

Interrupt Definition

31

32

33

34

35

$003C⁽³⁾

$003E⁽³⁾

$0040⁽³⁾

$0042⁽³⁾

$0044⁽³⁾

USART1, RX

USART1, Rx Complete

USART1 Data Register Empty

USART1, Tx Complete

Two-wire Serial Interface

USART1, UDRE

USART1, TX

TWI

SPM READY

Store Program Memory Ready

Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at

reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 273.

2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the Boot

Flash section. The address of each interrupt vector will then be address in this table added to

the start address of the boot Flash section.

3. The Interrupts on address $0030 - $0044 do not exist in ATmega103 compatibility mode.

Table 24 shows Reset and interrupt vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt

vectors are not used, and regular program code can be placed at these locations. This is also

the case if the Reset Vector is in the Application section while the interrupt vectors are in the

Boot section or vice versa.

Table 24. Reset and Interrupt Vectors Placement

BOOTRST

IVSEL

Reset Address

$0000

Interrupt Vectors Start Address

$0002

1

0

1

0

1

$0000

Boot Reset Address + $0002

$0002

Boot Reset Address

Boot Reset Address + $0002

Note:

The Boot Reset Address is shown in Table 112 on page 284. For the BOOTRST fuse “1” means

unprogrammed while “0” means programmed.

61

2467P–AVR–08/07

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega128 is:

Address LabelsCode

Comments

$0000

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

$0012

$0014

$0016

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

$0030

$0032

$0034

$0036

$0038

$003A

$003C

$003E

$0040

$0042

$0044

;

jmp

RESET

; Reset Handler

EXT_INT0 ; IRQ0 Handler

EXT_INT1 ; IRQ1 Handler

EXT_INT2 ; IRQ2 Handler

EXT_INT3 ; IRQ3 Handler

EXT_INT4 ; IRQ4 Handler

EXT_INT5 ; IRQ5 Handler

EXT_INT6 ; IRQ6 Handler

EXT_INT7 ; IRQ7 Handler

TIM2_COMP ; Timer2 Compare Handler

TIM2_OVF ; Timer2 Overflow Handler

TIM1_CAPT ; Timer1 Capture Handler

TIM1_COMPA; Timer1 CompareA Handler

TIM1_COMPB; Timer1 CompareB Handler

TIM1_OVF ; Timer1 Overflow Handler

TIM0_COMP ; Timer0 Compare Handler

TIM0_OVF ; Timer0 Overflow Handler

SPI_STC

; SPI Transfer Complete Handler

USART0_RXC; USART0 RX Complete Handler

USART0_DRE; USART0,UDR Empty Handler

USART0_TXC; USART0 TX Complete Handler

ADC

; ADC Conversion Complete Handler

; EEPROM Ready Handler

EE_RDY

ANA_COMP ; Analog Comparator Handler

TIM1_COMPC; Timer1 CompareC Handler

TIM3_CAPT ; Timer3 Capture Handler

TIM3_COMPA; Timer3 CompareA Handler

TIM3_COMPB; Timer3 CompareB Handler

TIM3_COMPC; Timer3 CompareC Handler

TIM3_OVF ; Timer3 Overflow Handler

USART1_RXC; USART1 RX Complete Handler

USART1_DRE; USART1,UDR Empty Handler

USART1_TXC; USART1 TX Complete Handler

TWI

; Two-wire Serial Interface Interrupt Handler

; SPM Ready Handler

SPM_RDY

$0046

$0047

$0048

RESET:ldir16, high(RAMEND); Main program start

out

ldi

SPH,r16

; Set stack pointer to top of RAM

r16, low(RAMEND)

SPL,r16

$0049

$004A

out

sei

; Enable interrupts

$004B

...

<instr> xxx

... ...

...

62

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses is:

Address LabelsCode

Comments

$0000

$0001

$0002

RESET:ldi

out

r16,high(RAMEND); Main program start

SPH,r16

; Set stack pointer to top of RAM

ldi

r16,low(RAMEND)

SPL,r16

$0003

$0004

out

sei

; Enable interrupts

$0005

;

<instr> xxx

.org $F002

$F002

jmp

...

jmp

EXT_INT0 ; IRQ0 Handler

EXT_INT1 ; IRQ1 Handler

$F004

...

;

$F044

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST fuse is programmed and the Boot section size set to 8K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address

.org $0002

$0002

LabelsCode

Comments

jmp

...

jmp

EXT_INT0 ; IRQ0 Handler

EXT_INT1 ; IRQ1 Handler

$0004

...

;

$0044

SPM_RDY

; Store Program Memory Ready Handler

;

.org $F000

$F000

$F001

$F002

RESET: ldi

r16,high(RAMEND); Main program start

SPH,r16 ; Set stack pointer to top of RAM

out

ldi

r16,low(RAMEND)

SPL,r16

$F003

$F004

out

sei

; Enable interrupts

$F005

<instr> xxx

When the BOOTRST fuse is programmed, the Boot section size set to 8K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses is:

Address

Labels

Code

Comments

;

.org $F000

$F000

$F002

jmp

RESET

; Reset handler

EXT_INT0 ; IRQ0 Handler

$F004

...

jmp

...

jmp

EXT_INT1 ; IRQ1 Handler

...

;

$F044

SPM_RDY ; Store Program Memory Ready Handler

r16,high(RAMEND); Main program start

$F046

$F047

$F048

RESET: ldi

out

SPH,r16

; Set stack pointer to top of RAM

ldi

r16,low(RAMEND)

63

2467P–AVR–08/07

$F049

$F04A

out

sei

SPL,r16

; Enable interrupts

$F04B

<instr> xxx

Moving Interrupts

Between Application

and Boot Space

The General Interrupt Control Register controls the placement of the interrupt vector table.

MCU Control Register

– MCUCR

Bit

7

6

SRW10

R/W

0

5

SE

R/W

0

4

3

2

1

IVSEL

R/W

0

IVCE

R/W

0

SRE

R/W

0

SM1

R/W

0

SM0

R/W

0

SM2

R/W

0

MCUCR

Read/Write

Initial Value

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash

memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot

Loader section of the flash. The actual address of the start of the Boot Flash section is deter-

mined by the BOOTSZ fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming” on page 273 for details. To avoid unintentional changes of interrupt vector

tables, a special write procedure must be followed to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If interrupt vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-

Write Self-Programming” on page 273 for details on Boot Lock bits.

64

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.

Assembly Code Example

Move_interrupts:

; Enable change of interrupt vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to boot flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of interrupt vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to boot flash section */

MCUCR = (1<<IVSEL);

}

65

2467P–AVR–08/07

I/O Ports

Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 29. Refer to “Electrical Charac-

teristics” on page 318 for a complete list of parameters.

Figure 29. I/O Pin Equivalent Schematic

R_PU

Pxn

Logic

C_PIN

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O regis-

ters and bit locations are listed in “Register Description for I/O Ports” on page 87.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

In addition, the Pull-up Disable – PUD bit in SFIOR disables the pull-up function for all pins in all

ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

67. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 71. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as General Digital I/O.

66

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Ports as General

Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional

description of one I/O port pin, here generically called Pxn.

Figure 30. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

Q

D

Pxn

PORTxn

Q _CLR

WPx

RRx

RESET

SLEEP

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WPx:

RRx:

RPx:

WRITE DDRx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

READ DDRx

SLEEP:

WRITE PORTx

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

Note:

1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O, SLEEP,

and PUD are common to all ports.

Configuring the Pin

Each port pin consists of three Register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O Ports” on page 87, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when a Reset condition becomes

active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output

67

2467P–AVR–08/07

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be written to one to

disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 25 summarizes the control signals for the pin value.

Table 25. Port Pin Configurations

PUD

DDxn PORTxn (in SFIOR)

I/O

Pull-up Comment

0

X

Input

No

Tri-state (Hi-Z)

Pxn will source current if ext. pulled

low.

0

1

0

1

0

1

Input

Yes

No

Tri-state (Hi-Z)

X

Output

Output Low (Sink)

Output High (Source)

Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the preceding latch consti-

tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near

the edge of the internal clock, but it also introduces a delay. Figure 31 shows a timing diagram of

the synchronization when reading an externally applied pin value. The maximum and minimum

propagation delays are denoted t_pd,maxand t_pd,minrespectively.

Figure 31. Synchronization when Reading an Externally Applied Pin Value

SYSTEM CLK

in r17, PINx

XXX

INSTRUCTIONS

SYNC LATCH

PINxn

0xFF

r17

0x00

t_{pd, max}

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

68

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows t_pd,maxand t_pd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 32. The out instruction sets the “SYNC LATCH” signal at the positive edge of the

clock. In this case, the delay t_pdthrough the synchronizer is one system clock period.

Figure 32. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

0xFF

nop

in r17, PINx

out PORTx, r16

INSTRUCTIONS

SYNC LATCH

PINxn

0xFF

0x00

r17

t

pd

69

2467P–AVR–08/07

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example⁽¹⁾

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable

and Sleep Modes

As shown in Figure 30, the digital input signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, Standby mode, and Extended Standby mode to avoid

high power consumption if some input signals are left floating, or have an analog signal level

close to V_CC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External Interrupt

Request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari-

ous other alternate functions as described in “Alternate Port Functions” on page 71.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned sleep modes, as the clamping in these sleep modes produces the requested

logic change.

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Unconnected pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

Alternate Port

Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 33 shows

how the port pin control signals from the simplified Figure 30 can be overridden by alternate

functions. The overriding signals may not be present in all port pins, but the figure serves as a

generic description applicable to all port pins in the AVR microcontroller family.

Figure 33. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

Pxn

Q

D

PORTxn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RRx

RESET

1

0

SYNCHRONIZER

RPx

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WPx:

RPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

I/O CLOCK

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

DIxn:

AIOxn:

:

DIGITAL INPUT PIN n ON PORTx

ANALOG INPUT/OUTPUT PIN n ON PORTx

SLEEP:

SLEEP CONTROL

Note:

1. WPx, WDx, RLx, RPx, and RDx are common to all pins within the same port. clk_I/O, SLEEP,

and PUD are common to all ports. All other signals are unique for each pin.

71

2467P–AVR–08/07

Table 26 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 33 are not shown in the succeeding tables. The overriding signals are generated internally in

the modules having the alternate function.

Table 26. Generic Description of Overriding Signals for Alternate Functions.

Signal

Name

Full Name

Description

PUOE

Pull-up

Override Enable

If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV

DDOE

DDOV

PVOE

Pull-up

Override Value

If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

Data Direction

Override Enable

If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

Data Direction

Override Value

If DDOE is set, the Output Driver is enabled/disabled

when DDOV is set/cleared, regardless of the setting of the

DDxn Register bit.

Port Value

Override Enable

If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output Driver is enabled, the port Value

is controlled by the PORTxn Register bit.

PVOV

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of

the setting of the PORTxn Register bit.

DIEOE

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU-state (Normal mode, Sleep

modes).

DIEOV

DI

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state

(Normal mode, Sleep modes).

Digital Input

This is the Digital Input to alternate functions. In the

figure, the signal is connected to the output of the schmitt

trigger but before the synchronizer. Unless the Digital

Input is used as a clock source, the module with the

alternate function will use its own synchronizer.

AIO

Analog

Input/output

This is the Analog Input/output to/from alternate functions.

The signal is connected directly to the pad, and can be

used bi-directionally.

The following subsections shortly describes the alternate functions for each port, and relates the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Special Function IO

Register – SFIOR

Bit

7

6

–

5

–

4

–

3

ACME

R/W

0

2

1

0

TSM

R/W

0

PUD

R/W

0

PSR0

R/W

0

PSR321

R/W

0

SFIOR

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 2 – PUD: Pull-up disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 67 for more details about this feature.

Alternate Functions of The Port A has an alternate function as the address low byte and data lines for the External

Port A

Memory Interface.

Table 27. Port A Pins Alternate Functions

Port Pin

PA7

Alternate Function

AD7 (External memory interface address and data bit 7)

AD6 (External memory interface address and data bit 6)

AD5 (External memory interface address and data bit 5)

AD4 (External memory interface address and data bit 4)

AD3 (External memory interface address and data bit 3)

AD2 (External memory interface address and data bit 2)

AD1 (External memory interface address and data bit 1)

AD0 (External memory interface address and data bit 0)

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 28 and Table 29 relates the alternate functions of Port A to the overriding signals shown in

Figure 33 on page 71.

Table 28. Overriding Signals for Alternate Functions in PA7..PA4

Signal

Name

PUOE

PUOV

PA7/AD7

PA6/AD6

PA5/AD5

PA4/AD4

SRE

~(WR | ADA⁽¹⁾) •

PORTA7 • PUD

~(WR | ADA) •

PORTA6 • PUD

~(WR | ADA) •

PORTA5 • PUD

~(WR | ADA) •

PORTA4 • PUD

DDOE

DDOV

PVOE

PVOV

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

A7 • ADA | D7

OUTPUT • WR

A6 • ADA | D6

OUTPUT • WR

A5 • ADA | D5

OUTPUT • WR

A4 • ADA | D4

OUTPUT • WR

DIEOE

DIEOV

DI

0

D7 INPUT

–

D6 INPUT

–

D5 INPUT

–

D4 INPUT

–

AIO

Note:

1. ADA is short for ADdress Active and represents the time when address is output. See “Exter-

nal Memory Interface” on page 26 for details.

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2467P–AVR–08/07

Table 29. Overriding Signals for Alternate Functions in PA3..PA0

Signal

Name

PUOE

PUOV

PA3/AD3

PA2/AD2

PA1/AD1

PA0/AD0

SRE

~(WR | ADA) •

PORTA3 • PUD

~(WR | ADA) •

PORTA2 • PUD

~(WR | ADA) •

PORTA1 • PUD

~(WR | ADA) •

PORTA0 • PUD

DDOE

DDOV

PVOE

PVOV

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

WR | ADA

SRE

A3 • ADA | D3

OUTPUT • WR

A2• ADA | D2

OUTPUT • WR

A1 • ADA | D1

OUTPUT • WR

A0 • ADA | D0

OUTPUT • WR

DIEOE

DIEOV

DI

0

D3 INPUT

–

D2 INPUT

–

D1 INPUT

–

D0 INPUT

–

AIO

Alternate Functions of The Port B pins with alternate functions are shown in Table 30.

Port B

Table 30. Port B Pins Alternate Functions

Port Pin Alternate Functions

OC2/OC1C⁽¹⁾(Output Compare and PWM Output for Timer/Counter2 or Output

Compare and PWM Output C for Timer/Counter1)

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

OC1B (Output Compare and PWM Output B for Timer/Counter1)

OC1A (Output Compare and PWM Output A for Timer/Counter1)

OC0 (Output Compare and PWM Output for Timer/Counter0)

MISO (SPI Bus Master Input/Slave Output)

MOSI (SPI Bus Master Output/Slave Input)

SCK (SPI Bus Serial Clock)

SS (SPI Slave Select input)

Note:

1. OC1C not applicable in ATmega103 compatibility mode.

The alternate pin configuration is as follows:

• OC2/OC1C, Bit 7

OC2, Output Compare Match output: The PB7 pin can serve as an external output for the

Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to

serve this function. The OC2 pin is also the output pin for the PWM mode timer function.

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the

Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set (one))

to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

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ATmega128(L)

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ATmega128(L)

• OC1B, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the

Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one))

to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

• OC1A, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the

Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one))

to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

• OC0, Bit 4

OC0, Output Compare Match output: The PB4 pin can serve as an external output for the

Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to

serve this function. The OC0 pin is also the output pin for the PWM mode timer function.

• MISO – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to

be an input, the pull-up can still be controlled by the PORTB3 bit.

• MOSI – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB2 bit.

• SCK – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is

enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced

to be an input, the pull-up can still be controlled by the PORTB1 bit.

• SS – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an

input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven

low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals shown in

Figure 33 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,

while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

75

2467P–AVR–08/07

Table 31. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name PB7/OC2/OC1C

PB6/OC1B

PB5/OC1A

PB4/OC0

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

0

OC2/OC1C ENABLE⁽¹⁾OC1B ENABLE OC1A ENABLE OC0 ENABLE

OC2/OC1C⁽¹⁾

OC1B

OC1A

OC0B

0

–

0

–

0

–

0

–

AIO

Note:

1. See “Output Compare Modulator (OCM1C2)” on page 161 for details. OC1C does not exist in

ATmega103 compatibility mode.

Table 32. Overriding Signals for Alternate Functions in PB3..PB0

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PB3/MISO

SPE • MSTR

PORTB3 • PUD

SPE • MSTR

0

PB2/MOSI

SPE • MSTR

PORTB2 • PUD

SPE • MSTR

0

PB1/SCK

PB0/SS

SPE • MSTR

PORTB1 • PUD PORTB0 • PUD

SPE • MSTR

0

SPE • MSTR

0

SPE • MSTR

0

SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT

0

SPI MSTR INPUT

–

SPI SLAVE INPUT

–

SCK INPUT

–

SPI SS

–

AIO

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ATmega128(L)

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ATmega128(L)

Alternate Functions of In ATmega103 compatibility mode, Port C is output only. The ATmega128 is by default shipped

Port C

in compatibility mode. Thus, if the parts are not programmed before they are put on the PCB,

PORTC will be output during first power up, and until the ATmega103 compatibility mode is dis-

abled. The Port C has an alternate function as the address high byte for the External Memory

Interface.

Table 33. Port C Pins Alternate Functions

Port Pin

PC7

Alternate Function

A15

A14

A13

A12

A11

A10

A9

PC6

PC5

PC4

PC3

PC2

PC1

PC0

A8

Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in

Figure 33 on page 71.

Table 34. Overriding Signals for Alternate Functions in PC7..PC4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PC7/A15

PC6/A14

PC5/A13

PC4/A12

SRE • (XMM⁽¹⁾<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

0

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

1

SRE • (XMM<1)

SRE • (XMM<2)

SRE • (XMM<3)

SRE • (XMM<4)

A15

0

A14

0

A13

0

A12

0

–

AIO

–

Note:

1. XMM = 0 in ATmega103 compatibility mode.

77

2467P–AVR–08/07

Table 35. Overriding Signals for Alternate Functions in PC3..PC0⁽¹⁾

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PC3/A11

PC2/A10

PC1/A9

PC0/A8

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

0

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

1

SRE • (XMM<5)

SRE • (XMM<6)

SRE • (XMM<7)

A11

0

A10

0

A9

0

A8

0

–

AIO

–

Note:

1. XMM = 0 in ATmega103 compatibility mode.

Alternate Functions of The Port D pins with alternate functions are shown in Table 36.

Port D

Table 36. Port D Pins Alternate Functions

Port Pin

PD7

Alternate Function

T2 (Timer/Counter2 Clock Input)

T1 (Timer/Counter1 Clock Input)

XCK1⁽¹⁾(USART1 External Clock Input/Output)

ICP1 (Timer/Counter1 Input Capture Pin)

PD6

PD5

PD4

PD3

INT3/TXD1⁽¹⁾(External Interrupt3 Input or UART1 Transmit Pin)

INT2/RXD1⁽¹⁾(External Interrupt2 Input or UART1 Receive Pin)

INT1/SDA⁽¹⁾(External Interrupt1 Input or TWI Serial DAta)

INT0/SCL⁽¹⁾(External Interrupt0 Input or TWI Serial CLock)

PD2

PD1

PD0

Note:

1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.

The alternate pin configuration is as follows:

• T2 – Port D, Bit 7

T2, Timer/Counter2 counter source.

• T1 – Port D, Bit 6

T1, Timer/Counter1 counter source.

• XCK1 – Port D, Bit 5

XCK1, USART1 External clock. The Data Direction Register (DDD4) controls whether the clock

is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1

operates in Synchronous mode.

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ATmega128(L)

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ATmega128(L)

• ICP1 – Port D, Bit 4

ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture Pin for Timer/Counter1.

• INT3/TXD1 – Port D, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the

MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD3.

• INT2/RXD1 – Port D, Bit 2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the

MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled

this pin is configured as an input regardless of the value of DDD2. When the USART forces this

pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

• INT1/SDA – Port D, Bit 1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the

MCU.

SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the

Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data

I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-

press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver

with slew-rate limitation.

• INT0/SCL – Port D, Bit 0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the

MCU.

SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the

Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock

I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-

press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver

with slew-rate limitation.

Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in

Figure 33 on page 71.

79

2467P–AVR–08/07

Table 37. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PD7/T2

PD6/T1

PD5/XCK1

PD4/ICP1

0

UMSEL1

0

XCK1 OUTPUT

0

T2 INPUT

–

T1 INPUT

–

XCK1 INPUT

–

ICP1 INPUT

–

AIO

Table 38. Overriding Signals for Alternate Functions in PD3..PD0⁽¹⁾

Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1

PD1/INT1/SDA

PD0/INT0/SCL

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

TXEN1

RXEN1

TWEN

0

PORTD2 • PUD

PORTD1 • PUD PORTD0 • PUD

TXEN1

RXEN1

TWEN

1

0

SDA_OUT

SCL_OUT

TWEN

TXEN1

0

TWEN

TXD1

0

INT3 ENABLE

INT2 ENABLE

1

INT1 ENABLE

1

INT0 ENABLE

1

INT3 INPUT

–

INT2 INPUT/RXD1 INT1 INPUT

– SDA INPUT

INT0 INPUT

SCL INPUT

AIO

Note:

1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins

PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between

the AIO outputs shown in the port figure and the digital logic of the TWI module.

80

ATmega128(L)

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ATmega128(L)

Alternate Functions of The Port E pins with alternate functions are shown in Table 39.

Port E

Table 39. Port E Pins Alternate Functions

Port Pin Alternate Function

PE7

PE6

INT7/ICP3⁽¹⁾(External Interrupt 7 Input or Timer/Counter3 Input Capture Pin)

INT6/ T3⁽¹⁾(External Interrupt 6 Input or Timer/Counter3 Clock Input)

INT5/OC3C⁽¹⁾(External Interrupt 5 Input or Output Compare and PWM Output C

for Timer/Counter3)

PE5

PE4

PE3

PE2

INT4/OC3B⁽¹⁾(External Interrupt4 Input or Output Compare and PWM Output B for

Timer/Counter3)

AIN1/OC3A ⁽¹⁾(Analog Comparator Negative Input or Output Compare and PWM

Output A for Timer/Counter3)

AIN0/XCK0⁽¹⁾(Analog Comparator Positive Input or USART0 external clock

input/output)

PE1

PE0

PDO/TXD0 (Programming Data Output or UART0 Transmit Pin)

PDI/RXD0 (Programming Data Input or UART0 Receive Pin)

Note:

1. ICP3, T3, OC3C, OC3B, OC3B, OC3A, and XCK0 not applicable in ATmega103 compatibility

mode.

• INT7/ICP3 – Port E, Bit 7

INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source.

ICP3 – Input Capture Pin3: The PE7 pin can act as an Input Capture Pin for Timer/Counter3.

• INT6/T3 – Port E, Bit 6

INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.

T3, Timer/Counter3 counter source.

• INT5/OC3C – Port E, Bit 5

INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source.

OC3C, Output Compare Match C output: The PE5 pin can serve as an External output for the

Timer/Counter3 Output Compare C. The pin has to be configured as an output (DDE5 set “one”)

to serve this function. The OC3C pin is also the output pin for the PWM mode timer function.

• INT4/OC3B – Port E, Bit 4

INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source.

OC3B, Output Compare Match B output: The PE4 pin can serve as an External output for the

Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set (one))

to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.

• AIN1/OC3A – Port E, Bit 3

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of

the Analog Comparator.

OC3A, Output Compare Match A output: The PE3 pin can serve as an External output for the

Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set “one”)

to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.

• AIN0/XCK0 – Port E, Bit 2

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of

the Analog Comparator.

81

2467P–AVR–08/07

XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock

is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0

operates in Synchronous mode.

• PDO/TXD0 – Port E, Bit 1

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is

used as data output line for the ATmega128.

TXD0, UART0 Transmit pin.

• PDI/RXD0 – Port E, Bit 0

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used

as data input line for the ATmega128.

RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the

USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0.

When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the inter-

nal pull-up.

Table 40 and Table 41 relates the alternate functions of Port E to the overriding signals shown in

Figure 33 on page 71.

Table 40. Overriding Signals for Alternate Functions PE7..PE4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PE7/INT7/ICP3

PE6/INT6/T3

PE5/INT5/OC3C

PE4/INT4/OC3B

0

OC3C ENABLE

OC3C

OC3B ENABLE

OC3B

0

INT7 ENABLE

1

INT6 ENABLE

1

INT5 ENABLE

1

INT4 ENABLE

1

INT7 INPUT/ICP3

INPUT

INT7 INPUT/T3

INPUT

INT5 INPUT

INT4 INPUT

AIO

–

82

ATmega128(L)

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ATmega128(L)

Table 41. Overriding Signals for Alternate Functions in PE3..PE0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PE3/AIN1/OC3A

PE2/AIN0/XCK0

PE1/PDO/TXD0

PE0/PDI/RXD0

0

TXEN0

RXEN0

0

PORTE0 • PUD

0

TXEN0

RXEN0

0

1

0

OC3B ENABLE

UMSEL0

XCK0 OUTPUT

0

TXEN0

0

OC3B

TXD0

0

–

0

XCK0 INPUT

AIN0 INPUT

RXD0

–

AIO

AIN1 INPUT

Alternate Functions of The Port F has an alternate function as analog input for the ADC as shown in Table 42. If some

Port F

Port F pins are configured as outputs, it is essential that these do not switch when a conversion

is in progress. This might corrupt the result of the conversion. In ATmega103 compatibility mode

Port F is input only. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI),

PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.

Table 42. Port F Pins Alternate Functions

Port Pin

PF7

Alternate Function

ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select)

ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

ADC3 (ADC input channel 3)

PF6

PF5

PF4

PF3

PF2

ADC2 (ADC input channel 2)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-

ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When

the JTAG interface is enabled, this pin can not be used as an I/O pin.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5.

83

2467P–AVR–08/07

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is

enabled, this pin can not be used as an I/O pin.

• ADC3 – ADC0 – Port F, Bit 3..0

Analog to Digital Converter, Channel 3..0.

Table 43. Overriding Signals for Alternate Functions in PF7..PF4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PF7/ADC7/TDI

PF6/ADC6/TDO

JTAGEN

0

PF5/ADC5/TMS

PF4/ADC4/TCK

JTAGEN

1

JTAGEN

0

JTAGEN

0

JTAGEN

0

SHIFT_IR +

SHIFT_DR

PVOE

PVOV

DIEOE

DIEOV

DI

0

JTAGEN

0

TDO

0

JTAGEN

0

–

0

–

0

–

0

–

AIO

TDI/ADC7 INPUT ADC6 INPUT

TMS/ADC5

INPUT

TCKADC4 INPUT

Table 44. Overriding Signals for Alternate Functions in PF3..PF0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PF3/ADC3

PF2/ADC2

PF1/ADC1

PF0/ADC0

0

–

AIO

ADC3 INPUT

ADC2 INPUT

ADC1 INPUT

ADC0 INPUT

84

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Alternate Functions of In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and

Port G

Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows:

Table 45. Port G Pins Alternate Functions

Port Pin

PG4

Alternate Function

TOSC1 (RTC Oscillator Timer/Counter0)

TOSC2 (RTC Oscillator Timer/Counter0)

ALE (Address Latch Enable to external memory)

RD (Read strobe to external memory)

WR (Write strobe to external memory)

PG3

PG2

PG1

PG0

• TOSC1 – Port G, Bit 4

TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous

clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the input of the

inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the

pin can not be used as an I/O pin.

• TOSC2 – Port G, Bit 3

TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous

clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the inverting

output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and

the pin can not be used as an I/O pin.

• ALE – Port G, Bit 2

ALE is the external data memory Address Latch Enable signal.

• RD – Port G, Bit 1

RD is the external data memory read control strobe.

• WR – Port G, Bit 0

WR is the external data memory write control strobe.

Table 46 and Table 47 relates the alternate functions of Port G to the overriding signals shown in

Figure 33 on page 71.

Table 46. Overriding Signals for Alternate Functions in PG4..PG1

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PG4/TOSC1

PG3/TOSC2

PG2/ALE

PG1/RD

AS0

SRE

0

SRE

0

AS0

SRE

1

SRE

1

0

SRE

ALE

0

SRE

RD

0

AS0

0

–

AIO

T/C0 OSC INPUT

T/C0 OSC OUTPUT

–

85

2467P–AVR–08/07

Table 47. Overriding Signals for Alternate Functions in PG0

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

DI

PG0/WR

SRE

0

SRE

1

SRE

WR

0

–

AIO

–

86

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Register

Description for I/O

Ports

Port A Data Register –

PORTA

Bit

7

PORTA7

R/W

0

6

PORTA6

R/W

0

5

PORTA5

R/W

0

4

PORTA4

R/W

0

3

PORTA3

R/W

0

2

PORTA2

R/W

0

1

0

PORTA1

R/W

0

PORTA0

R/W

0

PORTA

DDRA

PINA

Read/Write

Initial Value

Port A Data Direction

Register – DDRA

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

Read/Write

Initial Value

Port A Input Pins

Address – PINA

Bit

7

6

PINA6

R

5

PINA5

R

4

PINA4

R

3

PINA3

R

2

PINA2

R

1

PINA1

R

0

PINA0

R

PINA7

R

Read/Write

Initial Value

N/A

Port B Data Register –

PORTB

Bit

7

PORTB7

R/W

0

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB

DDRB

PINB

Read/Write

Initial Value

Port B Data Direction

Register – DDRB

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

Read/Write

Initial Value

Port B Input Pins

Address – PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

Read/Write

Initial Value

N/A

Port C Data Register –

PORTC

Bit

7

PORTC7

R/W

0

6

PORTC6

R/W

0

5

PORTC5

R/W

0

4

PORTC4

R/W

0

3

PORTC3

R/W

0

2

PORTC2

R/W

0

1

PORTC1

R/W

0

PORTC0

R/W

0

PORTC

Read/Write

Initial Value

Port C Data Direction

Register – DDRC

Bit

7

DDC7

R/W

0

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

DDRC

Read/Write

Initial Value

87

2467P–AVR–08/07

Port C Input Pins

Address – PINC

Bit

7

PINC7

R

6

PINC6

R

5

PINC5

R

4

PINC4

R

3

PINC3

R

2

PINC2

R

1

PINC1

R

0

PINC0

R

PINC

Read/Write

Initial Value

N/A

In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-Pull

Zero Output. The port pins assumes their initial value, even if the clock is not running. Note that

the DDRC and PINC Registers are available in ATmega103 compatibility mode, and should not

be used for 100% back-ward compatibility.

Port D Data Register –

PORTD

Bit

7

PORTD7

R/W

0

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

Read/Write

Initial Value

Port D Data Direction

Register – DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

Read/Write

Initial Value

Port D Input Pins

Address – PIND

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

Read/Write

Initial Value

N/A

Port E Data Register –

PORTE

Bit

7

PORTE7

R/W

0

6

PORTE6

R/W

0

5

PORTE5

R/W

0

4

PORTE4

R/W

0

3

PORTE3

R/W

0

2

PORTE2

R/W

0

1

PORTE1

R/W

0

PORTE0

R/W

0

PORTE

DDRE

PINF

Read/Write

Initial Value

Port E Data Direction

Register – DDRE

Bit

7

DDE7

R/W

0

6

DDE6

R/W

0

5

DDE5

R/W

0

4

DDE4

R/W

0

3

DDE3

R/W

0

2

DDE2

R/W

0

1

DDE1

R/W

0

DDE0

R/W

0

Read/Write

Initial Value

Port E Input Pins

Address – PINE

Bit

7

PINE7

R

6

PINE6

R

5

PINE5

R

4

PINE4

R

3

PINE3

R

2

PINE2

R

1

PINE1

R

0

PINE0

R

Read/Write

Initial Value

N/A

Port F Data Register –

PORTF

Bit

7

PORTF7

R/W

0

6

PORTF6

R/W

0

5

PORTF5

R/W

0

4

PORTF4

R/W

0

3

PORTF3

R/W

0

2

PORTF2

R/W

0

1

PORTF1

R/W

0

PORTF0

R/W

0

PORTF

Read/Write

Initial Value

88

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Port F Data Direction

Register – DDRF

Bit

7

DDF7

R/W

0

6

DDF6

R/W

0

5

DDF5

R/W

0

4

DDF4

R/W

0

3

DDF3

R/W

0

2

DDF2

R/W

0

1

0

DDF1

R/W

0

DDF0

R/W

0

DDRF

Read/Write

Initial Value

Port F Input Pins

Address – PINF

Bit

7

PINF7

R

6

PINF6

R

5

PINF5

R

4

PINF4

R

3

PINF3

R

2

PINF2

R

1

PINF1

R

0

PINF0

R

PINF

Read/Write

Initial Value

N/A

Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode

where Port F serves as digital input only.

Port G Data Register –

PORTG

Bit

7

–

6

–

5

–

4

PORTG4

R/W

0

3

PORTG3

R/W

0

2

PORTG2

R/W

0

1

PORTG1

R/W

0

PORTG0

R/W

0

PORTG

DDRG

PING

Read/Write

Initial Value

R

0

R

0

R

0

Port G Data Direction

Register – DDRG

Bit

7

–

6

–

5

–

4

DDG4

R/W

0

3

DDG3

R/W

0

2

DDG2

R/W

0

1

DDG1

R/W

0

DDG0

R/W

0

Read/Write

Initial Value

R

0

R

0

R

0

Port G Input Pins

Address – PING

Bit

7

–

6

–

5

–

4

PING4

R

3

PING3

R

2

PING2

R

1

PING1

R

0

PING0

R

Read/Write

Initial Value

R

0

R

0

R

0

N/A

Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the

ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR,

RD and ALE).

89

2467P–AVR–08/07

External

Interrupts

The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts

will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen-

erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or

a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-

isters – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is

configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that

recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock,

described in “Clock Systems and their Distribution” on page 36. Low level interrupts and the

edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. This makes the MCU less sensitive to

noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the

Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-

tor is voltage dependent as shown in the “Electrical Characteristics” on page 318. The MCU will

wake up if the input has the required level during this sampling or if it is held until the end of the

start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and

their Distribution” on page 36. If the level is sampled twice by the Watchdog Oscillator clock but

disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be

generated. The required level must be held long enough for the MCU to complete the wake up to

trigger the level interrupt.

External Interrupt

Control Register A –

EICRA

Bit

7

ISC31

R/W

0

6

ISC30

R/W

0

5

ISC21

R/W

0

4

ISC20

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

EICRA

Read/Write

Initial Value

This Register can not be reached in ATmega103 compatibility mode, but the initial value defines

INT3:0 as low level interrupts, as in ATmega103.

• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 48. Edges on INT3..INT0 are registered asynchro-

nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 49 will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-

rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.

Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the

EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be

cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the

interrupt is re-enabled.

Table 48. Interrupt Sense Control⁽¹⁾

ISCn1

ISCn0 Description

The low level of INTn generates an interrupt request.

0

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Table 48. Interrupt Sense Control⁽¹⁾

ISCn1

ISCn0 Description

0

1

0

1

Reserved

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 49. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min

Minimum pulse width for

Typ

Max

Units

t_INT

50

ns

asynchronous external interrupt

External Interrupt

Control Register B –

EICRB

Bit

7

ISC71

R/W

0

6

ISC70

R/W

0

5

ISC61

R/W

0

4

ISC60

R/W

0

3

ISC51

R/W

0

2

ISC50

R/W

0

1

0

ISC41

R/W

0

ISC40

R/W

0

EICRB

Read/Write

Initial Value

• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 50. The value on the INT7:4 pins are sampled before

detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock

period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.

Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is

enabled. If low level interrupt is selected, the low level must be held until the completion of the

currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will

generate an interrupt request as long as the pin is held low.

Table 50. Interrupt Sense Control⁽¹⁾

ISCn1 ISCn0 Description

0

1

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request

The falling edge between two samples of INTn generates an interrupt

request.

1

0

The rising edge between two samples of INTn generates an interrupt

request.

1

Note:

1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

External Interrupt

Mask Register –

EIMSK

Bit

7

6

5

4

3

2

1

0

IINT0

R/W

0

INT7

R/W

0

INT6

R/W

0

INT5

R/W

0

INT4

R/W

0

INT3

R/W

0

INT2

R/W

0

INT1

R/W

0

EIMSK

Read/Write

Initial Value

• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable

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When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set

(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the

External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-

rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger

an interrupt request even if the pin is enabled as an output. This provides a way of generating a

software interrupt.

External Interrupt Flag

Register – EIFR

Bit

7

INTF7

R/W

0

6

INTF6

R/W

0

5

INTF5

R/W

0

4

INTF4

R/W

0

3

INTF3

R/W

0

2

INTF2

R/W

0

1

INTF1

R/W

0

IINTF0

R/W

0

EIFR

Read/Write

Initial Value

• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep

mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input

Enable and Sleep Modes” on page 70 for more information.

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8-bit

Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main

features are:

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Timer/Counter0

with PWM and

Asynchronous

Operation

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34. For the actual place-

ment of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O registers, including

I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are

listed in the “8-bit Timer/Counter Register Description” on page 104.

Figure 34. 8-bit Timer/Counter Block Diagram

TCCRn

count

clear

TOVn

(Int.Req.)

Control Logic

TOP

direction

clk_Tn

TOSC1

TOSC2

BOTTOM

T/C

Oscillator

Prescaler

Timer/Counter

TCNTn

= 0

= 0xFF

clk _I/O

OCn

(Int.Req.)

Waveform

Generation

=

OCRn

clk _I/O

Synchronized Status flags

Synchronization Unit

clk _ASY

Status flags

ASSRn

asynchronous mode

select (ASn)

Registers

The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt

request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and

TIMSK are not shown in the figure since these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

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tive when no clock source is selected. The output from the clock select logic is referred to as the

timer clock (clk_T0).

The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the waveform generator to generate

a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare

Unit” on page 95. for details. The compare match event will also set the compare flag (OCF0)

which can be used to generate an output compare interrupt request.

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. However, when using the register or bit

defines in a program, the precise form must be used (i.e., TCNT0 for accessing Timer/Counter0

counter value and so on).

The definitions in Table 51 are also used extensively throughout the document.

Table 51. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The

assignment is dependent on the mode of operation.

Timer/Counter

Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk_T0is by default equal to the MCU clock, clk_I/O. When the AS0

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asyn-

chronous Status Register – ASSR” on page 107. For details on clock sources and prescaler, see

“Timer/Counter Prescaler” on page 110.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

35 shows a block diagram of the counter and its surrounding environment.

Figure 35. Counter Unit Block Diagram

DATA BUS

TOVn

(Int.Req.)

TOSC1

count

T/C

Oscillator

clk _Tn

clear

TCNTn

Control Logic

Prescaler

direction

TOSC2

clk

bottom

top

I/O

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Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

direction Selects between increment and decrement.

clear

clk_T0

top

Clear TCNT0 (set all bits to zero).

Timer/Counter clock.

Signalizes that TCNT0 has reached maximum value.

bottom

Signalizes that TCNT0 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the output compare output

OC0. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 98.

The Timer/Counter overflow (TOV0) flag is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

Output Compare

Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the

output compare flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the output

compare flag generates an output compare interrupt. The OCF0 flag is automatically cleared

when the interrupt is executed. Alternatively, the OCF0 flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The waveform generator uses the match signal to

generate an output according to operating mode set by the WGM01:0 bits and compare output

mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for han-

dling the special cases of the extreme values in some modes of operation (“Modes of Operation”

on page 98). Figure 36 shows a block diagram of the output compare unit.

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Figure 36. Output Compare Unit, Block Diagram

DATA BUS

OCRn

TCNTn

= (8-bit Comparator )

OCFn (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCxy

WGMn1:0

COMn1:0

The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0 Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0 buffer Register, and if double buffering is disabled

the CPU will access the OCR0 directly.

Force Output

Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0) bit. Forcing compare match will not set the

OCF0 flag or reload/clear the timer, but the OC0 pin will be updated as if a real compare match

had occurred (the COM01:0 bits settings define whether the OC0 pin is set, cleared or toggled).

Compare Match

Blocking by TCNT0

Write

All CPU write operations to the TCNT0 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0 to be initialized

to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output

Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the output compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0 value, the compare match will be missed, resulting in incorrect waveform gen-

eration. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0 should be performed before setting the Data Direction Register for the port

pin to output. The easiest way of setting the OC0 value is to use the force output compare

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(FOC0) strobe bit in normal mode. The OC0 Register keeps its value even when changing

between waveform generation modes.

Be aware that the COM01:0 bits are not double buffered together with the compare value.

Changing the COM01:0 bits will take effect immediately.

Compare Match

Output Unit

The Compare Output mode (COM01:0) bits have two functions. The waveform generator uses

the COM01:0 bits for defining the Output Compare (OC0) state at the next compare match. Also,

the COM01:0 bits control the OC0 pin output source. Figure 37 shows a simplified schematic of

the logic affected by the COM01:0 bit setting. The I/O registers, I/O bits, and I/O pins in the fig-

ure are shown in bold. Only the parts of the General I/O Port Control Registers (DDR and PORT)

that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference

is for the internal OC0 Register, not the OC0 pin.

Figure 37. Compare Match Output Unit, Schematic

COMn1

Waveform

Generator

COMn0

FOCn

D

Q

1

0

OCn

D

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the output compare (OC0) from the waveform

generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output)

is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-

ter bit for the OC0 pin (DDR_OC0) must be set as output before the OC0 value is visible on the

pin. The port override function is independent of the waveform generation mode.

The design of the output compare pin logic allows initialization of the OC0 state before the out-

put is enabled. Note that some COM01:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 104.

Compare Output Mode The waveform generator uses the COM01:0 bits differently in normal, CTC, and PWM modes.

and Waveform

Generation

For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no action on the OC0

Register is to be performed on the next compare match. For compare output actions in the non-

PWM modes refer to Table 53 on page 105. For fast PWM mode, refer to Table 54 on page 105,

and for phase correct PWM refer to Table 55 on page 106.

A change of the COM01:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0 strobe bits.

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Modes of

Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is

defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output

mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM01:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See “Compare Match Output Unit” on page 97.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102.

Normal Mode

The simplest mode of operation is the normal mode (WGM01:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter overflow flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 flag, the timer resolution can be increased by software. There

are no special cases to consider in the normal mode, a new counter value can be written

anytime.

The output compare unit can be used to generate interrupts at some given time. Using the out-

put compare to generate waveforms in normal mode is not recommended, since this will occupy

too much of the CPU time.

Clear Timer on

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manip-

Compare Match (CTC) ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value

Mode

(TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its

resolution. This mode allows greater control of the compare match output frequency. It also sim-

plifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 38. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0, and then counter (TCNT0)

is cleared.

Figure 38. CTC Mode, Timing Diagram

OCn Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMn1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the

TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0 is lower than the current

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value of TCNT0, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to Toggle mode

(COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the

pin is set to output. The waveform generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2

when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation:

f

clk_I/O

f

= ----------------------------------------------

OCn

2 ⋅ N ⋅ (1 + OCRn)

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the output compare (OC0) is cleared on the compare

match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the

output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagram shown as a histo-

gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0 and TCNT0.

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Figure 39. Fast PWM Mode, Timing Diagram

OCRn Interrupt Flag Set

OCRn Update

and

TOVn Interrupt Flag Set

TCNTn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter overflow flag (TOV0) is set each time the counter reaches Max If the interrupt

is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Set-

ting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM01:0 to 3 (See Table 54 on page 105). The actual OC0 value

will only be visible on the port pin if the data direction for the port pin is set as output. The PWM

waveform is generated by setting (or clearing) the OC0 Register at the compare match between

OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the

counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be

a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a

constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0 to toggle its logical level on each compare match (COM01:0 = 1). The waveform

generated will have a maximum frequency of f_oc0= f_{clk_I/O}/2 when OCR0 is set to zero. This fea-

ture is similar to the OC0 toggle in CTC mode, except the double buffer feature of the output

compare unit is enabled in the fast PWM mode.

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Phase Correct PWM

Mode

The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the output compare (OC0) is cleared on the compare match

between TCNT0 and OCR0 while counting up, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM

mode the counter is incremented until the counter value matches Max When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 40.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0.

Figure 40. Phase Correct PWM Mode, Timing Diagram

OCn Interrupt Flag Set

OCRn Update

TOVn Interrupt Flag Set

TCNTn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

OCn

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-

put can be generated by setting the COM01:0 to 3 (See Table 55 on page 106). The actual OC0

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match

between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0

Register at compare match between OCR0 and TCNT0 when the counter decrements. The

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PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

f

clk_I/O

f

= -----------------

OCnPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of Period 2 in Figure 40 OCn has a transition from high to low even though there

is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.

There are two cases that give a transition without Compare Match:

•

OCR0 changes its value from MAX, like in Figure 40. When the OCR0 value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

•

The timer starts counting from a higher value than the one in OCR0, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

Timer/Counter

Timing Diagrams

Figure 41 and Figure 42 contain timing data for the Timer/Counter operation. The Timer/Counter

is a synchronous design and the timer clock (clk_T0) is therefore shown as a clock enable signal.

The figure shows the count sequence close to the MAX value. Figure 43 and Figure 44 show the

same timing data, but with the prescaler enabled. The figures illustrate when interrupt flags are

set.

The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk_T0)

is therefore shown as a clock enable signal. In asynchronous mode, clk_I/Oshould be replaced by

the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are

set. Figure 41 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 41. Timer/Counter Timing Diagram, No Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 42 shows the same timing data, but with the prescaler enabled.

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Figure 42. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 43 shows the setting of OCF0 in all modes except CTC mode.

Figure 43. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRn

OCFn

OCRn - 1

OCRn

OCRn + 1

OCRn + 2

OCRn Value

Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

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Figure 44. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRn

TOP

OCFn

8-bit

Timer/Counter

Register

Description

Timer/Counter Control

Register – TCCR0

Bit

7

FOC0

W

6

5

4

COM00

R/W

0

3

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

WGM00

R/W

0

COM01

R/W

0

WGM01

R/W

0

TCCR0

Read/Write

Initial Value

0

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-

ing compatibility with future devices, this bit must be set to zero when TCCR0 is written when

operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare

match is forced on the waveform generation unit. The OC0 output is changed according to its

COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the

value present in the COM01:0 bits that determines the effect of the forced compare.

A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0 as TOP.

The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 52 and “Modes of Operation” on

page 98.

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Table 52. Waveform Generation Mode Bit Description

WGM01⁽¹⁾WGM00⁽¹⁾Timer/Counter

Update of

TOV0 Flag

Set on

Mode

(CTC0)

(PWM0)

Mode of Operation TOP

OCR0 at

Immediate

TOP

0

1

0

1

Normal

0xFF

MAX

PWM, Phase

Correct

BOTTOM

2

3

1

0

1

CTC

OCR0 Immediate

0xFF BOTTOM

MAX

Fast PWM

Note:

1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM01:0: Compare Match Output Mode

These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits

are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.

However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set

in order to enable the output driver.

When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0

bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a

normal or CTC mode (non-PWM).

Table 53. Compare Output Mode, non-PWM Mode

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0 disconnected.

Toggle OC0 on compare match

Clear OC0 on compare match

Set OC0 on compare match

Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 54. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM01

COM00

Description

0

1

0

1

0

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on compare match, set OC0 at BOTTOM,

(non-inverting mode)

1

Set OC0 on compare match, clear OC0 at BOTTOM,

(inverting mode)

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare

match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 99

for more details.

Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct

PWM mode.

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Table 55. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM01 COM00 Description

0

1

0

1

0

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on compare match when up-counting. Set OC0 on compare

match when downcounting.

1

Set OC0 on compare match when up-counting. Clear OC0 on compare

match when downcounting.

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

101 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter, see Table

56.

Table 56. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_T0S/(No prescaling)

clk_T0S/8 (From prescaler)

clk_T0S/32 (From prescaler)

clk_T0S/64 (From prescaler)

clk_T0S/128 (From prescaler)

clk_{T S}/256 (From prescaler)

0

clk_{T S}/1024 (From prescaler)

0

Timer/Counter

Register – TCNT0

Bit

7

6

5

4

3

2

1

0

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.

Output Compare

Register – OCR0

Bit

7

6

5

4

3

2

1

0

OCR0[7:0]

OCR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an output compare interrupt, or to

generate a waveform output on the OC0 pin.

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Asynchronous

Operation of the

Timer/Counter

Asynchronous Status

Register – ASSR

Bit

7

–

6

–

5

–

4

–

3

2

1

0

AS0

R/W

0

TCN0UB

OCR0UB

TCR0UB

ASSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 3 – AS0: Asynchronous Timer/Counter0

When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clk_I/O. When AS0 is

written to one, Timer/Counter is clocked from a crystal Oscillator connected to the Timer Oscilla-

tor 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and

TCCR0 might be corrupted.

• Bit 2 – TCN0UB: Timer/Counter0 Update Busy

When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.

When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.

• Bit 1 – OCR0UB: Output Compare Register0 Update Busy

When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set.

When OCR0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.

• Bit 0 – TCR0UB: Timer/Counter Control Register0 Update Busy

When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set.

When TCCR0 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value.

If a write is performed to any of the three Timer/Counter0 Registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0,

the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary stor-

age register is read.

Asynchronous

Operation of

Timer/Counter0

When Timer/Counter0 operates asynchronously, some considerations must be taken.

•

Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter0, the Timer Registers TCNT0, OCR0, and TCCR0 might be corrupted. A

safe procedure for switching clock source is:

1. Disable the Timer/Counter0 interrupts by clearing OCIE0 and TOIE0.

2. Select clock source by setting AS0 as appropriate.

3. Write new values to TCNT0, OCR0, and TCCR0.

4. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.

5. Clear the Timer/Counter0 interrupt flags.

6. Enable interrupts, if needed.

•

The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external

clock to the TOSC1 pin may result in incorrect Timer/Counter0 operation. The CPU main

clock frequency must be more than four times the Oscillator frequency.

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•

When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not

write a new value before the contents of the Temporary Register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means that e.g., writing to TCNT0 does not disturb an OCR0 write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

Register – ASSR has been implemented.

When entering Power-save or Extended Standby mode after having written to TCNT0,

OCR0, or TCCR0, the user must wait until the written register has been updated if

Timer/Counter0 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare0

interrupt is used to wake up the device, since the output compare function is disabled during

writing to OCR0 or TCNT0. If the write cycle is not finished, and the MCU enters sleep mode

before the OCR0UB bit returns to zero, the device will never receive a compare match

interrupt, and the MCU will not wake up.

•

If Timer/Counter0 is used to wake the device up from Power-save or Extended Standby

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-

entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the

device will fail to wake up. If the user is in doubt whether the time before re-entering Power-

save or Extended Standby mode is sufficient, the following algorithm can be used to ensure

that one TOSC1 cycle has elapsed:

1. Write a value to TCCR0, TCNT0, or OCR0.

2. Wait until the corresponding Update Busy flag in ASSR returns to zero.

3. Enter Power-save or Extended Standby mode.

•

When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter0

is always running, except in Power-down and Standby modes. After a Power-up Reset or

wake-up from Power-down or Standby mode, the user should be aware of the fact that this

Oscillator might take as long as one second to stabilize. The user is advised to wait for at

least one second before using Timer/Counter0 after power-up or wake-up from Power-down

or Standby mode. The contents of all Timer/Counter0 Registers must be considered lost

after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-

up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

•

Description of wake up from Power-save or Extended Standby mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction

following SLEEP.

Reading of the TCNT0 Register shortly after wake-up from Power-save may give an

incorrect result. Since TCNT0 is clocked on the asynchronous TOSC clock, reading TCNT0

must be done through a register synchronized to the internal I/O clock domain.

Synchronization takes place for every rising TOSC1 edge. When waking up from Power-

save mode, and the I/O clock (clk_I/O) again becomes active, TCNT0 will read as the previous

value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC

clock after waking up from Power-save mode is essentially unpredictable, as it depends on

the wake-up time. The recommended procedure for reading TCNT0 is thus as follows:

1. Write any value to either of the registers OCR0 or TCCR0.

2. Wait for the corresponding Update Busy Flag to be cleared.

3. Read TCNT0.

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•

During asynchronous operation, the synchronization of the interrupt flags for the

asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting

of the interrupt flag. The output compare pin is changed on the timer clock and is not

synchronized to the processor clock.

Timer/Counter

Interrupt Mask

Register – TIMSK

Bit

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

1

OCIE0

R/W

0

TOIE0

R/W

0

TIMSK

Read/Write

Initial Value

• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

Timer/Counter

Interrupt Flag Register

– TIFR

Bit

7

OCF2

R/W

0

6

TOV2

R/W

0

5

4

OCF1A

R/W

0

3

OCF1B

R/W

0

2

TOV1

R/W

0

1

OCF0

R/W

0

TOV0

R/W

0

ICF1

R/W

0

TIFR

Read/Write

Initial Value

• Bit 1 – OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the

data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and

OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed. In

PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.

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Timer/Counter Prescaler Figure 45. Prescaler for Timer/Counter0

clk_I/O

clk_T0S

10-BIT T/C PRESCALER

Clear

TOSC1

AS0

PSR0

0

CS00

CS01

CS02

TIMER/COUNTER0 CLOCK SOURCE

clk_T0

The clock source for Timer/Counter0 is named clk_T0. clk_T0is by default connected to the

main system clock clk_I/O. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro-

nously clocked from the TOSC1 pin. This enables use of Timer/Counter0 as a Real

Time Counter (RTC). When AS0 is set, pins TOSC1 and TOSC2 are disconnected from

Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve

as an independent clock source for Timer/Counter0. The Oscillator is optimized for use

with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not

recommended.

For Timer/Counter0, the possible prescaled selections are: clk_T0S/8, clk_T0S/32, clk_T0S/64,

clk_T0S/128, clk_T0S/256, and clk_T0S/1024. Additionally, clk_T0Sas well as 0 (stop) may be

selected. Setting the PSR0 bit in SFIOR resets the prescaler. This allows the user to

operate with a predictable prescaler.

Special Function IO Register –

SFIOR

Bit

7

6

–

5

–

4

–

3

ACME

R/W

0

2

1

PSR0

R/W

0

PSR321

R/W

0

TSM

R/W

0

PUD

R/W

0

SFIOR

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this

mode, the value that is written to the PSR0 and PSR321 bits is kept, hence keeping the

corresponding prescaler reset signals asserted. This ensures that the corresponding

Timer/Counters are halted and can be configured to the same value without the risk of

one of them advancing during configuration. When the TSM bit is written to zero, the

PSR0 and PSR321 bits are cleared by hardware, and the Timer/Counters start counting

simultaneously.

• Bit 1 – PSR0: Prescaler Reset Timer/Counter0

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ATmega128(L)

When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared

immediately by hardware. If this bit is written when Timer/Counter0 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set.

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16-bit

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. The main features are:

• True 16-bit Design (i.e.,Allows 16-bit PWM)

• Three Independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

Timer/Counter

(Timer/Counter

1 and

• Input Capture Noise Canceler

Timer/Counter3

)

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Ten Independent Interrupt Sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B,

OCF3C, and ICF3)

Restrictions in

ATmega103

Compatibility Mode

Note that in ATmega103 compatibility mode, only one 16-bit Timer/Counter is available

(Timer/Counter1). Also note that in ATmega103 compatibility mode, the Timer/Counter1 has two

Compare Registers (Compare A and Compare B) only.

Overview

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a program, the precise form must be

used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 46. For the actual

placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “16-bit Timer/Counter Register Description” on page 133.

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Figure 46. 16-bit Timer/Counter Block Diagram

Count

TOVx

(Int.Req.)

Clear

Control Logic

Direction

Clock Select

TCLK

Edge

Detector

Tx

TOP BOTTOM

( From Prescaler )

Timer/Counter

TCNTx

=

= 0

OCFxA

(Int.Req.)

Waveform

Generation

OCxA

OCxB

OCxC

=

OCRxA

OCFxB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRxB

OCFxC

(Int.Req.)

Waveform

Generation

=

OCRxC

( From Analog

Comparator Ouput )

ICFx (Int.Req.)

Edge

Detector

Noise

Canceler

ICRx

ICPx

TCCRxA

TCCRxB

TCCRxC

Note:

Refer to Figure 1 on page 2, Table 30 on page 74, and Table 39 on page 81 for Timer/Counter1

and 3 pin placement and description.

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-

ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 115. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the

Timer Interrupt Flag Register (TIFR) and Extended Timer Interrupt Flag Register (ETIFR). All

interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK) and Extended

Timer Interrupt Mask Register (ETIMSK). (E)TIFR and (E)TIMSK are not shown in the figure

since these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the clock select logic is referred to as the timer clock (clk ).

n

T

The double buffered Output Compare Registers (OCRnA/B/C) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the waveform gener-

ator to generate a PWM or variable frequency output on the Output Compare Pin (OCnA/B/C).

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See “Output Compare Units” on page 121.. The compare match event will also set the compare

match flag (OCFnA/B/C) which can be used to generate an output compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture Pin (ICPn) or on the Analog Comparator pins (See

“Analog Comparator” on page 227.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using

OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used

as an alternative, freeing the OCRnA to be used as PWM output.

Definitions

The following definitions are used extensively throughout the document:

Table 57. Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x0000.

MAX

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be one of the fixed values:

0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn

Register. The assignment is dependent of the mode of operation.

Compatibility

The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit

AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version

regarding:

•

All 16-bit Timer/Counter related I/O register address locations, including timer interrupt

registers.

•

Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.

Interrupt vectors.

The following control bits have changed name, but have same functionality and register location:

•

PWMn0 is changed to WGMn0.

PWMn1 is changed to WGMn1.

CTCn is changed to WGMn2.

The following registers are added to the 16-bit Timer/Counter:

•

Timer/Counter Control Register C (TCCRnC).

Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC.

The following bits are added to the 16-bit Timer/Counter Control Registers:

•

COM1C1:0 are added to TCCR1A.

FOCnA, FOCnB, and FOCnC are added in the new TCCRnC Register.

WGMn3 is added to TCCRnB.

Interrupt flag and mask bits for output compare unit C are added.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special

cases.

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Accessing 16-bit

Registers

The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU

via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write opera-

tions. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-

bit access. The same Temporary Register is shared between all 16-bit registers within each 16-

bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of

a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the

low byte written are both copied into the 16-bit register in the same clock cycle. When the low

byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the

Temporary Register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C

16-bit registers does not involve using the Temporary Register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit timer registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit

access.

Assembly Code Examples⁽¹⁾

...

; Set TCNTn to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNTnH,r17

outTCNTnL,r16

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

...

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNTn to 0x01FF */

TCNTn = 0x1FF;

/* Read TCNTn into i */

i = TCNTn;

...

Note:

1. See “About Code Examples” on page 9.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

the main code and the interrupt code update the temporary register, the main code must disable

the interrupts during the 16-bit access.

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The following code examples show how to do an atomic read of the TCNTn Register contents.

Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_ReadTCNTn:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNTn into r17:r16

in r16,TCNTnL

in r17,TCNTnH

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNTn( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Read TCNTn into i */

i = TCNTn;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. See “About Code Examples” on page 9.

The assembly code example returns the TCNTn value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNTn Register contents.

Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_WriteTCNTn:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNTn to r17:r16

outTCNTnH,r17

outTCNTnL,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

void TIM16_WriteTCNTn( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Set TCNTn to i */

TCNTn = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. See “About Code Examples” on page 9.

The assembly code example requires that the r17:r16 register pair contains the value to be

written to TCNTn.

Reusing the

Temporary High Byte

Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

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Timer/Counter

Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located

in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler,

see “Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 143.

Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 47 shows a block diagram of the counter and its surroundings.

Figure 47. Counter Unit Block Diagram

DATA BUS(8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Clear

Edge

Detector

Tn

TCNTnH (8-bit) TCNTnL (8-bit)

TCNTn (16-bit Counter)

clk_Tn

Control Logic

Direction

( From Prescaler )

TOP

BOTTOM

Signal description (internal signals):

Count

Increment or decrement TCNTn by 1.

Direction Select between increment and decrement.

Clear

Clear TCNTn (set all bits to zero).

Timer/Counter clock.

clk_T

n

TOP

Signalize that TCNTn has reached maximum value.

BOTTOM Signalize that TCNTn has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-

taining the upper 8 bits of the counter, and Counter Low (TCNTnL) containing the lower 8 bits.

The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNTnH I/O location, the CPU accesses the high byte Temporary Register

(TEMP). The Temporary Register is updated with the TCNTnH value when the TCNTnL is read,

and TCNTnH is updated with the Temporary Register value when TCNTnL is written. This

allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit

data bus. It is important to notice that there are special cases of writing to the TCNTn Register

when the counter is counting that will give unpredictable results. The special cases are

described in the sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each Timer Clock (clk ). The clk can be generated from an external or internal clock

n

T

source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 =

0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent

of whether clk_T_nis present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).

There are close connections between how the counter behaves (counts) and how waveforms

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are generated on the output compare outputs OCnx. For more details about advanced counting

sequences and waveform generation, see “Modes of Operation” on page 124.

The Timer/Counter Overflow (TOVn) flag is set according to the mode of operation selected by

the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.

Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the

Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle,

and other features of the signal applied. Alternatively the time-stamps can be used for creating a

log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 48. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded. The

small “n” in register and bit names indicates the Timer/Counter number.

Figure 48. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ACO*

ACIC*

ICNC

ICES

Analog

Comparator

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPn

Note:

The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not

Timer/Counter3.

When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively

on the analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at

the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn =

1), the Input Capture flag generates an Input Capture interrupt. The ICFn flag is automatically

cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by

writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low

byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied

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into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it

will access the TEMP Register.

The ICRn Register can only be written when using a Waveform Generation mode that utilizes

the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera-

tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn

Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location

before the low byte is written to ICRnL.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 115.

Input Capture Pin

Source

The main trigger source for the Input Capture unit is the Input Capture Pin (ICPn).

Timer/Counter1 can alternatively use the analog comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the analog

Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture flag

must therefore be cleared after the change.

Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the Tn pin (Figure 59 on page 143). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICRn to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICPn pin.

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in

Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICRn Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

Using the Input

Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICRn Register before the next event occurs, the ICRn will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICRn

Register has been read. After a change of the edge, the Input Capture flag (ICFn) must be

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICFn flag is not required (if an interrupt handler is used).

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Output Compare

Units

The 16-bit comparator continuously compares TCNTn with the Output Compare Register

(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output

Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the output com-

pare flag generates an output compare interrupt. The OCFnx flag is automatically cleared when

the interrupt is executed. Alternatively the OCFnx flag can be cleared by software by writing a

logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an

output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and

Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the wave-

form generator for handling the special cases of the extreme values in some modes of operation

(See “Modes of Operation” on page 124.)

A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the waveform generator.

Figure 49 shows a block diagram of the output compare unit. The small “n” in the register and bit

names indicates the device number (n = n for Timer/Counter n), and the “x” indicates output

compare unit (A/B/C). The elements of the block diagram that are not directly a part of the output

compare unit are gray shaded.

Figure 49. Output Compare Unit, Block Diagram

DATABUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit) TCNTnL (8-bit)

TCNTn (16-bit Counter)

OCRnx Buffer (16-bit Register)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

=

(16-bit Comparator )

OCFnx (Int.Req.)

TOP

OCnx

Waveform Generator

BOTTOM

WGMn3:0

COMnx1:0

The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare

Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

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The OCRnx Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCRnx buffer register, and if double buffering is disabled

the CPU will access the OCRnx directly. The content of the OCR1x (buffer or compare) register

is only changed by a write operation (the Timer/Counter does not update this register automati-

cally as the TCNTn- and ICRn Register). Therefore OCRnx is not read via the high byte

Temporary Register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCRnx registers must be done via the TEMP Regis-

ter since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCRnxL) is written to the lower 8 bits, the

high byte will be copied into the upper 8 bits of either the OCRnx buffer or OCRnx Compare

Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 115.

Force Output

Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the

OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare

match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or

toggled).

Compare Match

Blocking by TCNTn

Write

All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the

same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.

Using the Output

Compare Unit

Since writing TCNTn in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNTn when using any of the output compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting.

The setup of the OCnx should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OCnx value is to use the force output compare

(FOCnx) strobe bits in normal mode. The OCnx Register keeps its value even when changing

between waveform generation modes.

Be aware that the COMnx1:0 bits are not double buffered together with the compare value.

Changing the COMnx1:0 bits will take effect immediately.

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Compare Match

Output Unit

The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses

the COMnx1:0 bits for defining the output compare (OCnx) state at the next compare match.

Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 50 shows a simplified

schematic of the logic affected by the COMnx1:0 bit setting. The I/O registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR

and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx

state, the reference is for the internal OCnx Register, not the OCnx pin. If a system Reset occur,

the OCnx Register is reset to “0”.

Figure 50. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the output compare (OCnx) from the Waveform

Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The data direction

register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible

on the pin. The port override function is generally independent of the waveform generation

mode, but there are some exceptions. Refer to Table 58, Table 59 and Table 60 for details.

The design of the output compare pin logic allows initialization of the OCnx state before the out-

put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of

operation. See “16-bit Timer/Counter Register Description” on page 133.

The COMnx1:0 bits have no effect on the Input Capture unit.

Compare Output Mode The waveform generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.

and Waveform

Generation

For all modes, setting the COMnx1:0 = 0 tells the waveform generator that no action on the

OCnx Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 58 on page 133. For fast PWM mode refer to Table 59 on page

134, and for phase correct and phase and frequency correct PWM refer to Table 60 on page

134.

A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOCnx strobe bits.

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Modes of

Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is

defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output

mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the waveform generation mode bits do. The COMnx1:0 bits control whether the PWM

output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM

modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a

compare match (See “Compare Match Output Unit” on page 123.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 131.

Normal Mode

The simplest mode of operation is the normal mode (WGMn3:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in

the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOVn flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The output compare units can be used to generate interrupts at some given time. Using the out-

put compare to generate waveforms in normal mode is not recommended, since this will occupy

too much of the CPU time.

Clear Timer on

In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register

Compare Match (CTC) are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

Mode

the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =

12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

The timing diagram for the CTC mode is shown in Figure 51. The counter value (TCNTn)

increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn)

is cleared.

Figure 51. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

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An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,

changing the TOP to a value close to BOTTOM when the counter is running with none or a low

prescaler value must be done with care since the CTC mode does not have the double buffering

feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the

counter will miss the compare match. The counter will then have to count to its maximum value

(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many

cases this feature is not desirable. An alternative will then be to use the fast PWM mode using

OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.

For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical

level on each compare match by setting the compare output mode bits to toggle mode

(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre-

quency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero (0x0000). The waveform frequency is

n

defined by the following equation:

f

clk_I/O

f

= --------------------------------------------------

OCnA

2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the normal mode of operation, the TOVn flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the output compare (OCnx) is cleared

on the compare match between TCNTn and OCRnx, and setat BOTTOM. In inverting compare

output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope

operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-

rect and phase and frequency correct PWM modes that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or

OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max-

imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

FPWM

log(2)

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =

14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 52. The figure shows

fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing

diagram shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes

represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set

when a compare match occurs.

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Figure 52. Fast PWM Mode, Timing Diagram

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition

the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or

ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the compare registers. If the TOP value is lower than any of the com-

pare registers, a compare match will never occur between the TCNTn and the OCRnx. Note that

when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Reg-

isters are written.

The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP

value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICRn value written is lower than the current value of TCNTn. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location

to be written anytime. When the OCRnA I/O location is written the value written will be put into

the OCRnA buffer Register. The OCRnA Compare Register will then be updated with the value

in the buffer register at the next timer clock cycle the TCNTn matches TOP. The update is done

at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.

Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COMnx1:0 to 3 (See Table 59 on page 134). The actual OCnx

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at

the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

126

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ----------------------------------

OCnxPWM

N ⋅ (1 + TOP)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COMnx1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only

if OCRnA is used to define the TOP value (WGMn3:0 = 15). The waveform generated will have

a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCRnA is set to zero (0x0000). This feature is

n

similar to the OCnA toggle in CTC mode, except the double buffer feature of the output compare

unit is enabled in the fast PWM mode.

Phase Correct PWM

Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting compare output mode, the output compare (OCnx) is cleared

on the compare match between TCNTn and OCRnx while counting up, and set on the compare

match while downcounting. In inverting Output Compare mode, the operation is inverted. The

dual-slope operation has lower maximum operation frequency than single slope operation. How-

ever, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for

motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set to

0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

PCPWM

log(2)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn

(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 53. The figure

shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter-

rupt flag will be set when a compare match occurs.

127

2467P–AVR–08/07

Figure 53. Phase Correct PWM Mode, Timing Diagram

OCRnx / TOP Update

and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When

either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accord-

ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer

value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the compare registers. If the TOP value is lower than any of the com-

pare registers, a compare match will never occur between the TCNTn and the OCRnx. Note that

when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Reg-

isters are written. As the third period shown in Figure 53 illustrates, changing the TOP actively

while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical

output. The reason for this can be found in the time of update of the OCRnx Register. Since the

OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the

length of the falling slope is determined by the previous TOP value, while the length of the rising

slope is determined by the new TOP value. When these two values differ the two slopes of the

period will differ in length. The difference in length gives the unsymmetrical result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COMnx1:0 to 3 (See Table 60 on page 134). The

actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as

output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis-

ter at the compare match between OCRnx and TCNTn when the counter increments, and

clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when

128

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCRnx Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

If OCnA is used to define the TOP value (WGMn3:0 = 11) and COMnA1:0 = 1, the OCnA Output

will toggle with a 50% duty cycle.

Phase and Frequency The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

Correct PWM Mode

mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

output compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while

counting up, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCRnx Register is updated by the OCRnx buffer Register, (see Figure 53

and Figure 54).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and

the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can

be calculated using the following equation:

log(TOP + 1)

R

= ----------------------------------

PFCPWM

log(2)

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNTn value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 54. The figure shows phase and frequency correct PWM

mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram

shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a

compare match occurs.

129

2467P–AVR–08/07

Figure 54. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx / TOP Update

and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx

Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn

is used for defining the TOP value, the OCnA or ICFn flag set when TCNTn has reached TOP.

The interrupt flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the compare registers. If the TOP value is lower than any of the com-

pare registers, a compare match will never occur between the TCNTn and the OCRnx.

As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical

in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and

the falling slopes will always be equal. This gives symmetrical output pulses and is therefore fre-

quency correct.

Using the ICRn Register for defining TOP works well when using fixed TOP values. By using

ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM

waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM

and an inverted PWM output can be generated by setting the COMnx1:0 to 3 (See Table 60 on

page 134). The actual OCnx value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)

the OCnx Register at the compare match between OCRnx and TCNTn when the counter

increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and

TCNTn when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPFCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

130

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

The extreme values for the OCRnx Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA Output

will toggle with a 50% duty cycle.

Timer/Counter

Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_Tn) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for

modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx.

Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 56 shows the same timing data, but with the prescaler enabled.

Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

131

2467P–AVR–08/07

Figure 57 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOVn flag at BOTTOM.

Figure 57. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

Figure 58 shows the same timing data, but with the prescaler enabled.

Figure 58. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

132

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

16-bit

Timer/Counter

Register

Description

Timer/Counter1

Control Register A –

TCCR1A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

COM1C1

R/W

2

COM1C0

R/W

1

0

WGM11

R/W

0

WGM10

R/W

0

TCCR1A

Read/Write

Initial Value

0

Timer/Counter3

Control Register A –

TCCR3A

Bit

7

COM3A1

R/W

6

COM3A0

R/W

5

COM3B1

R/W

4

COM3B0

R/W

3

COM3C1

R/W

2

COM3C0

R/W

1

WGM31

R/W

0

WGM30

R/W

0

TCCR3A

Read/Write

Initial Value

0

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A

• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B

• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C

The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,

and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the

OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or

both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-

tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,

the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-

ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or

OCnC pin must be set in order to enable the output driver.

When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is

dependent of the WGMn3:0 bits setting. Table 58 shows the COMnx1:0 bit functionality when

the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).

Table 58. Compare Output Mode, non-PWM

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

0

1

0

1

0

1

Normal port operation, OCnA/OCnB/OCnC

disconnected.

Toggle OCnA/OCnB/OCnC on compare

match.

Clear OCnA/OCnB/OCnC on compare

match (set output to low level).

Set OCnA/OCnB/OCnC on compare match

(set output to high level).

133

2467P–AVR–08/07

Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM

mode

Table 59. Compare Output Mode, Fast PWM

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

0

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

1

WGMn3:0 = 15: Toggle OCnA on Compare

Match, OCnB/OCnC disconnected (normal

port operation).

For all other WGMn settings, normal port

operation, OCnA/OCnB/OCnC

disconnected.

1

0

1

Clear OCnA/OCnB/OCnC on compare

match, set OCnA/OCnB/OCnC at BOTTOM,

(non-inverting mode)

Set OCnA/OCnB/OCnC on compare match,

clear OCnA/OCnB/OCnC at BOTTOM,

(inverting mode)

Note:

A

special

case

occurs

when

OCRnA/OCRnB/OCRnC

equals

TOP

and

COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear

is done at BOTTOM. See “Fast PWM Mode” on page 125. for more details.

Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor-

rect and frequency correct PWM mode.

Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

COMnA1/COMnB1/

COMnC1

COMnA0/COMnB0/

COMnC0

Description

0

Normal port operation, OCnA/OCnB/OCnC

disconnected.

0

1

WGMn3:0 = 9 or 11: Toggle OCnA on

Compare Match, OCnB/OCnC disconnected

(normal port operation).

For all other WGMn settings, normal port

operation, OCnA/OCnB/OCnC

disconnected.

1

0

1

Clear OCnA/OCnB/OCnC on compare

match when up-counting. Set

OCnA/OCnB/OCnC on compare match

when downcounting.

Set OCnA/OCnB/OCnC on compare match

when up-counting. Clear

OCnA/OCnB/OCnC on compare match

when downcounting.

Note:

A

special

case

occurs

when

OCRnA/OCRnB/OCRnC

equals

TOP

and

COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 127. for more

details.

134

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 61. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 124.)

Table 61. Waveform Generation Mode Bit Description

WGMn2

(CTCn)

WGMn1

(PWMn1) (PWMn0)

WGMn0

Timer/Counter Mode of

Operation⁽¹⁾

Update of

OCRnx at

TOVn Flag

Set on

Mode WGMn3

TOP

0

1

2

3

4

5

6

7

8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal

0xFFFF Immediate

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

0x00FF

0x01FF

0x03FF

OCRnA

0x00FF

0x01FF

0x03FF

TOP

BOTTOM

MAX

TOP

Immediate

BOTTOM

Fast PWM, 8-bit

TOP

Fast PWM, 9-bit

TOP

Fast PWM, 10-bit

TOP

PWM, Phase and Frequency

Correct

ICRn

BOTTOM

9

1

0

1

PWM, Phase and Frequency

Correct

OCRnA

10

11

12

13

14

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICRn

OCRnA

ICRn

–

TOP

BOTTOM

MAX

TOP

Immediate

–

(Reserved)

–

Fast PWM

ICRn

OCRnA

BOTTOM

TOP

15

Fast PWM

TOP

Note:

1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

135

2467P–AVR–08/07

Timer/Counter1

Control Register B –

TCCR1B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

–

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

TCCR1B

Read/Write

Initial Value

R

0

Timer/Counter3

Control Register B –

TCCR3B

Bit

7

ICNC3

R/W

0

6

ICES3

R/W

0

5

–

4

WGM33

R/W

0

3

WGM32

R/W

0

2

CS32

R/W

0

1

CS31

R/W

0

CS30

R/W

0

TCCR3B

Read/Write

Initial Value

R

0

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is

activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four

successive equal valued samples of the ICPn pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture

event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICESn setting, the counter value is copied into the

Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the

TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

• Bit 2:0 – CSn2:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter, see Figure

55 and Figure 56.

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ATmega128(L)

Table 62. Clock Select Bit Description

CSn2

CSn1

CSn0

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source. (Timer/Counter stopped)

clk_I/O/1 (No prescaling

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on Tn pin. Clock on falling edge

External clock source on Tn pin. Clock on rising edge

If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

Timer/Counter1

Control Register C –

TCCR1C

Bit

7

FOC1A

W

6

FOC1B

W

5

FOC1C

W

4

–

3

–

2

–

1

–

0

–

TCCR1C

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

Timer/Counter3

Control Register C –

TCCR3C

Bit

7

FOC3A

W

6

FOC3B

W

5

FOC3C

W

4

–

3

–

2

–

1

–

0

–

TCCR3C

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B

• Bit 5 – FOCnC: Force Output Compare for Channel C

The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare

match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed

according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-

mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the

effect of the forced compare.

A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare Match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB/FOCnB bits are always read as zero.

• Bit 4:0 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be written to zero when TCCRnC is written.

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Timer/Counter1 –

TCNT1H and TCNT1L

Bit

7

6

5

4

3

2

1

0

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Timer/Counter3 –

TCNT3H and TCNT3L

Bit

7

6

5

4

3

2

1

0

TCNT3[15:8]

TCNT3[7:0]

TCNT3H

TCNT3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This Temporary Register is shared by all the other 16-bit registers. See “Accessing 16-

bit Registers” on page 115.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-

pare match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock

for all compare units.

Output Compare

Register 1 A –

Bit

7

6

5

4

3

2

1

0

OCR1AH and OCR1AL

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Output Compare

Register 1 B –

Bit

7

6

5

4

3

2

1

0

OCR1BH and OCR1BL

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Output Compare

Register 1 C –

Bit

7

6

5

4

3

2

1

0

OCR1CH and OCR1CL

OCR1C[15:8]

OCR1C[7:0]

OCR1CH

OCR1CL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Output Compare

Register 3 A –

Bit

7

6

5

4

3

2

1

0

OCR3AH and OCR3AL

OCR3A[15:8]

OCR3A[7:0]

OCR3AH

OCR3AL

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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ATmega128(L)

Output Compare

Register 3 B –

Bit

7

6

5

4

3

2

1

0

OCR3BH and OCR3BL

OCR3B[15:8]

OCR3B[7:0]

OCR3BH

OCR3BL

R/W

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Output Compare

Register 3 C –

Bit

7

6

5

4

3

2

1

0

OCR3CH and OCR3CL

OCR3C[15:8]

OCR3C[7:0]

OCR3CH

OCR3CL

R/W

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNTn). A match can be used to generate an output compare interrupt, or to

generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This Temporary Register is shared by all the other

16-bit registers. See “Accessing 16-bit Registers” on page 115.

Input Capture Register

1 – ICR1H and ICR1L

Bit

7

6

5

4

3

2

1

0

ICR1[15:8]

ICR1[7:0]

ICR1H

ICR1L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Input Capture Register

3 – ICR3H and ICR3L

Bit

7

6

5

4

3

2

1

0

ICR3[15:8]

ICR3[7:0]

ICR3H

ICR3L

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the

ICPn pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Cap-

ture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This Temporary Register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 115.

Timer/Counter

Interrupt Mask

Register – TIMSK

Bit

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

1

OCIE0

R/W

0

TOIE0

R/W

0

TIMSK

Read/Write

Initial Value

Note:

This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are

described in this section. The remaining bits are described in their respective timer sections.

• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

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When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding interrupt

vector (See “Interrupts” on page 60.) is executed when the ICF1 flag, located in TIFR, is set.

• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF1A flag, located in TIFR,

is set.

• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF1B flag, located in TIFR,

is set.

• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding interrupt vector

(see “Interrupts” on page 60) is executed when the TOV1 flag, located in TIFR, is set.

Extended

Timer/Counter

Interrupt Mask

Register – ETIMSK

Bit

7

–

6

–

5

TICIE3

R/W

0

4

OCIE3A

R/W

0

3

OCIE3B

R/W

0

2

TOIE3

R/W

0

1

OCIE3C

R/W

0

OCIE1C

R/W

0

ETIMSK

Read/Write

Initial Value

R

0

R

0

Note:

This register is not available in ATmega103 compatibility mode.

• Bit 7:6 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be set to zero when ETIMSK is written.

• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Input Capture Interrupt is enabled. The corresponding interrupt

vector (see “Interrupts” on page 60) is executed when the ICF3 flag, located in ETIFR, is set.

• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare A Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF3A flag, located in

ETIFR, is set.

• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare B Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF3B flag, located in

ETIFR, is set.

• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding interrupt vector

(see “Interrupts” on page 60) is executed when the TOV3 flag, located in ETIFR, is set.

• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable

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ATmega128(L)

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter3 Output Compare C Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF3C flag, located in

ETIFR, is set.

• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare C Match Interrupt is enabled. The corresponding

interrupt vector (see “Interrupts” on page 60) is executed when the OCF1C flag, located in

ETIFR, is set.

Timer/Counter

Interrupt Flag Register

– TIFR

Bit

7

OCF2

R/W

0

6

TOV2

R/W

0

5

4

OCF1A

R/W

0

3

OCF1B

R/W

0

2

TOV1

R/W

0

1

OCF0

R/W

0

TOV0

R/W

0

ICF1

R/W

0

TIFR

Read/Write

Initial Value

Note:

This register contains flag bits for several Timer/Counters, but only timer 1 bits are described in

this section. The remaining bits are described in their respective timer sections.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set when the

counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.

OCF1A is automatically cleared when the Output Compare Match A interrupt vector is executed.

Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a forced output compare (FOC1B) strobe will not set the OCF1B flag.

OCF1B is automatically cleared when the Output Compare Match B interrupt vector is executed.

Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In normal and CTC modes, the

TOV1 flag is set when the timer overflows. Refer to Table 61 on page 135 for the TOV1 flag

behavior when using another WGMn3:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

Extended

Timer/Counter

Interrupt Flag Register

– ETIFR

Bit

7

–

6

–

5

4

3

2

1

0

ICF3

R/W

OCF3A

R/W

OCF3B

R/W

TOV3

R/W

OCF3C

R/W

OCF1C

R/W

ETIFR

Read/Write

R/W

141

2467P–AVR–08/07

Initial Value

0

• Bit 7:6 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be set to zero when ETIFR is written.

• Bit 5 – ICF3: Timer/Counter3, Input Capture Flag

This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register

(ICR3) is set by the WGM3:0 to be used as the TOP value, the ICF3 flag is set when the counter

reaches the TOP value.

ICF3 is automatically cleared when the Input Capture 3 interrupt vector is executed. Alterna-

tively, ICF3 can be cleared by writing a logic one to its bit location.

• Bit 4 – OCF3A: Timer/Counter3, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output

Compare Register A (OCR3A).

Note that a forced output compare (FOC3A) strobe will not set the OCF3A flag.

OCF3A is automatically cleared when the Output Compare Match 3 A interrupt vector is exe-

cuted. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.

• Bit 3 – OCF3B: Timer/Counter3, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output

Compare Register B (OCR3B).

Note that a forced output compare (FOC3B) strobe will not set the OCF3B flag.

OCF3B is automatically cleared when the Output Compare Match 3 B interrupt vector is exe-

cuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.

• Bit 2 – TOV3: Timer/Counter3, Overflow Flag

The setting of this flag is dependent of the WGM3:0 bits setting. In normal and CTC modes, the

TOV3 flag is set when the timer overflows. Refer to Table 52 on page 105 for the TOV3 flag

behavior when using another WGM3:0 bit setting.

TOV3 is automatically cleared when the Timer/Counter3 Overflow interrupt vector is executed.

Alternatively, TOV3 can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF3C: Timer/Counter3, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output

Compare Register C (OCR3C).

Note that a forced output compare (FOC3C) strobe will not set the OCF3C flag.

OCF3C is automatically cleared when the Output Compare Match 3 C interrupt vector is exe-

cuted. Alternatively, OCF3C can be cleared by writing a logic one to its bit location.

• Bit 0 – OCF1C: Timer/Counter1, Output Compare C Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register C (OCR1C).

Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag.

OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is exe-

cuted. Alternatively, OCF1C can be cleared by writing a logic one to its bit location.

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Timer/Counter3, Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler module, but

the Timer/Counters can have different prescaler settings. The description below applies to all of

the mentioned Timer/Counters.

Timer/Counter2,

and

Timer/Counter1

Prescalers

Internal Clock Source The Timer/Counter can be clocked directly by the System Clock (by setting the CSn2:0 = 1).

This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to

system clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used

as a clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64,

f_{CLK_I/O}/256, or f_{CLK_I/O}/1024.

Prescaler Reset

The prescaler is free running, i.e., operates independently of the clock select logic of the

Timer/Counter, and it is shared by Timer/Counter1, Timer/Counter2, and Timer/Counter3. Since

the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will

have implications for situations where a prescaled clock is used. One example of prescaling arti-

facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The

number of system clock cycles from when the timer is enabled to the first count occurs can be

from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is

connected to.

External Clock Source An external clock source applied to the Tn pin can be used as Timer/Counter clock

(clk_T1/clk_T2/clk_T3). The Tn pin is sampled once every system clock cycle by the pin synchroniza-

tion logic. The synchronized (sampled) signal is then passed through the edge detector. Figure

59 shows a functional equivalent block diagram of the Tn synchronization and edge detector

logic. The registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch

is transparent in the high period of the internal system clock.

The edge detector generates one clk /clk /clk ₃pulse for each positive (CSn2:0 = 7) or nega-

2

T1

T

tive (CSn2:0 = 6) edge it detects.

Figure 59. Tn Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

143

2467P–AVR–08/07

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3

CK

10-BIT T/C PRESCALER

Clear

PSR321

T3

T2

T1

0

CS30

CS31

CS32

CS20

CS21

CS22

CS10

CS11

CS12

TIMER/COUNTER3 CLOCK SOURCE

TIMER/COUNTER2 CLOCK SOURCE

TIMER/COUNTER1 CLOCK SOURCE

clk_T3

clk_T2

clk_T1

Note:

The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 59.

Special Function IO

Register – SFIOR

Bit

7

6

–

5

–

4

–

3

ACME

R/W

0

2

1

PSR0

R/W

0

PSR321

R/W

0

TSM

R/W

0

PUD

R/W

0

SFIOR

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding

prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted

and can be configured to the same value without the risk of one of them advancing during con-

figuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by

hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1

When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 prescaler will be

reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note

that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a

reset of this prescaler will affect all three timers.

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ATmega128(L)

8-bit

Timer/Counter2

with PWM

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main

features are:

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 61. For the actual place-

ment of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O registers, including

I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are

listed in the “8-bit Timer/Counter Register Description” on page 157.

Figure 61. 8-Bit Timer/Counter Block Diagram

TCCRn

count

TOVn

(Int.Req.)

clear

Control Logic

TOP

Clock Select

direction

clk

Tn

Edge

Detector

Tn

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

= 0

= 0xFF

OCn

(Int.Req.)

Waveform

Generation

OCn

=

OCRn

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt

request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag

Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other

timer units.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T2 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the clock select logic is referred to as the timer clock (clk_T2).

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The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the waveform generator to generate

a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare

Unit” on page 147. for details. The compare match event will also set the compare flag (OCF2)

which can be used to generate an output compare interrupt request.

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2

counter value and so on).

The definitions in Table 63 are also used extensively throughout the document.

Table 63. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX

TOP

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The

assignment is dependent on the mode of operation.

Timer/Counter

Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the clock select logic which is controlled by the clock select (CS22:0) bits located

in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see

“Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 143.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

62 shows a block diagram of the counter and its surroundings.

Figure 62. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

Edge

Detector

Tn

clk_Tn

clear

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count Increment or decrement TCNT2 by 1.

direction Select between increment and decrement.

clear

clk_Tn

top

Clear TCNT2 (set all bits to zero).

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT2 has reached maximum value.

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bottom

Signalize that TCNT2 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T2). clk_T2can be generated from an external or internal clock source,

selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk_T2is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR2). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the output compare output

OC2. For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 149.

The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by

the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

Output Compare

Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the

output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global inter-

rupt flag in SREG is set), the output compare flag generates an output compare interrupt. The

OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag

can be cleared by software by writing a logical one to its I/O bit location. The waveform genera-

tor uses the match signal to generate an output according to operating mode set by the

WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used

by the waveform generator for handling the special cases of the extreme values in some modes

of operation (see “Modes of Operation” on page 149). Figure 63 shows a block diagram of the

output compare unit.

Figure 63. Output Compare Unit, Block Diagram

DATA BUS

OCRn

TCNTn

= (8-bit Comparator )

OCFn (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCn

WGMn1:0

COMn1:0

The OCR2 Register is double buffered when using any of the pulse width modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

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ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2 Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR2 buffer Register, and if double buffering is disabled

the CPU will access the OCR2 directly.

Force Output

Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the force output compare (FOC2) bit. Forcing compare match will not set the

OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real compare match

had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).

Compare Match

Blocking by TCNT2

Write

All CPU write operations to the TCNT2 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized

to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output

Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the output compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2 value, the compare match will be missed, resulting in incorrect waveform gen-

eration. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC2 should be performed before setting the Data Direction Register for the port

pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare

(FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing

between waveform generation modes.

Be aware that the COM21:0 bits are not double buffered together with the compare value.

Changing the COM21:0 bits will take effect immediately.

Compare Match

Output Unit

The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses

the COM21:0 bits for defining the output compare (OC2) state at the next compare match. Also,

the COM21:0 bits control the OC2 pin output source. Figure 64 shows a simplified schematic of

the logic affected by the COM21:0 bit setting. The I/O registers, I/O bits, and I/O pins in the fig-

ure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT)

that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference

is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is

reset to “0”.

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Figure 64. Compare Match Output Unit, Schematic

COMn1

Waveform

Generator

COMn0

FOCn

D

Q

1

0

OCn

D

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the output compare (OC2) from the waveform

generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output)

is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-

ter bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the

pin. The port override function is independent of the Waveform Generation mode.

The design of the output compare pin logic allows initialization of the OC2 state before the out-

put is enabled. Note that some COM21:0 bit settings are reserved for certain modes of

operation. See “8-bit Timer/Counter Register Description” on page 157.

Compare Output Mode The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM modes.

and Waveform

Generation

For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2

Register is to be performed on the next compare match. For compare output actions in the non-

PWM modes refer to Table 65 on page 158. For fast PWM mode, refer to Table 66 on page 158,

and for phase correct PWM refer to Table 67 on page 158.

A change of the COM21:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2 strobe bits.

Modes of

Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output

mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM21:0 bits control whether the output should be set, cleared, or toggled at a compare

match (see “Compare Match Output Unit” on page 148).

For detailed timing information refer to Figure 68, Figure 69, Figure 70, and Figure 71 in

“Timer/Counter Timing Diagrams” on page 155.

Normal Mode

The simplest mode of operation is the normal mode (WGM21:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

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overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter overflow flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 flag, the timer resolution can be increased by software. There

are no special cases to consider in the normal mode, a new counter value can be written

anytime.

The output compare unit can be used to generate interrupts at some given time. Using the out-

put compare to generate waveforms in normal mode is not recommended, since this will occupy

too much of the CPU time.

Clear Timer on

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manip-

Compare Match (CTC) ulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value

Mode

(TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its

resolution. This mode allows greater control of the compare match output frequency. It also sim-

plifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 65. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2 and then counter (TCNT2)

is cleared.

Figure 65. CTC Mode, Timing Diagram

OCn Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMn1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the

TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR2 is lower than the current

value of TCNT2, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical

level on each compare match by setting the compare output mode bits to toggle mode

(COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the

pin is set to output. The waveform generated will have a maximum frequency of f_OC2= f_{clk_I/O}/2

when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation:

f

clk_I/O

f

= ----------------------------------------------

OCn

2 ⋅ N ⋅ (1 + OCRn)

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The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the output compare (OC2) is cleared on the compare

match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the

output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 66. The TCNT2 value is in the timing diagram shown as a histo-

gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted

PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2 and TCNT2.

Figure 66. Fast PWM Mode, Timing Diagram

OCRn Interrupt Flag Set

OCRn Update

and

TOVn Interrupt Flag Set

TCNTn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-

ting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM21:0 to 3 (see Table 66 on page 158). The actual OC2 value

will only be visible on the port pin if the data direction for the port pin is set as output. The PWM

waveform is generated by setting (or clearing) the OC2 Register at the compare match between

OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the

counter is cleared (changes from MAX to BOTTOM).

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The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR2 Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be

a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a

constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform

generated will have a maximum frequency of f_OC2= f_{clk_I/O}/2 when OCR2 is set to zero. This fea-

ture is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output

compare unit is enabled in the fast PWM mode.

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Phase Correct PWM

Mode

The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the output compare (OC2) is cleared on the compare match

between TCNT2 and OCR2 while counting up, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM

mode the counter is incremented until the counter value matches Max When the counter

reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 67.

The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.

Figure 67. Phase Correct PWM Mode, Timing Diagram

OCn Interrupt Flag Set

OCRn Update

TOVn Interrupt Flag Set

TCNTn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

OCn

1

2

3

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-

put can be generated by setting the COM21:0 to 3 (see Table 67 on page 158). The actual OC2

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC2 Register at the compare match

between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2

Register at compare match between OCR2 and TCNT2 when the counter decrements. The

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PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

f

clk_I/O

f

= -----------------

OCnPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of Period 2 in Figure 67 OCn has a transition from high to low even though there

is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.

There are two cases that give a transition without a Compare Match:

•

OCR2A changes its value from MAX, like in Figure 67. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

•

The timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

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Timer/Counter

Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T2) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set. Figure 68 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 68. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 69 shows the same timing data, but with the prescaler enabled.

Figure 69. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 70 shows the setting of OCF2 in all modes except CTC mode.

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Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRn

OCFn

OCRn - 1

OCRn

OCRn + 1

OCRn + 2

OCRn Value

Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.

Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRn

TOP

OCFn

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8-bit

Timer/Counter

Register

Description

Timer/Counter Control

Register – TCCR2

Bit

7

FOC2

W

6

WGM20

R/W

0

5

COM21

R/W

0

4

COM20

R/W

0

3

WGM21

R/W

0

2

CS22

R/W

0

1

CS21

R/W

0

CS20

R/W

0

TCCR2

Read/Write

Initial Value

0

• Bit 7 – FOC2: Force Output Compare

The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written

when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate com-

pare match is forced on the waveform generation unit. The OC2 output is changed according to

its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the

value present in the COM21:0 bits that determines the effect of the forced compare.

A FOC2 strobe will not generate any interrupt, nor will it clear the Timer in CTC mode using

OCR2 as TOP.

The FOC2 bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 64 and “Modes of Operation” on

page 149.

Table 64. Waveform Generation Mode Bit Description

WGM21 WGM20 Timer/Counter Mode

Update of TOV2 Flag

OCR2 at Set on

Mode

(CTC2)

(PWM2) of Operation

TOP

0xFF

0

1

2

3

0

1

0

1

0

1

Normal

Immediate MAX

TOP BOTTOM

PWM, Phase Correct

CTC

OCR2 Immediate MAX

0xFF BOTTOM MAX

Fast PWM

Note:

The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. How-

ever, the functionality and location of these bits are compatible with previous versions of the timer.

• Bit 5:4 – COM21:0: Compare Match Output Mode

These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits

are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.

However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be

set in order to enable the output driver.

When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0

bit setting. Table 65 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a

normal or CTC mode (non-PWM).

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Table 65. Compare Output Mode, Non-PWM Mode

COM21

COM20

Description

0

1

0

1

0

1

Normal port operation, OC2 disconnected.

Toggle OC2 on compare match

Clear OC2 on compare match

Set OC2 on compare match

Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Table 66. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM21

COM20

Description

0

1

0

1

0

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match, set OC2 at BOTTOM,

(non-inverting mode)

1

Set OC2 on compare match, clear OC2 at BOTTOM,

(inverting mode)

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 151

for more details.

Table 67 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct

PWM mode.

Table 67. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM21 COM20 Description

0

1

0

1

0

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match when up-counting. Set OC2 on compare

match when downcounting.

1

Set OC2 on compare match when up-counting. Clear OC2 on compare

match when downcounting.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

153 for more details.

• Bit 2:0 – CS22:0: Clock Select

The three clock select bits select the clock source to be used by the Timer/Counter.

Table 68. Clock Select Bit Description

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

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Table 68. Clock Select Bit Description

CS22

CS21

CS20

Description

1

0

1

0

1

clk_I/O/1024 (From prescaler)

External clock source on T2 pin. Clock on falling edge

External clock source on T2 pin. Clock on rising edge

If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

Timer/Counter

Register – TCNT2

Bit

7

6

5

4

3

2

1

0

TCNT2[7:0]

TCNT2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.

Output Compare

Register – OCR2

Bit

7

6

5

4

3

2

1

0

OCR2[7:0]

OCR2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an output compare interrupt, or to

generate a waveform output on the OC2 pin.

Timer/Counter

Interrupt Mask

Register – TIMSK

Bit

7

OCIE2

R/W

0

6

TOIE2

R/W

0

5

TICIE1

R/W

0

4

OCIE1A

R/W

0

3

OCIE1B

R/W

0

2

TOIE1

R/W

0

1

OCIE0

R/W

0

TOIE0

R/W

0

TIMSK

Read/Write

Initial Value

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

Timer/Counter

Interrupt Flag Register

– TIFR

Bit

7

6

5

4

3

2

1

0

OCF2

R/W

TOV2

R/W

ICF1

R/W

OCF1A

R/W

OCF1B

R/W

TOV1

R/W

OCF0

R/W

TOV0

R/W

TIFR

Read/Write

159

2467P–AVR–08/07

Initial Value

0

• Bit 7 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and

OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.

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ATmega128(L)

Output

Compare

Modulator

(OCM1C2)

Overview

The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier

frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit

Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details

about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)”

on page 112 and “8-bit Timer/Counter2 with PWM” on page 145. Note that this feature is not

available in ATmega103 compatibility mode.

Figure 72. Output Compare Modulator, Block Diagram

OC1C

OC2

Timer/Counter 1

Timer/Counter 2

OC1C /

OC2 / PB7

When the modulator is enabled, the two output compare channels are modulated together as

shown in the block diagram (Figure 72).

Description

The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The

outputs of the Output Compare units (OC1C and OC2) overrides the normal PORTB7 Register

when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and

OC2 are enabled at the same time, the modulator is automatically enabled.

The functional equivalent schematic of the modulator is shown on Figure 73. The schematic

includes part of the Timer/Counter units and the port B pin 7 output driver circuit.

Figure 73. Output Compare Modulator, Schematic

COM21

COM20

Vcc

COM1C1

COM1C0

Modulator

0

1

( From Waveform Generator )

D

Q

1

0

OC1C

OC1C /

OC2 / PB7

( From Waveform Generator )

D

Q

OC2

D

Q

PORTB7

DDRB7

DATABUS

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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by

the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the

COMnx1:0 bit setting.

Timing Example

Figure 74 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate

in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle

Compare Output mode (COMnx1:0 = 1).

Figure 74. Output Compare Modulator, Timing Diagram

clk_I/O

OC1C

(FPWM Mode)

OC2

(CTC Mode)

PB7

(PORTB7 = 0)

PB7

(PORTB7 = 1)

1

2

3

(Period)

In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated

by the Output Compare unit C of the Timer/Counter1.

The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is

equal to the number of system clock cycles of one period of the carrier (OC2). In this example

the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure

74 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2

high time is one cycle longer than the period 3 high time, but the result on the PB7 output is

equal in both periods.

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ATmega128(L)

Serial

Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega128 and peripheral devices or between several AVR devices. The ATmega128 SPI

includes the following features:

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

Figure 75. SPI Block Diagram

DIVIDER

/2/4/8/16/32/64/128

Note:

Refer to Figure 1 on page 2 and Table 30 on page 74 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 76. The sys-

tem consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and

Slave prepare the data to be sent in their respective Shift Registers, and the Master generates

the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-

ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In

– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling

high the Slave Select, SS, line.

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When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the 8 bits

into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmis-

sion flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is

requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the

end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the

buffer register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this state, software may update the contents of the SPI Data

Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin

until the SS pin is driven low. As one byte has been completely shifted, the end of transmission

flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is

requested. The Slave may continue to place new data to be sent into SPDR before reading the

incoming data. The last incoming byte will be kept in the buffer register for later use.

Figure 76. SPI Master-Slave Interconnection

SHIFT

ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the minimum low and high period should be:

Low period: Longer than 2 CPU clock cycles.

High period: Longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden

according to Table 69. For more details on automatic port overrides, refer to “Alternate Port

Functions” on page 71.

Table 69. SPI Pin Overrides⁽¹⁾

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

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ATmega128(L)

Note:

1. See “Alternate Functions of Port B” on page 74 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission. DDR_SPI in the examples must be replaced by the actual data direction

register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the

actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace

DD_MOSI with DDB5 and DDR_SPI with DDRB.

Assembly Code Example⁽¹⁾

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example⁽¹⁾

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

Note:

1. See “About Code Examples” on page 9.

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The following code examples show how to initialize the SPI as a slave and how to perform a sim-

ple reception.

Assembly Code Example⁽¹⁾

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in

r16,SPDR

ret

C Code Example⁽¹⁾

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return data register */

return SPDR;

}

Note:

1. See “About Code Examples” on page 9.

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ATmega128(L)

SS Pin

Functionality

Slave Mode

When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user

configured as an output, and the SPI is passive, which means that it will not receive incoming

data. Note that the SPI logic will be reset once the SS pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

Master Mode

When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the

SPI becoming a slave, the MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is

set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI master

mode.

SPI Control Register –

SPCR

Bit

7

SPIE

R/W

0

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

SPR1

R/W

0

SPR0

R/W

0

SPE

R/W

0

SPCR

Read/Write

Initial Value

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the global interrupt enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

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and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 77 and Figure 78 for an example. The CPOL functionality is summa-

rized below:

Table 70. CPOL functionality

CPOL

Leading edge

Rising

Trailing edge

Falling

0

1

Falling

Rising

• Bit 2 – CPHA: Clock Phase

The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 77 and Figure 78 for an example. The CPHA func-

tionality is summarized below:

Table 71. CPHA functionality

CPHA

Leading edge

Sample

Trailing edge

Setup

0

1

Setup

Sample

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have

no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f_oscis

shown in the following table:

Table 72. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

f_osc/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f_osc/16

f_osc/64

f_osc/128

f_osc/2

f_osc/8

f_osc/32

f_osc/64

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ATmega128(L)

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ATmega128(L)

SPI Status Register –

SPSR

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

WCOL

SPI2X

R/W

0

SPSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega128 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 72). This means that the minimum SCK period will be 2 CPU clock

periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_osc/4 or

lower.

The SPI interface on the ATmega128 is also used for program memory and EEPROM down-

loading or uploading. See page 300 for SPI Serial Programming and verification.

SPI Data Register –

SPDR

Bit

7

6

5

4

3

2

1

0

MSB

R/W

X

LSB

R/W

X

SPDR

Read/Write

Initial Value

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a Read/Write Register used for data transfer between the register file

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

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Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

77 and Figure 78. Data bits are shifted out and latched in on opposite edges of the SCK signal,

ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table

70 and Table 71, as done below:

Table 73. CPOL and CPHA Functionality

Leading edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing edge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI mode

CPOL = 0, CPHA = 0

CPOL = 0, CPHA = 1

CPOL = 1, CPHA = 0

CPOL = 1, CPHA = 1

0

1

2

3

Figure 77. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

Figure 78. SPI Transfer Format with CPHA = 1

SCK (CPOL = 0)

mode 1

SCK (CPOL = 1)

mode 3

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0)

LSB first (DORD = 1)

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

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ATmega128(L)

USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

Dual USART

The ATmega128 has two USART’s, USART0 and USART1. The functionality for both USART’s

is described below. USART0 and USART1 have different I/O registers as shown in “Register

Summary” on page 361. Note that in ATmega103 compatibility mode, USART1 is not available,

neither is the UBRR0H or UCRS0C Registers. This means that in ATmega103 compatibility

mode, the ATmega128 supports asynchronous operation of USART0 only.

Overview

A simplified block diagram of the USART transmitter is shown in Figure 79. CPU accessible I/O

registers and I/O pins are shown in bold.

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Figure 79. USART Block Diagram

Clock Generator

UBRR[H:L]

OSC

BAUD RATE GENERATOR

SYNC LOGIC

CONTROL

XCK

TxD

RxD

Transmitter

TX

CONTROL

UDR (Transmit)

PARITY

GENERATOR

CONTROL

TRANSMIT SHIFT REGISTER

Receiver

CLOCK

RECOVERY

RX

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

PARITY

CHECKER

UDR (Receive)

UCSRA

UCSRB

UCSRC

Note:

Refer to Figure 1 on page 2, Table 36 on page 78, and Table 39 on page 81 for USART pin

placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all units.

The clock generation logic consists of synchronization logic for external clock input used by syn-

chronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only

used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, parity generator and control logic for handling different serial frame formats. The

write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the receiver includes a parity checker, control logic, a Shift Register and a two level

receive buffer (UDR). The receiver supports the same frame formats as the Transmitter, and can

detect frame error, data overrun and parity errors.

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ATmega128(L)

AVR USART vs. AVR

UART – Compatibility

The USART is fully compatible with the AVR UART regarding:

•

Bit locations inside all USART registers

Baud Rate Generation

Transmitter Operation

Transmit Buffer Functionality

Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in some

special cases:

•

A second buffer register has been added. The two buffer registers operate as a circular FIFO

buffer. Therefore the UDR must only be read once for each incoming data! More important is

the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the

data in the receive buffer. Therefore the status bits must always be read before the UDR

Register is read. Otherwise the error status will be lost since the buffer state is lost.

•

The receiver Shift Register can now act as a third buffer level. This is done by allowing the

received data to remain in the serial Shift Register (see Figure 79) if the buffer registers are

full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun

(DOR) error conditions.

The following control bits have changed name, but have same functionality and register location:

•

CHR9 is changed to UCSZ2

OR is changed to DOR

Clock Generation

The clock generation logic generates the base clock for the transmitter and receiver. The

USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-

chronous, Master Synchronous, and Slave Synchronous mode. The UMSEL bit in USART

Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-

ation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA

Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK

pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave

mode). The XCK pin is only active when using Synchronous mode.

Figure 80 shows a block diagram of the clock generation logic.

Figure 80. Clock Generation Logic, Block Diagram

UBRR

U2X

fosc

UBRR+1

Prescaling

Down-Counter

/ 2

/ 4

/ 2

0

1

0

1

OSC

txclk

UMSEL

rxclk

DDR_XCK

Sync

Register

Edge

Detector

xcki

0

1

XCK

xcko

DDR_XCK

UCPOL

1

0

Signal description:

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txclk Transmitter clock. (Internal Signal)

rxclk Receiver base clock. (Internal Signal)

xcki

Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

Internal Clock

Generation – The

Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 80.

The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when

the UBRRL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= fosc/(UBRR+1)). The transmitter divides the

baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator

output is used directly by the receiver’s clock and data recovery units. However, the recovery

units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the

UMSEL, U2X and DDR_XCK bits.

Table 74 contains equations for calculating the baud rate (in bits per second) and for calculating

the UBRR value for each mode of operation using an internally generated clock source.

Table 74. Equations for Calculating Baud Rate Register Setting

Equation for Calculating

Baud Rate⁽¹⁾

Equation for Calculating

UBRR Value

Operating Mode

Asynchronous Normal Mode

(U2X = 0)

f

OSC

f

OSC

BAUD = --------------------------------------

UBRR = ----------------------- – 1

16(UBRR + 1)

16BAUD

Asynchronous Double Speed

Mode (U2X = 1)

f

OSC

f

OSC

BAUD = -----------------------------------

UBRR = -------------------- – 1

8(UBRR + 1)

8BAUD

Synchronous Master Mode

f

OSC

f

OSC

BAUD = -----------------------------------

UBRR = -------------------- – 1

2(UBRR + 1)

2BAUD

Note:

BAUD Baud rate (in bits per second, bps)

f_OSCSystem Oscillator clock frequency

1. The baud rate is defined to be the transfer rate in bit per second (bps).

UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)

Some examples of UBRR values for some system clock frequencies are found in Table 82 (see

page 194).

Double Speed

Operation (U2X)

The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect

for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

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External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 80 for details.

External clock input from the XCK pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the transmitter and receiver. This process introduces

a two CPU clock period delay and therefore the maximum external XCK clock frequency is lim-

ited by the following equation:

f

OSC

-----------

f

<

XCK

4

Note that f_oscdepends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

Synchronous Clock

Operation

When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input

(slave) or clock output (master). The dependency between the clock edges and data sampling or

data change is the same. The basic principle is that data input (on RxD) is sampled at the oppo-

site XCK clock edge of the edge the data output (TxD) is changed.

Figure 81. Synchronous Mode XCK Timing.

UCPOL = 1

XCK

RxD / TxD

Sample

UCPOL = 0

XCK

RxD / TxD

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is

used for data change. As Figure 81 shows, when UCPOL is zero the data will be changed at ris-

ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at

falling XCK edge and sampled at rising XCK edge.

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Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

•

1 start bit

5, 6, 7, 8, or 9 data bits

no, even or odd parity bit

1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 82 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 82. Frame Formats

FRAME

(IDLE)

St

0

1

2

3

4

[5]

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

(n)

P

Start bit, always low.

Data bits (0 to 8).

Parity bit. Can be odd or even.

Stop bit, always high.

Sp

IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB

and UCSRC. The receiver and transmitter use the same setting. Note that changing the setting

of any of these bits will corrupt all ongoing communication for both the receiver and transmitter.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The receiver ignores the

second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first

stop bit is zero.

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

P

= d

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1

3 2 1 0

even

n – 1

3 2 1 0

odd

P_evenParity bit using even parity

P_odd

d_n

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

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USART

Initialization

The USART has to be initialized before any communication can take place. The initialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

global interrupt flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no

ongoing transmissions during the period the registers are changed. The TXC flag can be used to

check that the Transmitter has completed all transfers, and the RXC flag can be used to check

that there are no unread data in the receive buffer. Note that the TXC flag must be cleared

before each transmission (before UDR is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

registers.

Assembly Code Example⁽¹⁾

USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example⁽¹⁾

#define FOSC 1843200// Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void main( void )

{

...

USART_Init ( MYUBRR );

...

}

void USART_Init( unsigned int ubrr )

{

/* Set baud rate */

UBRRH = (unsigned char)(ubrr>>8);

UBRRL = (unsigned char)ubrr;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<USBS)|(3<<UCSZ0);

}

Note:

1. See “About Code Examples” on page 9.

More advanced initialization routines can be made that include frame format as parameters,

disable interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed

directly in the main routine, or be combined with initialization code for other I/O modules.

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Data Transmission The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB

Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid-

den by the USART and given the function as the transmitter’s serial output. The baud rate, mode

of operation and frame format must be set up once before doing any transmissions. If synchro-

nous operation is used, the clock on the XCK pin will be overridden and used as transmission

clock.

– The USART

Transmitter

Sending Frames with

5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or

immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the baud register,

U2X bit or by XCK depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDRE) flag. When using frames with less than eight bits, the most signifi-

cant bits written to the UDR are ignored. The USART has to be initialized before the function can

be used. For the assembly code, the data to be sent is assumed to be stored in Register R16

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example⁽¹⁾

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

Note:

1. See “About Code Examples” on page 9..

The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before

loading it with new data to be transmitted. If the data register empty interrupt is utilized, the inter-

rupt routine writes the data into the buffer.

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Sending Frames with

9 Data Bit

If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB

before the low byte of the character is written to UDR. The following code examples show a

transmit function that handles 9 bit characters. For the assembly code, the data to be sent is

assumed to be stored in Registers R17:R16.

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Copy 9th bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

Note:

1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of the UCSRB is static. I.e., only the TXB8 bit of the UCSRB Register is used after

initialization.

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for other protocol handling as for example synchronization.

Transmitter Flags and The USART Transmitter has two flags that indicate its state: USART Data Register Empty

Interrupts

(UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts.

The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRA Register.

When the Data Register empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that

global interrupts are enabled). UDRE is cleared by writing UDR. When interrupt-driven data

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transmission is used, the data register empty Interrupt routine must either write new

data to UDR in order to clear UDRE or disable the data register empty interrupt, other-

wise a new interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit

Shift Register has been shifted out and there are no new data currently present in the

transmit buffer. The TXC flag bit is automatically cleared when a transmit complete inter-

rupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is

useful in half-duplex communication interfaces (like the RS485 standard), where a

transmitting application must enter receive mode and free the communication bus

immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART

Transmit Complete Interrupt will be executed when the TXC flag becomes set (provided

that global interrupts are enabled). When the transmit complete interrupt is used, the

interrupt handling routine does not have to clear the TXC flag, this is done automatically

when the interrupt is executed.

Parity Generator

The parity generator calculates the parity bit for the serial frame data. When parity bit is

enabled (UPM1 = 1), the transmitter control logic inserts the parity bit between the last

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective

until ongoing and pending transmissions are completed, i.e., when the Transmit Shift

Register and Transmit Buffer register do not contain data to be transmitted. When dis-

abled, the Transmitter will no longer override the TxD pin.

Data Reception – The

USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Register to one. When the receiver is enabled, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the receiver’s serial

input. The baud rate, mode of operation and frame format must be set up once before

any serial reception can be done. If synchronous operation is used, the clock on the

XCK pin will be used as transfer clock.

Receiving Frames with 5 to 8

Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows

the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive

Shift Register until the first stop bit of a frame is received. A second stop bit will be

ignored by the receiver. When the first stop bit is received, i.e., a complete serial frame

is present in the Receive Shift Register, the contents of the Shift Register will be moved

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

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The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXC) flag. When using frames with less than eight bits the most significant

bits of the data read from the UDR will be masked to zero. The USART has to be initialized

before the function can be used.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in

r16, UDR

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

Note:

1. See “About Code Examples” on page 9.

The function simply waits for data to be present in the receive buffer by checking the RXC flag,

before reading the buffer and returning the value.

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Receiving Frames with If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB

9 Data Bits

before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE status

flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will

change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and UPE

bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both nine bit

characters and the status bits.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in

r18, UCSRA

r17, UCSRB

r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<UPE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example⁽¹⁾

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<UPE) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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Note:

1. See “About Code Examples” on page 9..

The receive function example reads all the I/O registers into the register file before any compu-

tation is done. This gives an optimal receive buffer utilization since the buffer location read will

be free to accept new data as early as possible.

Receive Compete Flag The USART Receiver has one flag that indicates the receiver state.

and Interrupt

The Receive Complete (RXC) flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0),

the receive buffer will be flushed and consequently the RXC bit will become zero.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive

Complete Interrupt will be executed as long as the RXC flag is set (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt

will occur once the interrupt routine terminates.

Receiver Error Flags

The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity

Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are

located in the receive buffer together with the frame for which they indicate the error status. Due

to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR),

since reading the UDR I/O location changes the buffer read location. Another equality for the

error flags is that they can not be altered by software doing a write to the flag location. However,

all flags must be set to zero when the UCSRA is written for upward compatibility of future

USART implementations. None of the error flags can generate interrupts.

The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one),

and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag

is not affected by the setting of the USBS bit in UCSRC since the receiver ignores all, except for

the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to

UCSRA.

The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A data

overrun occurs when the receive buffer is full (two characters), it is a new character waiting in

the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one

or more serial frame lost between the frame last read from UDR, and the next frame read from

UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA.

The DOR flag is cleared when the frame received was successfully moved from the Shift Regis-

ter to the receive buffer.

The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a parity error

when received. If parity check is not enabled the UPE bit will always be read zero. For compati-

bility with future devices, always set this bit to zero when writing to UCSRA. For more details see

“Parity Bit Calculation” on page 176 and “Parity Checker” on page 184.

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Parity Checker

The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity

check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity

checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit from the serial frame. The result of the check is stored in the receive buffer together

with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to

check if the frame had a Parity Error.

The UPE bit is set if the next character that can be read from the receive buffer had a parIty

Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is

valid until the Receive buffer (UDR) is read.

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the receiver will no

longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed

when the receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive

Buffer

The receiver buffer FIFO will be flushed when the receiver is disabled, i.e. the buffer will be emp-

tied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is

cleared. The following code example shows how to flush the receive buffer.

Assembly Code Example⁽¹⁾

USART_Flush:

sbis UCSRA, RXC

ret

in

rjmp USART_Flush

C Code Example⁽¹⁾

r16, UDR

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

Note:

1. See “About Code Examples” on page 9..

The USART includes a clock recovery and a data recovery unit for handling asynchronous

data reception. The clock recovery logic is used for synchronizing the internally generated

baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery

logic samples and low pass filters each incoming bit, thereby improving the noise immunity of

the receiver. The asynchronous reception operational range depends on the accuracy of the

internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

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Asynchronous Clock

Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 83

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for normal mode, and 8 times the baud rate for Double Speed mode. The horizon-

tal arrows illustrate the synchronization variation due to the sampling process. Note the larger

time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero

are samples done when the RxD line is idle (i.e., no communication activity).

Figure 83. Start Bit Sampling

RxD

IDLE

START

BIT 0

Sample

(U2X = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

Sample

(U2X = 1)

0

2

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

Asynchronous Data

Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in normal mode and 8 states

for each bit in Double Speed mode. Figure 84 shows the sampling of the data bits and the parity

bit. Each of the samples is given a number that is equal to the state of the recovery unit.

Figure 84. Sampling of Data and Parity Bit

RxD

BIT n

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the receiver only uses the first stop bit of a frame. Figure 85 shows the sampling of the

stop bit and the earliest possible beginning of the start bit of the next frame.

185

2467P–AVR–08/07

Figure 85. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxD

STOP 1

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2X = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 85. For Double Speed mode the first low level must be delayed to (B).

(C) marks a stop bit of full length. The early start bit detection influences the operational range of

the receiver.

Asynchronous

Operational Range

The operational range of the Receiver is dependent on the mismatch between the received bit

rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too

slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see

Table 75) base frequency, the Receiver will not be able to synchronize the frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

(D + 2)S

(D + 1)S + S

(D + 1)S

S – 1 + D ⋅ S + S

R

= -----------------------------------

R

= ------------------------------------------

fast

slow

M

F

D

S

Sum of character size and parity size (D = 5 to 10-bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

S_F

First sample number used for majority voting. S_F= 8 for Normal Speed and S_F= 4

for Double Speed mode.

S_MMiddle sample number used for majority voting. S_M= 9 for Normal Speed and

S_M= 5 for Double Speed mode.

R

_slowis the ratio of the slowest incoming data rate that can be accepted in relation to the receiver

baud rate. R_fastis the ratio of the fastest incoming data rate that can be accepted in relation to

the receiver baud rate.

Table 75 and Table 76 list the maximum receiver baud rate error that can be tolerated. Note that

normal speed mode has higher toleration of baud rate variations.

186

ATmega128(L)

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ATmega128(L)

Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X =

0)

D

Max Total

Error %

Recommended Max

Receiver Error %

# (Data+Parity Bit)

R_slow

%

R_fast%

5

6

93,20

94,12

94,81

95,36

95,81

96,17

106,67

105,79

105,11

104,58

104,14

103,78 %

+6.67/-6.8

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

3.0

2.5

2.0

1.5

7

8

9

10

Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X =

1)

D

Max Total

Error %

Recommended Max

Receiver Error %

# (Data+Parity Bit)

R_slow

%

R_fast%

5

6

94,12

94,92

95,52

96,00

96,39

96,70

105,66

104,92

104,35

103,90

103,53

103,23

+5.66/-5.88

+4.92/-5.08

+4.35/-4.48

+3.90/-4.00

+3.53/-3.61

+3.23/-3.30

2.5

2.0

1.5

1.0

7

8

9

10

The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the receiver and transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator the system clock may differ more than 2% depending of the resonators tolerance. The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of the system frequency to get the baud rate wanted. In this case an UBRR value

that gives an acceptable low error can be used if possible.

Multi-processor

Communication

Mode

Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering

function of incoming frames received by the USART receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The transmitter is unaffected by the MPCM

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the receiver is set up for frames with 9

data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the

frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the

frame type bit is zero the frame is a data frame.

187

2467P–AVR–08/07

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

Using MPCM

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The

ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame

(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character

frame format.

The following procedure should be used to exchange data in Multi-processor Communication

mode:

1. All slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).

2. The master MCU sends an address frame, and all slaves receive and read this frame. In

the slave MCUs, the RXC flag in UCSRA will be set as normal.

3. Each slave MCU reads the UDR Register and determines if it has been selected. If so, it

clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and keeps

the MPCM setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other slave MCUs, which still have the MPCM bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCM bit and waits for a new address frame from master. The process then repeats

from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver

must change between using n and n+1 character frame formats. This makes full-duplex opera-

tion difficult since the transmitter and receiver uses the same character size setting. If 5- to 8-bit

character frames are used, the transmitter must be set to use two stop bit (USBS = 1) since the

first stop bit is used for indicating the frame type.

Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCM bit. The

MPCM bit shares the same I/O location as the TXC flag and this might accidentally be cleared

when using SBI or CBI instructions.

188

ATmega128(L)

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ATmega128(L)

USART Register

Description

USARTn I/O Data

Register – UDRn

Bit

7

6

5

4

3

2

1

0

RXBn[7:0]

TXBn[7:0]

UDRn (Read)

UDRn (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share

the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer

Register (TXBn) will be the destination for data written to the UDRn Register location. Reading

the UDRn Register location will return the contents of the receive data buffer register (RXBn).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn flag in the UCSRAn Register is set.

Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify

write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC

and SBIS), since these also will change the state of the FIFO.

USART Control and

Status Register A –

UCSRnA

Bit

7

RXCn

R

6

TXCn

R/W

0

5

4

FEn

R

3

DORn

R

2

UPEn

R

1

U2Xn

R/W

0

MPCMn

R/W

0

UDREn

UCSRnA

Read/Write

Initial Value

R

1

0

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see descrip-

tion of the TXCIEn bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is

one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data

Register Empty interrupt (see description of the UDRIEn bit).

UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

189

2467P–AVR–08/07

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the

parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-Processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The transmitter is unaffected by the MPCMn setting. For more detailed

information see “Multi-processor Communication Mode” on page 187.

USARTn Control and

Status Register B –

UCSRnB

Bit

7

RXCIEn

R/W

0

6

TXCIEn

R/W

0

5

UDRIEn

R/W

0

4

RXENn

R/W

0

3

TXENn

R/W

0

2

UCSZn2

R/W

1

0

TXB8n

R/W

0

RXB8n

UCSRnB

Read/Write

Initial Value

R

0

• Bit 7 – RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt

will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is writ-

ten to one and the RXC bit in UCSRnA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter-

rupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the global interrupt flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXENn: Receiver Enable

Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port

operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn and UPEn flags.

• Bit 3 – TXENn: Transmitter Enable

190

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal

port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn

to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and transmit buffer register do not contain data to be transmit-

ted. When disabled, the transmitter will no longer override the TxDn port.

• Bit 2 – UCSZn2: Character Size

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits

(character size) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8

RXB8n is the ninth data bit of the received character when operating with serial frames with 9-

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8

TXB8n is the 9th data bit in the character to be transmitted when operating with serial frames

with 9 data bits. Must be written before writing the low bits to UDRn.

USART Control and

Status Register C –

UCSRnC

Bit

7

–

6

UMSELn

R/W

0

5

UPMn1

R/W

0

4

UPMn0

R/W

0

3

USBSn

R/W

0

2

UCSZn1

R/W

1

UCSZn0

R/W

1

0

UCPOLn

R/W

0

UCSRnC

Read/Write

Initial Value

R/W

0

Note that this register is not available in ATmega103 compatibility mode.

• Bit 7 – Reserved Bit

This bit is reserved for future use. For compatibility with future devices, these bit must be written

to zero when UCSRnC is written.

• Bit 6 – UMSELn: USART Mode Select

This bit selects between Asynchronous and Synchronous mode of operation.

Table 77. UMSELn Bit Settings

UMSELn

Mode

0

1

Asynchronous Operation

Synchronous Operation

• Bit 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting.

If a mismatch is detected, the UPEn flag in UCSRnA will be set.

Table 78. UPMn Bits Settings

UPMn1

UPMn0

Parity Mode

0

1

0

1

0

1

Disabled

(Reserved)

Enabled, Even Parity

Enabled, Odd Parity

191

2467P–AVR–08/07

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Table 79. USBSn Bit Settings

USBSn

Stop Bit(s)

1-bit

0

1

2-bits

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(character size) in a frame the Receiver and Transmitter use.

Table 80. UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

5-bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when Asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

Table 81. UCPOLn Bit Settings

Transmitted Data Changed (Output of

UCPOLn TxDn Pin)

Received Data Sampled (Input on

RxDn Pin)

0

1

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

USART Baud Rate

Registers – UBRRnL

and UBRRnH

Bit

15

14

13

12

11

10

9

8

–

UBRRn[11:8]

UBRRnH

UBRRnL

UBRRn[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

UBRRnH is not available in mega103 compatibility mode

192

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRnH is written.

• Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register

This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four

most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn

baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud

rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

193

2467P–AVR–08/07

Examples of Baud For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-

chronous operation can be generated by using the UBRR settings in Table 82. UBRR values

Rate Setting

which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the

table. Higher error ratings are acceptable, but the receiver will have less noise resistance when

the error ratings are high, especially for large serial frames (see “Asynchronous Operational

Range” on page 186). The error values are calculated using the following equation:

BaudRate_{Closest Match}

⎛

⎞

Error[%] = ------------------------------------------------------- – 1 • 100%

⎝

⎠

BaudRate

Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f_osc= 1.0000 MHz f_osc= 1.8432 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR

f_osc= 2.0000 MHz

U2X = 0 U2X = 1

UBRR

Baud

Rate

(bps)

Error

0.2%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.0%

-25.0%

0.0%

–

Error

0.0%

–

UBRR

Error

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

–

2400

25

12

6

51

25

12

8

47

23

11

7

95

47

23

15

11

7

51

25

12

8

103

51

25

16

12

8

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

0

0.0%

Max ⁽¹⁾

62.5 kbps

UBRR = 0, Error = 0.0%

125 kbps

115.2 kbps

230.4 kbps

125 kbps

250 kbps

1.

194

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 83. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f_osc= 3.6864 MHz f_osc= 4.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR

f_osc= 7.3728 MHz

Baud

Rate

(bps)

U2X = 0

U2X = 1

UBRR

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

–

Error

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

Error

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

UBRR

191

95

47

31

23

15

11

7

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

191

95

47

31

23

15

11

7

103

51

25

16

12

8

207

103

51

34

25

16

12

8

383

191

95

63

47

31

23

15

11

7

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

0.5M

–

0

–

0

1

1M

–

0

Max ⁽¹⁾

230.4 kbps

UBRR = 0, Error = 0.0%

460.8 kbps

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

1.

195

2467P–AVR–08/07

Table 84. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f_osc= 8.0000 MHz f_osc= 11.0592 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR

f_osc= 14.7456 MHz

U2X = 0 U2X = 1

UBRR UBRR

Baud

Rate

(bps)

Error

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

Error

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

–

Error

0.0%

-7.8%

Error

0.0%

5.3%

-7.8%

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

416

207

103

68

51

34

25

16

12

8

287

143

71

47

35

23

17

11

8

575

287

143

95

71

47

35

23

17

11

5

383

191

95

63

47

31

23

15

11

7

767

383

191

127

95

63

47

31

23

15

7

6

3

5

1

3

2

3

1

3

2

5

3

6

0.5M

0

1

–

2

1

3

1M

–

0

–

0

1

Max ⁽¹⁾

0.5 Mbps

UBRR = 0, Error = 0.0%

1 Mbps

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1.

196

ATmega128(L)

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ATmega128(L)

Table 85. Examples of UBRR Settings for Commonly Used Oscillator Frequencies

f_osc= 16.0000 MHz f_osc= 18.4320 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR UBRR UBRR UBRR

f_osc= 20.0000 MHz

Baud

Rate

(bps)

U2X = 0

U2X = 1

UBRR

Error

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

Error

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

-3.5%

0.0%

Error

0.0%

-7.8%

–

Error

0.0%

2.4%

-7.8%

–

UBRR

520

259

129

86

64

42

32

21

15

10

4

Error

0.0%

0.2%

-0.2%

0.2%

0.9%

-1.4%

1.7%

-1.4%

8.5%

0.0%

–

Error

0.0%

0.2%

-0.2%

0.2%

-0.2%

0.2%

0.9%

-1.4%

0.0%

–

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

416

207

103

68

51

34

25

16

12

8

832

416

207

138

103

68

51

34

25

16

8

479

239

119

79

59

39

29

19

14

9

959

479

239

159

119

79

59

39

29

19

9

1041

520

259

173

129

86

64

42

32

21

3

4

10

3

7

4

8

4

9

0.5M

1

3

–

4

–

4

1M

0

1

–

Max ⁽¹⁾

1 Mbps

UBRR = 0, Error = 0.0%

2 Mbps

1.152 Mbps

2.304 Mbps

1.25 Mbps

2.5 Mbps

1.

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Two-wire Serial

Interface

Features

• Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up when AVR is in Sleep Mode

Two-wire Serial

Interface Bus

Definition

The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The

TWI protocol allows the systems designer to interconnect up to 128 different devices using only

two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-

ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All

devices connected to the bus have individual addresses, and mechanisms for resolving bus

contention are inherent in the TWI protocol.

Figure 86. TWI Bus Interconnection

V_CC

Device 1

Device 3

Device 2

Device n

R1

R2

........

SDA

SCL

TWI Terminology

The following definitions are frequently encountered in this section.

Table 86. TWI Terminology

Term

Description

Master

The device that initiates and terminates a transmission. The master also

generates the SCL clock

Slave

The device addressed by a master

The device placing data on the bus

The device reading data from the bus

Transmitter

Receiver

Electrical

Interconnection

As depicted in Figure 86, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line

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high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any

bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 321. Two

different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,

and one valid for bus speeds up to 400 kHz.

Data Transfer and

Frame Format

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 87. Data Validity

SDA

SCL

Data Stable

Data Change

START and STOP

Conditions

The master initiates and terminates a data transmission. The transmission is initiated when the

master issues a START condition on the bus, and it is terminated when the master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behavior, and therefore START is used to describe both

START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As

depicted below, START and STOP conditions are signalled by changing the level of the SDA

line when the SCL line is high.

Figure 88. START, REPEATED START and STOP Conditions

SDA

SCL

START

STOP START

REPEATED START

STOP

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Address Packet

Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one

READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera-

tion is to be performed, otherwise a write operation should be performed. When a slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed slave is busy, or for some other reason can not service the mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a master wishes to transmit the same message to several

slaves in the system. When the general call address followed by a Write bit is transmitted on the

bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by all the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 89. Address Packet Format

Addr MSB

Addr LSB

R/W

ACK

SDA

SCL

1

2

7

8

9

START

Data Packet Format

All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an

acknowledge bit. During a data transfer, the master generates the clock and the START and

STOP conditions, while the receiver is responsible for acknowledging the reception. An

Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL

cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has

received the last byte, or for some reason cannot receive any more bytes, it should inform the

transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

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Figure 90. Data Packet Format

Data MSB

Data LSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

1

2

7

8

9

STOP, REPEATED

START or Next

Data Byte

SLA+R/W

Data Byte

Combining Address

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets

and Data Packets Into and a STOP condition. An empty message, consisting of a START followed by a STOP condi-

a Transmission

tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement

handshaking between the master and the slave. The slave can extend the SCL low period by

pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the

slave, or the slave needs extra time for processing between the data transmissions. The slave

extending the SCL low period will not affect the SCL high period, which is determined by the

master. As a consequence, the slave can reduce the TWI data transfer speed by prolonging the

SCL duty cycle.

Figure 91 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP condition, depending on the software protocol imple-

mented by the application software.

Figure 91. Typical Data Transmission

Addr MSB

Addr LSB R/W

ACK

Data MSB

Data LSB ACK

SDA

SCL

1

2

7

8

9

1

2

7

8

9

START

SLA+R/W

Data Byte

STOP

Multi-master Bus

Systems,

Arbitration and

Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken

in order to ensure that transmissions will proceed as normal, even if two or more masters initiate

a transmission at the same time. Two problems arise in multi-master systems:

•

An algorithm must be implemented allowing only one of the masters to complete the

transmission. All other masters should cease transmission when they discover that they

have lost the selection process. This selection process is called arbitration. When a

contending master discovers that it has lost the arbitration process, it should immediately

switch to slave mode to check whether it is being addressed by the winning master. The fact

that multiple masters have started transmission at the same time should not be detectable to

the slaves, i.e., the data being transferred on the bus must not be corrupted.

•

Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a

lockstep fashion. This will facilitate the arbitration process.

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2467P–AVR–08/07

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from

all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one

from the master with the shortest high period. The low period of the combined clock is equal to

the low period of the master with the longest low period. Note that all masters listen to the SCL

line, effectively starting to count their SCL high and low time-out periods when the combined

SCL line goes high or low, respectively.

Figure 92. SCL Synchronization between Multiple Masters

TA _low

TA _high

SCL from

master A

SCL from

master B

SCL Bus

Line

TB_low

TB_high

Masters Start

Counting Low Period

Counting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting

data. If the value read from the SDA line does not match the value the master had output, it has

lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value

while another master outputs a low value. The losing master should immediately go to slave

mode, checking if it is being addressed by the winning master. The SDA line should be left high,

but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one master remains, and this may take many

bits. If several masters are trying to address the same slave, arbitration will continue into the

data packet.

Figure 93. Arbitration Between two Masters

START

Master A loses

Arbitration, SDA_ASDA

SDA from

Master A

SDA from

Master B

SDA Line

Synchronized

SCL Line

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ATmega128(L)

Note that arbitration is not allowed between:

•

A REPEATED START condition and a data bit

A STOP condition and a data bit

A REPEATED START and a STOP condition

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

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2467P–AVR–08/07

Overview of the

TWI Module

The TWI module is comprised of several submodules, as shown in Figure 94. All registers drawn

in a thick line are accessible through the AVR data bus.

Figure 94. Overview of the TWI Module

SCL

SDA

Spike

Filter

Spike

Filter

Slew-rate

Control

Slew-rate

Control

Bus Interface Unit

Bit Rate Generator

START / STOP

Control

Spike Suppression

Prescaler

Address/Data Shift

Register (TWDR)

Bit Rate Register

(TWBR)

Arbitration detection

Ack

Address Match Unit

Control Unit

Address Register

(TWAR)

Status Register

(TWSR)

Control Register

(TWCR)

State Machine and

Status control

Address Comparator

Scl and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

Bit Rate Generator

Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the

CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note

that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

CPU Clock frequency

SCL frequency = -----------------------------------------------------------

TWPS

16 + 2(TWBR) ⋅ 4

•

TWBR = Value of the TWI Bit Rate Register

TWPS = Value of the prescaler bits in the TWI Status Register

Note:

Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus

line load. See Table 133 on page 321 for value of pull-up resistor.

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

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ATmega128(L)

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up

if addressed by a master.

If the TWI has initiated a transmission as master, the Arbitration Detection hardware continu-

ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

Address Match Unit

The Address Match unit checks if received address bytes match the 7-bit address in the TWI

Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a master. If another interrupt (e.g., INT0)

occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-

tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the

only enabled interrupt when entering Power-down.

Control Unit

The Control unit monitors the TWI bus and generates responses corresponding to settings in the

TWI Control Register (TWCR). When an event requiring the attention of the application occurs

on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-

tus Register (TWSR) is updated with a status code identifying the event. The TWSR only

contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,

the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TWINT flag is set, the SCL line is held low. This allows the application

software to complete its tasks before allowing the TWI transmission to continue.

The TWINT flag is set in the following situations:

•

After the TWI has transmitted a START/REPEATED START condition

After the TWI has transmitted SLA+R/W

After the TWI has transmitted an address byte

After the TWI has lost arbitration

After the TWI has been addressed by own slave address or general call

After the TWI has received a data byte

After a STOP or REPEATED START has been received while still addressed as a slave

When a bus error has occurred due to an illegal START or STOP condition

205

2467P–AVR–08/07

TWI Register

Description

TWI Bit Rate Register

– TWBR

Bit

7

TWBR7

R/W

0

6

TWBR6

R/W

0

5

TWBR5

R/W

0

4

TWBR4

R/W

0

3

TWBR3

R/W

0

2

TWBR2

R/W

0

1

TWBR1

R/W

0

TWBR0

R/W

0

TWBR

Read/Write

Initial Value

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 204 for calculating bit rates.

TWI Control Register –

TWCR

Bit

7

TWINT

R/W

0

6

TWEA

R/W

0

5

TWSTA

R/W

0

4

TWSTO

R/W

0

3

2

TWEN

R/W

0

1

–

0

TWIE

R/W

0

TWWC

TWCR

Read/Write

Initial Value

R

0

R

0

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a

master access by applying a START condition to the bus, to generate a receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application

software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the

TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched.

The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not

automatically cleared by hardware when executing the interrupt routine. Also note that clearing

this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR),

TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing

this flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to

one, the ACK pulse is generated on the TWI bus if the following conditions are met:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire

Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one

again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a master on the Two-

wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con-

dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition

is detected, and then generates a new START condition to claim the bus Master status. TWSTA

must be cleared by software when the START condition has been transmitted.

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• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire

Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-

matically. In slave mode, setting the TWSTO bit can be used to recover from an error condition.

This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed

Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is

low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to

one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the

slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT flag is high.

TWI Status Register –

TWSR

Bit

7

TWS7

R

6

TWS6

R

5

TWS5

R

4

TWS4

R

3

TWS3

R

2

–

1

TWPS1

R/W

0

TWPS0

R/W

0

TWSR

Read/Write

Initial Value

R

0

1

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status

codes are described later in this section. Note that the value read from TWSR contains both the

5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-

caler bits to zero when checking the Status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 87. TWI Bit Rate Prescaler

TWPS1

TWPS0

Prescaler Value

0

1

0

1

0

1

4

16

64

To calculate bit rates, see “Bit Rate Generator Unit” on page 204. The value of TWPS1..0 is

used in the equation.

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2467P–AVR–08/07

TWI Data Register –

TWDR

Bit

7

TWD7

R/W

1

6

TWD6

R/W

1

5

TWD5

R/W

1

4

TWD4

R/W

1

3

TWD3

R/W

1

2

TWD2

R/W

1

TWD1

R/W

1

0

TWD0

R/W

1

TWDR

Read/Write

Initial Value

In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.

This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register

cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-

ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted

in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep

mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost

bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is

controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the Two-wire Serial Bus.

TWI (Slave) Address

Register – TWAR

Bit

7

TWA6

R/W

1

6

TWA5

R/W

1

5

TWA4

R/W

1

4

TWA3

R/W

1

3

TWA2

R/W

1

2

TWA1

R/W

1

TWA0

R/W

1

0

TWGCE

R/W

0

TWAR

Read/Write

Initial Value

The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of

TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and

not needed in the master modes. In multimaster systems, TWAR must be set in masters which

can be addressed as slaves by other masters.

The LSB of TWAR is used to enable recognition of the general call address ($00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.

Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in

order to detect actions on the TWI bus.

When the TWINT flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 95 is a simple example of how the application can interface to the TWI hardware. In this

example, a master wishes to transmit a single data byte to a slave. This description is quite

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abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Figure 95. Interfacing the Application to the TWI in a Typical Transmission

1. Application

writes to TWCR

to initiate

transmission of

START

3. Check TWSR to see if START

was sent. Application loads

SLA+W into TWDR, and loads

appropriate control signals into

TWCR, making sure that TWINT

is written to one, and TWSTA is

written to zero.

5. Check TWSR to see if SLA+W

was sent and ACK received.

Application loads data into TWDR,

and loads appropriate control signals

into TWCR, making sure that TWINT

is written to one.

7. Check TWSR to see if data

was sent and ACK received.

Application loads appropriate

control signals to send STOP

into TWCR, making sure that

TWINT is written to one

TWI bus

START

SLA+W

A

Data

A

STOP

Indicates

TWINT set

2. TWINT set.

Status code indicates

START condition sent

4. TWINT set.

6. TWINT set.

Status code indicates

data sent, ACK received

Status code indicates

SLA+W sendt, ACK

received

TWI

Hardware

Action

1. The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instructing the TWI hardware to transmit a START

condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the START condition.

2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and

TWSR is updated with a status code indicating that the START condition has success-

fully been sent.

3. The application software should now examine the value of TWSR, to make sure that the

START condition was successfully transmitted. If TWSR indicates otherwise, the applica-

tion software might take some special action, like calling an error routine. Assuming that

the status code is as expected, the application must load SLA+W into TWDR. Remember

that TWDR is used both for address and data. After TWDR has been loaded with the

desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware

to transmit the SLA+W present in TWDR. Which value to write is described later on.

However, it is important that the TWINT bit is set in the value written. Writing a one to

TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in

TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate

transmission of the address packet.

4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and

TWSR is updated with a status code indicating that the address packet has successfully

been sent. The status code will also reflect whether a slave acknowledged the packet or

not.

5. The application software should now examine the value of TWSR, to make sure that the

address packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some special

action, like calling an error routine. Assuming that the status code is as expected, the

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application must load a data packet into TWDR. Subsequently, a specific value must be

written to TWCR, instructing the TWI hardware to transmit the data packet present in

TWDR. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the data packet.

6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR

is updated with a status code indicating that the data packet has successfully been sent.

The status code will also reflect whether a slave acknowledged the packet or not.

7. The application software should now examine the value of TWSR, to make sure that the

data packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some special

action, like calling an error routine. Assuming that the status code is as expected, the

application must write a specific value to TWCR, instructing the TWI hardware to transmit

a STOP condition. Which value to write is described later on. However, it is important that

the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI

will not start any operation as long as the TWINT bit in TWCR is set. Immediately after

the application has cleared TWINT, the TWI will initiate transmission of the STOP condi-

tion. Note that TWINT is NOT set after a STOP condition has been sent.

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Even though this example is simple, it shows the principles involved in all TWI transmissions.

These can be summarized as follows:

•

When the TWI has finished an operation and expects application response, the TWINT flag

is set. The SCL line is pulled low until TWINT is cleared.

•

When the TWINT flag is set, the user must update all TWI Registers with the value relevant

for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be

transmitted in the next bus cycle.

•

After all TWI Register updates and other pending application software tasks have been

completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a

one to TWINT clears the flag. The TWI will then commence executing whatever operation

was specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note that the code

below assumes that several definitions have been made for example by using include-files.

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Assembly Code Example

C Example

TWCR = (1<<TWINT)|(1<<TWSTA)|

Comments

ldi r16,

1

2

(1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)

Send START condition

(1<<TWEN)

out TWCR, r16

wait1:

while (!(TWCR & (1<<TWINT)))

in

r16,TWCR

;

Wait for TWINT flag set. This indicates that the

START condition has been transmitted

sbrs r16,TWINT

rjmp wait1

in

r16,TWSR

if ((TWSR & 0xF8) != START)

3

Check value of TWI Status Register. Mask

prescaler bits. If status different from START

go to ERROR

andi r16, 0xF8

cpi r16, START

brne ERROR

ERROR();

ldi r16, SLA_W

out TWDR, r16

TWDR = SLA_W;

TWCR = (1<<TWINT) |

(1<<TWEN);

Load SLA_W into TWDR Register. Clear

TWINT bit in TWCR to start transmission of

address

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait2:

while (!(TWCR & (1<<TWINT)))

4

5

Wait for TWINT flag set. This indicates that the

SLA+W has been transmitted, and

ACK/NACK has been received.

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait2

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_SLA_ACK)

Check value of TWI Status Register. Mask

prescaler bits. If status different from

MT_SLA_ACK go to ERROR

andi r16, 0xF8

cpi r16, MT_SLA_ACK

brne ERROR

ERROR();

ldi r16, DATA

out TWDR, r16

TWDR = DATA;

TWCR = (1<<TWINT) |

(1<<TWEN);

Load DATA into TWDR Register. Clear TWINT

bit in TWCR to start transmission of data

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait3:

while (!(TWCR & (1<<TWINT)))

6

7

Wait for TWINT flag set. This indicates that the

DATA has been transmitted, and ACK/NACK

has been received.

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait3

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_DATA_ACK)

Check value of TWI Status Register. Mask

prescaler bits. If status different from

MT_DATA_ACK go to ERROR

andi r16, 0xF8

cpi r16, MT_DATA_ACK

brne ERROR

ERROR();

ldi r16,

(1<<TWINT)|(1<<TWEN)|

TWCR = (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO);

Transmit STOP condition

(1<<TWSTO)

out TWCR, r16

Note:

For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with

instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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Transmission

Modes

The TWI can operate in one of four major modes. These are named Master Transmitter (MT),

Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these

modes can be used in the same application. As an example, the TWI can use MT mode to write

data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters

are present in the system, some of these might transmit data to the TWI, and then SR mode

would be used. It is the application software that decides which modes are legal.

The following sections describe each of these modes. Possible status codes are described

along with figures detailing data transmission in each of the modes. These figures contain the

following abbreviations:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In Figure 97 to Figure 103, circles are used to indicate that the TWINT flag is set. The numbers

in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At

these points, actions must be taken by the application to continue or complete the TWI transfer.

The TWI transfer is suspended until the TWINT flag is cleared by software.

When the TWINT flag is set, the status code in TWSR is used to determine the appropriate soft-

ware action. For each status code, the required software action and details of the following serial

transfer are given in Table 88 to Table 91. Note that the prescaler bits are masked to zero in

these tables.

Master Transmitter

Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see

Figure 96). In order to enter a Master mode, a START condition must be transmitted. The format

of the following address packet determines whether Master Transmitter or Master Receiver

mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,

MR mode is entered. All the status codes mentioned in this section assume that the prescaler

bits are zero or are masked to zero.

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Figure 96. Data Transfer in Master Transmitter Mode

V_CC

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to

transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI

will then test the Two-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT flag is set by hard-

ware, and the status code in TWSR will be $08 (See Table 88). In order to enter MT mode,

SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are $18, $20, or $38. The appropriate action to be taken for each of these status codes is

detailed in Table 88.

When SLA+W has been successfully transmitted, a data packet should be transmitted. This is

done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,

the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-

ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the

transfer. This is accomplished by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-

ing a STOP condition or a repeated START condition. A STOP condition is generated by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

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After a repeated START condition (state $10) the Two-wire Serial Interface can access the

same slave again, or a new slave without transmitting a STOP condition. Repeated START

enables the master to switch between slaves, Master Transmitter mode and Master Receiver

mode without losing control of the bus.

Table 88. Status Codes for Master Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

Application Software Response

Status of the Two-wire Serial

Bus and Two-wire Serial Inter-

face Hardware

To TWCR

To/from TWDR

STA

STO

0

TWINT

1

TWEA

X

are 0

Next Action Taken by TWI Hardware

$08

$10

A START condition has been Load SLA+W

transmitted

0

SLA+W will be transmitted;

ACK or NOT ACK will be received

A

repeated START condition Load SLA+W or

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

SLA+R will be transmitted;

has been transmitted

Load SLA+R

Logic will switch to master receiver mode

$18

$20

$28

$30

$38

SLA+W has been transmitted;

ACK has been received

Load data byte or

0

1

X

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

SLA+W has been transmitted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

0

1

0

1

X

Data byte has been transmitted; Load data byte or

ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

0

1

0

1

X

Data byte has been transmitted; Load data byte or

NOT ACK has been received

No TWDR action or

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO flag will be reset

1

0

1

X

No TWDR action or

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

Arbitration lost in SLA+W or data No TWDR action or

bytes

0

1

0

1

X

Two-wire Serial Bus will be released and not addressed

slave mode entered

A START condition will be transmitted when the bus be-

comes free

No TWDR action

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Figure 97. Formats and States in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

DATA

A

P

transmission

to a slave

receiver

$08

$18

$28

Next transfer

started with a

repeated start

condition

R_S

SLA

W

R

$10

Not acknowledge

received after the

slave address

A

P

$20

MR

Not acknowledge

received after a data

byte

A

P

$30

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

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Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see

Figure 98). In order to enter a Master mode, a START condition must be transmitted. The format

of the following address packet determines whether Master Transmitter or Master Receiver

mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted,

MR mode is entered. All the status codes mentioned in this section assume that the prescaler

bits are zero or are masked to zero.

Figure 98. Data Transfer in Master Receiver Mode

V_CC

Device 1

MASTER

RECEIVER

Device 2

SLAVE

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to

one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will

then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes

free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the

status code in TWSR will be $08 (See Table 88). In order to enter MR mode, SLA+R must be

transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be

cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-

ing value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are $38, $40, or $48. The appropriate action to be taken for each of these status codes is

detailed in Table 97. Received data can be read from the TWDR Register when the TWINT flag

is set high by hardware. This scheme is repeated until the last byte has been received. After the

last byte has been received, the MR should inform the ST by sending a NACK after the last

received data byte. The transfer is ended by generating a STOP condition or a repeated START

condition. A STOP condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

After a repeated START condition (state $10) the Two-wire Serial Interface can access the

same slave again, or a new slave without transmitting a STOP condition. Repeated START

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enables the master to switch between slaves, Master Transmitter mode and Master Receiver

mode without losing control over the bus.

Figure 99. Formats and States in the Master Receiver Mode

MR

Successfull

S

SLA

R

A

DATA

A

DATA

A

P

reception

from a slave

receiver

$08

$40

$50

$58

Next transfer

started with a

repeated start

condition

R_S

SLA

R

$10

Not acknowledge

received after the

slave address

W

A

P

$48

MT

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

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Table 89. Status Codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

Status of the Two-wire Serial

Bus and Two-wire Serial Inter-

face Hardware

To TWCR

STA

To/from TWDR

STO

0

TWINT

1

TWEA

X

Next Action Taken by TWI Hardware

$08

A START condition has been Load SLA+R

transmitted

0

SLA+R will be transmitted

ACK or NOT ACK will be received

$10

A

repeated START condition Load SLA+R or

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

has been transmitted

Load SLA+W

Logic will switch to master transmitter mode

$38

$40

$48

Arbitration lost in SLA+R or NOT No TWDR action or

0

1

0

1

X

Two-wire Serial Bus will be released and not addressed

slave mode will be entered

A START condition will be transmitted when the bus

ACK bit

No TWDR action

becomes free

SLA+R has been transmitted;

ACK has been received

No TWDR action or

No TWDR action

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

SLA+R has been transmitted;

NOT ACK has been received

No TWDR action or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO flag will

be reset

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

$50

$58

Data byte has been received;

ACK has been returned

Read data byte or

Read data byte

0

1

0

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0

1

Data byte has been received;

NOT ACK has been returned

Read data byte or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO flag will

be reset

Read data byte

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO flag will be reset

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see

Figure 100). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 100. Data Transfer in Slave Receiver Mode

V_CC

Device 1

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

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The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 90. The

slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode

(see states $68 and $78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the slave is not able to

receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave

address. However, the Two-wire Serial Bus is still monitored and address recognition may

resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily

isolate the TWI from the Two-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared

(by writing it to one). Further data reception will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte

present on the bus when waking up from these sleep modes.

220

ATmega128(L)

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ATmega128(L)

Table 90. Status Codes for Slave Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

Status of the Two-wire Serial Bus

and Two-wire Serial Interface

Hardware

To TWCR

STA

To/from TWDR

STO

0

TWINT

1

TWEA

0

Next Action Taken by TWI Hardware

$60

$68

$70

$78

Own SLA+W has been received;

ACK has been returned

No TWDR action or

No TWDR action

X

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

X

0

1

0

Arbitration lost in SLA+R/W as No TWDR action or

master; own SLA+W has been

received; ACK has been returned

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

No TWDR action

X

0

1

0

General call address has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

No TWDR action

X

0

1

0

Arbitration lost in SLA+R/W as No TWDR action or

master; General call address has

Data byte will be received and NOT ACK will be

returned

been received; ACK has been

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

$80

$88

Previously addressed with own Read data byte or

SLA+W; data has been received;

Data byte will be received and NOT ACK will be

returned

ACK has been returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with own Read data byte or

SLA+W; data has been received;

NOT ACK has been returned

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

0

1

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

Read data byte or

1

0

1

0

Read data byte

1

0

1

0

$90

$98

Previously addressed with

general call; data has been re-

ceived; ACK has been returned

Read data byte or

X

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Read data byte or

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

0

1

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode;

own SLA will be recognized;

Read data byte or

1

0

1

0

Read data byte

1

0

1

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

$A0

A

STOP condition or repeated No Action

0

1

0

1

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

START condition has been

received while still addressed as

slave

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

1

0

1

0

1

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

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2467P–AVR–08/07

Figure 101. Formats and States in the Slave Receiver Mode

Reception of the

S

SLA

W

A

DATA

A

DATA

A

P or S

own slave address

and one or more

data bytes. All are

acknowledged

$60

$80

A

$A0

Last data byte received

is not acknowledged

P or S

$88

Arbitration lost as master

and addressed as slave

A

$68

A

Reception of the general call

address and one or more data

bytes

General Call

DATA

A

DATA

A

P or S

$70

$90

$A0

Last data byte received is

not acknowledged

A

P or S

$98

Arbitration lost as master and

addressed as slave by general call

A

$78

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

n

Slave Transmitter

Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see

Figure 102). All the status codes mentioned in this section assume that the prescaler bits are

zero or are masked to zero.

Figure 102. Data Transfer in Slave Transmitter Mode

V_CC

Device 1

SLAVE

TRANSMITTER

Device 2

MASTER

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

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ATmega128(L)

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ATmega128(L)

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

The upper seven bits are the address to which the Two-wire Serial Interface will respond when

addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgment of the device’s own slave address or the general call address. TWSTA and

TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 91. The

Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master

mode (see state $B0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State $C0 or state $C8 will be entered, depending on whether the master receiver transmits

a NACK or ACK after the final byte. The TWI is switched to the not addressed slave mode, and

will ignore the master if it continues the transfer. Thus the master receiver receives all “1” as

serial data. State $C8 is entered if the master demands additional data bytes (by transmitting

ACK), even though the slave has transmitted the last byte (TWEA zero and expecting NACK

from the master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire

Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep

and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is

cleared (by writing it to one). Further data transmission will be carried out as normal, with the

AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the

SCL line may be held low for a long time, blocking other data transmissions.

Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte

present on the bus when waking up from these sleep modes.

Table 91. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

Status of the Two-wire Serial Bus

and Two-wire Serial Interface

Hardware

To TWCR

To/from TWDR

STA

STO

TWINT

TWEA

Next Action Taken by TWI Hardware

223

2467P–AVR–08/07

Table 91. Status Codes for Slave Transmitter Mode

$A8

$B0

$B8

$C0

Own SLA+R has been received;

ACK has been returned

Load data byte or

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Load data byte

Arbitration lost in SLA+R/W as Load data byte or

master; own SLA+R has been

received; ACK has been returned

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Load data byte

Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

0

1

0

1

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Switched to the not addressed slave mode;

own SLA will be recognized;

No TWDR action or

No TWDR action

1

0

1

0

1

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

$C8

Last data byte in TWDR has been No TWDR action or

transmitted (TWEA = “0”); ACK

0

1

0

1

Switched to the not addressed slave mode;

no recognition of own SLA or GCA

Switched to the not addressed slave mode;

own SLA will be recognized;

has been received

No TWDR action or

GCA will be recognized if TWGCE = “1”

Switched to the not addressed slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

1

0

1

0

1

No TWDR action

Switched to the not addressed slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

Figure 103. Formats and States in the Slave Transmitter Mode

Reception of the

own slave address

and one or

S

SLA

R

A

DATA

A

DATA

A

P or S

more data bytes

$A8

A

$B8

$C0

Arbitration lost as master

and addressed as slave

$B0

Last data byte transmitted.

Switched to not addressed

slave (TWEA = '0')

A

All 1's

P or S

$C8

Any number of data bytes

and their associated acknowledge bits

From master to slave

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the Two-wire Serial Bus. The

prescaler bits are zero or masked to zero

From slave to master

n

Miscellaneous States

There are two status codes that do not correspond to a defined TWI state, see Table 92.

224

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Status $F8 indicates that no relevant information is available because the TWINT flag is not set.

This occurs between other states, and when the TWI is not involved in a serial transfer.

Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR

are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.

Table 92. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

Application Software Response

To TWCR

Status of the Two-wire Serial

Bus and Two-wire Serial Inter-

face Hardware

To/from TWDR

STA

STO

TWINT

1

TWEA

X

are 0

Next Action Taken by TWI Hardware

Wait or proceed current transfer

$F8

$00

No relevant state information No TWDR action

available; TWINT = “0”

No TWCR action

Bus error due to an illegal No TWDR action

START or STOP condition

0

1

Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

Combining Several

TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated

2. The EEPROM must be instructed what location should be read

3. The reading must be performed

4. The transfer must be finished

Note that data is transmitted both from master to slave and vice versa. The master must instruct

the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multimaster sys-

tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the

master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 104. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter

ADDRESS

Master Receiver

DATA

S

SLA+W

A

Rs

SLA+R

A

P

S = START

Transmitted from master to slave

Rs = REPEATED START

Transmitted from slave to master

P = STOP

Multi-master

Systems and

Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

225

2467P–AVR–08/07

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a slave receiver.

Figure 105. An Arbitration Example

V_CC

Device 1

MASTER

TRANSMITTER

Device 3

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device n

R1

R2

........

SDA

SCL

Several different scenarios may arise during arbitration, as described below:

•

Two or more masters are performing identical communication with the same slave. In this

case, neither the slave nor any of the masters will know about the bus contention.

•

Two or more masters are accessing the same slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters

trying to output a one on SDA while another master outputs a zero will lose the arbitration.

Losing masters will switch to not addressed slave mode or wait until the bus is free and

transmit a new START condition, depending on application software action.

•

Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another master outputs a zero will

lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if

they are being addressed by the winning master. If addressed, they will switch to SR or ST

mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they

will switch to not addressed slave mode or wait until the bus is free and transmit a new

START condition, depending on application software action.

This is summarized in Figure 106. Possible status values are given in circles.

Figure 106. Possible Status Codes Caused by Arbitration

START

SLA

Data

STOP

Arbitration lost in SLA

Arbitration lost in Data

Own

No

38

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Address / General Call

received

Yes

Write

68/78

B0

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Direction

Read

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

226

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Analog

Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger

the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate

interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on com-

parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is

shown in Figure 107.

Figure 107. Analog Comparator Block Diagram

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

1)

OUTPUT

Notes: 1. See Table 94 on page 229.

2. Refer to Figure 1 on page 2 and Table 39 on page 81 for Analog Comparator pin placement.

Special Function IO

Register – SFIOR

Bit

7

6

–

5

–

4

–

3

ACME

R/W

0

2

1

PSR0

R/W

0

PSR321

R/W

0

TSM

R/W

0

PUD

R/W

0

SFIOR

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 3 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 228.

Analog Comparator

Control and Status

Register – ACSR

Bit

7

6

ACBG

R/W

0

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

ACD

R/W

0

ACSR

Read/Write

Initial Value

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

227

2467P–AVR–08/07

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. See “Internal Voltage Reference” on page 54.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 – 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

Input Capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection

between the analog comparator and the Input Capture function exists. To make the comparator

trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask

Register (TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 93.

Table 93. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

Analog

Comparator

Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

SFIOR) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

228

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

94. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 94. Analog Comparator Multiplexed Input

ACME

ADEN

MUX2..0

xxx

Analog Comparator Negative Input

0

1

x

1

0

AIN1

xxx

AIN1

000

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

001

010

011

100

101

110

111

229

2467P–AVR–08/07

Analog to

Digital

Converter

Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

•

2 LSB Absolute Accuracy

• 13 - 260 µs Conversion Time

• Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)

• 8 Multiplexed Single Ended Input Channels

• 7 Differential Input Channels

• 2 Differential Input Channels with Optional Gain of 10x and 200x

• Optional Left Adjustment for ADC Result Readout

• 0 - VCC ADC Input Voltage Range

• Selectable 2.56 V ADC Reference Voltage

• Free Running or Single Conversion Mode

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The ATmega128 features a 10-bit successive approximation ADC. The ADC is connected to an

8-channel Analog Multiplexer which allows 8 single-ended voltage inputs constructed from the

pins of Port F. The single-ended voltage inputs refer to 0V (GND).

The device also supports 16 differential voltage input combinations. Two of the differential inputs

(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing

amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage

before the A/D conversion. Seven differential analog input channels share a common negative

terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x

or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be

expected.

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 108.

The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than

0.3V from V_CC. See the paragraph “ADC Noise Canceler” on page 236 on how to connect this

pin.

Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

230

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 108. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC DATA REGISTER

(ADCH/ADCL)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

PRESCALER

MUX DECODER

CONVERSION LOGIC

AVCC

INTERNAL 2.56V

REFERENCE

SAMPLE & HOLD

COMPARATOR

AREF

AGND

10-BIT DAC

-

+

BANDGAP

REFERENCE

ADC7

SINGLE ENDED / DIFFERENTIAL SELECTION

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

POS.

INPUT

MUX

ADC MULTIPLEXER

OUTPUT

GAIN

AMPLIFIER

+

-

NEG.

INPUT

MUX

231

2467P–AVR–08/07

Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be

connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve

noise immunity.

The analog input channel and differential gain are selected by writing to the MUX bits in

ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can

be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as

positive and negative inputs to the differential gain amplifier.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input channel pair by the selected gain factor. This amplified value then

becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is

bypassed altogether.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

Starting a

Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

In Free Running mode, the ADC is constantly sampling and updating the ADC Data Register.

Free Running mode is selected by writing the ADFR bit in ADCSRA to one. The first conversion

must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will

perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is

cleared or not.

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Prescaling and

Figure 109. ADC Prescaler

Conversion Timing

ADEN

CK

Reset

7-BIT ADC PRESCALER

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle. See “Differential Gain Channels” on

page 235 for details on differential conversion timing.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC data registers, and ADIF is set. In single conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 95.

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Figure 110. ADC Timing Diagram, First Conversion (Single Conversion Mode)

First Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

MSB of Result

ADCH

ADCL

LSB of Result

MUX and REFS

Update

Conversion

Complete

Sample &Hold

MUX and REFS

Update

Figure 111. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

Figure 112. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

MSB of Result

LSB of Result

Sample & Hold

MUX and REFS

Update

Conversion

Complete

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Table 95. ADC Conversion Time

Sample & Hold (Cycles from

Start of Conversion)

Conversion Time

(Cycles)

Condition

First conversion

13.5

1.5

25

13

Normal conversions, single ended

Normal conversions, differential

1.5/2.5

13/14

Differential Gain

Channels

When using differential gain channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK_ADC2equal to half the ADC

clock. This synchronization is done automatically by the ADC interface in such a way that the

sample-and-hold occurs at a specific edge of CK_ADC2. A conversion initiated by the user (i.e., all

single conversions, and the first free running conversion) when CK_ADC2is low will take the same

amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled

clock cycle). A conversion initiated by the user when CK_ADC2is high will take 14 ADC clock

cycles due to the synchronization mechanism. In free running mode, a new conversion is initi-

ated immediately after the previous conversion completes, and since CK_ADC2is high at this time,

all automatically started (i.e., all but the first) free running conversions will take 14 ADC clock

cycles.

The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may

be subjected to non-linear amplification. An external low-pass filter should be used if the input

signal contains higher frequency components than the gain stage bandwidth. Note that the ADC

clock frequency is independent of the gain stage bandwidth limitation. E.g. the ADC clock period

may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this

channel.

Changing Channel The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

or Reference

Selection

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

Special care should be taken when changing differential channels. Once a differential channel

has been selected, the gain stage may take as much as 125 µs to stabilize to the new value.

Thus conversions should not be started within the first 125 µs after selecting a new differential

channel. Alternatively, conversion results obtained within this period should be discarded.

The same settling time should be observed for the first differential conversion after changing

ADC reference (by changing the REFS1:0 bits in ADMUX).

If the JTAG Interface is enabled, the function of ADC channels on PORTF7:4 is overridden.

Refer to Table 42, “Port F Pins Alternate Functions,” on page 83.

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ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

When switching to a differential gain channel, the first conversion result may have a poor accu-

racy due to the required settling time for the automatic offset cancellation circuitry. The user

should preferably disregard the first conversion result.

ADC Voltage

Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either AV_CC, internal 2.56V reference, or external AREF pin.

AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is gener-

ated from the internal bandgap reference (V_BG) through an internal amplifier. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and ground. V_REFcan

also be measured at the AREF pin with a high impedant voltmeter. Note that V_REFis a high

impedant source, and only a capacitive load should be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56 V as

reference selection. The first ADC conversion result after switching reference voltage source

may be inaccurate, and the user is advised to discard this result.

If differential channels are used, the selected reference should not be closer to AVCC than

indicated in Table 136 on page 325.

ADC Noise

Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

1. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be

enabled.

2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If

another interrupt wakes up the CPU before the ADC conversion is complete, that

interrupt will be executed, and an ADC Conversion Complete interrupt request will be

generated when the ADC conversion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption. If the ADC is enabled in such

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sleep modes and the user wants to perform differential conversions, the user is advised to

switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a

valid result.

Analog Input Circuitry The Analog Input circuitry for single ended channels is illustrated in Figure 113. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

If differential gain channels are used, the input circuitry looks somewhat different, although

source impedances of a few hundred kΩ or less is recommended.

Signal components higher than the Nyquist frequency (f_ADC/ 2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 113. Analog Input Circuitry

I_IH

ADCn

1..100 kΩ

C_S/H= 14 pF

I_IL

V_CC/2

Analog Noise

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

Canceling Techniques analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

1. Keep analog signal paths as short as possible. Make sure analog tracks run over the

ground plane, and keep them well away from high-speed switching digital tracks.

2. The AVCC pin on the device should be connected to the digital V_CCsupply voltage

via an LC network as shown in Figure 114.

3. Use the ADC noise canceler function to reduce induced noise from the CPU.

4. If any ADC port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

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2467P–AVR–08/07

Figure 114. ADC Power Connections

(AD0) PA0 51

VCC

GND

52

53

(ADC7) PF7 54

(ADC6) PF6 55

(ADC5) PF5 56

(ADC4) PF4 57

(ADC3) PF3 58

(ADC2) PF2 59

(ADC1) PF1

(ADC0) PF0

60

61

10mH

62

63

64

AREF

GND

AVCC

100nF

1

Offset Compensation

Schemes

The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea-

surements as much as possible. The remaining offset in the analog path can be measured

directly by selecting the same channel for both differential inputs. This offset residue can be then

subtracted in software from the measurement results. Using this kind of software based offset

correction, offset on any channel can be reduced below one LSB.

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ADC Accuracy

Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

•

Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB.

Figure 115. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

•

Gain Error: After adjusting for offset, the gain error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 116. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

•

Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

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Figure 117. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V

Input Voltage

REF

•

Differential Non-linearity (DNL): The maximum deviation of the actual code width (the

interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0

LSB.

Figure 118. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

•

Quantization Error: Due to the quantization of the input voltage into a finite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.

Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared

to an ideal transition for any code. This is the compound effect of offset, gain error,

differential error, non-linearity, and quantization error. Ideal value: 0.5 LSB.

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ADC Conversion

Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 97 on page 242 and Table 98 on page 243). 0x000 represents ground, and 0x3FF repre-

sents the selected reference voltage minus one LSB.

If differential channels are used, the result is

(V

– V

) ⋅ GAIN ⋅ 512

NEG

POS

ADC = ------------------------------------------------------------------------

V

REF

where V_POSis the voltage on the positive input pin, V_NEGthe voltage on the negative input pin,

GAIN the selected gain factor, and V_REFthe selected voltage reference. The result is presented

in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user

wants to perform a quick polarity check of the results, it is sufficient to read the MSB of the result

(ADC9 in ADCH). If this bit is one, the result is negative, and if this bit is zero, the result is posi-

tive. Figure 119 shows the decoding of the differential input range.

Table 96 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is

selected with a gain of GAIN and a reference voltage of V_REF

.

Figure 119. Differential Measurement Range

Output Code

0x1FF

0x000

0

Differential Input

Voltage (Volts)

- V_REF/GAIN

0x3FF

V

_REF/GAIN

0x200

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Table 96. Correlation Between Input Voltage and Output Codes

V_ADCn

Read code

0x1FF

0x1FE

...

Corresponding decimal value

V_ADCm+ V_REF/GAIN

511

510

...

V_ADCm+ 511/512 V_REF/GAIN

...

V

_ADCm+ 1/512 V_REF/GAIN

V_ADCm

_ADCm- 1/512 V_REF/GAIN

0x001

0x000

0x3FF

...

1

0

V

-1

...

V_ADCm- 511/512 V_REF/GAIN

0x201

0x200

-511

-512

V_ADCm- V_REF/GAIN

Example:

ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result)

Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270

ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the

result: ADCL = 0x70, ADCH = 0x02.

ADC Multiplexer

Selection Register –

ADMUX

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

MUX4

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

ADMUX

Read/Write

Initial Value

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 97. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

Table 97. Voltage Reference Selections for ADC

REFS1

REFS0 Voltage Reference Selection

0

1

0

1

0

1

AREF, Internal Vref turned off

AVCC with external capacitor at AREF pin

Reserved

Internal 2.56V Voltage Reference with external capacitor at AREF pin

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing

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conversions. For a complete description of this bit, see “The ADC Data Register – ADCL and

ADCH” on page 245.

• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

These bits also select the gain for the differential channels. See Table 98 for details. If these bits

are changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSRA is set).

Table 98. Input Channel and Gain Selections

Single Ended

MUX4..0 Input

Positive Differential

Input

Negative Differential

Input

Gain

00000

00001

00010

00011

00100

00101

00110

00111

01000⁽¹⁾

01001

01010⁽¹⁾

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

N/A

ADC0

ADC1

ADC0

ADC1

ADC2

ADC3

ADC2

ADC3

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

ADC4

ADC0

ADC2

ADC1

ADC2

10x

200x

10x

200x

1x

N/A

1x

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Table 98. Input Channel and Gain Selections (Continued)

Single Ended

MUX4..0 Input

Positive Differential

Input

Negative Differential

Input

Gain

11101

11110

11111

ADC5

N/A

ADC2

1x

1.23V (V_BG

0V (GND)

)

Note:

1. Can be used for offset calibration.

ADC Control and

Status Register A –

ADCSRA

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADFR

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

ADCSRA

Read/Write

Initial Value

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADFR: ADC Free Running Select

When this bit is written to one, the ADC operates in Free Running mode. In this mode, the ADC

samples and updates the data registers continuously. Writing zero to this bit will terminate Free

Running mode.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the data registers are updated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the

ADC.

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Table 99. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

The ADC Data

Register – ADCL and

ADCH

ADLAR = 0:

Bit

15

14

13

12

11

10

9

8

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

ADLAR = 1:

Bit

15

14

13

12

11

10

9

8

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers. If differential

channels are used, the result is presented in two’s complement form.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 241.

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JTAG Interface

and On-chip

Debug System

Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

• Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

– Program Counter

– EEPROM and Flash Memories

• Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Breakpoints on Single Address or Address Range

– Data Memory Breakpoints on Single Address or Address Range

• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• On-chip Debugging Supported by AVR Studio

Overview

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

•

Testing PCBs by using the JTAG Boundary-scan capability

Programming the non-volatile memories, Fuses and Lock bits

On-chip debugging

A brief description is given in the following sections. Detailed descriptions for Programming via

the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Program-

ming Via the JTAG Interface” on page 305 and “IEEE 1149.1 (JTAG) Boundary-scan” on page

252, respectively. The On-chip Debug support is considered being private JTAG instructions,

and distributed within ATMEL and to selected third party vendors only.

Figure 120 shows a block diagram of the JTAG interface and the On-chip Debug system. The

TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller

selects either the JTAG Instruction Register or one of several Data Registers as the scan chain

(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG

instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the data registers used for

board-level testing. The JTAG Programming Interface (actually consisting of several physical

and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal

Scan Chain and Break Point Scan Chain are used for On-chip debugging only.

Test Access Port – The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins

constitute the Test Access Port –– TAP. These pins are:

TAP

•

TMS: Test mode select. This pin is used for navigating through the TAP-controller state

machine.

•

TCK: Test clock. JTAG operation is synchronous to TCK.

TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data

Register (Scan Chains).

•

TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

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ATmega128(L)

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not

provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the

TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP

input signals are internally pulled high and the JTAG is enabled for Boundary-scan and program-

ming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP

controller is not shifting data, and must therefore be connected to a pull-up resistor or other

hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The

device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-

tored by the debugger to be able to detect External Reset sources. The debugger can also pull

the RESET pin low to reset the whole system, assuming only open collectors on the Reset line

are used in the application.

Figure 120. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

BOUNDARY SCAN CHAIN

TDI

JTAG PROGRAMMING

TDO

TAP

INTERFACE

TCK

TMS

CONTROLLER

AVR CPU

INTERNAL

SCAN

CHAIN

FLASH

MEMORY

Address

Data

PC

Instruction

INSTRUCTION

REGISTER

ID

REGISTER

BREAKPOINT

UNIT

M

U

X

FLOW CONTROL

UNIT

BYPASS

REGISTER

DIGITAL

PERIPHERAL

UNITS

BREAKPOINT

SCAN CHAIN

JTAG / AVR CORE

COMMUNICATION

INTERFACE

ADDRESS

DECODER

OCD STATUS

AND CONTROL

I/O PORT n

247

2467P–AVR–08/07

Figure 121. TAP Controller State Diagram

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

1

Shift-DR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-

scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions

depicted in Figure 121 depend on the signal present on TMS (shown adjacent to each state tran-

sition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-

Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

•

At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift

Instruction Register – Shift-IR state. While in this state, shift the 4 bits of the JTAG

instructions into the JTAG instruction register from the TDI input at the rising edge of TCK.

The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR

state. The MSB of the instruction is shifted in when this state is left by setting TMS high.

While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out

248

ATmega128(L)

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ATmega128(L)

on the TDO pin. The JTAG Instruction selects a particular Data Register as path between

TDI and TDO and controls the circuitry surrounding the selected Data Register.

•

Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is

latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-

IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.

At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift

Data Register – Shift-DR state. While in this state, upload the selected Data Register

(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI

input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must

be held low during input of all bits except the MSB. The MSB of the data is shifted in when

this state is left by setting TMS high. While the Data Register is shifted in from the TDI pin,

the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the

TDO pin.

•

Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data

Register has a latched parallel-output, the latching takes place in the Update-DR state. The

Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting

JTAG instruction and using Data Registers, and some JTAG instructions may select certain

functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.

Note:

Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be

entered by holding TMS high for 5 TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in “Bibliography”

on page 251.

Using the

Boundary-scan

Chain

A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1

(JTAG) Boundary-scan” on page 252.

Using the On-chip As shown in Figure 120, the hardware support for On-chip Debugging consists mainly of

Debug System

•

A scan chain on the interface between the internal AVR CPU and the internal peripheral

units

•

Break point unit

Communication interface between the CPU and JTAG system

All read or modify/write operations needed for implementing the Debugger are done by applying

AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O

memory mapped location which is part of the communication interface between the CPU and the

JTAG system.

The Break point Unit implements Break on Change of Program Flow, Single Step Break, two

Program Memory Breakpoints, and two combined break points. Together, the four break points

can be configured as either:

•

4 single Program Memory break points

3 Single Program Memory break point + 1 single Data Memory break point

2 single Program Memory break points + 2 single Data Memory break points

2 single Program Memory break points + 1 Program Memory break point with mask (“range

break point”)

•

2 single Program Memory break points + 1 Data Memory break point with mask “range

break point”.

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2467P–AVR–08/07

A debugger, like the AVR Studio^®, may however use one or more of these resources for its inter-

nal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG

Instructions” on page 250.

The JTAGEN fuse must be programmed to enable the JTAG Test Access Port. In addition, the

OCDEN fuse must be programmed and no Lock bits must be set for the On-chip Debug system

to work. As a security feature, the On-chip Debug system is disabled when any Lock bits are set.

Otherwise, the On-chip Debug system would have provided a back-door into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR device with

On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.

AVR Studio supports source level execution of Assembly programs assembled with Atmel Cor-

poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.

AVR Studio runs under Microsoft^®Windows^®95/98/2000 and Windows NT^®and Windows XP^®.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide found in the

Online Help in AVR Studio. Only highlights are presented in this document.

All necessary execution commands are available in AVR Studio, both on source level and on

disassembly level. The user can execute the program, single step through the code either by

tracing into or stepping over functions, step out of functions, place the cursor on a statement and

execute until the statement is reached, stop the execution, and reset the execution target. In

addition, the user can have an unlimited number of code break points (using the BREAK instruc-

tion) and up to two data memory break points, alternatively combined as a mask (range) break

point.

On-chip Debug

Specific JTAG

Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within

ATMEL and to selected third-party vendors only. Instruction opcodes are listed for reference.

PRIVATE0; $8

PRIVATE1; $9

PRIVATE2; $A

PRIVATE3; $B

Private JTAG instruction for accessing On-chip Debug system.

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ATmega128(L)

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ATmega128(L)

On-chip Debug

Related Register in

I/O Memory

On-chip Debug

Register – OCDR

Bit

7

MSB/IDRD

R/W

6

5

4

3

2

1

0

LSB

R/W

0

OCDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The OCDR Register provides a communication channel from the running program in the micro-

controller to the debugger. The CPU can transfer a byte to the debugger by writing to this

location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate

to the debugger that the register has been written. When the CPU reads the OCDR Register the

7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the

IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR

Register can only be accessed if the OCDEN fuse is programmed, and the debugger enables

access to the OCDR Register. In all other cases, the standard I/O location is accessed.

Refer to the debugger documentation for further information on how to use this register.

Using the JTAG

Programming

Capabilities

Programming of AVR parts via JTAG is performed via the four-pin JTAG port, TCK, TMS, TDI,

and TDO. These are the only pins that need to be controlled/observed to perform JTAG pro-

gramming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN

fuse must be programmed and the JTD bit in the MCUCSR Register must be cleared to enable

the JTAG Test Access Port.

The JTAG programming capability supports:

•

Flash programming and verifying

EEPROM programming and verifying

Fuse programming and verifying

Lock bit programming and verifying

The Lock bit security is exactly as in Parallel Programming mode. If the Lock bits LB1 or LB2 are

programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a

security feature that ensures no back-door exists for reading out the content of a secured

device.

The details on programming through the JTAG interface and programming specific JTAG

instructions are given in the section “Programming Via the JTAG Interface” on page 305.

Bibliography

For more information about general Boundary-scan, the following literature can be consulted:

•

IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan

Architecture, IEEE, 1993

•

Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,

1992

251

2467P–AVR–08/07

IEEE 1149.1

(JTAG) Boundary-

scan

Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the JTAG Standard

• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

• Supports the Optional IDCODE Instruction

• Additional Public AVR_RESET Instruction to Reset the AVR

System Overview

The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-

ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by

the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to

drive values at their output pins, and observe the input values received from other devices. The

controller compares the received data with the expected result. In this way, Boundary-scan pro-

vides a mechanism for testing interconnections and integrity of components on Printed Circuits

Boards by using the four TAP signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-

LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be

used for testing the Printed Circuit Board. Initial scanning of the data register path will show the

ID-code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have

the AVR device in reset during Test mode. If not reset, inputs to the device may be determined

by the scan operations, and the internal software may be in an undetermined state when exiting

the Test mode. Entering Reset, the outputs of any Port Pin will instantly enter the high imped-

ance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be

issued to make the shortest possible scan chain through the device. The device can be set in

the Reset state either by pulling the external RESET pin low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data.

The data from the output latch will be driven out on the pins as soon as the EXTEST instruction

is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for

setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST

instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the

external pins during normal operation of the part.

The JTAGEN fuse must be programmed and the JTD bit in the I/O register MCUCSR must be

cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher

than the internal chip frequency is possible. The chip clock is not required to run.

Data Registers

The data registers relevant for Boundary-scan operations are:

•

Bypass Register

Device Identification Register

Reset Register

Boundary-scan Chain

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ATmega128(L)

Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is

selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR

controller state. The Bypass Register can be used to shorten the scan chain on a system when

the other devices are to be tested.

Device Identification

Register

Figure 122 shows the structure of the Device Identification Register.

Figure 122. The Format of the Device Identification Register

LSB

MSB

Bit

31

28

27

12

11

1

0

Device ID

Version

Part Number

Manufacturer ID

1

4 bits

16 bits

11 bits

1-bit

Version

Version is a 4-bit number identifying the revision of the component. The JTAG version number

follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.

Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega128 is listed in Table 100.

Table 100. AVR JTAG Part Number

Part Number

JTAG Part Number (Hex)

ATmega128

0x9702

Manufacturer ID

The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID

for ATMEL is listed in Table 101.

Table 101. Manufacturer ID

Manufacturer

JTAG Manufacturer ID (Hex)

ATMEL

0x01F

Reset Register

The Reset Register is a Test Data Register used to reset the part. Since the AVR tri-states Port

Pins when reset, the Reset Register can also replace the function of the unimplemented optional

JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the External Reset low. The part is

reset as long as there is a high value present in the Reset Register. Depending on the Fuse set-

tings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to “Clock

Sources” on page 37) after releasing the Reset Register. The output from this Data Register is

not latched, so the Reset will take place immediately, as shown in Figure 123.

253

2467P–AVR–08/07

Figure 123. Reset Register

To

TDO

From Other Internal and

External Reset Sources

From

TDI

Internal Reset

D

Q

ClockDR · AVR_RESET

Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-

ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections.

See “Boundary-scan Chain” on page 255 for a complete description.

Boundary-scan

Specific JTAG

Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the

JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction

is not implemented, but all outputs with tri-state capability can be set in high-impedant state by

using the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which data register is selected as path between TDI and TDO for each instruction.

EXTEST; $0

Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing

circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output

Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip

connections, the interface between the analog and the digital logic is in the scan chain. The con-

tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-

register is loaded with the EXTEST instruction.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

Shift-DR: The Internal Scan Chain is shifted by the TCK input.

Update-DR: Data from the scan chain is applied to output pins.

IDCODE; $1

Optional JTAG instruction selecting the 32-bit ID Register as Data Register. The ID Register

consists of a version number, a device number and the manufacturer code chosen by JEDEC.

This is the default instruction after power-up.

The active states are:

•

Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.

Shift-DR: The IDCODE scan chain is shifted by the TCK input.

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ATmega128(L)

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ATmega128(L)

SAMPLE_PRELOAD;

$2

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the

input/output pins without affecting the system operation. However, the output latched are not

connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However,

the output latches are not connected to the pins.

AVR_RESET; $C

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or

releasing the JTAG Reset source. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as Data Register. Note that the Reset will be active as long as there

is a logic 'one' in the Reset Chain. The output from this chain is not latched.

The active states are:

•

Shift-DR: The Reset Register is shifted by the TCK input.

BYPASS; $F

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•

Capture-DR: Loads a logic “0” into the Bypass Register.

Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

Boundary-scan

Related Register in

I/O Memory

MCU Control and

Status Register –

MCUCSR

The MCU Control and Status Register contains control bits for general MCU functions, and pro-

vides information on which reset source caused an MCU Reset.

Bit

7

6

–

5

–

4

3

2

1

0

JTD

R/W

0

JTRF

R/W

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUCSR

Read/Write

Initial Value

R

0

R

0

See Bit Description

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit

is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the

JTAG interface, a timed sequence must be followed when changing this bit: The application soft-

ware must write this bit to the desired value twice within four cycles to change its value.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to

one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a Reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

Boundary-scan

Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connection.

255

2467P–AVR–08/07

Scanning the Digital

Port Pins

Figure 124 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The

cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a

bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –

ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are

not used in the following description

The Boundary-scan logic is not included in the figures in the Data Sheet. Figure 125 shows a

simple digital Port Pin as described in the section “I/O Ports” on page 66. The Boundary-scan

details from Figure 124 replaces the dashed box in Figure 125.

When no alternate port function is present, the Input Data – ID corresponds to the PINxn Regis-

ter value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 125 to make the

scan chain read the actual pin value. For Analog function, there is a direct connection from the

external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-

tal logic and the analog circuitry.

Figure 124. Boundary-scan Cell for Bi-directional Port Pin with Pull-Up Function.

ShiftDR

To Next Cell

EXTEST

Vcc

Pullup Enable (PUE)

0

1

FF2

Q

LD2

0

1

D

Q

G

Output Control (OC)

FF1

D Q

LD1

0

1

0

1

D

G

Q

Output Data (OD)

0

1

FF0

D

LD0

0

1

Port Pin (PXn)

0

1

Q

D

G

Q

Input Data (ID)

From Last Cell

ClockDR

UpdateDR

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ATmega128(L)

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ATmega128(L)

Figure 125. General Port Pin Schematic diagram

See Boundary-Scan description

for details!

PUExn

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

OCxn

Q

D

Pxn

PORTxn

ODxn

Q _CLR

WPx

RRx

IDxn

RESET

SLEEP

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

CLK _I/O

PUD:

PULLUP DISABLE

WDx:

RDx:

WPx:

RRx:

RPx:

WRITE DDRx

PUExn:

OCxn:

ODxn:

IDxn:

PULLUP ENABLE for pin Pxn

OUTPUT CONTROL for pin Pxn

OUTPUT DATA to pin Pxn

INPUT DATA from pin Pxn

SLEEP CONTROL

READ DDRx

WRITE PORTx

READ PORTx REGISTER

READ PORTx PIN

I/O CLOCK

SLEEP:

CLK _I/O

:

Boundary-scan and

The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-

the Two-wire Interface chain; Two-wire Interface Enable – TWIEN. As shown in Figure 126, the TWIEN signal enables

a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general

scan cell as shown in Figure 130 is attached to the TWIEN signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan

support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in

the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-

scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to

drive contention.

257

2467P–AVR–08/07

Figure 126. Additional Scan Signal for the Two-wire Interface

PUExn

OCxn

ODxn

Pxn

TWIEN

SRC

Slew-rate limited

IDxn

Scanning the RESET

The RESET pin accepts 5V active low logic for standard Reset operation, and 12V active high

logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 127 is

inserted both for the 5V Reset signal; RSTT, and the 12V Reset signal; RSTHV.

Figure 127. Observe-only Cell

To

cell

From system pin

To system logic

FF1

0

1

D

Q

From

ClockDR

Scanning the Clock

Pins

The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-

tor, External RC, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal

Oscillator, and Ceramic Resonator.

Figure 128 shows how each Oscillator with external connection is supported in the scan chain.

The Enable signal is supported with a general boundary-scan cell, while the Oscillator/Clock out-

put is attached to an observe-only cell. In addition to the main clock, the Timer Oscillator is

scanned in the same way. The output from the internal RC Oscillator is not scanned, as this

Oscillator does not have external connections.

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2467P–AVR–08/07

ATmega128(L)

Figure 128. Boundary-scan Cells for Oscillators and Clock Options

XTAL1/TOSC1

XTAL2/TOSC2

To

EXTEST

Oscillator

ShiftDR

cell

From Digital Logic

0

1

To System Logic

OUTPUT

ENABLE

FF1

0

1

D

Q

D

G

Q

0

1

D

Q

From

ClockDR

UpdateDR

From

ClockDR

Table 102 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator.

Table 102. Scan Signals for the Oscillators^(1)(2)(3)

Scanned Clock

Enable signal Line

Scanned Clock Line

when not Used

Clock Option

EXTCLKEN

OSCON

EXTCLK (XTAL1)

OSCCK

External Clock

0

External Crystal

External Ceramic Resonator

RCOSCEN

OSC32EN

TOSKON

RCCK

External RC

1

0

OSC32CK

TOSCK

Low Freq. External Crystal

32 kHz Timer Oscillator

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between

the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is

preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock

configuration is considered fixed for a given application. The user is advised to scan the same

clock option as to be used in the final system. The enable signals are supported in the scan

chain because the system logic can disable clock options in sleep modes, thereby disconnect-

ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported

in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-

nal capacitors to run unless the fuse is correctly programmed.

Scanning the Analog

Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 129. The

Boundary-scan cell from Figure 130 is attached to each of these signals. The signals are

described in Table 103.

The Comparator need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

259

2467P–AVR–08/07

Figure 129. Analog comparator

BANDGAP

REFERENCE

ACBG

ACO

AC_IDLE

ACME

ADCEN

ADC MULTIPLEXER

OUTPUT

Figure 130. General Boundary-scan Cell used for Signals for Comparator and ADC

To

Cell

EXTEST

From Digital Logic/

From Analog Ciruitry

0

1

To Analog Circuitry/

To Digital Logic

0

1

D

Q

D

G

Q

From

ClockDR

UpdateDR

260

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 103. Boundary-scan Signals for the Analog Comparator

Direction as

Seen from the

Comparator

Recommended

Input when not

in Use

Output values when

Recommended

Inputs are Used

Signal

Name

Description

AC_IDLE Input

Turns off Analog

comparator when

true

1

Depends upon µC

code being executed

ACO

Output

Analog

Will become

0

Comparator

Output

input to µC code

being executed

ACME

ACBG

Input

Uses output

signal from ADC

mux when true

0

Depends upon µC

code being executed

Bandgap

Depends upon µC

Reference enable

code being executed

Scanning the ADC

Figure 131 shows a block diagram of the ADC with all relevant control and observe signals. The

Boundary-scan cell from Figure 127 is attached to each of these signals. The ADC need not be

used for pure connectivity testing, since all analog inputs are shared with a digital port pin as

well.

Figure 131. Analog to Digital Converter

VCCREN

AREF

IREFEN

2.56V

ref

To Comparator

PASSEN

MUXEN_7

ADC_7

MUXEN_6

ADC_6

MUXEN_5

ADC_5

MUXEN_4

ADC_4

ADCBGEN

SCTEST

1.22V

ref

EXTCH

MUXEN_3

ADC_3

PRECH

AREF

DACOUT

COMP

MUXEN_2

ADC_2

MUXEN_1

ADC_1

MUXEN_0

ADC_0

DAC_9..0

10-bit DAC

+

-

COMP

G20

G10

ADCEN

ACTEN

GNDEN

+

NEGSEL_2

NEGSEL_1

NEGSEL_0

10x

-

20x

-

HOLD

ADC_2

ADC_1

ST

ACLK

AMPEN

ADC_0

The signals are described briefly in Table 104.

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2467P–AVR–08/07

Table 104. Boundary-scan Signals for the ADC

Direction

as Seen

from the

ADC

Recommen- Output Values when

ded Input

when not

in Use

Recommended Inputs

are Used, and CPU is

not Using the ADC

Signal

Name

Description

COMP

ACLK

Output

Input

Comparator Output

0

Clock signal to gain

stages implemented

as Switch-cap filters

ACTEN

Input

Enable path from gain

stages to the

comparator

0

ADCBGEN

Enable Band-gap

reference as negative

input to comparator

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

DAC_3

DAC_2

DAC_1

DAC_0

EXTCH

Input

Power-on signal to the

ADC

0

1

0

1

0

1

0

1

Power-on signal to the

gain stages

Bit 9 of digital value to

DAC

Bit 8 of digital value to

DAC

Bit 7 of digital value to

DAC

Bit 6 of digital value to

DAC

Bit 5 of digital value to

DAC

Bit 4 of digital value to

DAC

Bit 3 of digital value to

DAC

Bit 2 of digital value to

DAC

Bit 1 of digital value to

DAC

Bit 0 of digital value to

DAC

Connect ADC

channels 0 - 3 to by-

pass path around gain

stages

G10

G20

Input

Enable 10x gain

Enable 20x gain

0

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ATmega128(L)

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ATmega128(L)

Table 104. Boundary-scan Signals for the ADC (Continued)

Direction

as Seen

from the

ADC

Recommen- Output Values when

ded Input

when not

in Use

Recommended Inputs

are Used, and CPU is

not Using the ADC

Signal

Name

Description

GNDEN

Input

Ground the negative

input to comparator

when true

0

HOLD

Input

Sample & Hold signal.

Sample analog signal

when low. Hold signal

when high. If gain

1

stages are used, this

signal must go active

when ACLK is high.

IREFEN

Input

Enables Band-gap

reference as AREF

signal to DAC

0

MUXEN_7

MUXEN_6

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

Input

Input Mux bit 7

Input Mux bit 6

Input Mux bit 5

Input Mux bit 4

Input Mux bit 3

Input Mux bit 2

Input Mux bit 1

Input Mux bit 0

0

1

0

1

0

NEGSEL_2 Input

NEGSEL_1 Input

NEGSEL_0 Input

Input Mux for negative

input for differential

signal, bit 2

Input Mux for negative

input for differential

signal, bit 1

0

Input Mux for negative

input for differential

signal, bit 0

PASSEN

PRECH

Input

Enable pass-gate of

gain stages.

1

Precharge output latch

of comparator. (Active

low)

263

2467P–AVR–08/07

Table 104. Boundary-scan Signals for the ADC (Continued)

Direction

as Seen

from the

ADC

Recommen- Output Values when

ded Input

when not

in Use

Recommended Inputs

are Used, and CPU is

not Using the ADC

Signal

Name

Description

SCTEST

Input

Switch-cap TEST

enable. Output from

x10 gain stage send

out to Port Pin having

ADC_4

0

ST

Output of gain stages

will settle faster if this

signal is high first two

ACLK periods after

AMPEN goes high.

VCCREN

Selects Vcc as the

ACC reference

voltage.

Note:

Incorrect setting of the switches in Figure 131 will make signal contention and may damage the

part. There are several input choices to the S&H circuitry on the negative input of the output com-

parator in Figure 131. Make sure only one path is selected from either one ADC pin, Bandgap

reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 104 should

be used. The user is recommended not to use the Differential Gain stages during scan. Switch-

Cap based gain stages require fast operation and accurate timing which is difficult to obtain

when used in a scan chain. Details concerning operations of the differential gain stage is there-

fore not provided.

The AVR ADC is based on the analog circuitry shown in Figure 131 with a successive approxi-

mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is

usually to ensure that an applied analog voltage is measured within some limits. This can easily

be done without running a successive approximation algorithm: apply the lower limit on the digi-

tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit

on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with

a digital port pin as well.

When using the ADC, remember the following

•

The Port Pin for the ADC channel in use must be configured to be an input with pull-up

disabled to avoid signal contention.

•

In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when

enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before

controlling/observing any ADC signal, or perform a dummy conversion before using the first

result.

•

The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal

low (Sample mode).

As an example, consider the task of verifying a 1.5V 5% input signal at ADC channel 3 when

the power supply is 5.0V and AREF is externally connected to V_CC

.

The lower limit is:

The upper limit is:

1024 ⋅ 1,5V ⋅ 0,95 ⁄ 5V = 291 = 0x123

1024 ⋅ 1,5V ⋅ 1,05 ⁄ 5V = 323 = 0x143

264

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

The recommended values from Table 104 are used unless other values are given in the algo-

rithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown. The column

“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register

with the succeeding columns. The verification should be done on the data scanned out when

scanning in the data on the same row in the table.

Table 105. Algorithm for Using the ADC

PA3.

Data

PA3.

Control

Pullup_

Enable

Step

Actions

ADCEN

DAC

MUXEN

HOLD

PRECH

SAMPLE_

PRELOAD

1

0x200

0x08

1

0

2

3

4

5

EXTEST

1

0x200

0x123

0x08

0

1

0

Verify the

COMP bit

scanned

6

1

0x200

0x08

1

0

out to be 0

7

1

0x200

0x143

0x08

0

1

0

8

9

10

Verify the

COMP bit

scanned

11

1

0x200

0x08

1

0

out to be 1

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-

quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at

least five times the number of scan bits divided by the maximum hold time, t_hold,max

265

2467P–AVR–08/07

ATmega128

Boundary-scan

Order

Table 106 shows the Scan order between TDI and TDO when the Boundary-scan Chain is

selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The

scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in

the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the

analog circuits, which constitute the most significant bits of the scan chain regardless of which

physical pin they are connected to. In Figure 124, PXn. Data corresponds to FF0, PXn. Control

corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is

not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 106. ATmega128 Boundary-scan Order

Bit Number

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

Signal Name

AC_IDLE

ACO

Module

Comparator

ACME

AINBG

COMP

ADC

PRIVATE_SIGNAL1⁽¹⁾

ACLK

ACTEN

PRIVATE_SIGNAL1⁽²⁾

ADCBGEN

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

DAC_3

DAC_2

DAC_1

DAC_0

EXTCH

G10

G20

GNDEN

HOLD

IREFEN

MUXEN_7

266

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 106. ATmega128 Boundary-scan Order (Continued)

Bit Number

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

Signal Name

MUXEN_6

Module

ADC

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

NEGSEL_2

NEGSEL_1

NEGSEL_0

PASSEN

PRECH

SCTEST

ST

VCCREN

PEN

Programming enable (observe only)

Port E

PE0.Data

PE0.Control

PE0.Pullup_Enable

PE1.Data

PE1.Control

PE1.Pullup_Enable

PE2.Data

PE2.Control

PE2.Pullup_Enable

PE3.Data

PE3.Control

PE3.Pullup_Enable

PE4.Data

PE4.Control

PE4.Pullup_Enable

PE5.Data

PE5.Control

PE5.Pullup_Enable

PE6.Data

PE6.Control

267

2467P–AVR–08/07

Table 106. ATmega128 Boundary-scan Order (Continued)

Bit Number

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

Signal Name

PE6.Pullup_Enable

PE7.Data

Module

Port E

PE7.Control

PE7.Pullup_Enable

PB0.Data

Port B

PB0.Control

PB0.Pullup_Enable

PB1.Data

PB1.Control

PB1.Pullup_Enable

PB2.Data

PB2.Control

PB2.Pullup_Enable

PB3.Data

PB3.Control

PB3.Pullup_Enable

PB4.Data

PB4.Control

PB4.Pullup_Enable

PB5.Data

PB5.Control

PB5.Pullup_Enable

PB6.Data

PB6.Control

PB6.Pullup_Enable

PB7.Data

PB7.Control

PB7.Pullup_Enable

PG3.Data

Port G

PG3.Control

PG3.Pullup_Enable

PG4.Data

PG4.Control

PG4.Pullup_Enable

TOSC

32 kHz Timer Oscillator

TOSCON

268

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 106. ATmega128 Boundary-scan Order (Continued)

Bit Number

103

102

101

100

99

Signal Name

RSTT

Module

Reset Logic

(Observe-only)

RSTHV

EXTCLKEN

OSCON

Enable signals for main Clock/Oscillators

RCOSCEN

98

OSC32EN

97

EXTCLK (XTAL1)

OSCCK

Clock input and Oscillators for the main clock

(Observe-only)

96

95

RCCK

94

OSC32CK

93

TWIEN

TWI

92

PD0.Data

Port D

91

PD0.Control

PD0.Pullup_Enable

PD1.Data

90

89

88

PD1.Control

PD1.Pullup_Enable

PD2.Data

87

86

85

PD2.Control

PD2.Pullup_Enable

PD3.Data

84

83

82

PD3.Control

PD3.Pullup_Enable

PD4.Data

81

80

79

PD4.Control

PD4.Pullup_Enable

PD5.Data

78

77

76

PD5.Control

PD5.Pullup_Enable

PD6.Data

75

74

73

PD6.Control

PD6.Pullup_Enable

PD7.Data

72

71

70

PD7.Control

PD7.Pullup_Enable

PG0.Data

69

68

Port G

269

2467P–AVR–08/07

Table 106. ATmega128 Boundary-scan Order (Continued)

Bit Number

67

Signal Name

PG0.Control

Module

Port G

66

PG0.Pullup_Enable

PG1.Data

65

64

PG1.Control

63

PG1.Pullup_Enable

PC0.Data

62

Port C

61

PC0.Control

60

PC0.Pullup_Enable

PC1.Data

59

58

PC1.Control

57

PC1.Pullup_Enable

PC2.Data

56

55

PC2.Control

54

PC2.Pullup_Enable

PC3.Data

53

52

PC3.Control

51

PC3.Pullup_Enable

PC4.Data

50

49

PC4.Control

48

PC4.Pullup_Enable

PC5.Data

47

46

PC5.Control

45

PC5.Pullup_Enable

PC6.Data

44

43

PC6.Control

42

PC6.Pullup_Enable

PC7.Data

41

40

PC7.Control

39

PC7.Pullup_Enable

PG2.Data

38

Port G

Port A

37

PG2.Control

36

PG2.Pullup_Enable

PA7.Data

35

34

PA7.Control

33

PA7.Pullup_Enable

PA6.Data

32

270

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 106. ATmega128 Boundary-scan Order (Continued)

Bit Number

Signal Name

PA6.Control

Module

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Port A

PA6.Pullup_Enable

PA5.Data

PA5.Control

PA5.Pullup_Enable

PA4.Data

PA4.Control

PA4.Pullup_Enable

PA3.Data

PA3.Control

PA3.Pullup_Enable

PA2.Data

PA2.Control

PA2.Pullup_Enable

PA1.Data

PA1.Control

PA1.Pullup_Enable

PA0.Data

PA0.Control

PA0.Pullup_Enable

PF3.Data

Port F

PF3.Control

PF3.Pullup_Enable

PF2.Data

8

7

PF2.Control

6

PF2.Pullup_Enable

PF1.Data

5

4

PF1.Control

3

PF1.Pullup_Enable

PF0.Data

2

1

PF0.Control

0

PF0.Pullup_Enable

Notes: 1. PRIVATE_SIGNAL1 should always scanned in as zero.

2. PRIVATE_SIGNAL2 should always scanned in as zero.

271

2467P–AVR–08/07

Boundary-scan

Description

Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description.

272

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Boot Loader

Support – Read-

While-Write

Self-

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for

downloading and uploading program code by the MCU itself. This feature allows flexible applica-

tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The

Boot Loader program can use any available data interface and associated protocol to read code

and write (program) that code into the Flash memory, or read the code from the program mem-

ory. The program code within the Boot Loader section has the capability to write into the entire

Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it

can also erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot

Lock bits which can be set independently. This gives the user a unique flexibility to select differ-

ent levels of protection.

Programming

Boot Loader

Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page⁽¹⁾Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note:

1. A page is a section in the flash consisting of several bytes (see Table 123 on page 291) used

during programming. The page organization does not affect normal operation.

Application and

Boot Loader Flash

Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 133). The size of the different sections is configured by the BOOTSZ

fuses as shown in Table on page 284 and Figure 133. These two sections can have different

level of protection since they have different sets of Lock bits.

Application Section

The application section is the section of the Flash that is used for storing the application code.

The protection level for the application section can be selected by the application Boot Lock bits

(Boot Lock bits 0), see Table on page 275. The application section can never store any Boot

Loader code since the SPM instruction is disabled when executed from the application section.

Boot Loader Section – While the application section is used for storing the application code, the The Boot Loader soft-

BLS

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 109 on page 276.

Read-While-Write

and No Read-

While-Write Flash

Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is dependent on which address that is being programmed. In addition to the two

sections that are configurable by the BOOTSZ fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table

Note: on page 284 and Figure 133 on page 275. The main difference between the two sections

is:

•

When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

•

When erasing or writing a page located inside the NRWW section, the CPU is halted during

the entire operation.

Note that the user software can never read any code that is located inside the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

273

2467P–AVR–08/07

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

Read-While-Write

Section – RWW

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by a

call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown

state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader Sec-

tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy

bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read

as logical one as long as the RWW section is blocked for reading. After a programming is com-

pleted, the RWWSB must be cleared by software before reading code located in the RWW

section. See “Store Program Memory Control and Status Register – SPMCSR” on page 277. for

details on how to clear RWWSB.

No Read-While-Write

Section – NRWW

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire page erase or page write operation.

Table 107. Read-While-Write Features

Which Section does the Z-

pointer Address During the

Programming?

Which Section can be

Read During

Read-While-

Write

Supported?

Is the CPU

Halted?

Programming?

RWW section

NRWW section

None

No

Yes

No

NRWW section

Yes

Figure 132. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

Z-pointer

Addresses NRWW

Section

Z-pointer

No Read-While-Write

(NRWW) Section

Addresses RWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

274

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 133. Memory Sections⁽¹⁾

Program Memory

BOOTSZ = '10'

Program Memory

BOOTSZ = '11'

$0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

Application Flash Section

Boot Loader Flash Section

End Application

Start Boot Loader

Flashend

Start Boot Loader

Flashend

$0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

$0000

Application Flash Section

Application flash Section

End RWW, End Application

End RWW

Start NRWW, Start Boot Loader

Start NRWW

Application Flash Section

Boot Loader Flash Section

End Application

Boot Loader Flash Section

Start Boot Loader

Flashend

Note:

1. The parameters in the figure above are given in Table on page 284.

Boot Loader Lock If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives

the user a unique flexibility to select different levels of protection.

Bits

The user can select:

•

To protect the entire Flash from a software update by the MCU

To protect only the Boot Loader Flash section from a software update by the MCU

To protect only the Application Flash section from a software update by the MCU

Allow software update in the entire Flash

See Table 108 and Table 109 for further details. The Boot Lock bits can be set in software and in

Serial or Parallel Programming mode, but they can be cleared by a chip erase command only.

The general Write Lock (Lock bit mode 2) does not control the programming of the Flash mem-

ory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit mode 3) does not

control reading nor writing by LPM/SPM, if it is attempted.

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Table 108. Boot Lock Bit0 Protection Modes (Application Section)⁽¹⁾

BLB0 mode BLB02 BLB01 Protection

No restrictions for SPM or LPM accessing the Application

section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If interrupt

vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If interrupt

vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 109. Boot Lock Bit1 Protection Modes (Boot Loader Section)⁽¹⁾

BLB1

BLB1 mode BLB12

1

0

Protection

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If interrupt

vectors are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

3

4

0

LPM executing from the Application section is not allowed

to read from the Boot Loader section. If interrupt vectors

are placed in the Application section, interrupts are

disabled while executing from the Boot Loader section.

0

1

Note:

1. “1” means unprogrammed, “0´means programmed

Entering the Boot Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,

Loader Program

the Boot Reset Fuse can be programmed so that the Reset Vector Reset is pointing to the Boot

Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the

application code is loaded, the program can start executing the application code. Note that the

fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial or parallel programming interface.

Table 110. Boot Reset Fuse⁽¹⁾

BOOTRST

Reset Address

1

Reset Vector = Application Reset (address $0000)

0

Reset Vector = Boot Loader Reset (see Table 112 on page 284)

Note:

1. “1” means unprogrammed, “0´means programmed

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ATmega128(L)

Store Program

Memory Control and

Status Register –

SPMCSR

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

Bit

7

SPMIE

R/W

0

6

5

–

4

RWWSRE

R/W

3

BLBSET

R/W

2

PGWRT

R/W

0

1

PGERS

R/W

0

SPMEN

R/W

0

RWWSB

SPMCSR

Read/Write

Initial Value

R

0

R

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN

bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (page erase or page write) operation to the RWW section is initiated,

the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section can-

not be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

self-programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega128 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When Programming (page erase or page write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SPMEN will be cleared). Then, if

the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while

the Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is writ-

ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will

be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-

pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit

set, or if no SPM instruction is executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg-

ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “Reading the Fuse and Lock Bits from Software” on page 281 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes page write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a page write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire page write operation if the NRWW section is

addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes page erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase,

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2467P–AVR–08/07

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

page write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During page erase and page write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

Addressing the

Flash During Self-

Programming

The Z-pointer together with RAMPZ are used to address the SPM commands. For details on

how to use the RAMPZ, see “RAM Page Z Select Register – RAMPZ” on page 14.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 123 on page 291), the program counter can be

treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 134. Note that the page erase and page write operations are addressed

independently. Therefore it is of major importance that the Boot Loader software addresses the

same page in both the page erase and page write operation. Once a programming operation is

initiated, the address is latched and the Z-pointer/RAMPZ can be used for other operations.

The only SPM operation that does not use the Z-pointer/RAMPZ is setting the Boot Loader Lock

bits. The content of the Z-pointer/RAMPZ is ignored and will have no effect on the operation.

The (E)LPM instruction does also use the Z-pointer/RAMPZ to store the address. Since this

instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used.

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ATmega128(L)

Figure 134. Addressing the Flash During SPM⁽¹⁾

BIT 15 ZPCMSB

ZPAGEMSB

1

0

RAMPZ

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

PCWORD[PAGEMSB:0]:

00

INSTRUCTION WORD

01

02

PAGEEND

Notes: 1. The different variables used in Figure 134 are listed in Table 114 on page 285.

2. PCPAGE and PCWORD are listed in Table 124 on page 292.

Self-Programming The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the page

erase command or between a page erase and a page write operation:

the Flash

Alternative 1, fill the buffer before a page erase

•

Fill temporary page buffer

Perform a page erase

Perform a page write

Alternative 2, fill the buffer after page erase

•

Perform a page erase

Fill temporary page buffer

Perform a page write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the page erase and page write operation is addressing the same

page. See “Simple Assembly Code Example for a Boot Loader” on page 282 for an assembly

code example.

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Performing Page

Erase by SPM

To execute page erase, set up the address in the Z-pointer and RAMPZ, write “X0000011” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and

R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the

Z-pointer must be written zero during this operation.

•

Page Erase to the RWW section: The NRWW section can be read during the page erase.

Page Erase to the NRWW section: The CPU is halted during the operation.

Filling the Temporary

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

Buffer (Page Loading) “00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a page write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a System Reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

Note:

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

Performing a Page

Write

To execute page write, set up the address in the Z-pointer and RAMPZ, write “X0000101” to

SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and

R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must

be written zero during this operation.

•

Page Write to the RWW section: The NRWW section can be read during the page write.

Page Write to the NRWW section: The CPU is halted during the operation.

Using the SPM

Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling

the SPMCSR Register in software. When using the SPM interrupt, the interrupt vectors should

be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is

blocked for reading. How to move the interrupts is described in “Interrupts” on page 60.

Consideration While

Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

Prevent Reading the

RWW Section During

Self-Programming

During Self-Programming (either page erase or page write), the RWW section is always blocked

for reading. The user software itself must prevent that this section is addressed during the Self-

Programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is

busy. During Self-Programming the interrupt vector table should be moved to the BLS as

described in “Interrupts” on page 60, or the interrupts must be disabled. Before addressing the

RWW section after the programming is completed, the user software must clear the RWWSB by

writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 282 for

an example.

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ATmega128(L)

Setting the Boot

Loader Lock Bits by

SPM

To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR

and execute SPM within four clock cycles after writing SPMCSR. The only accessible lock bits

are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft-

ware update by the MCU.

Bit

R0

7

6

5

4

3

2

1

0

1

BLB12

BLB11

BLB02

BLB01

1

See Table 108 and Table 109 for how the different settings of the Boot Loader Bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It

is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the lock-bits. When pro-

gramming the Lock Bits the entire Flash can be read during the operation.

EEPROM Write

Prevents Writing to

SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Lock Bits from

Software

Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

The algorithm for reading the Fuse Low bits is similar to the one described above for reading the

Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and

SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low bits (FLB) will be

loaded in the destination register as shown below. Refer to Table 119 on page 288 for a detailed

description and mapping of the Fuse Low bits.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High bits (FHB) will be loaded in the destination register as shown below.

Refer to Table 118 on page 288 for detailed description and mapping of the Fuse High bits.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse bits, load $0002 in the Z-pointer. When an LPM instruction is

executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the

value of the Extended Fuse bits (EFB) will be loaded in the destination register as shown below.

Refer to Table 117 on page 287 for detailed description and mapping of the Fuse High bits.

Bit

Rd

7

6

5

4

3

2

1

0

–

EFB1

EFB0

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Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

Preventing Flash

Corruption

During periods of low V_CC,the Flash program can be corrupted because the supply voltage is too

low for the CPU and the Flash to operate properly. These issues are the same as for board level

systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock

bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V_CCReset Protection circuit can

be used. If a Reset occurs while a write operation is in progress, the write operation will

be completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down Sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

Programming Time for The calibrated RC Oscillator is used to time Flash accesses. Table 111 shows the typical pro-

Flash when Using

SPM

gramming time for Flash accesses from the CPU.

Table 111. SPM Programming Time.

Symbol

Min Programming Time Max Programming Time

3.7 ms 4.5 ms

Flash write (page erase, page write,

and write lock bits by SPM)

Simple Assembly

Code Example for a

Boot Loader

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during self-programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcsrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

Write_page:

;PAGESIZEB is page size in BYTES, not words

; page erase

ldi spmcsrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

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ATmega128(L)

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB);init loop variable

ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcsrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

; execute page write

subi ZL, low(PAGESIZEB)

sbci ZH, high(PAGESIZEB)

;restore pointer

;not required for PAGESIZEB<=256

ldi spmcsrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB);init loop variable

ldi loophi, high(PAGESIZEB);not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

Rdloop:

;restore pointer

lpm r0, Z+

ld

r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

lds temp1, SPMCSR

sbrs temp1, RWWSB

yet

; If RWWSB is set, the RWW section is not ready

ret

; re-enable the RWW section

ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

lds temp1, SPMCSR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcsrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

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Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

sts SPMCSR, spmcsrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

ATmega128 Boot

Loader Parameters

In Table 112 through Table 114, the parameters used in the description of the self programming

are given.

Table 112. Boot Size Configuration

Boot

Reset

Boot

Loader

Flash

Address

(start Boot

Loader

Application

Flash

Section

End

Application

section

Boot

Size

BOOTSZ1

BOOTSZ0

Pages

Section

Section)

512

words

$0000 -

$FDFF

$FE00 -

$FFFF

1

4

$FDFF

$FBFF

$F7FF

$EFFF

$FE00

$FC00

$F800

$F000

1024

words

$0000 -

$FBFF

$FC00 -

$FFFF

1

0

1

0

8

2048

words

$0000 -

$F7FF

$F800 -

$FFFF

16

32

4096

words

$0000 -

$EFFF

$F000 -

$FFFF

Note:

The different BOOTSZ fuse configurations are shown in Figure 133

Table 113. Read-While-Write Limit⁽¹⁾

Section

Pages

480

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

$0000 - $EFFF

$F000 - $FFFF

32

Note:

1. For details about these two section, see “No Read-While-Write Section – NRWW” on page

274 and “Read-While-Write Section – RWW” on page 274

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ATmega128(L)

Table 114. Explanation of Different Variables Used in Figure 134 and the Mapping to the Z-

Pointer⁽³⁾

Corresponding

Variable

Z-value

Description⁽²⁾

15

6

Most significant bit in the program counter. (The

program counter is 16 bits PC[15:0])

PCMSB

Most significant bit which is used to address the

words within one page (128 words in a page

requires 7 bits PC [6:0]).

PAGEMSB

ZPCMSB

Z16⁽¹⁾

Z7

Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

ZPAGEMSB

PCPAGE

PC[15:7]

PC[6:0]

Z16⁽¹⁾:Z8

Z7:Z1

Program counter page address: Page select, for

page erase and page write

Program counter word address: Word select, for

filling temporary buffer (must be zero during

page write operation)

PCWORD

Notes: 1. The Z-register is only 16 bits wide. Bit 16 is located in the RAMPZ register in the I/O map.

2. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.

3. See “Addressing the Flash During Self-Programming” on page 278 for details about the use of

Z-pointer during self-programming.

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Memory

Programming

Program and Data The ATmega128 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 116. The Lock bits can only be

erased to “1” with the Chip Erase command.

Memory Lock Bits

Table 115. Lock Bit Byte

Lock Bit Byte

Bit No.

Description

–

Default Value

7

6

5

4

3

2

1

0

1 (unprogrammed)

–

BLB12

Boot lock bit

Lock bit

BLB11

BLB02

BLB01

LB2

LB1

Lock bit

Note:

“1” means unprogrammed, “0´means programmed

Table 116. Lock Bit Protection Modes

Memory Lock Bits Protection Type

LB mode

LB2

LB1

1

2

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is

disabled in Parallel and SPI/JTAG Serial Programming

mode. The Fuse bits are locked in both Serial and Parallel

Programming mode.⁽¹⁾

1

0

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and SPI/JTAG Serial

Programming mode. The Fuse bits are locked in both

Serial and Parallel Programming mode.⁽¹⁾

3

BLB0 mode BLB02 BLB01

No restrictions for SPM or (E)LPM accessing the

Application section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If interrupt

vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

3

4

0

1

(E)LPM executing from the Boot Loader section is not

allowed to read from the Application section. If interrupt

vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

BLB1 mode BLB12 BLB11

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Table 116. Lock Bit Protection Modes (Continued)

Memory Lock Bits

Protection Type

No restrictions for SPM or (E)LPM accessing the Boot

Loader section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section,

and (E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If interrupt

vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader section.

3

0

(E)LPM executing from the Application section is not

allowed to read from the Boot Loader section. If interrupt

vectors are placed in the Application section, interrupts

are disabled while executing from the Boot Loader section.

4

0

1

Notes: 1. Program the fuse bits before programming the Lock bits.

2. “1” means unprogrammed, “0´means programmed

Fuse Bits

The ATmega128 has three fuse bytes. Table 117 - Table 119 describe briefly the functionality of

all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logi-

cal zero, “0”, if they are programmed.

Table 117. Extended Fuse Byte

Extended Fuse Byte

Bit No. Description

Default Value

–

7

6

5

4

3

2

1

0

–

1

–

1

–

1

–

1

–

1

–

1

M103C⁽¹⁾

WDTON⁽²⁾

ATmega103 compatibility mode

Watchdog Timer always on

0 (programmed)

1 (unprogrammed)

Notes: 1. See “ATmega103 and ATmega128 Compatibility” on page 4 for details.

2. See “Watchdog Timer Control Register – WDTCR” on page 56 for details.

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Table 118. Fuse High Byte

FuseHigh

Byte

Bit No. Description

Default Value

OCDEN⁽⁴⁾

7

Enable OCD

1 (unprogrammed, OCD

disabled)

JTAGEN⁽⁵⁾

SPIEN⁽¹⁾

6

5

Enable JTAG

0 (programmed, JTAG enabled)

Enable Serial Program and

Data Downloading

0 (programmed, SPI prog.

enabled)

CKOPT⁽²⁾

EESAVE

4

3

Oscillator options

1 (unprogrammed)

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed, EEPROM not

preserved)

BOOTSZ1

BOOTSZ0

BOOTRST

2

1

0

Select Boot Size (see Table 112

for details)

0 (programmed)⁽³⁾

1 (unprogrammed)

Select Boot Size (see Table 112

for details)

Select Reset Vector

Notes: 1. The SPIEN fuse is not accessible in SPI Serial Programming mode.

2. The CKOPT fuse functionality depends on the setting of the CKSEL bits. See “Clock

Sources” on page 37 for details.

3. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 112 on page 284

4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of lock bits

and the JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system

to be running in all sleep modes. This may increase the power consumption.

5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This

to avoid static current at the TDO pin in the JTAG interface.

Table 119. Fuse Low Byte

Fuse Low

Byte

Bit No. Description

Default Value

BODLEVEL

BODEN

SUT1

7

6

5

4

3

2

1

0

Brown out detector trigger level 1 (unprogrammed)

Brown out detector enable

Select start-up time

Select Clock source

1 (unprogrammed, BOD disabled)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Notes: 1. The default value of SUT1..0 results in maximum start-up time. See Table 14 on page 42 for

details.

2. The default setting of CKSEL3..0 results in Internal RC Oscillator @ 1 MHz. See Table 6 on

page 37 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

Latching of Fuses

The Fuse values are latched when the device enters Programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

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the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on

power-up in normal mode.

Signature Bytes

Calibration Byte

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space.

For the ATmega128 the signature bytes are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $97 (indicates 128KB Flash memory)

3. $002: $02 (indicates ATmega128 device when $001 is $97)

The ATmega128 stores four different calibration values for the internal RC Oscillator. These

bytes resides in the signature row high byte of the addresses 0x000, 0x0001, 0x0002, and

0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value is automatically

loaded into the OSCCAL Register. If other frequencies are used, the calibration value has to be

loaded manually, see “Oscillator Calibration Register – OSCCAL” on page 42 for details.

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Parallel

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATmega128. Pulses are assumed to be at

least 250 ns unless otherwise noted.

Programming

Parameters, Pin

Mapping, and

Commands

Signal Names

In this section, some pins of the ATmega128 are referenced by signal names describing their

functionality during parallel programming, see Figure 135 and Table 120. Pins not described in

the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 122.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 123.

Figure 135. Parallel Programming

+5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VCC

+5V

WR

AVCC

BS1

XA0

PB7 - PB0

DATA

XA1

PAGEL

+12 V

BS2

RESET

PA0

XTAL1

GND

Table 120. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

RDY/BSY

0: Device is busy programming, 1: Device is ready

for new command

PD1

O

OE

PD2

PD3

I

Output Enable (Active low)

Write Pulse (Active low)

WR

BS1

Byte Select 1 (“0” selects low byte, “1” selects high

byte)

PD4

PD5

I

XA0

XTAL Action Bit 0

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Table 120. Pin Name Mapping (Continued)

Signal Name in

Programming Mode Pin Name I/O Function

XA1

PD6

PD7

I

XTAL Action Bit 1

PAGEL

BS2

Program Memory and EEPROM data Page Load

Byte Select 2 (“0” selects low byte, “1” selects 2’nd

high byte)

PA0

I

DATA

PB7-0

I/O Bi-directional Data bus (Output when OE is low)

Table 121. Pin Values Used to Enter Programming Mode

PAGEL

XA1

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

XA0

BS1

Table 122. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS1)

Load Data (High or Low data byte for Flash determined by BS1)

Load Command

No Action, Idle

Table 123. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

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Table 124. No. of Words in a Page and no. of Pages in the Flash

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

64K words (128K bytes)

128 words

PC[6:0]

512

PC[15:7]

15

Table 125. No. of Words in a Page and no. of Pages in the EEPROM

EEPROM Size

Page Size

PCWORD

No. of Pages

PCPAGE

EEAMSB

4K bytes

8 bytes

EEA[2:0]

512

EEA[11:3]

8

Parallel

Programming

Enter Programming

Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5 V between V_CCand GND, and wait at least 100 µs.

2. Set RESET to “0” and toggle XTAL1 at least SIX times.

3. Set the Prog_enable pins listed in Table 121 on page 291 to “0000” and wait at least 100

ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V

has been applied to RESET, will cause the device to fail entering programming mode.

Note, if External Crystal or External RC configuration is selected, it may not be possible to apply

qualified XTAL1 pulses. In such cases, the following algorithm should be followed:

1. Set Prog_enable pins listed in Table on page 291 to “0000”.

2. Apply 4.5 - 5.5V between V_CCand GND simultaneously as 11.5 - 12.5V is applied to

RESET.

3. Wait 100 µs.

4. Re-program the fuses to ensure that External Clock is selected as clock source

(CKSEL3:0 = 0b0000) If Lock bits are programmed, a Chip Erase command must be

executed before changing the fuses.

5. Exit Programming mode by power the device down or by bringing RESET pin to 0b0.

6. Entering Programming mode with the original algorithm, as described above.

Considerations for

The loaded command and address are retained in the device during programming. For efficient

Efficient Programming programming, the following should be considered.

•

The command needs only be loaded once when writing or reading multiple memory

locations.

Skip writing the data value $FF, that is the contents of the entire EEPROM (unless the

EESAVE fuse is programmed) and Flash after a Chip Erase.

Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256-byte EEPROM. This consideration also applies to Signature bytes

reading.

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or the EEPROM are

reprogrammed.

Note:

1. The EEPRPOM memory is preserved during chip erase if the EESAVE fuse is programmed.

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Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the

Flash

The Flash is organized in pages, see Table 123 on page 291. When programming the Flash, the

program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 137 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address

the pages within the FLASH. This is illustrated in Figure 136 on page 294. Note that if less than

8 bits are required to address words in the page (pagesize < 256), the most significant bit(s) in

the address low byte are used to address the page when performing a page write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

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3. Set DATA = Address high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Set BS1 = “0”

2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high. (See Figure 137 for signal waveforms)

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

reset.

Figure 136. Addressing the Flash which is Organized in Pages

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 124 on page 292.

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Figure 137. Programming the Flash Waveforms

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW DATA LOW DATA HIGH

XX

ADDR. HIGH

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note:

“XX” is don’t care. The letters refer to the programming description above.

Programming the

EEPROM

The EEPROM is organized in pages, see Table 124 on page 292. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to “Programming the Flash” on page 293 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. C: Load Data ($00 - $FF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page:

1. Set BS1 to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page.

(See Figure 138 for signal waveforms.)

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Figure 138. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on

page 293 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”

on page 293 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

Programming the

Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”

on page 293 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “0” and BS2 to “0”.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

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Programming the

Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the

Flash” on page 293 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Programming the

The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the

Extended Fuse Bits

Flash” on page 293 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS2 to “1” and BS1 to “0”. This selects extended data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS2 to “0”. This selects low data byte.

Figure 139. Programming the Fuses

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

$40

DATA

XX

$40

DATA

XX

$40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

Programming the Lock The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on

Bits

page 293 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

Reading the Fuse and The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”

Lock Bits

on page 293 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

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4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

Figure 140. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse byte

Lock bits

0

1

0

DATA

BS2

BS1

Fuse high byte

1

BS2

Reading the Signature The algorithm for reading the Signature bytes is as follows (refer to Programming the Flash for

Bytes

details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte ($00 - $02).

3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

Reading the

Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to Programming the Flash for

details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Parallel Programming Figure 141. Parallel Programming Timing, Including some General Timing Requirements

Characteristics

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBX

t _BVWL

t_WLBX

PAGEL

t_PHPL

t_{WL WH}

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

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Figure 142. Parallel Programming Timing, Loading Sequence with Timing Requirements

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

The timing requirements shown in Figure 141 (i.e. t_DVXH, t_XHXL, and t_XLDX) also apply to loading

operation.

Figure 143. Parallel Programming Timing, Reading Sequence (Within the Same Page) with

Timing Requirements

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BHDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

Note:

The timing requirements shown in Figure 141 (i.e. t_DVXH, t_XHXL, and t_XLDX) also apply to reading

operation.

Table 126. Parallel Programming Characteristics, V_CC= 5 V 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

μA

ns

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

67

200

150

67

ns

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

ns

0

ns

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Table 126. Parallel Programming Characteristics, V_CC= 5 V 10% (Continued)

Symbol

t_XLPH

Parameter

Min

0

Typ

Max

Units

ns

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

BS1 Valid to WR Low

t_PLXH

150

67

150

67

150

0

ns

t_BVPH

t_PHPL

ns

t_PLBX

ns

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

ns

WR Pulse Width Low

ns

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

XTAL1 Low to OE Low

1

5

μs

ms

ns

3.7

7.5

0

10

t_BVDV

t_OLDV

t_OHDZ

BS1 Valid to DATA valid

OE Low to DATA Valid

0

250

ns

OE High to DATA Tri-stated

ns

Notes: 1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. t_{WLRH_CE}is valid for the Chip Erase command.

Serial

Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 127 on page 300, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO

are used to describe the serial data in and serial data out respectively. For ATmega128 these

pins are mapped to PDI and PDO.

SPI Serial

Programming Pin

Mapping

Even though the SPI Programming interface re-uses the SPI I/O module, there is one important

difference: The MOSI/MISO pins that are mapped to PB2 and PB3 in the SPI I/O module are not

used in the Programming interface. Instead, PE0 and PE1 are used for data in SPI Program-

ming mode as shown in Table 127.

Table 127. Pin Mapping SPI Serial Programming

Symbol

MOSI (PDI)

MISO (PDO)

SCK

Pins

PE0

PE1

PB1

I/O

Description

Serial data in

Serial data out

Serial clock

I

O

I

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ATmega128(L)

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ATmega128(L)

Figure 144. SPI Serial Programming and Verify⁽¹⁾

+2.7 - 5.5V

VCC

+2.7 - 5.5V⁽²⁾

PE0

PE1

PB1

PDI

AVCC

PDO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V_CC- 0.3V < AVCC < V_CC+ 0.3V, however, AVCC should always be within 2.7 - 5.5V.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-

tion. The Chip Erase operation turns the content of every memory location in both the Program

and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck≥ 12 MHz

High:> 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck≥ 12 MHz

SPI Serial

When writing serial data to the ATmega128, data is clocked on the rising edge of SCK.

Programming

Algorithm

When reading data from the ATmega128, data is clocked on the falling edge of SCK. See Figure

145 for timing details.

To program and verify the ATmega128 in the SPI Serial Programming mode, the following

sequence is recommended (See four byte instruction formats in Table 145):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

As an alternative to using the RESET signal, PEN can be held low during Power-on

Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is

important. If the programmer cannot guarantee that SCK is held low during power-up, the

PEN method cannot be used. The device must be powered down in order to commence

normal operation when using this method.

2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming

Enable serial instruction to pin MOSI.

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3. The SPI Serial Programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte ($53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all FOUR

bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The page size is found in Table 124 on

page 292. The memory page is loaded one byte at a time by supplying the 7 LSB of the

address and data together with the Load Program Memory Page instruction. To ensure

correct loading of the page, the data low byte must be loaded before data high byte is

applied for given address. The Program Memory Page is stored by loading the Write Pro-

gram Memory Page instruction with the 9 MSB of the address. If polling is not used, the

user must wait at least t_{WD_FLASH}before issuing the next page. (See Table 128).

Note: If other commands than polling (read) are applied before any write operation (Flash,

EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.

5. The EEPROM array is programmed one byte at a time by supplying the address and data

together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling is not used, the user must wait

at least t_{WD_EEPROM}before issuing the next byte. (See Table 128). In a chip erased device,

no $FFs in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page

being programmed will give the value $FF. At the time the device is ready for a new page, the

programmed value will read correctly. This is used to determine when the next page can be writ-

ten. Note that the entire page is written simultaneously and any address within the page can be

used for polling. Data polling of the Flash will not work for the value $FF, so when programming

this value, the user will have to wait for at least t_{WD_FLASH}before programming the next page. As

a chip-erased device contains $FF in all locations, programming of addresses that are meant to

contain $FF, can be skipped. See Table 128 for t_{WD_FLASH}value

Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the

address location being programmed will give the value $FF. At the time the device is ready for a

new byte, the programmed value will read correctly. This is used to determine when the next

byte can be written. This will not work for the value $FF, but the user should have the following in

mind: As a chip-erased device contains $FF in all locations, programming of addresses that are

meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed

without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and

the user will have to wait at least t_{WD_EEPROM}before programming the next byte. See Table 128

for t_{WD_EEPROM}value.

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ATmega128(L)

Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location, V_CC= 5 V

10%

Symbol

Minimum Wait Delay

t_{WD_FUSE}

4.5 ms

5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

10 ms

Figure 145. .SPI Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

(MISO)

MSB

SERIAL CLOCK INPUT

(SCK)

SAMPLE

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Table 129. SPI Serial Programming Instruction Set

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte4

Operation

Programming Enable

1010 1100

0101 0011

xxxx xxxx

Enable SPI Serial Programming after RESET

goes low.

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

Chip Erase EEPROM and Flash.

Read Program

Memory

0010 H000

aaaa aaaa

bbbb bbbb

oooo oooo Read H (high or low) data o from Program

memory at word address a:b.

Load Program

Memory Page

0100 H000

xxxx xxxx

xbbb bbbb

iiii iiii

Write H (high or low) data i to Program

Memory page at word address b. Data low

byte must be loaded before data high byte is

applied within the same address.

Write Program

Memory Page

0100 1100

1010 0000

1100 0000

0101 1000

aaaa aaaa

xxxx aaaa

0000 0000

bxxx xxxx

bbbb bbbb

xxxx xxxx

Write Program Memory Page at address a:b.

Read EEPROM

Memory

oooo oooo Read data o from EEPROM memory at

address a:b.

Write EEPROM

Memory

iiii iiii

Write data i to EEPROM memory at address

a:b.

Read Lock bits

xxoo oooo

Read Lock bits. “0” = programmed, “1” =

unprogrammed. See Table 115 on page

286 for details.

Write Lock bits

1010 1100

111x xxxx

xxxx xxxx

11ii iiii

Write Lock bits. Set bits = “0” to program Lock

bits. See Table 115 on page 286 for details.

Read Signature Byte

Write Fuse bits

0011 0000

1010 1100

xxxx xxxx

xxxx xxbb

oooo oooo Read Signature Byte o at address b.

1010 0000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.

See Table 119 on page 288 for details.

Write Fuse High Bits

1010 1100

0101 0000

1010 1000

1010 0100

0000 0000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.

See Table 118 on page 288 for details.

Write Extended Fuse

bits

xxxx xxii

Set bits = “0” to program, “1” to unprogram.

See Table 119 on page 288 for details.

Read Fuse bits

oooo oooo Read Fuse bits. “0” = programmed, “1” =

unprogrammed. See Table 119 on page

288 for details.

Read Extendend

Fuse bits

0101 0000

0101 1000

0011 1000

0000 1000

xxxx xxxx

0000 00bb

oooo oooo Read Extended Fuse bits. “0” = pro-grammed,

“1” = unprogrammed. See Table 119 on

page 288 for details.

Read Fuse High Bits

oooo oooo Read Fuse high bits. “0” = pro-grammed, “1” =

unprogrammed. See Table 118 on page

288 for details.

Read Calibration Byte

oooo oooo Read Calibration Byte o at address b.

Note:

a = address high bits

b = address low bits

H = 0 - Low byte, 1 - High Byte

o = data out

i = data in

x = don’t care

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ATmega128(L)

SPI Serial

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 322.

Programming

Characteristics

Programming Via

the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

TMS, TDI, and TDO. Control of the Reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is

default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be

cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit

will be cleared after two chip clocks, and the JTAG pins are available for programming. This pro-

vides a means of using the JTAG pins as normal port pins in running mode while still allowing In-

System Programming via the JTAG interface. Note that this technique can not be used when

using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must

be dedicated for this purpose.

As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

JTAG Instructions

useful for Programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which data register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 146.

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Figure 146. State Machine Sequence for Changing the Instruction Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

1

Shift-DR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

AVR_RESET ($C)

The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking

the device out from the Reset mode. The TAP controller is not reset by this instruction. The one

bit Reset Register is selected as Data Register. Note that the reset will be active as long as there

is a logic 'one' in the Reset Chain. The output from this chain is not latched.

The active states are:

•

Shift-DR: The Reset Register is shifted by the TCK input.

PROG_ENABLE ($4)

The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-

bit Programming Enable Register is selected as data register. The active states are the

following:

•

Shift-DR: the programming enable signature is shifted into the data register.

Update-DR: the programming enable signature is compared to the correct value, and

Programming mode is entered if the signature is valid.

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ATmega128(L)

PROG_COMMANDS

($5)

The AVR specific public JTAG instruction for entering programming commands via the JTAG

port. The 15-bit Programming Command Register is selected as data register. The active states

are the following:

•

Capture-DR: the result of the previous command is loaded into the data register.

Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous

command and shifting in the new command.

•

Update-DR: the programming command is applied to the Flash inputs.

Run-Test/Idle: one clock cycle is generated, executing the applied command.

PROG_PAGELOAD

($6)

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.

The 2048-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan

chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-

bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the

Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the

Shift-DR state by an internal state machine. This is the only active state:

•

Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically

loaded into the Flash page one byte at a time.

Note:

The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in

JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-

ming algorithm must be used.

PROG_PAGEREAD

($7)

The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.

The 2056-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan

chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Regis-

ter is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to

the Shift Register. The data are automatically transferred from the Flash page buffer byte by

byte in the Shift-DR state by an internal state machine. This is the only active state:

•

Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the

TCK input. The TDI input is ignored.

Note:

The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in

JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-

ming algorithm must be used.

Data Registers

The data registers are selected by the JTAG instruction registers described in section “Program-

ming Specific JTAG Instructions” on page 305. The data registers relevant for programming

operations are:

•

Reset Register

Programming Enable Register

Programming Command Register

Virtual Flash Page Load Register

Virtual Flash Page Read Register

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Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is

required to reset the part before entering programming mode.

A high value in the Reset Register corresponds to pulling the external Reset low. The part is

reset as long as there is a high value present in the Reset Register. Depending on the Fuse set-

tings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to “Clock

Sources” on page 37) after releasing the Reset Register. The output from this Data Register is

not latched, so the reset will take place immediately, as shown in Figure 123 on page 254.

Programming Enable

Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared

to the programming enable signature, binary code 1010_0011_0111_0000. When the contents

of the register is equal to the programming enable signature, programming via the JTAG port is

enabled. The Register is reset to 0 on Power-on Reset, and should always be reset when leav-

ing Programming mode.

Figure 147. Programming Enable Register

TDI

$A370

D

Q

A

T

A

Programming enable

=

ClockDR & PROG_ENABLE

TDO

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ATmega128(L)

Programming

Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in

programming commands, and to serially shift out the result of the previous command, if any. The

JTAG Programming Instruction Set is shown in Table 130. The state sequence when shifting in

the programming commands is illustrated in Figure 149.

Figure 148. Programming Command Register

TDI

S

T

R

O

B

E

S

Flash

EEPROM

A

Fuses

D

Lock Bits

D

R

E

S

/

D

A

T

A

TDO

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Table 130. JTAG Programming Instruction

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

Instruction

TDI sequence

TDO sequence

Notes

1a. Chip erase

0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1b. Poll for chip erase complete

2a. Enter Flash Write

0110011_10000000

0100011_00010000

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

2b. Load Address High Byte

2c. Load Address Low Byte

2d. Load Data Low Byte

2e. Load Data High Byte

2f. Latch Data

(9)

0010111_iiiiiiii

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

2h. Poll for Page Write complete

3a. Enter Flash Read

0110111_00000000

0100011_00000010

0000111_aaaaaaaa

0000011_bbbbbbbb

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

3b. Load Address High Byte

3c. Load Address Low Byte

3d. Read Data Low and High Byte

(9)

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

low byte

high byte

4a. Enter EEPROM Write

4b. Load Address High Byte

4c. Load Address Low Byte

4d. Load Data Byte

0100011_00010001

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(9)

4e. Latch Data

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(1)

4f. Write EEPROM Page

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

4g. Poll for Page Write complete

5a. Enter EEPROM Read

0110011_00000000

0100011_00000011

0000111_aaaaaaaa

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

5b. Load Address High Byte

(9)

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Table 130. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

Instruction

TDI sequence

TDO sequence

Notes

5c. Load Address Low Byte

5d. Read Data Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

6a. Enter Fuse Write

0100011_01000000

xxxxxxx_xxxxxxxx

6b. Load Data Low Byte⁽⁶⁾

0010011_iiiiiiii

(3)

(1)

6c. Write Fuse Extended byte

0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

6d. Poll for Fuse Write complete

6e. Load Data Low Byte⁽⁷⁾

6f. Write Fuse High byte

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

(1)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

6g. Poll for Fuse Write complete

6h. Load Data Low Byte⁽⁷⁾

6i. Write Fuse Low byte

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

(1)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

6j. Poll for Fuse Write complete

7a. Enter Lock bit Write

7b. Load Data Byte⁽⁹⁾

0110011_00000000

0100011_00100000

0010011_11iiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(4)

(1)

7c. Write Lock bits

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

7d. Poll for Lock bit Write complete

8a. Enter Fuse/Lock bit Read

8b. Read Extended Fuse Byte⁽⁶⁾

0110011_00000000

0100011_00000100

xxxxxox_xxxxxxxx

(2)

xxxxxxx_xxxxxxxx

0111010_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

8c. Read Fuse High Byte⁽⁷⁾

8d. Read Fuse Low Byte⁽⁸⁾

8e. Read Lock bits⁽⁹⁾

0111110_00000000

0111111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(5)

xxxxxxx_xxoooooo

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Table 130. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

Instruction

TDI sequence

TDO sequence

Notes

8f. Read Fuses and Lock bits

0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

fuse ext. byte

fuse high byte

fuse low byte

lock bits

9a. Enter Signature Byte Read

9b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

9c. Read Signature Byte

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

10b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

10c. Read Calibration Byte

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

11a. Load No Operation Command

0100011_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

normally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 117 on page 287

7. The bit mapping for Fuses High byte is listed in Table 118 on page 288

8. The bit mapping for Fuses Low byte is listed in Table 119 on page 288

9. The bit mapping for Lock bits byte is listed in Table 115 on page 286

10. Address bits exceeding PCMSB and EEAMSB (Table 123 and Table 124) are don’t care

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Figure 149. State Machine Sequence for Changing/Reading the Data Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

Virtual Flash Page

Load Register

The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of

bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically trans-

ferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting

with the LSB of the first instruction in the page and ending with the MSB of the last instruction in

the page. This provides an efficient way to load the entire Flash page buffer before executing

Page Write.

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2467P–AVR–08/07

Figure 150. Virtual Flash Page Load Register

STROBES

ADDRESS

State

machine

TDI

Flash

EEPROM

Fuses

Lock Bits

D

A

T

A

TDO

Virtual Flash Page

Read Register

The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of

bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically

transferred from the Flash data page byte by byte. The first eight cycles are used to transfer the

first byte to the internal Shift Register, and the bits that are shifted out during these 8 cycles

should be ignored. Following this initialization, data are shifted out starting with the LSB of the

first instruction in the page and ending with the MSB of the last instruction in the page. This pro-

vides an efficient way to read one full Flash page to verify programming.

Figure 151. Virtual Flash Page Read Register

STROBES

State

machine

TDI

ADDRESS

Flash

EEPROM

Fuses

Lock Bits

D

A

T

A

TDO

Programming

Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 130.

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EnteringProgramming 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

Mode

2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming

Enable Register.

Leaving Programming 1. Enter JTAG instruction PROG_COMMANDS.

Mode

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming

Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.

2. Start chip erase using programming instruction 1a.

3. Poll for chip erase complete using programming instruction 1b, or wait for t_{WLRH_CE}(refer

to Table Note: on page 299).

Programming the

Flash

Before programming the Flash a Chip Erase must be performed. See “Performing Chip Erase”

on page 315.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address high byte using programming instruction 2b.

4. Load address low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer to

Table Note: on page 299).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to

Table 123 on page 291) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page, starting with the LSB

of the first instruction in the page and ending with the MSB of the last instruction in the

page.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer to

Table Note: on page 299).

9. Repeat steps 3 to 8 until all data have been programmed.

315

2467P–AVR–08/07

Reading the Flash

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to

Table 123 on page 291) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page by shifting out all instruction words in the page, starting with the

LSB of the first instruction in the page and ending with the MSB of the last instruction in

the page. Remember that the first 8 bits shifted out should be ignored.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

Programming the

EEPROM

Before programming the EEPROM a Chip Erase must be performed. See “Performing Chip

Erase” on page 315.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address high byte using programming instruction 4b.

4. Load address low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for t_WLRH

(refer to Table Note: on page 299).

9. Repeat steps 3 to 8 until all data have been programmed.

Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM

Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM

316

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Programming the

Fuses

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data byte using programming instructions 6b. A bit value of “0” will program the cor-

responding fuse, a “1” will unprogram the fuse.

4. Write Extended Fuse byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for t_WLRH(refer to

Table Note: on page 299).

6. Load data byte using programming instructions 6e. A bit value of “0” will program the cor-

responding fuse, a “1” will unprogram the fuse.

7. Write Fuse high byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for t_WLRH(refer to

Table Note: on page 299).

9. Load data byte using programming instructions 6h. A “0” will program the fuse, a “1” will

unprogram the fuse.

10. Write Fuse low byte using programming instruction 6i.

11. Poll for Fuse write complete using programming instruction 6j, or wait for t_WLRH(refer to

Table Note: on page 299).

Programming the Lock 1. Enter JTAG instruction PROG_COMMANDS.

Bits

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the corre-

sponding lock bit, a “1” will leave the lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for t_WLRH(refer

to Table Note: on page 299).

Reading the Fuses

and Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8f.

To only read Extended Fuse byte, use programming instruction 8b.

To only read Fuse high byte, use programming instruction 8c.

To only read Fuse low byte, use programming instruction 8d.

To only read Lock bits, use programming instruction 8e.

Reading the Signature 1. Enter JTAG instruction PROG_COMMANDS.

Bytes

2. Enable Signature byte read using programming instruction 9a.

3. Load address $00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address $01 and address $02 to read the second and third

signature bytes, respectively.

Reading the

1. Enter JTAG instruction PROG_COMMANDS.

Calibration Byte

2. Enable Calibration byte read using programming instruction 10a.

3. Load address $00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

317

2467P–AVR–08/07

Electrical Characteristics

Note:

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manu-

factured on the same process technology. Min and Max values will be available after the device is characterized.

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins..................... 200.0 - 400.0mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 2.7V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

Input Low Voltage except

XTAL1 and RESET pins

(1)

V_IL

V_CC=2.7 - 5.5.

-0.5

0.2 V_CC

V

Input High Voltage except

XTAL1 and RESET pins

(2)

V_IH

V_CC=2.7 - 5.5.

0.6 V_CC

-0.5

V_CC+ 0.5

V

Input Low Voltage

XTAL1 pin

(1)

V_IL1

V_IH1

V_IL2

V_CC=2.7 - 5.5.

0.1 V_CC

Input High Voltage XTAL1

(2)

0.7 V_CC

-0.5

V_CC+ 0.5

Input Low Voltage

RESET pin

(1)

0.2 V_CC

Input High Voltage

RESET pin

(2)

V_IH2

V_OL

V_OH

I_IL

V_CC=2.7 - 5.5.

0.85 V_CC

V_CC+ 0.5

Output Low Voltage⁽³⁾

(Ports A,B,C,D, E, F, G)

I_OL= 20 mA, V_CC= 5V

0.7

0.5

V

I

_OL= 10 mA, V_CC= 3V

Output High Voltage⁽⁴⁾

(Ports A,B,C,D, E, F, G)

I

_OH= -20 mA, V_CC= 5V

4.2

2.2

V

I_OH= -10 mA, V_CC= 3V

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin low

(absolute value)

1.0

µA

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin high

(absolute value)

I_IH

R_RST

R_PEN

R_PU

Reset Pull-up Resistor

PEN Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

318

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

T_A= -40°C to 85°C, V_CC= 2.7V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

Min

Typ

Max

Units

Active 4 MHz, V_CC= 3V

(ATmega128L)

5.5

mA

Active 8 MHz, V_CC= 5V

(ATmega128)

19

2.5

11

mA

Power Supply Current

Idle 4 MHz, V_CC= 3V

(ATmega128L)

I_CC

Idle 8 MHz, V_CC= 5V

(ATmega128)

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

< 15

< 5

25

10

µA

Power-down mode

Analog Comparator

Input Offset Voltage

V_CC= 5V

V_in= V_CC/2

V_ACIO

I_ACLK

t_ACPD

40

50

mV

nA

ns

Analog Comparator

Input Leakage Current

V_CC= 5V

V_in= V_CC/2

-50

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 5.0V

750

500

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

TQFP and QFN/MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA.

3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA.

4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA.

5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state

conditions (non-transient), the following must be observed:

TQFP and QFN/MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA.

3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA.

4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA.

5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

External Clock

Figure 152. External Clock Drive Waveforms

Drive Waveforms

V

IH1

V

IL1

319

2467P–AVR–08/07

External Clock

Drive

Table 131. External Clock Drive

V_CC= 2.7V to 5.5V

V_CC= 4.5V to 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

0

Max

Min

0

Max

Units

MHz

ns

8

16

125

50

62.5

25

t_CHCX

t_CLCX

ns

Low Time

50

25

ns

t_CLCH

Rise Time

1.6

0.5

μs

t_CHCL

Fall Time

μs

Change in period from

one clock cycle to the

2

%

Δt_CLCL

Table 132. External RC Oscillator, Typical Frequencies

R [kΩ]⁽¹⁾

C [pF]

22

f⁽²⁾

33

650 kHz

10

22

2.0 MHz

Notes: 1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in

the table includes pin capacitance. This will vary with package type.

2. The frequency will vary with package type and board layout.

320

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Two-wire Serial Interface Characteristics

Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial

Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 153.

Table 133. Two-wire Serial Bus Requirements

Symbol Parameter

Condition

Min

-0.5

Max

0.3 V_CC

V_CC+ 0.5

–

Units

V

V_IL

Input Low-voltage

V_IH

V_hys

Input High-voltage

0.7 V_CC

V

(1)

(2)

Hysteresis of Schmitt Trigger Inputs

Output Low-voltage

0.05 V_CC

V

V_OL

t_r⁽¹⁾

3 mA sink current

0

0.4

V

(3)(2)

Rise Time for both SDA and SCL

Output Fall Time from V_IHminto V_ILmax

Spikes Suppressed by Input Filter

Input Current each I/O Pin

Capacitance for each I/O Pin

SCL Clock Frequency

20 + 0.1C_b

300

ns

µA

pF

kHz

(1)

t_of

10 pF < C_b< 400 pF⁽³⁾

0.1 V_CC< V_i< 0.9 V_CC

20 + 0.1C_b

250

t_SP

I_i

C_i⁽¹⁾

f_SCL

0

-10

–

50⁽²⁾

(1)

10

f_CK⁽⁴⁾> max(16f_SCL, 250kHz)⁽⁵⁾

0

400

V_CC– 0,4V

----------------------------

3mA

f_SCL≤ 100 kHz

1000ns

C_b

-------------------

Ω

Rp

Value of Pull-up resistor

V_CC– 0,4V

----------------------------

3mA

f

_SCL> 100 kHz

300ns

---------------

C_b

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz⁽⁶⁾

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0

–

µs

ns

µs

t_HD;STA

Hold Time (repeated) START Condition

Low Period of the SCL Clock

High period of the SCL clock

Set-up time for a repeated START condition

Data hold time

–

t_LOW

f

_SCL> 100 kHz⁽⁷⁾

–

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

–

t_HIGH

–

t_SU;STA

t_HD;DAT

t_SU;DAT

–

3.45

0.9

–

f

_SCL> 100 kHz

0

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

250

100

4.0

0.6

Data setup time

–

t_SU;STO

Setup time for STOP condition

–

Bus free time between a STOP and START

condition

t_BUF

f_SCL≤ 100 kHz

4.7

–

µs

Notes: 1. In ATmega128, this parameter is characterized and not 100% tested.

2. Required only for f_SCL> 100 kHz.

3. C_b= capacitance of one bus line in pF.

4. f_CK= CPU clock frequency

321

2467P–AVR–08/07

5. This requirement applies to all ATmega128 Two-wire Serial Interface operation. Other devices

connected to the Two-wire Serial Bus need only obey the general f_SCLrequirement.

6. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/f_SCL- 2/f_CK),

thus f_CKmust be greater than 6 MHz for the low time requirement to be strictly met at f_SCL

100 kHz.

=

7. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/f_SCL- 2/f_CK),

thus the low time requirement will not be strictly met for f_SCL> 308 kHz when f_CK= 8 MHz. Still,

ATmega128 devices connected to the bus may communicate at full speed (400 kHz) with other

ATmega128 devices, as well as any other device with a proper t_LOWacceptance margin.

Figure 153. Two-wire Serial Bus Timing

t

HIGH

t

r

of

t

LOW

SCL

SDA

t

HD;DAT

SU;STA

HD;STA

t

SU;DAT

t

SU;STO

t

BUF

SPI Timing

See Figure 154 and Figure 155 for details.

Characteristics

Table 134. SPI Timing Parameters

Description

SCK period

SCK high/low

Rise/Fall time

Setup

Mode

Master

Slave

Min

Typ

See Table 72

Max

1

2

50% duty cycle

3

3.6

10

4

5

Hold

10

ns

6

Out to SCK

SCK to out

SCK to out high

SS low to out

SCK period

SCK high/low⁽¹⁾

Rise/Fall time

Setup

0.5 • t_sck

10

7

8

10

9

15

10

11

12

13

14

15

16

17

18

Slave

4 • t_ck

2 • t_ck

Slave

1.6

µs

ns

Slave

10

Hold

Slave

SCK to out

SCK to SS high

SS high to tri-state

SS low to SCK

Slave

15

10

Slave

20

Slave

2 • t_ck

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

- 2 t_CLCLfor f_CK< 12 MHz

- 3 t_CLCLfor f_CK>12 MHz

322

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 154. SPI Interface Timing Requirements (Master Mode)

SS

6

1

2

3

SCK

(CPOL = 0)

2

SCK

(CPOL = 1)

4

5

MISO

(Data Input)

MSB

...

LSB

7

8

MOSI

(Data Output)

MSB

...

LSB

Figure 155. SPI Interface Timing Requirements (Slave Mode)

18

SS

10

16

9

SCK

(CPOL = 0)

11

SCK

(CPOL = 1)

13

14

12

MOSI

(Data Input)

MSB

...

LSB

15

17

MISO

(Data Output)

MSB

...

LSB

X

323

2467P–AVR–08/07

ADC Characteristics

Table 135. ADC Characteristics, Single Ended Channels

Symbol Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Resolution

Single Ended Conversion

10

Bits

Single Ended Conversion

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

1.5

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V

3.25

ADC clock = 1 MHz

Absolute Accuracy

Single Ended Conversion

(Including INL, DNL, Quantization Error, Gain

and Offset Error)

V_REF= 4V, V_CC= 4V

1.5

LSB

ADC clock = 200 kHz

Noise Reduction mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V

ADC clock = 1 MHz

3.75

Noise Reduction mode

Single Ended Conversion

Integral Non-Linearity (INL)

Differential Non-Linearity (DNL)

Gain Error

V

_REF= 4V, V_CC= 4V

0.75

0.5

1

LSB

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

Single Ended Conversion

Offset error

V_REF= 4V, V_CC= 4V

1

ADC clock = 200 kHz

Clock Frequency

50

13

1000

260

kHz

µs

V

Conversion Time

AVCC

V_REF

V_IN

Analog Supply Voltage

Reference Voltage

V

_CC- 0.3⁽²⁾

V_CC+ 0.3⁽³⁾

AVCC

V_REF

2.0

V

Input Voltage

GND

V

Input Bandwidth

38.5

kHz

V

V_INT

R_REF

R_AIN

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

2.3

55

2.56

32

2.7

kΩ

MΩ

100

Notes: 1. Values are guidelines only.

2. Minimum for AVCC is 2.7V.

3. Maximum for AVCC is 5.5V

324

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 136. ADC Characteristics, Differential Channels

Symbol Parameter

Condition

Gain = 1x

Gain = 10x

Gain = 200x

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

10

Units

Bits

Resolution

10

Bits

10

Bits

Gain = 1x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

17

7

LSB

Gain = 10x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Absolute Accuracy

Gain = 200x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Gain = 1x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

1.5

2

Integral Non-Linearity (INL)

Gain = 10x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

(Accuracy after Calibration for Offset and

Gain Error)

Gain = 200x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

5

Gain = 1x

Gain = 10x

Gain = 200x

1.5

0.5

%

Gain Error

Gain = 1x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

2

3

4

LSB

Gain = 10x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Offset Error

Gain = 200x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Clock Frequency

Conversion Time

50

65

200

260

kHz

µs

V

AVCC

V_REF

V_IN

Analog Supply Voltage

Reference Voltage

Input Voltage

V_CC- 0.3⁽²⁾

V_CC+ 0.3⁽³⁾

AVCC - 0.5

V_CC

2.0

V

GND

V

V_DIFF

Input Differential Voltage

ADC Conversion Output

Input Bandwidth

-V_REF/Gain

-511

V_REF/Gain

511

V

LSB

kHz

4

325

2467P–AVR–08/07

Table 136. ADC Characteristics, Differential Channels (Continued)

Symbol Parameter Condition

Min⁽¹⁾

Typ⁽¹⁾

2.56

32

Max⁽¹⁾

Units

V

V_INT

R_REF

R_AIN

Internal Voltage Reference

2.3

2.7

Reference Input Resistance

Analog Input Resistance

kΩ

55

100

MΩ

Notes: 1. Values are guidelines only.

2. Minimum for AVCC is 2.7V.

3. Maximum for AVCC is 5.5V.

326

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

External Data Memory Timing

Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

8 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

0.0

16

115

1.0t_CLCL-10

0.5t_CLCL-5⁽¹⁾

t_AVLL

Address Valid A to ALE Low

57.5

ns

Address Hold After ALE Low,

write access

5

3a

t_{LLAX_ST}

ns

Address Hold after ALE Low,

read access

5

3b

4

t_{LLAX_LD}

t_AVLLC

t_AVRL

ns

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

ALE Low to RD Low

57.5

115

47.5

40

0.5t_CLCL-5⁽¹⁾

1.0t_CLCL-10

0.5t_CLCL-15⁽²⁾

40

5

6

t_AVWL

t_LLWL

7

67.5

0.5t_CLCL+5⁽²⁾

8

t_LLRL

9

t_DVRH

t_RLDV

t_RHDX

t_RLRH

t_DVWL

t_WHDX

t_DVWH

t_WLWH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

RD Pulse Width

10

11

12

13

14

15

16

75

1.0t_CLCL-50

0

115

42.5

115

125

115

1.0t_CLCL-10

0.5t_CLCL-20⁽¹⁾

1.0t_CLCL-10

1.0t_CLCL

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

1.0t_CLCL-10

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

8 MHz Oscillator

Variable Oscillator

Min Max

Symbol

Parameter

Min

Max

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

16

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

200

2.0t_CLCL-50

240

2.0t_CLCL-10

2.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0t_CLCL-10

ns

327

2467P–AVR–08/07

Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

16

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

325

3.0t_CLCL-50

365

375

365

3.0t_CLCL-10

3.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-10

ns

Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

16

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

14 t_WHDX

15 t_DVWH

16 t_WLWH

325

3.0t_CLCL-50

365

240

375

365

3.0t_CLCL-10

2.0t_CLCL-10

3.0t_CLCL

ns

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-10

ns

Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state

4 MHz Oscillator

Variable Oscillator

Symbol

1/t_CLCL

t_LHLL

Parameter

Min

Max

Min

0.0

Max

Unit

MHz

ns

0

1

2

Oscillator Frequency

ALE Pulse Width

8

235

115

t_CLCL-15

0.5t_CLCL-10⁽¹⁾

t_AVLL

Address Valid A to ALE Low

ns

Address Hold After ALE Low,

write access

5

3a t_{LLAX_ST}

ns

Address Hold after ALE Low,

read access

5

3b t_{LLAX_LD}

ns

4

5

6

7

8

9

t_AVLLC

t_AVRL

t_AVWL

t_LLWL

t_LLRL

Address Valid C to ALE Low

Address Valid to RD Low

Address Valid to WR Low

ALE Low to WR Low

115

235

115

45

0.5t_CLCL-10⁽¹⁾

1.0t_CLCL-15

0.5t_CLCL-10⁽²⁾

45

130

0.5t_CLCL+5⁽²⁾

ALE Low to RD Low

t_DVRH

Data Setup to RD High

Read Low to Data Valid

Data Hold After RD High

10 t_RLDV

11 t_RHDX

190

1.0t_CLCL-60

0

328

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)

4 MHz Oscillator Variable Oscillator

Min Max

Symbol

12 t_RLRH

Parameter

Min

Max

Unit

ns

RD Pulse Width

235

105

235

250

235

1.0t_CLCL-15

0.5t_CLCL-20⁽¹⁾

1.0t_CLCL-15

1.0t_CLCL

13 t_DVWL

14 t_WHDX

15 t_DVWH

16 t_WLWH

Data Setup to WR Low

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

1.0t_CLCL-15

ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

4 MHz Oscillator

Variable Oscillator

Min Max

Symbol

Parameter

Min

Max

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

8

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

440

2.0t_CLCL-60

485

500

485

2.0t_CLCL-15

2.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

2.0t_CLCL-15

ns

Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

8

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

15 t_DVWH

16 t_WLWH

690

3.0t_CLCL-60

735

750

735

3.0t_CLCL-15

3.0t_CLCL

ns

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-15

ns

Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

4 MHz Oscillator Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

8

Unit

MHz

ns

0

1/t_CLCL

Oscillator Frequency

Read Low to Data Valid

RD Pulse Width

0.0

10 t_RLDV

12 t_RLRH

14 t_WHDX

15 t_DVWH

16 t_WLWH

690

3.0t_CLCL-60

735

485

750

735

3.0t_CLCL-15

2.0t_CLCL-15

3.0t_CLCL

ns

Data Hold After WR High

Data Valid to WR High

WR Pulse Width

ns

3.0t_CLCL-15

ns

329

2467P–AVR–08/07

Figure 156. External Memory Timing (SRWn1 = 0, SRWn0 = 0

T1

T2

T3

T4

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

T1

T2

T3

T4

T5

System Clock (CLK_CPU

)

1

ALE

4

2

7

A15:8 Prev. addr.

Address

15

3a

3b

13

Data

16

DA7:0 Prev. data

Address

6

XX

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

330

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 158. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

T1

T2

T3

T4

T5

T6

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 1)⁽¹⁾

T1

T2

T3

T4

T5

T6

T7

System Clock (CLK_CPU

)

1

ALE

4

2

7

Address

15

A15:8 Prev. addr.

3a

3b

13

DA7:0 Prev. data

Address

6

XX

Data

16

14

WR

9

11

DA7:0 (XMBK = 0)

Address

5

Data

10

8

12

RD

Note:

1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the

RAM (internal or external).

331

2467P–AVR–08/07

ATmega128

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock

source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f where

C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

Active Supply Current Figure 160. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

3.5

3

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

2.5

2

1.5

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

332

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 161. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

45

40

35

30

25

5.0 V

4.5 V

20

4.0 V

15

3.6 V

3.3 V

3.0 V

10

2.7 V

5

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 162. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

4

25 ˚C

-40 ˚C

85 ˚C

3.5

3

2.5

2

1.5

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

333

2467P–AVR–08/07

Figure 163. Active Supply Current vs. V_CC(Internal RC Oscillator, 2 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 2 MHz

8

7

6

5

4

3

2

1

0

-40 °C

25 °C

85 °C

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 164. Active Supply Current vs. V_CC(Internal RC Oscillator, 4 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 4 MHz

14

12

10

8

-40 °C

25 °C

85 °C

6

4

2

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

334

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 165. Active Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

25

20

15

10

5

-40 °C

25 °C

85 °C

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 166. Active Supply Current vs. V_CC(32 kHz External Oscillator)

ACTIVE SUPPLY CURRENT vs. V_CC

32 kHz EXTERNAL OSCILLATOR

140

120

100

80

60

40

20

0

25 °C

2.5

3

3.5

4

4.5

5

5.5

VCC (V)

335

2467P–AVR–08/07

Idle Supply Current

Figure 167. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

1.4

1.2

1

5.5 V

5.0 V

4.5 V

4.0 V

0.8

0.6

0.4

0.2

0

3.6 V

3.3 V

3.0 V

2.7 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 168. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

25

20

15

10

5

5.5 V

5.0 V

4.5 V

4.0 V

3.6 V

3.3 V

3.0 V

2.7 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

336

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 169. Idle Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

1.6

1.4

1.2

1

85 °C

25 °C

-40 °C

0.8

0.6

0.4

0.2

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 170. Idle Supply Current vs. V_CC(Internal RC Oscillator, 2 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 2 MHz

3

2.5

2

85 °C

25 °C

-40 °C

1.5

1

0.5

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

337

2467P–AVR–08/07

Figure 171. Idle Supply Current vs. V_CC(Internal RC Oscillator, 4 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 4 MHz

6

5

4

3

2

1

0

-40 °C

25 °C

85 °C

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 172. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

12

10

8

-40 °C

25 °C

85 °C

6

4

2

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

338

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 173. Idle Supply Current vs. V_CC(32 kHz External Oscillator)

IDLE SUPPLY CURRENT vs. V_CC

32 kHz EXTERNAL OSCILLATOR

60

50

40

30

20

10

0

25 °C

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Power-down Supply

Current

Figure 174. Power-down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

4.5

4

3.5

3

85 ˚C

2.5

2

1.5

1

-40 ˚C

25 ˚C

0.5

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

339

2467P–AVR–08/07

Figure 175. Power-down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

35

30

25

20

15

10

5

85 ˚C

25 ˚C

-40 ˚C

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Power-save Supply

Current

Figure 176. Power-save Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-SAVE SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

16

25 °C

14

12

10

8

6

4

2

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

340

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Standby Supply

Current

Figure 177. Standby Supply Current vs. V_CC,

STANDBY SUPPLY CURRENT vs. V_CC

0.2

0.18

0.16

0.14

0.12

0.1

6 MHz Xtal

6 MHz Res

4 MHz Res

4 MHz Xtal

2 MHz Res

2 MHz Xtal

0.08

0.06

0.04

0.02

0

455 kHz Res

1 MHz Res

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 178. Standby Supply Current vs. V_CC(CKOPT programmed)

STANDBY SUPPLY CURRENT vs. V_CC

CKOPT programmed

2.5

2

16 MHz Xtal

12 MHz Xtal

1.5

1

6 MHz Xtal

4 MHz Xtal

0.5

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

341

2467P–AVR–08/07

Pin Pull-up

Figure 179. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V

160

140

25 °C

85 °C

120

-40 °C

100

80

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V

_OP(V)

Figure 180. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V

80

25 °C

85 °C

70

60

-40 °C

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_OP(V)

342

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Pin Driver Strength

Figure 181. I/O Pin Source Current vs. Output Voltage (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

90

80

70

60

50

40

30

20

10

0

-40 °C

25 °C

85 °C

2.5

3

3.5

4

4.5

5

V

_OH(V)

Figure 182. I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

30

-40 °C

25 °C

85 °C

25

20

15

10

5

0

0.5

1

1.5

2

2.5

3

V

_OH(V)

343

2467P–AVR–08/07

Figure 183. I/O Pin Sink Current vs. Output Voltage (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

90

-40 °C

80

70

60

50

40

30

20

10

0

25 °C

85 °C

0

0.5

1

1.5

2

2.5

V

_OL(V)

Figure 184. I/O Pin Sink Current vs. Output Voltage, V_CC= 2.7V

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

35

30

25

20

15

10

5

-40 °C

25 °C

85 °C

0

0.5

1

1.5

2

2.5

V

_OL(V)

344

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Pin Thresholds and

Hysteresis

Figure 185. I/O Pin Input Threshold Voltage vs. V_CC(VIH, I/O Pin Read as ‘1’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

2.2

2

-40 °C

25 °C

85 °C

1.8

1.6

1.4

1.2

1

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 186. I/O Pin Input Threshold Voltage vs. V_CC(VIH, I/O Pin Read as ‘0’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

1.6

1.5

1.4

1.3

1.2

1.1

1

-40 °C

25 °C

85 °C

0.9

0.8

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

345

2467P–AVR–08/07

Figure 187. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V_CC

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

85 °C

25 °C

-40 °C

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

BOD Thresholds and

Analog Comparator

Offset

Figure 188. BOD Threshold vs. Temperature (BODLEVEL is 4.0V)

BOD THRESHOLDS vs. TEMPERATURE

BOD LEVEL IS 4.0 V

4.4

4.2

Rising V_CC

4

Falling V_CC

3.8

3.6

3.4

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

346

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 189. BOD Threshold vs. Temperature (BODLEVEL is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BOD LEVEL IS 2.7 V

3

2.8

Rising V_CC

2.6

Falling V_CC

2.4

2.2

2

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

Figure 190. Bandgap Voltage vs. Operating Voltage

BANDGAP VOLTAGE vs. V_CC

1.275

1.27

85 °C

-40 °C

25 °C

1.265

1.26

1.255

1.25

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

347

2467P–AVR–08/07

Internal Oscillator

Speed

Figure 191. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

1220

1200

1180

1160

1140

1120

1100

1080

1060

-40 °C

25 °C

85 °C

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 192. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

1.02

1

5.5 V

5.0 V

4.5 V

4.0 V

3.6 V

3.3 V

0.98

0.96

0.94

0.92

0.9

2.7 V

-60

-40

-20

0

20

40

60

80

100

Temperature

348

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 193. Calibrated 1 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. Vcc

1.02

1

-40 ˚C

25 ˚C

85 ˚C

0.98

0.96

0.94

0.92

0.9

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 194. 1 MHz RC Oscillator Frequency vs. Osccal Value

1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

1.5

1.4

1.3

1.2

1.1

1

25 ˚C

0.9

0.8

0.7

0.6

0.5

0.4

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

OSCCAL VALUE

349

2467P–AVR–08/07

Figure 195. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

2.05

2

1.95

1.9

5.5 V

5.0 V

4.5 V

4.0 V

3.6 V

3.3 V

2.7 V

1.85

1.8

1.75

-60

-40

-20

0

20

40

60

80

100

Temperature

Figure 196. Calibrated 2 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. Vcc

2.05

-40 ˚C

25 ˚C

85 ˚C

2

1.95

1.9

1.85

1.8

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

350

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 197. 2 MHz RC Oscillator Frequency vs. Osccal Value

2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

4

3.5

3

25 °C

2.5

2

1.5

1

0.5

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

OSCCAL VALUE

Figure 198. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

4.1

4.05

4

5.5 V

5.0 V

4.5 V

3.95

3.9

3.85

3.8

4.0 V

3.6 V

3.3 V

3.75

3.7

2.7 V

3.65

3.6

-60

-40

-20

0

20

40

60

80

100

Temperature

351

2467P–AVR–08/07

Figure 199. Calibrated 4 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc

4.1

4.05

4

-40 ˚C

25 ˚C

85 ˚C

3.95

3.9

3.85

3.8

3.75

3.7

3.65

3.6

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 200. 4 MHz RC Oscillator Frequency vs. Osccal Value

4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

9

8

7

6

5

4

3

2

1

0

25 ˚C

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

352

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 201. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

8.4

8.2

8

5.5 V

5.0 V

4.5 V

4.0 V

3.6 V

3.3 V

2.7 V

7.8

7.6

7.4

7.2

7

6.8

6.6

-60

-40

-20

0

20

40

60

80

100

Temperature

Figure 202. Calibrated 8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc

8.4

8.2

8

-40 ˚C

25 ˚C

85 ˚C

7.8

7.6

7.4

7.2

7

6.8

6.6

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

353

2467P–AVR–08/07

Figure 203. 8 MHz RC Oscillator Frequency vs. Osccal Value

8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

16

14

12

10

8

25 °C

6

4

2

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

OSCCAL VALUE

Current Consumption Figure 204. Brownout Detector Current vs. V_CC

of Peripheral Units

BROWNOUT DETECTOR CURRENT vs. V_CC

25

20

15

10

5

-40 °C

25 °C

85 °C

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

354

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 205. ADC Current vs. AV_CC(ADC at 50 kHz)

ADC CURRENT vs. AV_CC

ADC AT 50KHz

600

500

400

300

200

100

0

-40 °C

25 °C

85 °C

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 206. ADC Current vs. AV_CC(ADC at 1 MHz)

AREF CURRENT vs. AV_CC

250

200

150

100

50

25 °C

85 °C

-40 °C

0

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

355

2467P–AVR–08/07

Figure 207. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. VCC

100

90

80

70

60

50

40

30

20

10

0

85 °C

25 °C

-40 °C

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 208. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. VCC

9

8

7

6

5

4

3

2

1

0

-40 ˚C

25 ˚C

85 ˚C

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

356

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Current Consumption Figure 209. Reset Supply Current vs. V_CC(0.1 - 1.0 MHz, Excluding Current Through The

in Reset and Reset

Pulse width

Reset Pull-up)

RESET SUPPLY CURRENT vs. V_CC

EXCLUDING CURRENT THROUGH THE RESET PULLUP

4.5

4

5.5 V

3.5

3

5.0 V

4.5 V

4.0 V

3.6 V

3.3 V

3.0 V

2.7 V

2.5

2

1.5

1

0.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 210. Reset Supply Current vs. V_CC(1 - 20 MHz, Excluding Current Through The Reset

Pull-up)

RESET SUPPLY CURRENT vs. V_CC

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

40

5.5 V

35

5.0 V

30

4.5 V

25

4.0 V

20

3.6 V

3.3 V

3.0 V

2.7 V

15

10

5

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

357

2467P–AVR–08/07

Figure 211. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5.0V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 5V

120

25 °C

-40 °C

100

85 °C

80

60

40

20

0

1

2

3

4

5

6

V

_RESET(V)

Figure 212. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 2.7V

60

25 °C

85 °C

-40 °C

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V

_RESET(V)

358

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Figure 213. Reset Input Threshold Voltage vs. V_CC(VIH, Reset Pin Read as ‘1’)

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, RESET PIN READ AS '1'

2.5

2

-40 °C

25 °C

1.5

1

85 °C

0.5

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 214. Reset Input Threshold Voltage vs. V_CC(VIL, Reset Pin Read as ‘0’)

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

2.5

-40 ˚C

25 ˚C

85 ˚C

2

1.5

1

0.5

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

359

2467P–AVR–08/07

Figure 215. Reset Input Pin Hysteresis vs. V_CC

RESET INPUT PIN HYSTERESIS vs. V_CC

0.5

0.45

0.4

-40 ˚C

0.35

0.3

0.25

0.2

25 ˚C

85 ˚C

0.15

0.1

0.05

0

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 216. Reset Pulse width vs. V_CC(External Clock, 1 MHz)

RESET PULSE WIDTH vs. V_CC

External Clock, 1 MHz

1.2

1

0.8

0.6

0.4

0.2

0

85 °C

25 °C

-40 °C

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

360

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

($FF)

..

Reserved

UCSR1C

UDR1

–

($9E)

($9D)

($9C)

($9B)

($9A)

($99)

($98)

($97)

($96)

UMSEL1

UPM11

UPM10

USBS1

UCSZ11

UCSZ10

UCPOL1

191

189

190

192

USART1 I/O Data Register

UCSR1A

UCSR1B

UBRR1L

UBRR1H

Reserved

UCSR0C

Reserved

UBRR0H

Reserved

TCCR3C

TCCR3A

TCCR3B

TCNT3H

TCNT3L

OCR3AH

OCR3AL

OCR3BH

OCR3BL

OCR3CH

OCR3CL

ICR3H

RXC1

TXC1

UDRE1

UDRIE1

FE1

DOR1

UPE1

U2X1

MPCM1

TXB81

RXCIE1

TXCIE1

RXEN1

TXEN1

UCSZ12

RXB81

USART1 Baud Rate Register Low

– USART1 Baud Rate Register High

–

($95)

($94)

($93)

($92)

($91)

–

UMSEL0

UPM01

UPM00

USBS0

UCSZ01

UCSZ00

UCPOL0

191

192

–

($90)

($8F)

($8E)

($8D)

($8C)

–

USART0 Baud Rate Register High

–

FOC3A

COM3A1

ICNC3

FOC3B

COM3A0

ICES3

FOC3C

COM3B1

–

137

133

136

138

139

($8B)

($8A)

($89)

($88)

($87)

($86)

($85)

($84)

($83)

($82)

($81)

($80)

($7F)

($7E)

COM3B0

WGM33

COM3C1

WGM32

COM3C0

CS32

WGM31

CS31

WGM30

CS30

Timer/Counter3 – Counter Register High Byte

Timer/Counter3 – Counter Register Low Byte

Timer/Counter3 – Output Compare Register A High Byte

Timer/Counter3 – Output Compare Register A Low Byte

Timer/Counter3 – Output Compare Register B High Byte

Timer/Counter3 – Output Compare Register B Low Byte

Timer/Counter3 – Output Compare Register C High Byte

Timer/Counter3 – Output Compare Register C Low Byte

Timer/Counter3 – Input Capture Register High Byte

Timer/Counter3 – Input Capture Register Low Byte

ICR3L

Reserved

ETIMSK

ETIFR

–

OCIE3A

OCF3A

–

OCIE3B

OCF3B

–

TOIE3

TOV3

–

OCIE3C

OCF3C

–

OCIE1C

OCF1C

–

($7D)

($7C)

($7B)

($7A)

–

TICIE3

ICF3

–

140

141

–

Reserved

TCCR1C

OCR1CH

OCR1CL

Reserved

TWCR

FOC1A

FOC1B

FOC1C

–

137

138

($79)

($78)

($77)

($76)

($75)

Timer/Counter1 – Output Compare Register C High Byte

Timer/Counter1 – Output Compare Register C Low Byte

–

($74)

($73)

($72)

($71)

($70)

($6F)

($6E)

($6D)

($6C)

($6B)

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

TWIE

206

208

207

206

42

TWDR

Two-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

Two-wire Serial Interface Bit Rate Register

Oscillator Calibration Register

OSCCAL

Reserved

XMCRA

XMCRB

Reserved

EICRA

–

SRW01

–

SRW00

XMM2

–

SRW11

XMM1

–

SRL2

SRL1

SRL0

31

33

XMBK

–

XMM0

–

($6A)

($69)

($68)

($67)

($66)

($65)

($64)

($63)

ISC31

ISC30

ISC21

ISC20

–

ISC11

–

ISC10

–

ISC01

–

ISC00

–

90

Reserved

SPMCSR

Reserved

PORTG

DDRG

–

SPMIE

RWWSB

–

RWWSRE

–

BLBSET

–

PGWRT

–

PGERS

–

SPMEN

–

277

–

PORTG4

DDG4

PING4

PORTF4

PORTG3

DDG3

PING3

PORTF3

PORTG2

DDG2

PING2

PORTF2

PORTG1

DDG1

PING1

PORTF1

PORTG0

DDG0

PING0

PORTF0

89

88

–

PING

($62)

PORTF

PORTF7

PORTF6

PORTF5

361

2467P–AVR–08/07

Register Summary (Continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

($61)

DDRF

Reserved

SREG

DDF7

–

DDF6

–

DDF5

–

DDF4

–

DDF3

–

DDF2

–

DDF1

–

DDF0

–

89

($60)

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2B)

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

$03 ($23)

$02 ($22)

I

T

H

S

V

N

Z

C

11

SPH

SP15

SP7

SP14

SP6

SP13

SP5

XDIV5

–

SP12

SP4

SP11

SP3

SP10

SP2

SP9

SP8

14

SPL

SP1

SP0

14

XDIV

XDIVEN

–

XDIV6

–

XDIV4

–

XDIV3

–

XDIV2

–

XDIV1

–

XDIV0

RAMPZ0

ISC40

INT0

37

RAMPZ

EICRB

EIMSK

EIFR

14

ISC71

INT7

INTF7

OCIE2

OCF2

SRE

JTD

ISC70

INT6

INTF6

TOIE2

TOV2

SRW10

–

ISC61

INT5

INTF5

TICIE1

ICF1

SE

ISC60

INT4

INTF4

OCIE1A

OCF1A

SM1

ISC51

INT3

INTF3

OCIE1B

OCF1B

SM0

ISC50

INT2

INTF

TOIE1

TOV1

SM2

BORF

CS02

ISC41

INT1

INTF1

OCIE0

OCF0

IVSEL

EXTRF

CS01

91

INTF0

TOIE0

TOV0

IVCE

PORF

CS00

92

TIMSK

TIFR

109, 139, 159

109, 141, 159

MCUCR

MCUCSR

TCCR0

TCNT0

OCR0

31, 45, 64

–

JTRF

COM00

WDRF

WGM01

54, 254

104

106

107

133

136

138

139

157

159

251

56

FOC0

WGM00

COM01

Timer/Counter0 (8 Bit)

Timer/Counter0 Output Compare Register

ASSR

–

COM1B1

–

AS0

TCN0UB

COM1C0

CS12

OCR0UB

WGM11

CS11

TCR0UB

WGM10

CS10

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

COM1A1

ICNC1

COM1A0

ICES1

COM1B0

WGM13

COM1C1

WGM12

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Output Compare Register A High Byte

Timer/Counter1 – Output Compare Register A Low Byte

Timer/Counter1 – Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

TCCR2

TCNT2

OCR2

FOC2

WGM20

COM21

COM20

WGM21

CS22

CS21

CS20

Timer/Counter2 (8 Bit)

Timer/Counter2 Output Compare Register

IDRD/OCDR7

OCDR

WDTCR

SFIOR

EEARH

EEARL

EEDR

OCDR6

OCDR5

OCDR4

OCDR3

WDE

OCDR2

WDP2

PUD

OCDR1

WDP1

PSR0

OCDR0

WDP0

–

TSM

–

WDCE

–

ACME

PSR321

73, 110, 144, 227

21

EEPROM Address Register High

EEPROM Address Register Low Byte

EEPROM Data Register

21

22

EECR

–

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

22

PORTA

DDRA

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

87

PINA

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PORTB5

DDB5

PINA4

PORTB4

DDB4

PINA3

PINA2

PINA1

PINA0

87

PORTB

DDRB

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

87

PINB

PINB7

PORTC7

DDC7

PINB6

PORTC6

DDC6

PINB5

PORTC5

DDC5

PINB4

PORTC4

DDC4

PINB3

PINB2

PINB1

PINB0

87

PORTC

DDRC

PORTC3

DDC3

PORTC2

DDC2

PORTC1

DDC1

PORTC0

DDC0

87

PINC

PINC7

PORTD7

DDD7

PINC6

PORTD6

DDD6

PINC5

PORTD5

DDD5

PINC4

PORTD4

DDD4

PINC3

PINC2

PINC1

PORTD1

DDD1

PINC0

PORTD0

DDD0

88

PORTD

DDRD

PORTD3

DDD3

PORTD2

DDD2

88

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

88

SPDR

SPI Data Register

169

167

189

190

192

227

242

244

245

88

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

UDR0

USART0 I/O Data Register

UCSR0A

UCSR0B

UBRR0L

ACSR

RXC0

TXC0

UDRE0

UDRIE0

FE0

DOR0

UPE0

U2X0

MPCM0

TXB80

RXCIE0

TXCIE0

RXEN0

TXEN0

UCSZ02

RXB80

USART0 Baud Rate Register Low

ACD

REFS1

ADEN

ACBG

REFS0

ADSC

ACO

ADLAR

ADFR

ACI

MUX4

ADIF

ACIE

MUX3

ADIE

ACIC

MUX2

ADPS2

ACIS1

MUX1

ADPS1

ACIS0

MUX0

ADPS0

ADMUX

ADCSRA

ADCH

ADC Data Register High Byte

ADC Data Register Low byte

ADCL

PORTE

DDRE

PORTE7

DDE7

PORTE6

DDE6

PORTE5

DDE5

PORTE4

DDE4

PORTE3

DDE3

PORTE2

DDE2

PORTE1

DDE1

PORTE0

DDE0

88

362

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Register Summary (Continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$01 ($21)

$00 ($20)

PINE

PINF

PINE7

PINF7

PINE6

PINF6

PINE5

PINF5

PINE4

PINF4

PINE3

PINF3

PINE2

PINF2

PINE1

PINF1

PINE0

PINF0

88

89

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers $00 to $1F only.

363

2467P–AVR–08/07

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← $FF − Rd

Rd ← $00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1 / 2 / 3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1 / 2 / 3

1 / 2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

364

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

Branch if Interrupt Disabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1 / 2

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

LD

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

ELPM

SPM

IN

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Extended Load Program Memory

Extended Load Program Memory and Post-Inc

Store Program Memory

In Port

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (RAMPZ:Z)

Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1

(Z) ← R1:R0

Rd, Z

Rd, Z+

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd

Rd ← STACK

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

I

Clear Carry

C ← 0

Set Negative Flag

Clear Negative Flag

Set Zero Flag

N ← 1

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

I ← 1

CLI

I ← 0

I

SES

CLS

S ← 1

S

S ← 0

365

2467P–AVR–08/07

Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SEV

CLV

SET

CLT

SEH

CLH

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

V ← 1

V ← 0

T ← 1

T ← 0

H ← 1

H ← 0

V

T

H

1

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

366

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package⁽¹⁾

Operation Range

ATmega128L-8AC

ATmega128L-8MC

64A

Commercial

(0^oC to 70^oC)

64M1

ATmega128L-8AI

ATmega128L-8AU⁽²⁾

ATmega128L-8MI

ATmega128L-8MU⁽²⁾

64A

8

2.7 - 5.5V

64A

Industrial

(-40^oC to 85^oC)

64M1

ATmega128-16AC

ATmega128-16MC

64A

Commercial

(0^oC to 70^oC)

64M1

ATmega128-16AI

ATmega128-16AU⁽²⁾

ATmega128-16MI

ATmega128-16MU⁽²⁾

64A

16

4.5 - 5.5V

64A

Industrial

(-40^oC to 85^oC)

64M1

Notes: 1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

367

2467P–AVR–08/07

Packaging Information

64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

–

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

E1

B

14.10 Note 2

0.45

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64A

B

R

368

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

9.10

NOM

0.90

0.02

0.25

9.00

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.18

8.90

D

D2

E

5.20

5.40

5.60

K

Pin #1

Notch

(0.20 R)

8.90

9.00

9.10

e

b

E2

e

5.20

5.40

0.50 BSC

0.40

5.60

BOTTOM VIEW

L

0.35

0.45

1.55

K

1.25

1.40

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Note:

5/25/06

DRAWING NO. REV.

64M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

G

R

369

2467P–AVR–08/07

Errata

The revision letter in this section refers to the revision of the ATmega128 device.

ATmega128 Rev. M • First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; set global interrupt enable

370

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. L • First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

371

2467P–AVR–08/07

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; set global interrupt enable

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

372

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. I

• First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

373

2467P–AVR–08/07

Assembly Code Example:

CLI

; clear global interrupt enable

OUT XDIV, temp

; set new prescale value

; no operation

NOP

SEI

; no operation

; clear global interrupt enable

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. H • First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

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ATmega128(L)

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; clear global interrupt enable

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

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2467P–AVR–08/07

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. G • First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

376

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ATmega128(L)

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; set global interrupt enable

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

377

2467P–AVR–08/07

ATmega128 Rev. F • First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will

take longer than expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator

before the first conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register,

the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change.

Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,

follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; set global interrupt enable

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ATmega128(L)

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ATmega128(L)

4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL reg-

ister, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this

errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are

replaced by all-ones during Update-DR.

Problem Fix / Workaround

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction

or by entering the Test-Logic-Reset state of the TAP controller to read out the

contents of its Device ID Register and possibly data from succeeding devices of the

scan chain. Issue the BYPASS instruction to the ATmega128 while reading the

Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured

simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt

request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-

ister triggers an unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

379

2467P–AVR–08/07

Datasheet

Revision

History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

Changes from Rev. 1. Updated “Features” on page 1.

2467O-10/06 to

2. Added “Data Retention” on page 8.

Rev.

2467P-08/07

3. Updated Table 60 on page 134 and Table 95 on page 235.

4. Updated “C Code Example⁽¹⁾” on page 177.

5. Updated Figure 114 on page 238.

6. Updated “XTAL Divide Control Register – XDIV” on page 37.

7. Updated “Errata” on page 370.

8. Updated Table 34 on page 77.

9. Updated “Slave Mode” on page 167.

Changes from Rev. 1. Added note to “Timer/Counter Oscillator” on page 44.

2467N-03/06 to

Rev.

2. Updated “Fast PWM Mode” on page 125.

2467O-10/06

3. Updated Table 52 on page 105, Table 54 on page 105, Table 59 on page 134, Table 61

on page 135, Table 64 on page 157, and Table 66 on page 158.

4. Updated “Errata” on page 370.

Changes from Rev. 1. Updated note for Figure 1 on page 2.

2467M-11/04 to

Rev.

2467N-03/06

2. Updated “Alternate Functions of Port D” on page 78.

3. Updated “Alternate Functions of Port G” on page 85.

4. Updated “Phase Correct PWM Mode” on page 101.

5. Updated Table 59 on page 134, Table 60 on page 134.

6. Updated “Bit 2 – TOV3: Timer/Counter3, Overflow Flag” on page 142.

7. Updated “Serial Peripheral Interface – SPI” on page 163.

8. Updated Features in “Analog to Digital Converter” on page 230

9. Added note in “Input Channel and Gain Selections” on page 243.

10. Updated “Errata” on page 370.

380

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Changes from Rev. 1. Removed “analog ground”, replaced by “ground”.

2467L-05/04 to

Rev.

2467M-11/04

2. Updated Table 11 on page 41, Table 114 on page 285, Table 128 on page 303, and

Table 132 on page 320. Updated Figure 114 on page 238.

3. Added note to “Port C (PC7..PC0)” on page 5.

4. Updated “Ordering Information” on page 367.

Changes from Rev. 1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx

with ICPx.

2467K-03/04 to

Rev.

2. Updated Table 8 on page 39, Table 19 on page 51, Table 22 on page 57, Table 96 on

2467L-05/04

page 242, Table 126 on page 299, Table 128 on page 303, Table 132 on page 320, and

Table 134 on page 322.

3. Updated “External Memory Interface” on page 26.

4. Updated “Device Identification Register” on page 253.

5. Updated “Electrical Characteristics” on page 318.

6. Updated “ADC Characteristics” on page 324.

7. Updated “ATmega128 Typical Characteristics” on page 332.

8. Updated “Ordering Information” on page 367.

Changes from Rev. 1. Updated “Errata” on page 370.

2467J-12/03 to

Rev.

2467K-03/04

Changes from Rev. 1. Updated “Calibrated Internal RC Oscillator” on page 42.

2467I-09/03 to Rev.

2467J-12/03

Changes from Rev. 1. Updated note in “XTAL Divide Control Register – XDIV” on page 37.

2467H-02/03 to

Rev. 2467I-09/03

2. Updated “JTAG Interface and On-chip Debug System” on page 49.

3. Updated values for V_BOT(BODLEVEL = 1) in Table 19 on page 51.

4. Updated “Test Access Port – TAP” on page 246 regarding JTAGEN.

5. Updated description for the JTD bit on page 255.

6. Added a note regarding JTAGEN fuse to Table 118 on page 288.

7. Updated R_PUvalues in “DC Characteristics” on page 318.

381

2467P–AVR–08/07

8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in

“Errata” on page 370.

Changes from Rev. 1. Corrected the names of the two Prescaler bits in the SFIOR Register.

2467G-09/02 to

Rev. 2467H-02/03

2. Added Chip Erase as a first step under “Programming the Flash” on page 315 and

“Programming the EEPROM” on page 316.

3. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz

Crystal Oscillator” application note, which do not exist.

4. Corrected OCn waveforms in Figure 52 on page 126.

5. Various minor Timer1 corrections.

6. Added information about PWM symmetry for Timer0 and Timer2.

7. Various minor TWI corrections.

8. Added reference to Table 124 on page 292 from both SPI Serial Programming and Self

Programming to inform about the Flash Page size.

9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 280 about

writing to the EEPROM during an SPM Page load.

10. Removed ADHSM completely.

11. Added section “EEPROM Write During Power-down Sleep Mode” on page 25.

12. Updated drawings in “Packaging Information” on page 368.

Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

2467F-09/02 to

Rev. 2467G-09/02

Changes from Rev. 1. Added 64-pad QFN/MLF Package and updated “Ordering Information” on page 367.

2467E-04/02 to

Rev. 2467F-09/02

2. Added the section “Using all Locations of External Memory Smaller than 64 KB” on

page 33.

3. Added the section “Default Clock Source” on page 38.

4. Renamed SPMCR to SPMCSR in entire document.

5. When using external clock there are some limitations regards to change of frequency.

This is descried in “External Clock” on page 43 and Table 131, “External Clock

Drive,” on page 320.

6. Added a sub section regarding OCD-system and power consumption in the section

“Minimizing Power Consumption” on page 48.

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ATmega128(L)

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ATmega128(L)

7. Corrected typo (WGM-bit setting) for:

“Fast PWM Mode” on page 99 (Timer/Counter0).

“Phase Correct PWM Mode” on page 101 (Timer/Counter0).

“Fast PWM Mode” on page 151 (Timer/Counter2).

“Phase Correct PWM Mode” on page 153 (Timer/Counter2).

8. Corrected Table 81 on page 192 (USART).

9. Corrected Table 102 on page 259 (Boundary-Scan)

10. Updated Vil parameter in “DC Characteristics” on page 318.

Changes from Rev. 1. Updated the Characterization Data in Section “ATmega128 Typical Characteristics”

on page 332.

2467D-03/02 to

Rev. 2467E-04/02

2. Updated the following tables:

Table 19 on page 51, Table 20 on page 55, Table 68 on page 158, Table 102 on page 259,

and Table 136 on page 328.

3. Updated Description of OSCCAL Calibration Byte.

In the data sheet, it was not explained how to take advantage of the calibration bytes for 2,

4, and 8 MHz Oscillator selections. This is now added in the following sections:

Improved description of “Oscillator Calibration Register – OSCCAL” on page 42 and “Cali-

bration Byte” on page 289.

Changes from Rev. 1. Added more information about “ATmega103 Compatibility Mode” on page 5.

2467C-02/02 to

Rev. 2467D-03/02

2. Updated Table 2, “EEPROM Programming Time,” on page 23.

3. Updated typical Start-up Time in Table 7 on page 38, Table 9 and Table 10 on page 40,

Table 12 on page 41, Table 14 on page 42, and Table 16 on page 43.

4. Updated Table 22 on page 57 with typical WDT Time-out.

5. Corrected description of ADSC bit in “ADC Control and Status Register A – ADCSRA”

on page 244.

6. Improved description on how to do a polarity check of the ADC differential results in

“ADC Conversion Result” on page 241.

7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 256.

8. Improved description of addressing during SPM (usage of RAMPZ) on “Addressing

the Flash During Self-Programming” on page 278, “Performing Page Erase by SPM”

on page 280, and “Performing a Page Write” on page 280.

9. Added not regarding OCDEN Fuse below Table 118 on page 288.

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2467P–AVR–08/07

10. Updated Programming Figures:

Figure 135 on page 290 and Figure 144 on page 301 are updated to also reflect that AVCC

must be connected during Programming mode. Figure 139 on page 297 added to illustrate

how to program the fuses.

11. Added a note regarding usage of the PROG_PAGELOAD and PROG_PAGEREAD

instructions on page 307.

12. Added Calibrated RC Oscillator characterization curves in section “ATmega128 Typi-

cal Characteristics” on page 332.

13. Updated “Two-wire Serial Interface” section.

More details regarding use of the TWI Power-down operation and using the TWI as master

with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit

Rate Generator Unit” on page 204. Added the description at the end of “Address Match Unit”

on page 205.

14. Added a note regarding usage of Timer/Counter0 combined with the clock. See

“XTAL Divide Control Register – XDIV” on page 37.

Changes from Rev. 1. Corrected Description of Alternate Functions of Port G

2467B-09/01 to

Corrected description of TOSC1 and TOSC2 in “Alternate Functions of Port G” on page 85.

Rev. 2467C-02/02

2. Added JTAG Version Numbers for rev. F and rev. G

Updated Table 100 on page 256.

3

Added Some Preliminary Test Limits and Characterization Data

Removed some of the TBD's in the following tables and pages:

Table 19 on page 51, Table 20 on page 55, “DC Characteristics” on page 318, Table 131 on

page 320, Table 134 on page 322, and Table 136 on page 328.

4. Corrected “Ordering Information” on page 367.

5. Added some Characterization Data in Section “ATmega128 Typical Characteristics”

on page 332.

6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.

See “Leaving Programming Mode” on page 315.

7. Added Description on How to Access the Extended Fuse Byte Through JTAG Pro-

gramming Mode.

See “Programming the Fuses” on page 317 and “Reading the Fuses and Lock Bits” on page

317.

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ATmega128(L)

Table of

Features 1

Contents

Pin Configurations 2

Overview 2

Block Diagram 3

ATmega103 and ATmega128 Compatibility 4

Pin Descriptions 5

Resources 8

Data Retention 8

About Code Examples 9

AVR CPU Core 10

Introduction 10

Architectural Overview 10

ALU – Arithmetic Logic Unit 11

Status Register 11

General Purpose Register File 12

Stack Pointer 14

Instruction Execution Timing 14

Reset and Interrupt Handling 15

AVR ATmega128 Memories 18

In-System Reprogrammable Flash Program Memory 18

SRAM Data Memory 19

EEPROM Data Memory 21

I/O Memory 26

External Memory Interface 26

System Clock and Clock Options 36

Clock Systems and their Distribution 36

Clock Sources 37

Default Clock Source 38

Crystal Oscillator 39

Low-frequency Crystal Oscillator 40

External RC Oscillator 40

Calibrated Internal RC Oscillator 42

External Clock 43

Timer/Counter Oscillator 44

i

2467P–AVR–08/07

Power Management and Sleep Modes 45

Idle Mode 46

ADC Noise Reduction Mode 46

Power-down Mode 46

Power-save Mode 46

Standby Mode 47

Extended Standby Mode 47

Minimizing Power Consumption 48

System Control and Reset 50

Internal Voltage Reference 54

Watchdog Timer 55

Timed Sequences for Changing the Configuration of the Watchdog Timer 58

Interrupts 60

Interrupt Vectors in ATmega128 60

I/O Ports 66

Introduction 66

Ports as General Digital I/O 67

Alternate Port Functions 71

Register Description for I/O Ports 87

External Interrupts 90

8-bit Timer/Counter0 with PWM and Asynchronous Operation 93

Overview 93

Timer/Counter Clock Sources 94

Counter Unit 94

Output Compare Unit 95

Compare Match Output Unit 97

Modes of Operation 98

Timer/Counter Timing Diagrams 102

8-bit Timer/Counter Register Description 104

Asynchronous Operation of the Timer/Counter 107

Timer/Counter Prescaler 110

ii

ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 112

Overview 112

Accessing 16-bit Registers 115

Timer/Counter Clock Sources 118

Counter Unit 118

Input Capture Unit 119

Output Compare Units 121

Compare Match Output Unit 123

Modes of Operation 124

Timer/Counter Timing Diagrams 131

16-bit Timer/Counter Register Description 133

Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers

143

8-bit Timer/Counter2 with PWM 145

Overview 145

Timer/Counter Clock Sources 146

Counter Unit 146

Output Compare Unit 147

Compare Match Output Unit 148

Modes of Operation 149

Timer/Counter Timing Diagrams 155

8-bit Timer/Counter Register Description 157

Output Compare Modulator (OCM1C2) 161

Overview 161

Description 161

Serial Peripheral Interface – SPI 163

SS Pin Functionality 167

Data Modes 170

USART 171

Overview 171

Clock Generation 173

Frame Formats 176

USART Initialization 177

Data Transmission – The USART Transmitter 178

Data Reception – The USART Receiver 180

Multi-processor Communication Mode 187

USART Register Description 189

Examples of Baud Rate Setting 194

iii

2467P–AVR–08/07

Two-wire Serial Interface 198

Features 198

Two-wire Serial Interface Bus Definition 198

Data Transfer and Frame Format 199

Multi-master Bus Systems, Arbitration and Synchronization 201

Overview of the TWI Module 204

TWI Register Description 206

Using the TWI 208

Transmission Modes 213

Multi-master Systems and Arbitration 225

Analog Comparator 227

Analog Comparator Multiplexed Input 228

Analog to Digital Converter 230

Features 230

Operation 232

Starting a Conversion 232

Prescaling and Conversion Timing 233

Changing Channel or Reference Selection 235

ADC Noise Canceler 236

ADC Conversion Result 241

JTAG Interface and On-chip Debug System 246

Features 246

Overview 246

Test Access Port – TAP 246

TAP Controller 248

Using the Boundary-scan Chain 249

Using the On-chip Debug System 249

On-chip Debug Specific JTAG Instructions 250

On-chip Debug Related Register in I/O Memory 251

Using the JTAG Programming Capabilities 251

Bibliography 251

IEEE 1149.1 (JTAG) Boundary-scan 252

Features 252

System Overview 252

Data Registers 252

Boundary-scan Specific JTAG Instructions 254

Boundary-scan Related Register in I/O Memory 255

Boundary-scan Chain 255

ATmega128 Boundary-scan Order 266

Boundary-scan Description Language Files 272

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ATmega128(L)

2467P–AVR–08/07

ATmega128(L)

Boot Loader Support – Read-While-Write Self-Programming 273

Boot Loader Features 273

Application and Boot Loader Flash Sections 273

Read-While-Write and No Read-While-Write Flash Sections 273

Boot Loader Lock Bits 275

Entering the Boot Loader Program 276

Addressing the Flash During Self-Programming 278

Self-Programming the Flash 279

Memory Programming 286

Program and Data Memory Lock Bits 286

Fuse Bits 287

Signature Bytes 289

Calibration Byte 289

Parallel Programming Parameters, Pin Mapping, and Commands 290

Parallel Programming 292

Serial Downloading 300

SPI Serial Programming Pin Mapping 300

Programming Via the JTAG Interface 305

Electrical Characteristics 318

Absolute Maximum Ratings* 318

DC Characteristics 318

External Clock Drive Waveforms 319

External Clock Drive 320

Two-wire Serial Interface Characteristics 321

SPI Timing Characteristics 322

ADC Characteristics 324

External Data Memory Timing 327

ATmega128 Typical Characteristics 332

Register Summary 361

Instruction Set Summary 364

Ordering Information 367

Packaging Information 368

64A 368

64M1 369

v

2467P–AVR–08/07

Errata 370

ATmega128 Rev. M 370

ATmega128 Rev. L 371

ATmega128 Rev. I 373

ATmega128 Rev. H 374

ATmega128 Rev. G 376

ATmega128 Rev. F 378

Datasheet Revision History 380

Changes from Rev. 2467O-10/06 to Rev.2467P-08/07 380

Changes from Rev. 2467N-03/06 to Rev.2467O-10/06 380

Changes from Rev. 2467M-11/04 to Rev.2467N-03/06 380

Changes from Rev. 2467L-05/04 to Rev.2467M-11/04 381

Changes from Rev. 2467K-03/04 to Rev.2467L-05/04 381

Changes from Rev. 2467J-12/03 to Rev.2467K-03/04 381

Changes from Rev. 2467I-09/03 to Rev.2467J-12/03 381

Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03 381

Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03 382

Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02 382

Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02 382

Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02 383

Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02 383

Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02 384

Table of Contents i

vi

ATmega128(L)

2467P–AVR–08/07

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Product Contact

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avr@atmel.com

www.atmel.com/contacts

Literature Requests

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2467P–AVR–08/07


型号：	ATMEGA128-16AL
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, 16MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64 时钟 ATM 异步传输模式微控制器外围集成电路
文件：	总391页 (文件大小：6192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA128-16AL [ATMEL]

相关型号：

ATMEGA128-16AN

ATMEGA128-16AN

ATMEGA128-16ANR

ATMEGA128-16ANR

ATMEGA128-16AU

ATMEGA128-16AU

ATMEGA128-16AUR

ATMEGA128-16MC

ATMEGA128-16MI

ATMEGA128-16ML

ATMEGA128-16MN

ATMEGA128-16MN