ATMEGA16-16AU [ATMEL]
8-bit Microcontroller with 16K Bytes In-System Programmable Flash; 8位微控制器，带有16K字节的系统内可编程闪存
| 型号： | ATMEGA16-16AU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 16K Bytes In-System Programmable Flash |
| 文件： | 总24页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 16K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K Byte Internal SRAM
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
ATmega16
ATmega16L
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
Summary
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega16L
– 4.5 - 5.5V for ATmega16
• Speed Grades
– 0 - 8 MHz for ATmega16L
– 0 - 16 MHz for ATmega16
• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L
– Active: 1.1 mA
– Idle Mode: 0.35 mA
– Power-down Mode: < 1 µA
2466NS–AVR–10/06
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Pin Configurations
Figure 1. Pinout ATmega16
PDIP
(XCK/T0) PB0
PA0 (ADC0)
PA1 (ADC1)
PA2 (ADC2)
PA3 (ADC3)
PA4 (ADC4)
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7
RESET
VCC
GND
GND
AVCC
XTAL2
XTAL1
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP1) PD6
TQFP/QFN/MLF
(MOSI) PB5
PA4 (ADC4)
(MISO) PB6
(SCK) PB7
RESET
PA5 (ADC5)
PA6 (ADC6)
PA7 (ADC7)
AREF
VCC
GND
GND
XTAL2
AVCC
XTAL1
PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
(RXD) PD0
(TXD) PD1
(INT0) PD2
NOTE:
Bottom pad should
be soldered to ground.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
2
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Overview
The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
PA0 - PA7
PC0 - PC7
VCC
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
GND
AVCC
AREF
ADC
INTERFACE
MUX &
ADC
TWI
TIMERS/
COUNTERS
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
INTERNAL
OSCILLATOR
SRAM
XTAL1
INSTRUCTION
REGISTER
WATCHDOG
TIMER
GENERAL
PURPOSE
REGISTERS
OSCILLATOR
XTAL2
X
Y
Z
INSTRUCTION
DECODER
MCU CTRL.
& TIMING
RESET
INTERNAL
CALIBRATED
OSCILLATOR
CONTROL
LINES
INTERRUPT
UNIT
ALU
STATUS
REGISTER
AVR CPU
EEPROM
USART
PROGRAMMING
LOGIC
SPI
+
-
COMP.
INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
PB0 - PB7
PD0 - PD7
3
2466NS–AVR–10/06
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega16 provides the following features: 16K bytes of In-System Programmable
Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K
byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a
JTAG interface for Boundary-scan, On-chip Debugging support and programming, three
flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial
programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit
ADC with optional differential input stage with programmable gain (TQFP package only),
a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six
software selectable power saving modes. The Idle mode stops the CPU while allowing
the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and
interrupt system to continue functioning. The Power-down mode saves the register con-
tents but freezes the Oscillator, disabling all other chip functions until the next External
Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues
to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-
nous Timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low-power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface, by a conventional nonvolatile memory programmer, or
by an On-chip Boot program running on the AVR core. The boot program can use any
interface to download the application program in the Application Flash memory. Soft-
ware in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU
with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is
a powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.
The ATmega16 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
Pin Descriptions
VCC
Digital supply voltage.
GND
Ground.
Port A (PA7..PA0)
Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
buffers have symmetrical drive characteristics with both high sink and source capability.
When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source
current if the internal pull-up resistors are activated. The Port A pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
4
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega16 as listed
on page 56.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running. If the JTAG interface is
enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti-
vated even if a reset occurs.
Port C also serves the functions of the JTAG interface and other special features of the
ATmega16 as listed on page 59.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16 as listed
on page 61.
RESET
Reset Input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 36. Shorter pulses are not guaranteed to generate a reset.
XTAL1
XTAL2
AVCC
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting Oscillator amplifier.
AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter.
AREF
AREF is the analog reference pin for the A/D Converter.
Resources
A comprehensive set of development tools, application notes and datasheets are avail-
able for download on http://www.atmel.com/avr.
5
2466NS–AVR–10/06
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F ($5F)
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
SREG
SPH
I
–
T
–
H
–
S
–
V
–
N
Z
C
7
SP10
SP2
SP9
SP1
SP8
SP0
10
SPL
SP7
SP6
SP5
SP4
SP3
10
Timer/Counter0 Output Compare Register
OCR0
83
GICR
INT1
INTF1
OCIE2
OCF2
SPMIE
TWINT
SM2
INT0
INTF0
TOIE2
TOV2
RWWSB
TWEA
SE
INT2
INTF2
TICIE1
ICF1
–
–
–
–
IVSEL
–
IVCE
–
46, 67
GIFR
–
–
–
68
TIMSK
TIFR
OCIE1A
OCF1A
RWWSRE
TWSTO
SM0
OCIE1B
OCF1B
BLBSET
TWWC
ISC11
WDRF
WGM01
TOIE1
TOV1
PGWRT
TWEN
ISC10
BORF
CS02
OCIE0
OCF0
PGERS
–
TOIE0
TOV0
SPMEN
TWIE
ISC00
PORF
CS00
83, 114, 132
84, 115, 132
SPMCR
TWCR
MCUCR
MCUCSR
TCCR0
TCNT0
OSCCAL
OCDR
SFIOR
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L
250
TWSTA
SM1
178
ISC01
EXTRF
CS01
30, 66
JTD
ISC2
–
JTRF
39, 67, 229
FOC0
WGM00
COM01
COM00
81
83
Timer/Counter0 (8 Bits)
Oscillator Calibration Register
On-Chip Debug Register
28
$31(1) ($51)(1)
225
55,86,133,199,219
109
112
113
113
113
113
113
113
114
114
127
129
129
130
41
$30 ($50)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
$27 ($47)
$26 ($46)
$25 ($45)
$24 ($44)
$23 ($43)
$22 ($42)
$21 ($41)
ADTS2
COM1A1
ICNC1
ADTS1
COM1A0
ICES1
ADTS0
COM1B1
–
–
ACME
FOC1A
WGM12
PUD
FOC1B
CS12
PSR2
WGM11
CS11
PSR10
WGM10
CS10
COM1B0
WGM13
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
Timer/Counter1 – Output Compare Register A High Byte
Timer/Counter1 – Output Compare Register A Low Byte
Timer/Counter1 – Output Compare Register B High Byte
Timer/Counter1 – Output Compare Register B Low Byte
Timer/Counter1 – Input Capture Register High Byte
Timer/Counter1 – Input Capture Register Low Byte
TCCR2
TCNT2
OCR2
FOC2
Timer/Counter2 (8 Bits)
Timer/Counter2 Output Compare Register
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
ASSR
–
–
–
–
–
WDTOE
–
AS2
TCN2UB
WDP2
OCR2UB
WDP1
TCR2UB
WDP0
WDTCR
UBRRH
UCSRC
EEARH
EEARL
EEDR
–
–
WDE
URSEL
URSEL
–
–
UMSEL
–
–
UPM1
–
UBRR[11:8]
165
164
17
$20(2) ($40)(2)
UPM0
–
USBS
–
UCSZ1
–
UCSZ0
–
UCPOL
EEAR8
$1F ($3F)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$1B ($3B)
$1A ($3A)
$19 ($39)
$18 ($38)
$17 ($37)
$16 ($36)
$15 ($35)
$14 ($34)
$13 ($33)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
$02 ($22)
EEPROM Address Register Low Byte
EEPROM Data Register
17
17
EECR
–
–
–
–
EERIE
PORTA3
DDA3
EEMWE
PORTA2
DDA2
EEWE
PORTA1
DDA1
EERE
PORTA0
DDA0
17
PORTA
DDRA
PORTA7
DDA7
PORTA6
DDA6
PORTA5
DDA5
PORTA4
DDA4
64
64
PINA
PINA7
PINA6
PORTB6
DDB6
PINA5
PORTB5
DDB5
PINA4
PORTB4
DDB4
PINA3
PINA2
PINA1
PINA0
64
PORTB
DDRB
PORTB7
DDB7
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
64
64
PINB
PINB7
PINB6
PORTC6
DDC6
PINB5
PORTC5
DDC5
PINB4
PORTC4
DDC4
PINB3
PINB2
PINB1
PINB0
64
PORTC
DDRC
PINC
PORTC7
DDC7
PORTC3
DDC3
PORTC2
DDC2
PORTC1
DDC1
PORTC0
DDC0
65
65
PINC7
PINC6
PORTD6
DDD6
PINC5
PORTD5
DDD5
PINC4
PORTD4
DDD4
PINC3
PORTD3
DDD3
PINC2
PINC1
PORTD1
DDD1
PINC0
PORTD0
DDD0
65
PORTD
DDRD
PIND
PORTD7
DDD7
PORTD2
DDD2
65
65
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
65
SPDR
SPI Data Register
SPIF
140
140
138
161
162
163
165
200
215
217
218
218
180
180
SPSR
WCOL
SPE
–
–
–
–
–
SPI2X
SPR0
SPCR
SPIE
DORD
MSTR
CPOL
CPHA
SPR1
UDR
USART I/O Data Register
UCSRA
UCSRB
UBRRL
ACSR
RXC
TXC
UDRE
UDRIE
FE
DOR
PE
U2X
MPCM
TXB8
RXCIE
TXCIE
RXEN
TXEN
UCSZ2
RXB8
USART Baud Rate Register Low Byte
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ACI
MUX4
ADIF
ACIE
MUX3
ADIE
ACIC
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
TWDR
TWAR
Two-wire Serial Interface Data Register
TWA6 TWA5 TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
6
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
$01 ($21)
$00 ($20)
TWSR
TWBR
TWS7
–
179
178
Two-wire Serial Interface Bit Rate Register
Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug-
ger specific documentation for details on how to use the OCDR Register.
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
7
2466NS–AVR–10/06
Instruction Set Summary
Flags
Operands
Description
Operation
Mnemonics
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • ($FF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd ⊕ Rd
Rd ← $FF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
k
Direct Subroutine Call
Subroutine Return
PC ← k
4
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1 / 2 / 3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
k
k
8
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Flags
Operands
Description
Operation
Mnemonics
#Clocks
BRIE
BRID
k
k
Branch if Interrupt Enabled
Branch if Interrupt Disabled
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
1 / 2
1 / 2
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
T ← 1
T ← 0
H ← 1
V
T
T
H
Clear T in SREG
Set Half Carry Flag in SREG
9
2466NS–AVR–10/06
Flags
Operands
Description
Operation
Mnemonics
#Clocks
CLH
Clear Half Carry Flag in SREG
H ← 0
H
1
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
Watchdog Reset
Break
None
None
None
None
1
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-Chip Debug Only
BREAK
N/A
10
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Ordering Information
Speed (MHz)
Power Supply
Ordering Code
Package
Operation Range
ATmega16L-8AC
ATmega16L-8PC
ATmega16L-8MC
44A
40P6
44M1
Commercial
(0oC to 70oC)
ATmega16L-8AI
ATmega16L-8AU(1)
ATmega16L-8PI
ATmega16L-8PU(1)
ATmega16L-8MI
ATmega16L-8MU(1)
44A
44A
40P6
40P6
44M1
44M1
8
2.7 - 5.5V
Industrial
(-40oC to 85oC)
ATmega16-16AC
ATmega16-16PC
ATmega16-16MC
44A
40P6
44M1
Commercial
(0oC to 70oC)
ATmega16-16AI
ATmega16-16AU(1)
ATmega16-16PI
ATmega16-16PU(1)
ATmega16-16MI
ATmega16-16MU(1)
44A
44A
40P6
40P6
44M1
44M1
16
4.5 - 5.5V
Industrial
(-40oC to 85oC)
Note:
1. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-
tive). Also Halide free and fully Green.
Package Type
44A
44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
40P6
44M1
44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
11
2466NS–AVR–10/06
Packaging Information
44A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
12
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
40P6
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
A
–
eB
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
–
3.556
C
–
–
0.381
eB
e
17.526
2.540 TYP
09/28/01
DRAWING NO. REV.
40P6
TITLE
2325 Orchard Parkway
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
13
2466NS–AVR–10/06
44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
A3
TOP VIEW
A
K
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
1
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
NOM
0.90
NOTE
SYMBOL
E2
Option B
Option C
Pin #1
A
Chamfer
(C 0.30)
A1
A3
b
0.02
0.25 REF
0.23
0.18
6.90
5.00
6.90
0.30
7.10
5.40
7.10
D
7.00
K
Pin #1
Notch
(0.20 R)
D2
E
5.20
e
b
7.00
BOTTOM VIEW
E2
e
5.00
5.20
0.50 BSC
0.64
5.40
L
0.59
0.20
0.69
0.41
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
K
0.26
5/27/06
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)
44M1
G
R
14
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Errata
The revision letter in this section refers to the revision of the ATmega16 device.
ATmega16(L) Rev. M
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. L
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
15
2466NS–AVR–10/06
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. K
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
16
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. J
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. I
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
17
2466NS–AVR–10/06
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
–
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
ATmega16(L) Rev. H
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• IDCODE masks data from TDI input
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conver-
sion will take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Com-
parator before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous
timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock
is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the
value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare
Register, OCR2
3. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices
are replaced by all-ones during Update-DR.
Problem Fix / Workaround
–
If ATmega16 is the only device in the scan chain, the problem is not visible.
18
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
–
–
Select the Device ID Register of the ATmega16 by issuing the IDCODE
instruction or by entering the Test-Logic-Reset state of the TAP controller to
read out the contents of its Device ID Register and possibly data from
succeeding devices of the scan chain. Issue the BYPASS instruction to the
ATmega16 while reading the Device ID Registers of preceding devices of the
boundary scan chain.
If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega16 must be the fist device in the chain.
19
2466NS–AVR–10/06
Datasheet Revision
History
Please note that the referring page numbers in this section are referred to this docu-
ment. The referring revision in this section are referring to the document revision.
Rev. 2466N-10/06
1. Updated “Timer/Counter Oscillator” on page 31.
2. Updated “Fast PWM Mode” on page 102.
3. Updated Table 38 on page 83, Table 40 on page 84, Table 45 on page 112,
Table 47 on page 113, Table 50 on page 129 and Table 52 on page 130.
4. Updated C code example in “USART Initialization” on page 150.
5. Updated “Errata” on page 343.
Rev. 2466M-04/06
Rev. 2466L-06/05
1. Updated typos.
2. Updated “Serial Peripheral Interface – SPI” on page 136.
3. Updated Table 86 on page 222, Table 116 on page 279 ,Table 121 on page 298
and Table 122 on page 300.
1. Updated note in “Bit Rate Generator Unit” on page 179.
2. Updated values for VINT in “ADC Characteristics” on page 300.
3. Updated “Serial Programming Instruction set” on page 279.
4. Updated USART init C-code example in “USART” on page 145.
Rev. 2466K-04/05
1. Updated “Ordering Information” on page 11.
2. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame
Package QFN/MLF”.
3. Updated “Electrical Characteristics” on page 294.
1. Updated “Ordering Information” on page 11.
1. Removed references to analog ground.
Rev. 2466J-10/04
Rev. 2466I-10/04
2. Updated Table 7 on page 28, Table 15 on page 38, Table 16 on page 42, Table
81 on page 211, Table 116 on page 279, and Table 119 on page 296.
3. Updated “Pinout ATmega16” on page 2.
4. Updated features in “Analog to Digital Converter” on page 205.
5. Updated “Version” on page 230.
6. Updated “Calibration Byte” on page 264.
20
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
7. Added “Page Size” on page 265.
Rev. 2466H-12/03
Rev. 2466G-10/03
1. Updated “Calibrated Internal RC Oscillator” on page 29.
1. Removed “Preliminary” from the datasheet.
2. Changed ICP to ICP1 in the datasheet.
3. Updated “JTAG Interface and On-chip Debug System” on page 36.
4. Updated assembly and C code examples in “Watchdog Timer Control Regis-
ter – WDTCR” on page 43.
5. Updated Figure 46 on page 103.
6. Updated Table 15 on page 38, Table 82 on page 218 and Table 115 on page
279.
7. Updated “Test Access Port – TAP” on page 223 regarding JTAGEN.
8. Updated description for the JTD bit on page 232.
9. Added note 2 to Figure 126 on page 255.
10. Added a note regarding JTAGEN fuse to Table 105 on page 263.
11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical
Characteristics” on page 294.
12. Updated “ATmega16 Typical Characteristics” on page 302.
13. Fixed typo for 16 MHz QFN/MLF package in “Ordering Information” on page
11.
14. Added a proposal for solving problems regarding the JTAG instruction
IDCODE in “Errata” on page 15.
Rev. 2466F-02/03
1. Added note about masking out unused bits when reading the Program
Counter in “Stack Pointer” on page 12.
2. Added Chip Erase as a first step in “Programming the Flash” on page 291 and
“Programming the EEPROM” on page 292.
3. Added the section “Unconnected pins” on page 55.
4. Added tips on how to disable the OCD system in “On-chip Debug System” on
page 34.
5. Removed reference to the “Multi-purpose Oscillator” application note and
“32 kHz Crystal Oscillator” application note, which do not exist.
6. Added information about PWM symmetry for Timer0 and Timer2.
21
2466NS–AVR–10/06
7. Added note in “Filling the Temporary Buffer (Page Loading)” on page 256
about writing to the EEPROM during an SPM Page Load.
8. Removed ADHSM completely.
9. Added Table 73, “TWI Bit Rate Prescaler,” on page 183 to describe the TWPS
bits in the “TWI Status Register – TWSR” on page 182.
10. Added section “Default Clock Source” on page 25.
11. Added note about frequency variation when using an external clock. Note
added in “External Clock” on page 31. An extra row and a note added in Table
118 on page 296.
12. Various minor TWI corrections.
13. Added “Power Consumption” data in “Features” on page 1.
14. Added section “EEPROM Write During Power-down Sleep Mode” on page 22.
15. Added note about Differential Mode with Auto Triggering in “Prescaling and
Conversion Timing” on page 208.
16. Added updated “Packaging Information” on page 12.
1. Updated “DC Characteristics” on page 294.
Rev. 2466E-10/02
Rev. 2466D-09/02
1. Changed all Flash write/erase cycles from 1,000 to 10,000.
2. Updated the following tables: Table 4 on page 26, Table 15 on page 38, Table
42 on page 85, Table 45 on page 112, Table 46 on page 112, Table 59 on page
144, Table 67 on page 168, Table 90 on page 237, Table 102 on page 261, “DC
Characteristics” on page 294, Table 119 on page 296, Table 121 on page 298,
and Table 122 on page 300.
3. Updated “Errata” on page 15.
Rev. 2466C-03/02
1. Updated typical EEPROM programming time, Table 1 on page 20.
2. Updated typical start-up time in the following tables:
Table 3 on page 25, Table 5 on page 27, Table 6 on page 28, Table 8 on page 29,
Table 9 on page 29, and Table 10 on page 30.
3. Updated Table 17 on page 43 with typical WDT Time-out.
4. Added Some Preliminary Test Limits and Characterization Data.
Removed some of the TBD's in the following tables and pages:
Table 15 on page 38, Table 16 on page 42, Table 116 on page 272 (table removed
in document review #D), “Electrical Characteristics” on page 294, Table 119 on
page 296, Table 121 on page 298, and Table 122 on page 300.
5. Updated TWI Chapter.
22
ATmega16(L)
2466NS–AVR–10/06
ATmega16(L)
Added the note at the end of the “Bit Rate Generator Unit” on page 179.
6. Corrected description of ADSC bit in “ADC Control and Status Register A –
ADCSRA” on page 220.
7. Improved description on how to do a polarity check of the ADC doff results in
“ADC Conversion Result” on page 217.
8. Added JTAG version number for rev. H in Table 87 on page 230.
9. Added not regarding OCDEN Fuse below Table 105 on page 263.
10. Updated Programming Figures:
Figure 127 on page 265 and Figure 136 on page 277 are updated to also reflect that
AVCC must be connected during Programming mode. Figure 131 on page 273
added to illustrate how to program the fuses.
11. Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 283
and “PROG_PAGEREAD ($7)” on page 283.
12. Removed alternative algortihm for leaving JTAG Programming mode.
See “Leaving Programming Mode” on page 291.
13. Added Calibrated RC Oscillator characterization curves in section “ATmega16
Typical Characteristics” on page 302.
14. Corrected ordering code for QFN/MLF package (16MHz) in “Ordering Informa-
tion” on page 11.
15. Corrected Table 90, “Scan Signals for the Oscillators(1)(2)(3),” on page 237.
23
2466NS–AVR–10/06
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