ATMEGA169PV-8MU_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16K bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

– 512 bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1K byte Internal SRAM

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

ATmega169P

ATmega169PV

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Preliminary

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 54 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

• Speed Grade:

– ATmega169PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega169P: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 330 µA

32 kHz, 1.8V: 10 µA (including Oscillator)

32 kHz, 1.8V: 25 µA (including Oscillator and LCD)

– Power-down Mode:

0.1 µA at 1.8V

– Power-save Mode:

0.6 µA at 1.8V(Including 32 kHz RTC)

1. Pin Configurations

Figure 1-1. Pinout ATmega169P

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

1

2

3

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

48

47

46

INDEX CORNER

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

4

45

5

6

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

PC5 (SEG7)

44

43

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

7

8

9

42

41

40

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0 10

(SCK/PCINT9) PB1 11

(MOSI/PCINT10) PB2 12

(MISO/PCINT11) PB3 13

39 PC4 (SEG8)

PC3 (SEG9)

PC2 (SEG10)

PC1 (SEG11)

PC0 (SEG12)

38

37

36

(OC0A/PCINT12) PB4 14

(OC1A/PCINT13) PB5 15

(OC1B/PCINT14) PB6 16

35

34

33

PG1 (SEG13)

PG0 (SEG14)

Note:

The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If

the center pad is left unconnected, the package might loosen from the board.

1.1

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

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2. Overview

The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut-

ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC

INTERNAL

OSCILLATOR

ADC

AREF

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

JTAG TAP

TIMING AND

CONTROL

LCD

CONTROLLER/

DRIVER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

AVR CPU

UNIVERSAL

SERIAL INTERFACE

SPI

USART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega169P provides the following features: 16K bytes of In-System Programmable Flash

with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O

lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip

Debugging support and programming, a complete On-chip LCD controller with internal step-up

voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a

serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-

channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial

port, and five software selectable power saving modes. The Idle mode stops the CPU while

allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip

functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous

timer and the LCD controller continues to run, allowing the user to maintain a timer base and

operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction

mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,

to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator

Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com-

bined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex-

ible and cost effective solution to many embedded control applications.

The ATmega169P AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,

and Evaluation kits.

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2.2

Pin Descriptions

2.2.1

VCC

Digital supply voltage.

2.2.2

2.2.3

GND

Ground.

Port A (PA7:PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port A” on page 73.

2.2.4

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port B” on page 74.

2.2.5

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of special features of the ATmega169P as listed on ”Alternate

Functions of Port C” on page 77.

2.2.6

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port D” on page 79.

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2.2.7

Port E (PE7:PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port E” on page 81.

2.2.8

Port F (PF7:PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on

page 83

2.2.9

Port G (PG5:PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port G output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port G also serves the functions of various special features of the ATmega169P as listed on

page 85.

2.2.10

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page

47. Shorter pulses are not guaranteed to generate a reset.

2.2.11

2.2.12

2.2.13

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

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2.2.14

2.2.15

AREF

This is the analog reference pin for the A/D Converter.

LCDCAP

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 22-2 on page 235. This capacitor acts as a reservoir for LCD power (V_LCD). A large

capacitance reduces ripple on V_LCDbut increases the time until V_LCDreaches its target value.

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3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

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ATmega169P

4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

These code examples assume that the part specific header file is included before compilation.

For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"

instructions must be replaced with instructions that allow access to extended I/O. Typically

"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

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5. AVR CPU Core

5.1

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

5.2

Architectural Overview

Figure 5-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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ATmega169P

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega169P

has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

5.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

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5.4

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

5.4.1

SREG – AVR Status Register

The SREG is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

0x3F (0x5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

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• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

5.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 5-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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5.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 5-3 on page 14.

Figure 5-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

0

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

5.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0xFF. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

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5.6.1

SPH and SPL – Stack Pointer

Bit

15

–

14

–

13

–

12

–

11

–

10

SP10

SP2

2

9

SP9

SP1

1

8

SP8

SP0

0

0x3E (0x5E)

0x3D (0x5D)

SPH

SPL

SP7

7

SP6

6

SP5

5

SP4

4

SP3

3

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

5.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 5-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 5-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 5-5. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

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5.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section ”Memory Program-

ming” on page 295 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 56. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 56 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page

279.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

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CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMWE ; start EEPROM write

sbiEECR, EEWE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

5.8.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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6. AVR Memories

This section describes the different memories in the ATmega169P. The AVR architecture has

two main memory spaces, the Data Memory and the Program Memory space. In addition, the

ATmega169P features an EEPROM Memory for data storage. All three memory spaces are lin-

ear and regular.

6.1

In-System Reprogrammable Flash Program Memory

The ATmega169P contains 16K bytes On-chip In-System Reprogrammable Flash memory for

program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K

x 16. For software security, the Flash Program memory space is divided into two sections, Boot

Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega169P

Program Counter (PC) is 13 bits wide, thus addressing the 8K program memory locations. The

operation of Boot Program section and associated Boot Lock bits for software protection are

described in detail in ”Boot Loader Support – Read-While-Write Self-Programming” on page

279. ”Memory Programming” on page 295 contains a detailed description on Flash data serial

downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 15.

Figure 6-1. Program Memory Map

Program Memory

0x0000

Application Flash Section

Boot Flash Section

0x1FFF

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6.2

SRAM Data Memory

Figure 6-2 on page 19 shows how the ATmega169P SRAM Memory is organized.

The ATmega169P is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

The lower 1,280 data memory locations address both the Register File, the I/O memory,

Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register

File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,

and the next 1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 1,024 bytes of internal data SRAM in the ATmega169P are all accessible through all these

addressing modes. The Register File is described in ”General Purpose Register File” on page

13.

Figure 6-2. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

32 Registers

64 I/O Registers

160 Ext I/O Reg.

0x0100

Internal SRAM

(1024 x 8)

0x04FF

6.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 6-3 on page

20.

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Figure 6-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

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6.3

EEPROM Data Memory

The ATmega169P contains 512 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. This section describes the access between the EEPROM and

the CPU, specifying the EEPROM Address Registers, the EEPROM Data Register, and the

EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

”Serial Downloading” on page 309, ”Programming via the JTAG Interface” on page 314, and

”Parallel Programming Parameters, Pin Mapping, and Commands” on page 298 respectively.

6.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 6-1 on page 22. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered

power supplies, V_CCis likely to rise or fall slowly on power-up/down. This causes the device for

some period of time to run at a voltage lower than specified as minimum for the clock frequency

used. See ”Preventing EEPROM Corruption” on page 25 for details on how to avoid problems in

these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

The following procedure should be followed when writing the EEPROM (the order of steps 3 and

4 is not essential). See ”EEPROM Register Description” on page 26 for supplementary descrip-

tion for each register bit:

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ”Boot Loader

Support – Read-While-Write Self-Programming” on page 279 for details about Boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

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When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 6-1 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 6-1.

EEPROM Programming Time

Number of Calibrated

Symbol

RC Oscillator Cycles

Typical Programming Time

EEPROM write (from CPU)

27 072

3.3 ms

The following code examples show one assembly and one C function for writing to the

EEPROM. To avoid that interrupts will occur during execution of these functions, the examples

assume that interrupts are controlled (e.g. by disabling interrupts globally). The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

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Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

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Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

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6.3.2

6.3.3

EEPROM Write During Power-down Sleep Mode

When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time has

passed. However, when the write operation is completed, the clock continues running, and as a

consequence, the device does not enter Power-down entirely. It is therefore recommended to

verify that the EEPROM write operation is completed before entering Power-down.

Preventing EEPROM Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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6.4

EEPROM Register Description

6.4.1

EEARH and EEARL – EEPROM Address Register

Bit

15

14

13

12

11

10

9

8

EEAR8

EEAR0

0

0x22 (0x42)

0x21 (0x41)

–

EEARH

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

7

R

6

R

5

R

4

R

3

R

2

R

1

R

Read/Write

Initial Value

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15:9 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM

may be accessed.

6.4.2

EEDR – EEPROM Data Register

Bit

7

6

5

4

3

2

1

0

0x20 (0x40)

Read/Write

Initial Value

MSB

R/W

0

LSB

R/W

0

EEDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

6.4.3

EECR – EEPROM Control Register

Bit

0x1F (0x3F)

7

6

–

5

–

4

–

3

EERIE

R/W

0

2

EEMWE

R/W

0

1

EEWE

R/W

X

0

EERE

R/W

0

–

EECR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

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the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

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6.5

I/O Memory

The I/O space definition of the ATmega169P is shown in ”Register Summary” on page 370.

All ATmega169P I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com-

plex microcontroller with more peripheral units than can be supported within the 64 location

reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -

0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

6.6

General Purpose I/O Registers

The ATmega169P contains three General Purpose I/O Registers. These registers can be used

for storing any information, and they are particularly useful for storing global variables and Sta-

tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-

accessible using the SBI, CBI, SBIS, and SBIC instructions.

6.6.1

6.6.2

6.6.3

GPIOR2 – General Purpose I/O Register 2

Bit

0x2B (0x4B)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR1 – General Purpose I/O Register 1

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2A (0x4A)

Read/Write

Initial Value

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR0 – General Purpose I/O Register 0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x1E (0x3E)

Read/Write

Initial Value

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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7. System Clock and Clock Options

7.1

Clock Systems and their Distribution

Figure 7-1 on page 29 presents the principal clock systems in the AVR and their distribution. All

of the clocks need not be active at a given time. In order to reduce power consumption, the

clocks to modules not being used can be halted by using different sleep modes, as described in

”Power Management and Sleep Modes” on page 39. The clock systems are detailed below.

Figure 7-1. Clock Distribution

Asynchronous

Timer/Counter

General I/O

Modules

Flash and

EEPROM

CPU Core

RAM

LCD Controller

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_ASY

clk_FLASH

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

System Clock

Prescaler

Oscillator

Watchdog

Clock

Multiplexer

Timer/Counter

Oscillator

Crystal

Oscillator

Low-frequency

Crystal Oscillator

Calibrated RC

Oscillator

External Clock

7.1.1

7.1.2

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that start condition detection in the USI module is carried out asynchro-

nously when clk_I/Ois halted, enabling USI start condition detection in all sleep modes.

7.1.3

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

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7.1.4

Asynchronous Timer Clock – clk_ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller

to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated

clock domain allows using this Timer/Counter as a real-time counter even when the device is in

sleep mode. It also allows the LCD controller output to continue while the rest of the device is in

sleep mode.

7.1.5

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

7.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 7-1.

Device Clocking Options Select⁽¹⁾

Device Clocking Option

External Crystal/Ceramic Resonator

External Low-frequency Crystal

Calibrated Internal RC Oscillator

External Clock

CKSEL3:0

1111 - 1000

0111 - 0110

0010

0000

Reserved

0011, 0001, 0101, 0100

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 7-

2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Charac-

teristics” on page 335.

Table 7-2.

Typ Time-out (V_CC= 5.0V)

4.1 ms

65 ms

Number of Watchdog Oscillator Cycles

Typ Time-out (V_CC= 3.0V)

4.3 ms

69 ms

Number of Cycles

4K (4,096)

64K (65,536)

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7.3

7.4

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is the Internal RC Oscillator with longest start-up time and an initial system

clock prescaling of 8. This default setting ensures that all users can make their desired clock

source setting using an In-System or Parallel programmer.

Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nom-

inal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See

”System Clock Prescaler” on page 36. for more details. This clock may be selected as the sys-

tem clock by programming the CKSEL Fuses as shown in Table 7-3. If selected, it will operate

with no external components. During reset, hardware loads the calibration byte into the OSC-

CAL Register, see ”OSCCAL – Oscillator Calibration Register” on page 37, and thereby

automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency of 8

MHz 1ꢀ. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within

1ꢀ accuracy, by changing the OSCCAL register. When this Oscillator is used as the chip clock,

the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For

more information on the pre-programmed calibration value, see the section ”Calibration Byte” on

page 298..

Table 7-3.

Internal Calibrated RC Oscillator Operating Modes⁽¹⁾⁽³⁾

Frequency Range⁽²⁾(MHz)

CKSEL3:0

7.3 - 8.1

0010

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-4

Table 7-4.

Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1:0

00

6 CK

14CK

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms⁽¹⁾

01

6 CK

10

Reserved

11

Note:

1. The device is shipped with this option selected.

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7.5

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz crystal or a

ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 7-5. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

Figure 7-2. Crystal Oscillator Connections

C2

XTAL2 (TOSC2)

C1

XTAL1 (TOSC1)

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 7-5.

Table 7-5.

Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1 and

C2 for Use with Crystals (pF)

CKSEL3:1

100⁽¹⁾

101

Frequency Range (MHz)

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 -

–

12 - 22

110

111

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

7-6.

Table 7-6.

Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

CKSEL0

SUT1:0

(V_CC= 5.0V)

Recommended Usage

Ceramic resonator, fast

rising power

0

00

258 CK⁽¹⁾

1K CK⁽²⁾

16K CK

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

0

1

01

10

11

00

01

10

11

Ceramic resonator, BOD

enabled

Ceramic resonator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

14CK

Ceramic resonator, slowly

rising power

Crystal Oscillator, BOD

enabled

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator, slowly

rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

7.6

Low-frequency Crystal Oscillator

The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal.

When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR

must be taken into consideration. Both values are specified by the crystal vendor. ATmega169P

oscillator is optimized for very low power consumption, and thus when selecting crystals, see

Table 7-7 on page 33 for maximum ESR recommendations on 12.5 pF and 6 pF crystals

Table 7-7.

Maximum ESR Recommendation for 32.768 kHz Watch Crystal

Crystal CL (pF)

Max ESR [kΩ]⁽¹⁾

6

60

20

12.5

Note:

1. Maximum ESR is typical value based on characterization

The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 6 pF. Crys-

tals with recommended 6 pF load capacitance can be without external capacitors as shown in

Figure 7-3 on page 34.

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Figure 7-3. Crystal Oscillator Connections

TOSC2 (XTAL2)

TOSC1 (XTAL1)

Table 7-8.

Low-frequency Crystal Oscillator Internal load Capacitance

Min. (pF)

TBD

Typ. (pF)

Max. (pF)

6

TBD

Crystals specifying load capacitance (CL) higher than 6 pF, require external capacitors applied

as described in Figure 7-2 on page 32.

To find suitable load capacitance for a 32.768 kHz crystal, please consult the crystal datasheet.

The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or

“0111” as shown in Table 7-10. Start-up times are determined by the SUT Fuses as shown in

Table 7-9..

Table 7-9.

Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0

00

Additional Delay from Reset (V_CC= 5.0V) Recommended Usage

TBD

Fast rising power or BOD enabled

Slowly rising power

01

10

Stable frequency at start-up

11

Reserved

Table 7-10. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

CKSEL3..0

0110⁽¹⁾

Power-down and Power-save

Recommended Usage

TBD

0111

Stable frequency at start-up

Note:

1. This option should only be used if frequency stability at start-up is not important for the

application

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7.7

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

7-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 7-4. External Clock Drive Configuration

NC

XTAL2

EXTERNAL

CLOCK

XTAL1

GND

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 7-12.

Table 7-11. Crystal Oscillator Clock Frequency

CKSEL3..0

Frequency Range

0000

0 - 16 MHz

Table 7-12. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4.1 ms

14CK + 65 ms

Reserved

Fast rising power

Slowly rising power

10

11

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2ꢀ from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

36 for details.

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7.8

Timer/Counter Oscillator

ATmega169P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter

Oscillator. See ”Low-frequency Crystal Oscillator” on page 33 for details on the oscillator and

crystal requirements.

ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and

XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the

oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be

used when the Calibrated Internal RC Oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is

written to logic one. See ”Asynchronous operation of the Timer/Counter” on page 150 for further

description on selecting external clock as input instead of a 32.768 kHz watch crystal.

7.9

Clock Output Buffer

When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is

suitable when chip clock is used to drive other circuits on the system. The clock will be output

also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-

grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO

serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that

is output when the CKOUT Fuse is programmed.

7.10 System Clock Prescaler

The ATmega169P system clock can be divided by setting the ”CLKPR – Clock Prescale Regis-

ter” on page 37. This feature can be used to decrease the system clock frequency and power

consumption when the requirement for processing power is low. This can be used with all clock

source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.

clk_I/O, clk_ADC, clk_CPU, and clk_FLASHare divided by a factor as shown in Table 7-13.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted. From the time the CLKPS values are writ-

ten, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this

interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the

period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

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7.11 Register Description

7.11.1

OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

(0x66)

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. The factory-calibrated value is automat-

ically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C.

The application software can write this register to change the oscillator frequency. The oscillator

can be calibrated to any frequency in the range 7.3 - 8.1 MHz within 1ꢀ accuracy. Calibration

outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2ꢀ in the fre-

quency range 7.3 - 8.1 MHz.

7.11.2

CLKPR – Clock Prescale Register

Bit

7

6

–

5

–

4

–

3

2

1

0

CLKPCE

R/W

0

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

(0x61)

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 7-13.

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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock

source has a higher frequency than the maximum frequency of the device at the present operat-

ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8

Fuse setting. The Application software must ensure that a sufficient division factor is chosen if

the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 7-13. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

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8. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving-

power. The AVR provides various sleep modes allowing the user to tailor the power

consumption to the application’s requirements.

8.1

Sleep Modes

Figure 7-1 on page 29 presents the different clock systems in the ATmega169P, and their distri-

bution. The figure is helpful in selecting an appropriate sleep mode. Table 8-1 shows the

different sleep modes and their wake up sources.

Table 8-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

Sleep

Mode

Idle

X

X⁽²⁾

X

ADC NRM

X

X⁽³⁾

X⁽²⁾

Power-

down

X⁽³⁾

X

Power-

save

X

X⁽³⁾

X

Standby⁽¹⁾

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.

3. For INT0, only level interrupt.

To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP

instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which

sleep mode will be activated by the SLEEP instruction. See Table 8-2 on page 44 for a

summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

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8.2

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator,

ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This

sleep mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

8.3

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the USI

start condition detection, Timer/Counter2, LCD Controller, and the Watchdog to continue operat-

ing (if enabled). This sleep mode basically halts clk_I/O, clk_CPU, and clk_FLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an LCD controller interrupt, USI start condition interrupt, a Timer/Counter2 interrupt, an

SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can

wake up the MCU from ADC Noise Reduction mode.

8.4

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the

USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-

nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level

interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically

halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 61

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in ”Clock Sources” on page 30.

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8.5

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep.

The device can wake up from either Timer Overflow or Output Compare event from

Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2,

and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller

interrupt.

If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended

instead of Power-save mode.

The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously

in Power-save mode. The clock source for the two modules can be selected independent of

each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous

clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the

Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note

that even if the synchronous clock is running in Power-save, this clock is only available for the

LCD controller and Timer/Counter2.

8.6

8.7

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

Power Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 44, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See ”Supply Current of I/O modules” on page 340 for examples. In all other

sleep modes, the clock is already stopped.

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8.8

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

8.8.1

8.8.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to ”ADC - Analog to Digital Converter” on page

215 for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep

mode. Refer to ”AC - Analog Comparator” on page 211 for details on how to configure the Ana-

log Comparator.

8.8.3

8.8.4

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to ”Brown-out Detection” on page 49 for details

on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-

age Reference” on page 51 for details on the start-up time.

8.8.5

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to ”Watchdog Timer” on page 51 for details on how to configure the Watchdog Timer.

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8.8.6

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 69 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 214 and ”DIDR0 – Digital

Input Disable Register 0” on page 232 for details.

8.8.7

JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or

Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will

contribute significantly to the total current consumption. There are three alternative ways to

avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCSR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or

leaving the JTAG fuse unprogrammed disables the JTAG interface.

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8.9

Register Description

8.9.1

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

SE

R/W

0

0x33 (0x53)

Read/Write

Initial Value

SM2

R/W

0

SM1

R/W

0

SM0

R/W

0

SMCR

R

0

R

0

R

0

R

0

• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 8-2.

Table 8-2.

Sleep Mode Select

SM2

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Power-save

Reserved

Standby⁽¹⁾

Reserved

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

8.9.2

PRR – Power Reduction Register

Bit

(0x64)

7

6

–

5

–

4

PRLCD

R/W

0

3

PRTIM1

R/W

0

2

PRSPI

R/W

0

1

PRUSART0

R/W

0

PRADC

R/W

0

–

PRR

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7:5 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 4 - PRLCD: Power Reduction LCD

Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled

and the display discharged before shut down. See "Disabling the LCD" on page 217 for details

on how to disable the LCD controller.

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• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re initialized to ensure proper

operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When

waking up the USART again, the USART should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Note:

The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control

and Status Register” on page 213.

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9. System Control and Reset

9.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. This is also the case if the Reset Vector is in the Application section while the Interrupt

Vectors are in the Boot section or vice versa. The circuit diagram in Figure 9-1 on page 47

shows the reset logic. Table 9-1 on page 47 defines the electrical parameters of the reset

circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in ”Clock Sources” on page 30.

9.2

Reset Sources

The ATmega169P has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than

the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out Reset

threshold (V_BOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one

of the scan chains of the JTAG system. Refer to the section ”IEEE 1149.1 (JTAG) Boundary-

scan” on page 257 for details.

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Figure 9-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Register

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

Table 9-1.

Symbol

Reset Characteristics

Parameter

Condition

Min

Typ

Max

Units

Power-on Reset Threshold

Voltage (rising)

T_A= -40°C

to 85°C

0.7

1.0

1.4

V

V_POT

Power-on Reset Threshold

Voltage (falling)⁽¹⁾

T_A= -40°C

to 85°C

0.6

0.9

1.3

0.9 V_CC

2.5

V

V_RST

t_RST

RESET Pin Threshold Voltage

V_CC= 3V

0.2 V_CC

Minimum pulse width on RESET

V_CC= 3V

µs

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

Power-on Reset

9.2.1

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 9-1. The POR is activated whenever V_CCis below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

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Figure 9-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 9-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

9.2.2

External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see Table 9-1 on page 47) will generate a reset, even if the clock is not

running. Shorter pulses are not guaranteed to generate a reset. When the applied signal

reaches the Reset Threshold Voltage – V_RST– on its positive edge, the delay counter starts the

MCU after the Time-out period – t_TOUT– has expired.

Figure 9-4. External Reset During Operation

CC

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9.2.3

Brown-out Detection

ATmega169P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

=

V

Table 9-2.

BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2..0 Fuses Min V_BOT

Typ V_BOT

Max V_BOT

Units

111

110

101

100

011

010

001

000

BOD Disabled

1.7

2.5

4.1

1.8

2.7

4.3

2.0

2.9

4.5

V

Reserved

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-Out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 110 for ATmega169V.

Table 9-3.

Symbol

V_HYST

Brown-out Characteristics

Parameter

Min

Typ

50

2

Max

Units

mV

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

t_BOD

µs

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

9-5), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 9-5), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in Table 9-1.

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Figure 9-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

9.2.4

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 51 for details on operation of the Watchdog Timer.

Figure 9-6. Watchdog Reset During Operation

CC

CK

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9.3

Internal Voltage Reference

ATmega169P features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

9.3.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in Table 9-4. To save power, the reference is not always turned on. The

reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 9-4.

Symbol

Internal Voltage Reference Characteristics⁽¹⁾

Parameter

Condition

Min

Typ

Max

Units

V

_CC= 2.7V,

V_BG

t_BG

I_BG

Bandgap reference voltage

1.0

1.1

1.2

V

T_A= 25°C

V_CC= 2.7V,

T_A= 25°C

Bandgap reference start-up time

40

15

70

µs

Bandgap reference current

consumption

V_CC= 2.7V,

T_A= 25°C

µA

Note:

1. Values are guidelines only. Actual values are TBD.

9.4

Watchdog Timer

The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is

the typical value at V_CC= 5V. See characterization data for typical values at other V_CClevels. By

controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as

shown in Table 9-6 on page 55. The WDR – Watchdog Reset – instruction resets the Watchdog

Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.

Eight different clock cycle periods can be selected to determine the reset period. If the reset

period expires without another Watchdog Reset, the ATmega169P resets and executes from the

Reset Vector. For timing details on the Watchdog Reset, refer to Table 9-6 on page 55.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,

two different safety levels are selected by the fuse WDTON as shown in Table 9-5. Refer to

”Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 52 for

details.

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Table 9-5.

WDT Configuration as a Function of the Fuse Settings of WDTON

Safety

Level

WDT Initial

State

How to Disable the

WDT

How to Change Time-

out

WDTON

Unprogrammed

Programmed

1

2

Disabled

Enabled

Timed sequence

Always enabled

Timed sequence

Figure 9-7. Watchdog Timer

WATCHDOG

OSCILLATOR

9.4.1

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate

procedures are described for each level.

9.4.1.1

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out

period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or

changing the Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as

desired, but with the WDCE bit cleared.

9.4.1.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with

the WDCE bit cleared. The value written to the WDE bit is irrelevant.

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Assembly Code Example⁽¹⁾

WDT_off:

; Reset WDT

wdr

; Write logical one to WDCE and WDE

in r16, WDTCR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

/* Reset WDT */

__watchdog_reset();

/* Write logical one to WDCE and WDE */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

Note:

1. See ”About Code Examples” on page 9.

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9.5

Register Description

9.5.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

6

–

5

–

4

3

2

BORF

1

0

0x35 (0x55)

Read/Write

Initial Value

JTRF

R/W

WDRF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R/W

See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

9.5.2

WDTCR – Watchdog Timer Control Register

Bit

(0x60)

7

6

5

–

4

WDCE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

–

WDTCR

Read/Write

Initial Value

R

0

R

0

R

0

• Bits 7:5 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure. This bit must also be set when

changing the prescaler bits. See ”Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 52.

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• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See ”Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 52.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-

dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods

are shown in Table 9-6.

Table 9-6.

Watchdog Timer Prescale Select

Number of WDT

Oscillator Cycles

Typical Time-out at

V_CC= 3.0V

Typical Time-out at

V_CC= 5.0V

WDP2

WDP1

WDP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

15.4 ms

30.8 ms

61.6 ms

0.12 s

0.25 s

0.49 s

1.0 s

14.7 ms

29.3 ms

58.7 ms

0.12 s

0.23 s

0.47 s

0.9 s

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

2.0 s

1.9 s

Note:

Also see Figure 28-54 on page 363.

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

55

8018A–AVR–03/06

10. Interrupts

This section describes the specifics of the interrupt handling as performed in ATmega169P. For

a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on

page 16.

10.1 Interrupt Vectors in ATmega169P

Table 10-1. Reset and Interrupt Vectors

Vector Program

No.

Address⁽²⁾

Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset, and JTAG AVR Reset

1

0x0000⁽¹⁾

RESET

2

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

INT0

External Interrupt Request 0

Pin Change Interrupt Request 0

Pin Change Interrupt Request 1

Timer/Counter2 Compare Match

Timer/Counter2 Overflow

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART0, Rx Complete

3

PCINT0

4

PCINT1

5

TIMER2 COMP

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 OVF

TIMER0 COMP

TIMER0 OVF

SPI, STC

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

USART, RX

USART, UDREn

USART, TX

USI START

USI OVERFLOW

ANALOG COMP

ADC

USART0 Data Register Empty

USART0, Tx Complete

USI Start Condition

USI Overflow

Analog Comparator

ADC Conversion Complete

EEPROM Ready

EE READY

SPM READY

LCD

Store Program Memory Ready

LCD Start of Frame

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

reset, see ”Boot Loader Support – Read-While-Write Self-Programming” on page 279.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot

Flash Section. The address of each Interrupt Vector will then be the address in this table

added to the start address of the Boot Flash Section.

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Table 10-2 on page 57 shows reset and Interrupt Vectors placement for the various combina-

tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in

the Boot section or vice versa.

Table 10-2. Reset and Interrupt Vectors Placement⁽¹⁾

BOOTRST

IVSEL

Reset Address

0x0000

Interrupt Vectors Start Address

0x0002

1

0

1

0

1

0x0000

Boot Reset Address + 0x0002

0x0002

Boot Reset Address

Boot Reset Address + 0x0002

Note:

1. The Boot Reset Address is shown in Table 25-6 on page 291. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega169P is:

Address Labels Code

Comments

0x0000

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

;

jmp

RESET

; Reset Handler

EXT_INT0

PCINT0

; IRQ0 Handler

; PCINT0 Handler

PCINT1

; PCINT0 Handler

TIM2_COMP

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_COMP

TIM0_OVF

SPI_STC

; Timer2 Compare Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 CompareA Handler

; Timer1 CompareB Handler

; Timer1 Overflow Handler

; Timer0 Compare Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; USART0 RX Complete Handler

; USART0,UDRn Empty Handler

; USART0 TX Complete Handler

; USI Start Condition Handler

; USI Overflow Handler

; Analog Comparator Handler

; ADC Conversion Complete Handler

; EEPROM Ready Handler

; SPM Ready Handler

USART_RXCn

USART_DRE

USART_TXCn

USI_STRT

USI_OVFL

ANA_COMP

ADC

EE_RDY

SPM_RDY

LCD_SOF

; LCD Start of Frame Handler

0x002E RESET: ldi

r16, high(RAMEND); Main program start

0x002F

0x0030

out

ldi

SPH,r16

Set Stack Pointer to top of RAM

r16, low(RAMEND)

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0x0031

0x0032

out

sei

SPL,r16

; Enable interrupts

0x0033

...

<instr> xxx

... ...

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code

0x0000 RESET: ldi

Comments

r16,high(RAMEND); Main program start

0x0001

0x0002

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x0003

0x0004

out

sei

; Enable interrupts

0x0005

;

<instr> xxx

.org 0x1C02

0x1C02

0x1C04

...

jmp

...

jmp

EXT_INT0

; IRQ0 Handler

PCINT0

...

; PCINT0 Handler

;

0x1C2C

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code

.org 0x0002

Comments

0x0002

0x0004

...

jmp

...

jmp

EXT_INT0

PCINT0

...

; IRQ0 Handler

; PCINT0 Handler

;

0x002C

;

SPM_RDY

; Store Program Memory Ready Handler

.org 0x1C00

0x1C00 RESET: ldi

r16,high(RAMEND); Main program start

0x1C01

0x1C02

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x1C03

0x1C04

out

sei

; Enable interrupts

0x1C05

<instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code

Comments

;

.org 0x1C00

0x1C00

0x1C02

jmp

RESET

EXT_INT0

; Reset handler

; IRQ0 Handler

0x1C04

...

jmp

...

jmp

PCINT0

...

; PCINT0 Handler

;

0x1C2C

SPM_RDY

; Store Program Memory Ready Handler

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ATmega169P

;

0x1C2E RESET: ldi

r16,high(RAMEND); Main program start

0x1C2F

0x1C30

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x1C31

0x1C32

out

sei

; Enable interrupts

0x1C33

<instr> xxx

10.2 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table, see

”MCUCR – MCU Control Register” on page 60.

To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-

lowed to change the IVSEL bit:

a. Write the Interrupt Vector Change Enable (IVCE) bit to one.

b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section ”Boot Loader Support – Read-While-

Write Self-Programming” on page 279 for details on Boot Lock bits.

The following example shows how interrupts are moved.

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Assembly Code Example

Move_interrupts:

; Get MCUCR

in r16, MCUCR

mov r17, r16

; Enable change of Interrupt Vectors

ori r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ori r17, (1<<IVSEL)

out MCUCR, r17

ret

C Code Example

void Move_interrupts(void)

{

uchar temp;

/* Get MCUCR*/

temp = MCUCR;

/* Enable change of Interrupt Vectors */

MCUCR = temp | (1<<IVCE);

/* Move interrupts to Boot Flash section

*/ MCUCR = temp | (1<<IVSEL);

}

10.2.1

MCUCR – MCU Control Register

Bit

7

6

-

5

-

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

0x35 (0x55)

Read/Write

Initial Value

JTD

R/W

0

PUD

R/W

0

MCUCR

R

0

R

0

R

0

R

0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section ”Boot Loader Support – Read-While-Write

Self-Programming” on page 279 for details.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the description in ”Moving Interrupts Between Application and Boot

Space” on page 59. See Code Example.

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11. External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as

outputs. This feature provides a way of generating a software interrupt. The pin change interrupt

PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if

any enabled PCINT7..0 pin toggles. The PCMSK1 and PCMSK0 Registers control which pins

contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asyn-

chronously. This implies that these interrupts can be used for waking the part also from sleep

modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the External Interrupt Control Register A – EICRA. When the

INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as

the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the

presence of an I/O clock, described in ”Clock Systems and their Distribution” on page 29. Low

level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used

for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all

sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in ”System Clock and Clock Options” on page 29.

11.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 11-1 on page 61

Figure 11-1. Pin Change Interrupt

pin_lat

pcint_in_(0)

PCINT(0)

0

x

D

Q

pcint_syn

pcint_setflag

PCIF

pin_sync

PCINT(0) in PCMSK(x)

LE

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

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11.2 Register Description

11.2.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

ISC01

R/W

0

ISC00

R/W

0

(0x69)

EICRA

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 11-1. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

Table 11-1. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

11.2.2

EIMSK – External Interrupt Mask Register

Bit

7

PCIE1

R/W

0

6

PCIE0

R/W

0

5

–

4

–

3

–

2

–

1

–

0

0x1D (0x3D)

Read/Write

Initial Value

INT0

R/W

0

EIMSK

R

0

R

0

R

0

R

0

R

0

• Bit 7 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register.

• Bit 6 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

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interrupt request even if INT0 is configured as an output. The corresponding interrupt of External

Interrupt Request 0 is executed from the INT0 Interrupt Vector.

11.2.3

EIFR – External Interrupt Flag Register

Bit

0x1C (0x3C)

7

6

5

–

4

–

3

–

2

–

1

–

0

INTF0

R/W

0

PCIF1

PCIF0

R/W

0

EIFR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 6 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

11.2.4

PCMSK1 – Pin Change Mask Register 1

Bit

7

6

PCINT14

R/W

0

5

PCINT13

R/W

0

4

PCINT12

R/W

0

3

PCINT11

R/W

0

2

PCINT10

R/W

0

1

PCINT9

R/W

0

PCINT8

R/W

0

PCINT15

R/W

0

PCMSK1

(0x6C)

Read/Write

Initial Value

• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8

Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O

pin is disabled.

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11.2.5

PCMSK0 – Pin Change Mask Register 0

Bit

7

6

5

4

3

2

1

0

(0x6B)

PCINT7

R/W

0

PCINT6

R/W

0

PCINT5

R/W

0

PCINT4

R/W

0

PCINT3

R/W

0

PCINT2

R/W

0

PCINT1

R/W

0

PCINT0

R/W

0

PCMSK0

Read/Write

Initial Value

• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT7:0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the cor-

responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

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12. I/O-Ports

12.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 12-1 on page 65. Refer to

”Electrical Characteristics” on page 327 for a complete list of parameters.

Figure 12-1. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in ”Register Description for I/O-Ports” on page 88.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page

66. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in ”Alternate Port

Functions” on page 71. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

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12.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 12-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

SLEEP:

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

12.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description for I/O-Ports” on page 88, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

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12.2.2

12.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 12-1 on page 67 summarizes the control signals for the pin value.

Table 12-1. Port Pin Configurations

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

No

Comment

0

1

0

1

X

0

Input

Tri-state (Hi-Z)

0

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

0

1

Input

1

X

Output

No

Output Low (Sink)

Output High (Source)

1

No

12.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 12-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 12-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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Figure 12-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

XXX

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 12-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

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values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

12.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 12-2, the digital input signal can be clamped to ground at the input of the

Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in ”Alternate Port Functions” on page 71.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

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12.2.6

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

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12.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5

shows how the port pin control signals from the simplified Figure 12-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 12-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

WPx

Q _CLR

DIEOExn

DIEOVxn

SLEEP

RESET

WRx

1

0

RRx

RPx

SYNCHRONIZER

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

I/O CLOCK

DIGITAL INPUT PIN n ON PORTx

ANALOG INPUT/OUTPUT PIN n ON PORTx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

DIxn:

AIOxn:

:

SLEEP:

SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

Table 12-2 on page 72 summarizes the function of the overriding signals. The pin and port

indexes from Figure 12-5 on page 71 are not shown in the succeeding tables. The overriding

signals are generated internally in the modules having the alternate function.

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Table 12-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up Override

Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

DI

Digital Input

This is the Analog Input/output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

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12.3.1

Alternate Functions of Port A

The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller.

Table 12-3. Port A Pins Alternate Functions

Port Pin

PA7

Alternate Function

SEG3 (LCD Front Plane 3)

SEG2 (LCD Front Plane 2)

SEG1 (LCD Front Plane 1)

SEG0 (LCD Front Plane 0)

COM3 (LCD Back Plane 3)

COM2 (LCD Back Plane 2)

COM1 (LCD Back Plane 1)

COM0 (LCD Back Plane 0)

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Table 12-4 and Table 12-5 relates the alternate functions of Port A to the overriding signals

shown in Figure 12-5 on page 71.

Table 12-4. Overriding Signals for Alternate Functions in PA7..PA4

Signal Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PA7/SEG3

PA6/SEG2

PA5/SEG1

PA4/SEG0

LCDEN

0

LCDEN

0

–

LCDEN

0

–

AIO

SEG3

SEG2

SEG1

SEG0

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Table 12-5. Overriding Signals for Alternate Functions in PA3..PA0

Signal Name

PA3/COM3

PA2/COM2

PA1/COM1

PA0/COM0

LCDEN

0

LCDEN •

(LCDMUX>2)

LCDEN •

(LCDMUX>1)

LCDEN •

(LCDMUX>0)

PUOE

PUOV

0

LCDEN •

(LCDMUX>2)

LCDEN •

(LCDMUX>1)

LCDEN •

(LCDMUX>0)

DDOE

LCDEN

DDOV

PVOE

PVOV

PTOE

0

–

0

–

0

–

0

–

LCDEN •

(LCDMUX>2)

LCDEN •

(LCDMUX>1)

LCDEN •

(LCDMUX>0)

DIEOE

LCDEN

DIEOV

0

DI

AIO

–

COM3

COM2

COM1

COM0

12.3.2

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 12-6.

Table 12-6. Port B Pins Alternate Functions

Port Pin

Alternate Functions

OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change

Interrupt15).

PB7

OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change

Interrupt14).

PB6

PB5

PB4

OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change

Interrupt13).

OC0A/PCINT12 (Output Compare and PWM Output A for Timer/Counter0 or Pin Change

Interrupt12).

PB3

PB2

PB1

PB0

MISO/PCINT11 (SPI Bus Master Input/Slave Output or Pin Change Interrupt11).

MOSI/PCINT10 (SPI Bus Master Output/Slave Input or Pin Change Interrupt10).

SCK/PCINT9 (SPI Bus Serial Clock or Pin Change Interrupt9).

SS/PCINT8 (SPI Slave Select input or Pin Change Interrupt8).

The alternate pin configuration is as follows:

• OC2A/PCINT15, Bit 7

OC2, Output Compare Match A output: The PB7 pin can serve as an external output for the

Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB7 set (one))

to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt

source.

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• OC1B/PCINT14, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the

Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one))

to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt

source.

• OC1A/PCINT13, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the

Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one))

to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt

source.

• OC0A/PCINT12, Bit 4

OC0A, Output Compare Match A output: The PB4 pin can serve as an external output for the

Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB4 set (one))

to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt

source.

• MISO/PCINT11 – Port B, Bit 3

MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master,

this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as

a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an

input, the pull-up can still be controlled by the PORTB3 bit.

PCINT11, Pin Change Interrupt Source 11: The PB3 pin can serve as an external interrupt

source.

• MOSI/PCINT10 – Port B, Bit 2

MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave,

this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as

a Master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an

input, the pull-up can still be controlled by the PORTB2 bit.

PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt

source.

• SCK/PCINT9 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave,

this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as

a Master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an

input, the pull-up can still be controlled by the PORTB1 bit.

PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source.

• SS/PCINT8 – Port B, Bit 0

SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an

input regardless of the setting of DDB0. As a Slave, the SPI is activated when this pin is driven

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low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0.

When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit

PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.

Table 12-7 and Table 12-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 12-5 on page 71. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the

MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Table 12-7. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/OC2A/

PCINT15

PB6/OC1B/

PCINT14

PB5/OC1A/

PCINT13

PB4/OC0A/

PCINT12

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

0

OC2A ENABLE

OC1B ENABLE

OC1A ENABLE

OC0A ENABLE

OC2A

OC1B

OC1A

OC0A

–

PCINT15 • PCIE1

PCINT14 • PCIE1

PCINT13 • PCIE1

PCINT12 • PCIE1

1

PCINT15 INPUT

–

PCINT14 INPUT

–

PCINT13 INPUT

–

PCINT12 INPUT

–

AIO

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Table 12-8. Overriding Signals for Alternate Functions in PB3..PB0

Signal

Name

PB3/MISO/

PCINT11

PB2/MOSI/

PCINT10

PB1/SCK/

PCINT9

PB0/SS/

PCINT8

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

SPE • MSTR

PORTB3 • PUD

PORTB2 • PUD

PORTB1 • PUD

PORTB0 • PUD

SPE • MSTR

0

SPE • MSTR

0

SPI SLAVE OUTPUT

SPI MSTR OUTPUT

SCK OUTPUT

0

–

PCINT11 • PCIE1

1

PCINT10 • PCIE1

1

PCINT9 • PCIE1

1

PCINT8 • PCIE1

1

PCINT11 INPUT

SPI MSTR INPUT

PCINT10 INPUT

PCINT9 INPUT

SCK INPUT

PCINT8 INPUT

SPI SS

DI

SPI SLAVE INPUT

AIO

–

12.3.3

Alternate Functions of Port C

The Port C has an alternate function as the SEG5:12 for the LCD Controller

Table 12-9. Port C Pins Alternate Functions

Port Pin

PC7

Alternate Function

SEG5 (LCD Front Plane 5)

SEG6 (LCD Front Plane 6)

SEG7 (LCD Front Plane 7)

SEG8 (LCD Front Plane 8)

SEG9 (LCD Front Plane 9)

SEG10 (LCD Front Plane 10)

SEG11 (LCD Front Plane 11)

SEG12 (LCD Front Plane 12)

PC6

PC5

PC4

PC3

PC2

PC1

PC0

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Table 12-10 and Table 12-11 relate the alternate functions of Port C to the overriding signals

shown in Figure 12-5 on page 71.

Table 12-10. Overriding Signals for Alternate Functions in PC7..PC4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PC7/SEG5

PC6/SEG6

PC5/SEG7

PC4/SEG8

LCDEN

0

LCDEN

0

–

LCDEN

0

–

AIO

SEG5

SEG6

SEG7

SEG8

Table 12-11. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PC3/SEG9

PC2/SEG10

PC1/SEG11

PC0/SEG12

LCDEN

0

LCDEN

0

–

LCDEN

0

–

AIO

SEG9

SEG10

SEG11

SEG12

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12.3.4

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 12-12.

Table 12-12. Port D Pins Alternate Functions

Port Pin

PD7

Alternate Function

SEG15 (LCD front plane 15)

PD6

SEG16 (LCD front plane 16)

PD5

SEG17 (LCD front plane 17)

PD4

SEG18 (LCD front plane 18)

PD3

SEG19 (LCD front plane 19)

PD2

SEG20 (LCD front plane 20)

PD1

INT0/SEG21 (External Interrupt0 Input or LCD front plane 21)

PD0

ICP1/SEG22 (Timer/Counter1 Input Capture pin or LCD front plane 22)

The alternate pin configuration is as follows:

• SEG15 - SEG20 – Port D, Bit 7:2

SEG15-SEG20, LCD front plane 15-20.

• INT0/SEG21 – Port D, Bit 1

INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the

MCU.

SEG21, LCD front plane 21.

• ICP1/SEG22 – Port D, Bit 0

ICP1 – Input Capture pin1: The PD0 pin can act as an Input Capture pin for Timer/Counter1.

SEG22, LCD front plane 22

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Table 12-13 and Table 12-14 relates the alternate functions of Port D to the overriding signals

shown in Figure 12-5 on page 71.

Table 12-13. Overriding Signals for Alternate Functions PD7..PD4

Signal

Name

PUOE

PUOV

DDOE

PD7/SEG15

PD6/SEG16

PD5/SEG17

PD4/SEG18

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>2)

LCDEN •

(LCDPM>2)

0

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>2)

LCDEN •

(LCDPM>2)

DDOV

PVOE

PVOV

PTOE

0

–

0

–

0

–

0

–

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>1)

LCDEN •

(LCDPM>2)

LCDEN •

(LCDPM>2)

DIEOE

DIEOV

DI

0

–

AIO

SEG15

SEG16

SEG17

SEG18

Table 12-14. Overriding Signals for Alternate Functions in PD3..PD0

Signal

Name

PUOE

PUOV

DDOE

PD3/SEG19

PD2/SEG20

PD1/INT0/SEG21

PD0/ICP1/SEG22

LCDEN •

(LCDPM>3)

LCDEN •

(LCDPM>3)

LCDEN •

(LCDPM>4)

LCDEN •

(LCDPM>4)

0

LCDEN •

(LCDPM>3)

LCDEN •

(LCDPM>3)

LCDEN •

(LCDPM>4)

LCDEN •

(LCDPM>4)

DDOV

PVOE

PVOV

PTOE

0

–

0

–

0

–

0

–

LCDEN •

(LCDPM>3)

LCDEN •

(LCDPM>3)

LCDEN + (INT0

ENABLE)

LCDEN •

(LCDPM>4)

DIEOE

DIEOV

LCDEN • (INT0

ENABLE)

0

DI

–

INT0 INPUT

ICP1 INPUT

AIO

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12.3.5

Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 12-15.

Table 12-15. Port E Pins Alternate Functions

Port Pin

Alternate Function

PCINT7 (Pin Change Interrupt7)

CLKO (Divided System Clock)

PE7

PE6

PE5

DO/PCINT6 (USI Data Output or Pin Change Interrupt6)

DI/SDA/PCINT5 (USI Data Input or TWI Serial DAta or Pin Change Interrupt5)

USCK/SCL/PCINT4 (USART External Clock Input/Output or TWI Serial Clock or Pin

Change Interrupt4)

PE4

PE3

PE2

AIN1/PCINT3 (Analog Comparator Negative Input or Pin Change Interrupt3)

XCK/AIN0/ PCINT2 (USART External Clock or Analog Comparator Positive Input or Pin

Change Interrupt2)

PE1

PE0

TXD/PCINT1 (USART Transmit Pin or Pin Change Interrupt1)

RXD/PCINT0 (USART Receive Pin or Pin Change Interrupt0)

• PCINT7 – Port E, Bit 7

PCINT7, Pin Change Interrupt Source 7: The PE7 pin can serve as an external interrupt source.

CLKO, Divided System Clock: The divided system clock can be output on the PE7 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTE7 and DDE7 settings. It will also be output during reset.

• DO/PCINT6 – Port E, Bit 6

DO, Universal Serial Interface Data output.

PCINT6, Pin Change Interrupt Source 6: The PE6 pin can serve as an external interrupt source.

• DI/SDA/PCINT5 – Port E, Bit 5

DI, Universal Serial Interface Data input.

SDA, Two-wire Serial Interface Data:

PCINT5, Pin Change Interrupt Source 5: The PE5 pin can serve as an external interrupt source.

• USCK/SCL/PCINT4 – Port E, Bit 4

USCK, Universal Serial Interface Clock.

SCL, Two-wire Serial Interface Clock.

PCINT4, Pin Change Interrupt Source 4: The PE4 pin can serve as an external interrupt source.

• AIN1/PCINT3 – Port E, Bit 3

AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of

the Analog Comparator.

PCINT3, Pin Change Interrupt Source 3: The PE3 pin can serve as an external interrupt source.

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• XCK/AIN0/PCINT2 – Port E, Bit 2

XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is

output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper-

ates in synchronous mode.

AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of

the Analog Comparator.

PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.

• TXD/PCINT1 – Port E, Bit 1

TXD0, UART0 Transmit pin.

PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.

• RXD/PCINT0 – Port E, Bit 0

RXD, USART Receive pin. Receive Data (Data input pin for the USART). When the USART

Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the

USART forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.

PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.

Table 12-16 and Table 12-17 relates the alternate functions of Port E to the overriding signals

shown in Figure 12-5 on page 71.

Table 12-16. Overriding Signals for Alternate Functions PE7:PE4

Signal

Name

PE6/DO/

PCINT6

PE5/DI/SDA/

PCINT5

PE4/USCK/SCL/

PCINT4

PE7/PCINT7

PUOE

PUOV

DDOE

0

USI_TWO-WIRE

0

USI_TWO-WIRE

0

CKOUT⁽¹⁾

USI_TWO-WIRE

(SDA + PORTE5) •

DDE5

(USI_SCL_HOLD •

PORTE4) + DDE4

DDOV

PVOE

1

0

USI_THREE-

WIRE

USI_TWO-WIRE •

DDE5

CKOUT⁽¹⁾

USI_TWO-WIRE • DDE4

PVOV

PTOE

clk_I/O

–

DO

–

0

USITC

(PCINT5 • PCIE0) +

USISIE

(PCINT4 • PCIE0) +

USISIE

DIEOE

DIEOV

DI

PCINT7 • PCIE0 PCINT6 • PCIE0

1

DI/SDA INPUT

PCINT5 INPUT

USCKL/SCL INPUT

PCINT4 INPUT

PCINT7 INPUT

–

PCINT6 INPUT

–

AIO

–

Note:

1. CKOUT is one if the CKOUT Fuse is programmed

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Table 12-17. Overriding Signals for Alternate Functions in PE3:PE0

Signal

Name

PE3/AIN1/

PCINT3

PE2/XCK/AIN0/

PCINT2

PE1/TXD/

PCINT1

PE0/RXD/PCINT0

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

0

–

0

TXENn

RXENn

0

PORTE0 • PUD

TXENn

1

RXENn

0

–

XCK OUTPUT ENABLE TXENn

XCK

–

TXD

–

(PCINT3 • PCIE0)

+ AIN1D⁽¹⁾

(PCINT2 • PCIE0) +

AIN0D⁽¹⁾

DIEOE

PCINT1 • PCIE0

PCINT0 • PCIE0

DIEOV

DI

PCINT3 • PCIE0

PCINT3 INPUT

AIN1 INPUT

PCINT2 • PCIE0

XCK/PCINT2 INPUT

AIN0 INPUT

1

PCINT1 INPUT

–

RXD/PCINT0 INPUT

–

AIO

Note:

1. AIN0D and AIN1D is described in ”DIDR1 – Digital Input Disable Register 1” on page 214.

12.3.6

Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 12-18. If

some Port F pins are configured as outputs, it is essential that these do not switch when a con-

version is in progress. This might corrupt the result of the conversion. If the JTAG interface is

enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even

if a reset occurs.

Table 12-18. Port F Pins Alternate Functions

Port Pin

PF7

Alternate Function

ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)

ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

ADC3 (ADC input channel 3)

PF6

PF5

PF4

PF3

PF2

ADC2 (ADC input channel 2)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-

ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

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• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6.

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When

the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out

data, the TDO pin drives actively. In other states the pin is pulled high.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5.

TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state

machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4.

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is

enabled, this pin can not be used as an I/O pin.

• ADC3 - ADC0 – Port F, Bit 3:0

Analog to Digital Converter, Channel 3-0.

Table 12-19. Overriding Signals for Alternate Functions in PF7:PF4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PF7/ADC7/TDI

PF6/ADC6/TDO

PF5/ADC5/TMS

PF4/ADC4/TCK

JTAGEN

1

JTAGEN

0

SHIFT_IR + SHIFT_DR

0

JTAGEN

0

TDO

0

–

JTAGEN

0

–

0

–

0

–

0

–

TDI

ADC7 INPUT

TMS

ADC5 INPUT

TCK

ADC4 INPUT

AIO

ADC6 INPUT

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Table 12-20. Overriding Signals for Alternate Functions in PF3:PF0

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PF3/ADC3

PF2/ADC2

PF1/ADC1

PF0/ADC0

0

–

0

–

AIO

ADC3 INPUT

ADC2 INPUT

ADC1 INPUT

ADC0 INPUT

12.3.7

Alternate Functions of Port G

The alternate pin configuration is as follows:

Table 12-21. Port G Pins Alternate Functions⁽¹⁾

Port Pin

PG5

Alternate Function

RESET

PG4

T0/SEG23 (Timer/Counter0 Clock Input or LCD Front Plane 23)

T1/SEG24 (Timer/Counter1 Clock Input or LCD Front Plane 24)

SEG4 (LCD Front Plane 4)

PG3

PG2

PG1

SEG13 (LCD Front Plane 13)

PG0

SEG14 (LCD Front Plane 14)

Note:

1. Port G, PG5 is input only. Pull-up is always on.

See Table 26-3 on page 296 for RSTDISBL fuse.

The alternate pin configuration is as follows:

• RESET – Port G, Bit 5

RESET: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will function

as input with pull-up always on.

• T0/SEG23 – Port G, Bit 4

T0, Timer/Counter0 Counter Source.

SEG23, LCD front plane 23

• T1/SEG24 – Port G, Bit 3

T1, Timer/Counter1 Counter Source.

SEG24, LCD front plane 24

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• SEG4 – Port G, Bit 2

SEG4, LCD front plane 4

• SEG13 – Port G, Bit 1

SEG13, Segment driver 13

• SEG14 – Port G, Bit 0

SEG14, LCD front plane 14

Table 12-21 and Table 12-22 relates the alternate functions of Port G to the overriding signals

shown in Figure 12-5 on page 71.

Table 12-22. Overriding Signals for Alternate Functions in PG4

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

DI

PG4/T0/SEG23

LCDEN • (LCDPM>5)

0

LCDEN • (LCDPM>5)

1

0

–

LCDEN • (LCDPM>5)

0

T0 INPUT

SEG23

AIO

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ATmega169P

Table 12-23. Overriding Signals for Alternate Functions in PG3:0

Signal

Name

PUOE

PUOV

DDOE

PG3/T1/SEG24

PG2/SEG4

LCDEN

0

PG1/SEG13

PG0/SEG14

LCDEN •

(LCDPM>6)

LCDEN •

(LCDPM>0)

LCDEN • (LCDPM>0)

0

LCDEN •

(LCDPM>6)

LCDEN •

(LCDPM>0)

LCDEN

LCDEN • (LCDPM>0)

DDOV

PVOE

PVOV

PTOE

0

–

0

–

0

–

0

–

LCDEN •

(LCDPM>6)

LCDEN •

(LCDPM>0)

DIEOE

LCDEN

LCDEN • (LCDPM>0)

DIEOV

DI

0

T1 INPUT

SEG24

–

AIO

SEG4

SEG13

SEG14

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12.4 Register Description for I/O-Ports

12.4.1

MCUCR – MCU Control Register

Bit

7

6

-

5

-

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

0x35 (0x55)

Read/Write

Initial Value

JTD

R/W

0

PUD

R/W

0

MCUCR

R

0

R

0

R

0

R

0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-

figuring the Pin” on page 66 for more details about this feature.

12.4.2

12.4.3

12.4.4

12.4.5

12.4.6

12.4.7

PORTA – Port A Data Register

Bit

7

6

PORTA6

R/W

0

5

PORTA5

R/W

0

4

PORTA4

R/W

0

3

PORTA3

R/W

0

2

PORTA2

R/W

0

1

PORTA1

R/W

0

PORTA0

R/W

0

PORTA7

R/W

0

0x02 (0x22)

Read/Write

Initial Value

PORTA

DDRA

PINA

DDRA – Port A Data Direction Register

Bit

7

DDA7

R/W

0

6

DDA6

R/W

0

5

DDA5

R/W

0

4

DDA4

R/W

0

3

DDA3

R/W

0

2

DDA2

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

0x01 (0x21)

Read/Write

Initial Value

PINA – Port A Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x00 (0x20)

Read/Write

Initial Value

PINA7

R/W

N/A

PINA6

R/W

N/A

PINA5

R/W

N/A

PINA4

R/W

N/A

PINA3

R/W

N/A

PINA2

R/W

N/A

PINA1

R/W

N/A

PINA0

R/W

N/A

PORTB – Port B Data Register

Bit

7

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB7

R/W

0

PORTB

DDRB

PINB

0x05 (0x25)

Read/Write

Initial Value

DDRB – Port B Data Direction Register

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

0x04 (0x24)

Read/Write

Initial Value

PINB – Port B Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x03 (0x23)

Read/Write

Initial Value

PINB7

R/W

N/A

PINB6

R/W

N/A

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

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ATmega169P

12.4.8

12.4.9

PORTC – Port C Data Register

Bit

7

6

PORTC6

R/W

0

5

PORTC5

R/W

0

4

PORTC4

R/W

0

3

PORTC3

R/W

0

2

PORTC2

R/W

0

1

PORTC1

R/W

0

PORTC0

R/W

0

PORTC7

R/W

0

PORTC

DDRC

PINC

0x08 (0x28)

Read/Write

Initial Value

DDRC – Port C Data Direction Register

Bit

7

DDC7

R/W

0

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

0x07 (0x27)

Read/Write

Initial Value

12.4.10 PINC – Port C Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x06 (0x26)

Read/Write

Initial Value

PINC7

R/W

N/A

PINC6

R/W

N/A

PINC5

R/W

N/A

PINC4

R/W

N/A

PINC3

R/W

N/A

PINC2

R/W

N/A

PINC1

R/W

N/A

PINC0

R/W

N/A

12.4.11 PORTD – Port D Data Register

Bit

7

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD7

R/W

0

PORTD

DDRD

PIND

0x0B (0x2B)

Read/Write

Initial Value

12.4.12 DDRD – Port D Data Direction Register

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

0x0A (0x2A)

Read/Write

Initial Value

12.4.13 PIND – Port D Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x09 (0x29)

Read/Write

Initial Value

PIND7

R/W

N/A

PIND6

R/W

N/A

PIND5

R/W

N/A

PIND4

R/W

N/A

PIND3

R/W

N/A

PIND2

R/W

N/A

PIND1

R/W

N/A

PIND0

R/W

N/A

12.4.14 PORTE – Port E Data Register

Bit

7

6

PORTE6

R/W

0

5

PORTE5

R/W

0

4

PORTE4

R/W

0

3

PORTE3

R/W

0

2

PORTE2

R/W

0

1

PORTE1

R/W

0

PORTE0

R/W

0

PORTE7

R/W

0

PORTE

0x0E (0x2E)

Read/Write

Initial Value

12.4.15 DDRE – Port E Data Direction Register

Bit

7

DDE7

R/W

0

6

DDE6

R/W

0

5

DDE5

R/W

0

4

DDE4

R/W

0

3

DDE3

R/W

0

2

DDE2

R/W

0

1

DDE1

R/W

0

DDE0

R/W

0

0x0D (0x2D)

Read/Write

Initial Value

DDRE

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12.4.16 PINE – Port E Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x0C (0x2C)

Read/Write

Initial Value

PINE7

R/W

N/A

PINE6

R/W

N/A

PINE5

R/W

N/A

PINE4

R/W

N/A

PINE3

R/W

N/A

PINE2

R/W

N/A

PINE1

R/W

N/A

PINE0

R/W

N/A

PINE

PORTF

DDRF

PINF

12.4.17 PORTF – Port F Data Register

Bit

7

6

PORTF6

R/W

0

5

PORTF5

R/W

0

4

PORTF4

R/W

0

3

PORTF3

R/W

0

2

PORTF2

R/W

0

1

PORTF1

R/W

0

PORTF0

R/W

0

PORTF7

R/W

0

0x11 (0x31)

Read/Write

Initial Value

12.4.18 DDRF – Port F Data Direction Register

Bit

7

DDF7

R/W

0

6

DDF6

R/W

0

5

DDF5

R/W

0

4

DDF4

R/W

0

3

DDF3

R/W

0

2

DDF2

R/W

0

1

DDF1

R/W

0

DDF0

R/W

0

0x10 (0x30)

Read/Write

Initial Value

12.4.19 PINF – Port F Input Pins Address

Bit

7

6

5

4

3

2

1

0

0x0F (0x2F)

Read/Write

Initial Value

PINF7

R/W

N/A

PINF6

R/W

N/A

PINF5

R/W

N/A

PINF4

R/W

N/A

PINF3

R/W

N/A

PINF2

R/W

N/A

PINF1

R/W

N/A

PINF0

R/W

N/A

12.4.20 PORTG – Port G Data Register

Bit

7

6

–

5

–

4

PORTG4

R/W

0

3

PORTG3

R/W

0

2

PORTG2

R/W

0

1

PORTG1

R/W

0

PORTG0

R/W

0

PORTG

DDRG

PING

0x14 (0x34)

Read/Write

Initial Value

–

R

0

R

0

R

0

12.4.21 DDRG – Port G Data Direction Register

Bit

7

–

6

–

5

–

4

DDG4

R/W

0

3

DDG3

R/W

0

2

DDG2

R/W

0

1

DDG1

R/W

0

DDG0

R/W

0

0x13 (0x33)

Read/Write

Initial Value

R

0

R

0

R

0

12.4.22 PING – Port G Input Pins Address

Bit

7

–

6

–

5

–

4

3

2

1

0

0x12 (0x32)

Read/Write

Initial Value

PING4

R/W

N/A

PING3

R/W

N/A

PING2

R/W

N/A

PING1

R/W

N/A

PING0

R/W

N/A

R

0

R

0

R

0

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13. 8-bit Timer/Counter0 with PWM

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The

main features are:

• Single Compare Unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

13.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 13-1. For the actual

placement of I/O pins, refer to ”Pinout ATmega169P” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the ”8-bit Timer/Counter Register Description” on page 102.

Figure 13-1. 8-bit Timer/Counter Block Diagram

TCCRn

count

TOVn

(Int.Req.)

clear

Control Logic

TOP

Clock Select

direction

clk

Tn

Edge

Detector

Tn

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

= 0

= 0xFF

OCn

(Int.Req.)

Waveform

Generation

OCn

=

OCRn

13.1.1

Registers

The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-

rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt

Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-

ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

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The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output

Compare Unit” on page 93. for details. The compare match event will also set the Compare Flag

(OCF0A) which can be used to generate an Output Compare interrupt request.

13.1.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare unit number, in this case unit A. However, when using the register or bit defines in a

program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter

value and so on.

The definitions in Table 13-1 are also used extensively throughout the document.

Table 13-1. Timer/Counter Definitions

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x00.

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is dependent

on the mode of operation.

13.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres-

caler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 135.

13.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

13-2 shows a block diagram of the counter and its surroundings.

Figure 13-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

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Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

top

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the Output Compare output

OC0A. For more details about advanced counting sequences and waveform generation, see

”Modes of Operation” on page 96.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

13.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set

the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and

Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare

interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively,

the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The

Waveform Generator uses the match signal to generate an output according to operating mode

set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig-

nals are used by the Waveform Generator for handling the special cases of the extreme values

in some modes of operation (See ”Modes of Operation” on page 96.).

Figure 13-3 shows a block diagram of the Output Compare unit.

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Figure 13-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

Waveform Generator

OCnx

FOCn

WGMn1:0

COMnx1:0

The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is

disabled the CPU will access the OCR0A directly.

13.4.1

13.4.2

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the

OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare

match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or

toggled).

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

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13.4.3

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the Output Compare unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-

pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value.

Changing the COM0A1:0 bits will take effect immediately.

13.5 Compare Match Output Unit

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator

uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare

match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 13-4 shows a sim-

plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,

and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-

ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the

OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System

Reset occur, the OC0A Register is reset to “0”.

Figure 13-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCn

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform

Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-

ible on the pin. The port override function is independent of the Waveform Generation mode.

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The design of the Output Compare pin logic allows initialization of the OC0A state before the

output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of

operation. See ”8-bit Timer/Counter Register Description” on page 102.

13.5.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM

modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on

the OC0A Register is to be performed on the next compare match. For compare output actions

in the non-PWM modes refer to Table 13-3 on page 103. For fast PWM mode, refer to Table 13-

4 on page 103, and for phase correct PWM refer to Table 13-5 on page 103.

A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0A strobe bits.

13.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output

mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM

output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM

modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a

compare match (See ”Compare Match Output Unit” on page 95.).

For detailed timing information refer to Figure 13-8, Figure 13-9, Figure 13-10 and Figure 13-11

in ”Timer/Counter Timing Diagrams” on page 100.

13.6.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

13.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

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The timing diagram for the CTC mode is shown in Figure 13-5. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 13-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC0

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

13.6.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare

match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

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In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0A and TCNT0.

Figure 13-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.

Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0A1:0 to three (See Table 13-4 on page 103). The actual

OC0A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC0A Register at the compare

match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50ꢀ duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero. This

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feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

13.6.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match

between TCNT0 and OCR0A while upcounting, and set on the compare match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 13-7.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0.

Figure 13-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCn

(COMnx1:0 = 3)

OCn

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0A1:0 to three (See Table 13-5 on page 103).

The actual OC0A value will only be visible on the port pin if the data direction for the port pin is

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set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the

compare match between OCR0A and TCNT0 when the counter increments, and setting (or

clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter

decrements. The PWM frequency for the output when using phase correct PWM can be calcu-

lated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 13-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 13-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the way

up.

13.7 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 13-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 13-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 13-9 shows the same timing data, but with the prescaler enabled.

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Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 13-10 shows the setting of OCF0A in all modes except CTC mode.

Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 13-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 13-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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13.8 8-bit Timer/Counter Register Description

13.8.1

TCCR0A – Timer/Counter Control Register A

Bit

7

FOC0A

W

6

WGM00

R/W

0

5

COM0A1

R/W

4

COM0A0

R/W

3

WGM01

R/W

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

TCCR0A

0x24 (0x44)

Read/Write

Initial Value

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for

ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written

when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-

pare match is forced on the Waveform Generation unit. The OC0A output is changed according

to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is

the value present in the COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 13-2 and ”Modes of Operation”

on page 96.

Note:

1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.

Table 13-2. Waveform Generation Mode Bit Description⁽¹⁾

WGM01

(CTC0)

WGM00

(PWM0)

Timer/Counter Mode

of Operation

Update of

OCR0A at

TOV0 Flag Set

on

Mode

TOP

0

1

2

3

0

1

0

1

0

1

Normal

0xFF

OCR0A

0xFF

Immediate

TOP

MAX

PWM, Phase Correct

CTC

BOTTOM

MAX

Immediate

TOP

Fast PWM

MAX

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM0A1:0: Compare Match Output Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

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When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM01:0 bit setting. Table 13-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits

are set to a normal or CTC mode (non-PWM).

Table 13-3. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on compare match

Clear OC0A on compare match

Set OC0A on compare match

Table 13-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 13-4. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match, set OC0A at TOP

Set OC0A on compare match, clear OC0A at TOP

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 97

for more details.

Table 13-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-

rect PWM mode.

Table 13-5. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0A disconnected.

Reserved

Clear OC0A on compare match when up-counting. Set OC0A on

compare match when downcounting.

1

0

1

Set OC0A on compare match when up-counting. Clear OC0A on

compare match when downcounting.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on

page 99 for more details.

• Bit 2:0 – CS02:0: Clock Select

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The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 13-6. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

13.8.2

TCNT0 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

0x26 (0x46)

Read/Write

Initial Value

TCNT0[7:0]

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.

13.8.3

OCR0A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

0x27 (0x47)

Read/Write

Initial Value

OCR0A[7:0]

OCR0A

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

13.8.4

TIMSK0 – Timer/Counter 0 Interrupt Mask Register

Bit

(0x6E)

7

6

5

4

–

3

–

2

–

1

OCIE0A

R/W

0

TOIE0

R/W

0

–

TIMSK0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

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When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

13.8.5

TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bit

0x15 (0x35)

7

6

5

–

4

–

3

–

2

–

1

OCF0A

R/W

0

TOV0

R/W

0

–

TIFR0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the

data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt

Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In

phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at

0x00.

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14. 16-bit Timer/Counter1

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement. The main features are:

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Two independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

14.1 Overview

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

number. However, when using the register or bit defines in a program, the precise form must be

used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 14-1. For the actual

placement of I/O pins, refer to ”Pinout ATmega169P” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the ”16-bit Timer/Counter Register Description” on page 128.

The PRTIM1 bit in ”PRR – Power Reduction Register” on page 44 must be written to zero to

enable Timer/Counter1 module

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Figure 14-1. 16-bit Timer/Counter Block Diagram⁽¹⁾

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

OCnB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRnB

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICRn

ICPn

TCCRnA

TCCRnB

Note:

1. Refer to Figure 1-1 on page 2, Table 12-5 on page 74, and Table 12-11 on page 78 for

Timer/Counter1 pin placement and description.

14.1.1

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section ”Accessing 16-bit Registers” on

page 109. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with

the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk ).

1

T

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-

ator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See

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”Output Compare Units” on page 115.. The compare match event will also set the Compare

Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See ”AC

- Analog Comparator” on page 211.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using

OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used

as an alternative, freeing the OCR1A to be used as PWM output.

14.1.2

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x0000.

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is

dependent of the mode of operation.

TOP

14.1.3

Compatibility

The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit

AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version

regarding:

• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt

Registers.

• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register location:

• PWM10 is changed to WGM10.

• PWM11 is changed to WGM11.

• CTC1 is changed to WGM12.

The following bits are added to the 16-bit Timer/Counter Control Registers:

• FOC1A and FOC1B are added to TCCR1C.

• WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special

cases.

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14.2 Accessing 16-bit Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via

the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.

Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers within each 16-bit

timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a

16-bit register is written by the CPU, the high byte stored in the temporary register, and the low

byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of

a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-

rary register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-

bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit

access.

Assembly Code Examples⁽¹⁾

...

; Set TCNT1 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNT1H,r17

outTCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

Note:

1. See ”About Code Examples” on page 9.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

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the main code and the interrupt code update the temporary register, the main code must disable

the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNT1 Register contents.

Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. See ”About Code Examples” on page 9.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

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The following code examples show how to do an atomic write of the TCNT1 Register contents.

Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example⁽¹⁾

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

outTCNT1H,r17

outTCNT1L,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

__disable_interrupt();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. See ”About Code Examples” on page 9.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

14.2.1

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits

located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and

prescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 135.

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14.4 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Clear

Edge

Detector

Tn

TCNTnH (8-bit)

TCNTnL (8-bit)

clk_Tn

Control Logic

Direction

TCNTn (16-bit Counter)

( From Prescaler )

TOP

BOTTOM

Signal description (internal signals):

Count

Increment or decrement TCNT1 by 1.

Direction

Clear

Select between increment and decrement.

Clear TCNT1 (set all bits to zero).

clk_T

Timer/Counter clock.

1

TOP

Signalize that TCNT1 has reached maximum value.

BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-

taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight

bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNT1H value when the TCNT1L is read, and

TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk ). The clk ₁can be generated from an external or internal clock source,

1

T

selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the

timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of

whether clk_Tis present or not. A CPU write overrides (has priority over) all counter clear or

1

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OC1x. For more details about advanced counting

sequences and waveform generation, see ”Modes of Operation” on page 118.

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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by

the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

14.5 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 14-3. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded. The

small “n” in register and bit names indicates the Timer/Counter number.

Figure 14-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ACO*

ACIC*

ICNC

ICES

Analog

Comparator

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPn

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at

the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),

the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically

cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software

by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low

byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied

into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will

access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes

the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-

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tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1

Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location

before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers”

on page 109.

14.5.1

Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the T1 pin (Figure 15-1 on page 135). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICR1 to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

14.5.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in

Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

14.5.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICR1

Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be

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cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICF1 Flag is not required (if an interrupt handler is used).

14.6 Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register

(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output

Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-

pare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared

when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See ”Modes of Operation” on page 118.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 14-4 shows a block diagram of the Output Compare unit. The small “n” in the register and

bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output

Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output

Compare unit are gray shaded.

Figure 14-4. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

OCRnx Buffer (16-bit Register)

TCNTn (16-bit Counter)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

= (16-bit Comparator )

OCFnx (Int.Req.)

TOP

OCnx

Waveform Generator

BOTTOM

WGMn3:0

COMnx1:0

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the

double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

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prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-

put glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)

Register is only changed by a write operation (the Timer/Counter does not update this register

automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte

temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare

Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to ”Accessing 16-bit Registers”

on page 109.

14.6.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the

OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare

match had occurred (the COMx1:0 bits settings define whether the OC1x pin is set, cleared or

toggled).

14.6.2

14.6.3

Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the

same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT1 when using any of the Output Compare

units, independent of whether the Timer/Counter is running or not. If the value written to TCNT1

equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform

generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The

compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly,

do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-

pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

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14.7 Compare Match Output Unit

The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses

the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 14-5 shows a simplified

schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the

OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset

occur, the OC1x Register is reset to “0”.

Figure 14-5. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform

Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 14-1, Table 14-2 and Table 14-3 for

details.

The design of the Output Compare pin logic allows initialization of the OC1x state before the out-

put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of

operation. See ”16-bit Timer/Counter Register Description” on page 128.

The COM1x1:0 bits have no effect on the Input Capture unit.

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14.7.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OC1x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 14-1 on page 128. For fast PWM mode refer to Table 14-2 on

page 128, and for phase correct and phase and frequency correct PWM refer to Table 14-3 on

page 129.

A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

14.8 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output

mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare

match (See ”Compare Match Output Unit” on page 117.)

For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 126.

14.8.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in

the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

14.8.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =

12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

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The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNT1)

increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)

is cleared.

Figure 14-6. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-

ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a

low prescaler value must be done with care since the CTC mode does not have the double buff-

ering feature. If the new value written to OCR1A or ICR1 is lower than the current value of

TCNT1, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-

quency of f_{OC A}= f_{clk_I/O}/2 when OCR1A is set to zero (0x0000). The waveform frequency is

1

defined by the following equation:

f

clk_I/O

f

= --------------------------------------------------

OCnA

2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

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14.8.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on

the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare

Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-

ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct

and phase and frequency correct PWM modes that use dual-slope operation. This high fre-

quency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or

OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-

imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

FPWM

log(2)

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =

14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-7. The figure

shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the

timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1

slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will

be set when a compare match occurs.

Figure 14-7. Fast PWM Mode, Timing Diagram

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition

the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A

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or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP

value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICR1 value written is lower than the current value of TCNT1. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location

to be written anytime. When the OCR1A I/O location is written the value written will be put into

the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done

at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM1x1:0 to three (see Table on page 128). The actual OC1x

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at

the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ----------------------------------

OCnxPWM

N ⋅ (1 + TOP)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COM1x1:0 bits.)

A frequency (with 50ꢀ duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only

if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have

a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCR1A is set to zero (0x0000). This feature is

1

similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-

pare unit is enabled in the fast PWM mode.

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14.8.4

Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is

cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is

inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

PCPWM

log(2)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1

(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-8. The figure

shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter-

rupt Flag will be set when a compare match occurs.

Figure 14-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When

either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-

ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer

value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCR1x Registers are written. As the third period shown in Figure 14-8 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an

unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg-

ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This

implies that the length of the falling slope is determined by the previous TOP value, while the

length of the rising slope is determined by the new TOP value. When these two values differ the

two slopes of the period will differ in length. The difference in length gives the unsymmetrical

result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM1x1:0 to three (See Table 14-3 on page 129).

The actual OC1x value will only be visible on the port pin if the data direction for the port pin is

set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x

Register at the compare match between OCR1x and TCNT1 when the counter increments, and

clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If

OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output

will toggle with a 50ꢀ duty cycle.

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14.8.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while

upcounting, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 14-

8 and Figure 14-9).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and

the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can

be calculated using the following equation:

log(TOP + 1)

R

= ----------------------------------

PFCPWM

log(2)

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 14-9. The figure shows phase and frequency correct

PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-

sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a

compare match occurs.

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Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x

Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1

is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.

The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

As Figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 14-3 on

page 129). The actual OC1x value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)

the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-

ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and

TCNT1 when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPFCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

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The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be continuously low and if set equal to TOP the output will be set to

high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic val-

ues. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A

output will toggle with a 50ꢀ duty cycle.

14.9 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for

modes utilizing double buffering). Figure 14-10 shows a timing diagram for the setting of OCF1x.

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-11 shows the same timing data, but with the prescaler enabled.

Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams

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will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOV1 Flag at BOTTOM.

Figure 14-12. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

New OCRnx Value

Old OCRnx Value

Figure 14-13 shows the same timing data, but with the prescaler enabled.

Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk

I/O

clk

(clk^T/ⁿ8)

I/O

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn(FPWM)

and ICFn(if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

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14.10 16-bit Timer/Counter Register Description

14.10.1 TCCR1A – Timer/Counter1 Control Register A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

–

2

–

1

WGM11

R/W

0

WGM10

R/W

0

TCCR1A

(0x80)

Read/Write

Initial Value

R

0

R

0

• Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-

tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OC1A or OC1B pin must be set in order to enable the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-

dent of the WGM13:0 bits setting. Table 14-1 shows the COM1x1:0 bit functionality when the

WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 14-1. Compare Output Mode, non-PWM

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

1

Normal port operation, OC1A/OC1B disconnected.

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set output to

low level).

1

0

1

Set OC1A/OC1B on Compare Match (Set output to

high level).

Table 14-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast

PWM mode.

Table 14-2. Compare Output Mode, Fast PWM⁽¹⁾

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 14 or 15: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

0

1

Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at TOP

1

0

1

Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at TOP

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In

this case the compare match is ignored, but the set or clear is done at TOP. See ”Fast PWM

Mode” on page 120. for more details.

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Table 14-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase

correct or the phase and frequency correct, PWM mode.

Table 14-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM⁽¹⁾

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 8, 9, 10 or 11: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

0

1

Clear OC1A/OC1B on Compare Match when up-

counting. Set OC1A/OC1B on Compare Match when

downcounting.

1

0

1

Set OC1A/OC1B on Compare Match when up-

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See

”Phase Correct PWM Mode” on page 122. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-4. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See ”Modes of Operation” on page 118.).

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Table 14-4. Waveform Generation Mode Bit Description⁽¹⁾

WGM12

(CTC1)

WGM11

WGM10

Timer/Counter Mode of

Update of

OCR1x at

TOV1 Flag

Set on

Mode

WGM13

(PWM11) (PWM10) Operation

TOP

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal

0xFFFF

0x00FF

0x01FF

0x03FF

OCR1A

0x00FF

0x01FF

0x03FF

Immediate

TOP

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

BOTTOM

MAX

TOP

Immediate

TOP

Fast PWM, 8-bit

TOP

Fast PWM, 9-bit

TOP

Fast PWM, 10-bit

TOP

PWM, Phase and Frequency

Correct

8

9

1

0

1

ICR1

BOTTOM

PWM, Phase and Frequency

Correct

OCR1A

10

11

12

13

14

15

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICR1

OCR1A

ICR1

–

TOP

Immediate

–

BOTTOM

MAX

(Reserved)

–

Fast PWM

ICR1

OCR1A

TOP

Fast PWM

TOP

Note:

1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

14.10.2 TCCR1B – Timer/Counter1 Control Register B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

–

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

(0x81)

TCCR1B

Read/Write

Initial Value

R

0

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four

successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

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When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure

14-10 and Figure 14-11.

Table 14-5. Clock Select Bit Description

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_I/O/1 (No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.10.3 TCCR1C – Timer/Counter1 Control Register C

Bit

(0x82)

7

6

5

–

4

–

3

–

2

–

1

–

0

–

FOC1A

FOC1B

TCCR1C

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – FOC1A: Force Output Compare for Unit A

• Bit 6 – FOC1B: Force Output Compare for Unit B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.

However, for ensuring compatibility with future devices, these bits must be set to zero when

TCCR1A is written when operating in a PWM mode. When writing a logical one to the

FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.

The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the

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FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the

COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always read as zero.

14.10.4 TCNT1H and TCNT1L – Timer/Counter1

Bit

7

6

5

4

3

2

1

0

(0x85)

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

(0x84)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing 16-bit

Registers” on page 109.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-

pare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock

for all compare units.

14.10.5 OCR1AH and OCR1AL – Output Compare Register 1 A

Bit

7

6

5

4

3

2

1

0

(0x89)

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

(0x88)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

14.10.6 OCR1BH and OCR1BL – Output Compare Register 1 B

Bit

7

6

5

4

3

2

1

0

(0x8B)

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

(0x8A)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See ”Accessing 16-bit Registers” on page 109.

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14.10.7 ICR1H and ICR1L – Input Capture Register 1

Bit

7

6

5

4

3

2

1

0

(0x87)

ICR1[15:8]

ICR1[7:0]

ICR1H

ICR1L

(0x86)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See ”Accessing 16-bit Registers” on page 109.

14.10.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register

Bit

(0x6F)

7

6

5

4

–

3

–

2

OCIE1B

R/W

0

1

OCIE1A

R/W

0

TOIE1

R/W

0

–

ICIE1

TIMSK1

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

R

0

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (See ”Interrupts” on page 56.) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (See ”Interrupts” on page 56.) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See ”Interrupts” on page 56.) is executed when the TOV1 Flag, located in TIFR1, is set.

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14.10.9 TIFR1 – Timer/Counter1 Interrupt Flag Register

Bit

7

–

6

–

5

4

–

3

–

2

OCF1B

R/W

0

1

OCF1A

R/W

0

TOV1

R/W

0

0x16 (0x36)

Read/Write

Initial Value

ICF1

R/W

0

TIFR1

R

0

R

0

R

0

R

0

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the

counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,

the TOV1 Flag is set when the timer overflows. Refer to Table 14-4 on page 130 for the TOV1

Flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

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15. Timer/Counter0 and Timer/Counter1 Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters

can have different prescaler settings. The description below applies to both Timer/Counter1 and

Timer/Counter0.

15.1 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is

not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications

for situations where a prescaled clock is used. One example of prescaling artifacts occurs when

the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock

cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system

clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

15.2 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024.

15.3 External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk_T1/clk_T0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 15-1

on page 135 shows a functional equivalent block diagram of the T1/T0 synchronization and

edge detector logic. The registers are clocked at the positive edge of the internal system clock

(clk_I/O). The latch is transparent in the high period of the internal system clock.

The edge detector generates one clk_T1/clk_Tpulse for each positive (CSn2:0 = 7) or negative

0

(CSn2:0 = 6) edge it detects.

Figure 15-1. T1/T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50ꢀ duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾

clk_I/O

Clear

PSR10

T0

Synchronization

T1

Synchronization

clk_T1

clk_T0

Note:

1. The synchronization logic on the input pins (T1/T0) is shown in Figure 15-1.

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15.4 Register Description

15.4.1

GTCCR – General Timer/Counter Control Register

Bit

7

6

–

5

–

4

–

3

–

2

–

1

PSR2

R/W

0

PSR10

R/W

0

0x23 (0x43)

Read/Write

Initial Value

TSM

R/W

0

GTCCR

R

0

R

0

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-

caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and

can be configured to the same value without the risk of one of them advancing during configura-

tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,

and the Timer/Counters start counting simultaneously.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

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16. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The

main features are:

• Single Compare Unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

16.1 Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual

placement of I/O pins, refer to ”Pinout ATmega169P” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the ”8-bit Timer/Counter Register Description” on page 153.

Figure 16-1. 8-bit Timer/Counter Block Diagram

TCCRnx

count

TOVn

(Int.Req.)

clear

Control Logic

TOP

direction

clk_Tn

TOSC1

BOTTOM

T/C

Oscillator

Prescaler

TOSC2

Timer/Counter

TCNTn

= 0

= 0xFF

clk_I/O

OCnx

(Int.Req.)

Waveform

Generation

OCnx

=

OCRnx

clk_I/O

Synchronized Status flags

Synchronization Unit

clk_ASY

Status flags

ASSRn

asynchronous mode

select (ASn)

16.1.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-

rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register

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(TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2).

TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk_T2).

The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC2A). See ”Output

Compare Unit” on page 140. for details. The compare match event will also set the Compare

Flag (OCF2A) which can be used to generate an Output Compare interrupt request.

16.1.2

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2

counter value and so on.

The definitions in Table 16-1 are also used extensively throughout the section.

Table 16-1. Timer/Counter Definitions

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes zero (0x00).

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR2A Register. The assignment is dependent

on the mode of operation.

16.2 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk_T2is by default equal to the MCU clock, clk_I/O. When the AS2

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see ”ASSR

– Asynchronous Status Register” on page 156. For details on clock sources and prescaler, see

”Timer/Counter Prescaler” on page 152.

16.3 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

16-2 shows a block diagram of the counter and its surrounding environment.

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Figure 16-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

TOSC1

TOSC2

count

clear

T/C

Oscillator

clk _Tn

TCNTn

Control Logic

Prescaler

direction

clk

bottom

top

I/O

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT2 by 1.

Selects between increment and decrement.

Clear TCNT2 (set all bits to zero).

Timer/Counter clock.

clk_T2

top

Signalizes that TCNT2 has reached maximum value.

Signalizes that TCNT2 has reached minimum value (zero).

bottom

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T2). clk_T2can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk_T2is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A). There are close connections between how the

counter behaves (counts) and how waveforms are generated on the Output Compare output

OC2A. For more details about advanced counting sequences and waveform generation, see

”Modes of Operation” on page 143.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

16.4 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set

the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled (OCIE2A = 1), the

Output Compare Flag generates an Output Compare interrupt. The OCF2A Flag is automatically

cleared when the interrupt is executed. Alternatively, the OCF2A Flag can be cleared by soft-

ware by writing a logical one to its I/O bit location. The Waveform Generator uses the match

signal to generate an output according to operating mode set by the WGM21:0 bits and Com-

pare Output mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform

Generator for handling the special cases of the extreme values in some modes of operation

(”Modes of Operation” on page 143).

Figure 16-3 shows a block diagram of the Output Compare unit.

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Figure 16-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

Waveform Generator

OCnx

FOCn

WGMn1:0

COMnx1:0

The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare

Register to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is

disabled the CPU will access the OCR2A directly.

16.4.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the

OCF2A Flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare

match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or

toggled).

16.4.2

16.4.3

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the Output Compare unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

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The setup of the OC2A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com-

pare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM2A1:0 bits are not double buffered together with the compare value.

Changing the COM2A1:0 bits will take effect immediately.

16.5 Compare Match Output Unit

The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator

uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare

match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 16-4 shows a sim-

plified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits,

and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Regis-

ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the

OC2A state, the reference is for the internal OC2A Register, not the OC2A pin.

Figure 16-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform

Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is vis-

ible on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2A state before the

output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of

operation. See ”8-bit Timer/Counter Register Description” on page 153.

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16.5.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the

OC2A Register is to be performed on the next compare match. For compare output actions in

the non-PWM modes refer to Table 16-3 on page 154. For fast PWM mode, refer to Table 16-4

on page 154, and for phase correct PWM refer to Table 16-5 on page 154.

A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2A strobe bits.

16.6 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output

mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM

output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM

modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a

compare match (See ”Compare Match Output Unit” on page 142.).

For detailed timing information refer to ”Timer/Counter Timing Diagrams” on page 148.

16.6.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

16.6.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 16-5. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

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Figure 16-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCnx

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is

running with none or a low prescaler value must be done with care since the CTC mode does

not have the double buffering feature. If the new value written to OCR2A is lower than the cur-

rent value of TCNT2, the counter will miss the compare match. The counter will then have to

count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match

can occur.

For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC2A

_{clk_I/O}/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

16.6.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare

match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

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PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2A and TCNT2.

Figure 16-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.

Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2A1:0 to three (See Table 16-4 on page 154). The actual

OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare

match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

A frequency (with 50ꢀ duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform

generated will have a maximum frequency of f_oc2= f_{clk_I/O}/2 when OCR2A is set to zero. This fea-

ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

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16.6.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match

between TCNT2 and OCR2A while upcounting, and set on the compare match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 16-7.

The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2.

Figure 16-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM2A1:0 to three (See Table 16-5 on page 154).

The actual OC2A value will only be visible on the port pin if the data direction for the port pin is

set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the

compare match between OCR2A and TCNT2 when the counter increments, and setting (or

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clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter

decrements. The PWM frequency for the output when using phase correct PWM can be calcu-

lated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 16-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR2A changes its value from MAX, like in Figure 16-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting compare match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the way

up.

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16.7 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk_T2)

is therefore shown as a clock enable signal. In asynchronous mode, clk_I/Oshould be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 16-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 16-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 16-9 shows the same timing data, but with the prescaler enabled.

Figure 16-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 16-10 shows the setting of OCF2A in all modes except CTC mode.

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Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 16-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 16-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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16.8 Asynchronous operation of the Timer/Counter

16.8.1

Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A

safe procedure for switching clock source is:

a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2.

b. Select clock source by setting AS2 as appropriate.

c. Write new values to TCNT2, OCR2A, and TCCR2A.

d. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.

e. Clear the Timer/Counter2 Interrupt Flags.

f. Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not write

a new value before the contents of the temporary register have been transferred to its

destination. Each of the three mentioned registers have their individual temporary register,

which means that e.g. writing to TCNT2 does not disturb an OCR2A write in progress. To

detect that a transfer to the destination register has taken place, the Asynchronous Status

Register – ASSR has been implemented.

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2A, or TCCR2A, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if the Output Compare2 interrupt

is used to wake up the device, since the Output Compare function is disabled during writing to

OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the

OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the

MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction

mode, precautions must be taken if the user wants to re-enter one of these modes: The

interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-

entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device

will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or

ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that

one TOSC1 cycle has elapsed:

a. Write a value to TCCR2A, TCNT2, or OCR2A.

b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

c. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is

always running, except in Power-down and Standby modes. After a Power-up Reset or wake-

up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator

might take as long as one second to stabilize. The user is advised to wait for at least one

second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby

mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up

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from Power-down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock

(clk_I/O) again becomes active, TCNT2 will read as the previous value (before entering sleep)

until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-

save mode is essentially unpredictable, as it depends on the wake-up time. The recommended

procedure for reading TCNT2 is thus as follows:

a. Write any value to either of the registers OCR2A or TCCR2A.

b. Wait for the corresponding Update Busy Flag to be cleared.

c. Read TCNT2.

• During asynchronous operation, the synchronization of the Interrupt Flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting of

the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

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16.9 Timer/Counter Prescaler

Figure 16-12. Prescaler for Timer/Counter2

clk_I/O

clk_T2S

10-BIT T/C PRESCALER

Clear

TOSC1

AS2

PSR2

0

CS20

CS21

CS22

TIMER/COUNTER2 CLOCK SOURCE

clk_T2

The clock source for Timer/Counter2 is named clk_T2S. clk_T2Sis by default connected to the main

system I/O clock clk_IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. If

applying an external clock on TOSC1, the EXCLK bit in ASSR must be set.

For Timer/Counter2, the possible prescaled selections are: clk_T2S/8, clk_T2S/32, clk_T2S/64,

clk_T2S/128, clk_T2S/256, and clk_T2S/1024. Additionally, clk_T2Sas well as 0 (stop) may be selected.

Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-

dictable prescaler.

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16.10 8-bit Timer/Counter Register Description

16.10.1 TCCR2A – Timer/Counter Control Register A

Bit

7

FOC2A

W

6

WGM20

R/W

0

5

COM2A1

R/W

4

COM2A0

R/W

3

WGM21

R/W

0

2

CS22

R/W

0

1

CS21

R/W

0

CS20

R/W

0

(0xB0)

TCCR2A

Read/Write

Initial Value

0

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-

ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when

operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare

match is forced on the Waveform Generation unit. The OC2A output is changed according to its

COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the

value present in the COM2A1:0 bits that determines the effect of the forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6, 3 – WGM21:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum (TOP)

counter value, and what type of waveform generation to be used. Modes of operation supported

by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and

two types of Pulse Width Modulation (PWM) modes. See Table 16-2 and ”Modes of Operation”

on page 143.

Table 16-2. Waveform Generation Mode Bit Description⁽¹⁾

WGM21

(CTC2)

WGM20

(PWM2)

Timer/Counter Mode of

Operation

Update of

OCR2A at

TOV2 Flag

Set on

Mode

TOP

0

1

2

3

0

1

0

1

0

1

Normal

0xFF

OCR2A

0xFF

Immediate

TOP

MAX

PWM, Phase Correct

CTC

BOTTOM

MAX

Immediate

TOP

Fast PWM

MAX

Note:

1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.

However, the functionality and location of these bits are compatible with previous versions of

the timer.

• Bit 5:4 – COM2A1:0: Compare Match Output Mode A

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be

set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM21:0 bit setting. Table 16-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits

are set to a normal or CTC mode (non-PWM).

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Table 16-3. Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

0

1

0

1

0

1

Normal port operation, OC2A disconnected.

Toggle OC2A on compare match.

Clear OC2A on compare match.

Set OC2A on compare match.

Table 16-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Table 16-4. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

1

0

1

0

1

Normal port operation, OC2A disconnected.

Reserved

Clear OC2A on compare match, set OC2A at TOP.

Set OC2A on compare match, clear OC2A at TOP.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 144

for more details.

Table 16-5 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to phase cor-

rect PWM mode.

Table 16-5. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

1

Normal port operation, OC2A disconnected.

Reserved

Clear OC2A on compare match when up-counting. Set OC2A on

compare match when downcounting.

1

0

1

Set OC2A on compare match when up-counting. Clear OC2A on

compare match when downcounting.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-

pare match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on

page 146 for more details.

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• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

16-6.

Table 16-6. Clock Select Bit Description

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_T2S/(No prescaling)

clk_T2S/8 (From prescaler)

clk_T2S/32 (From prescaler)

clk_T2S/64 (From prescaler)

clk_T2S/128 (From prescaler)

clk_{T S}/256 (From prescaler)

2

clk_{T S}/1024 (From prescaler)

2

16.10.2 TCNT2 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

(0xB2)

TCNT2[7:0]

TCNT2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a compare match between TCNT2 and the OCR2A Register.

16.10.3 OCR2A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

(0xB3)

OCR2A[7:0]

OCR2A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2A pin.

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16.10.4 TIMSK2 – Timer/Counter2 Interrupt Mask Register

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

OCIE2A

R/W

0

TOIE2

R/W

0

(0x70)

TIMSK2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt

Flag Register – TIFR2.

16.10.5 TIFR2 – Timer/Counter2 Interrupt Flag Register

Bit

0x17 (0x37)

7

6

5

–

4

–

3

–

2

–

1

OCF2A

R/W

0

TOV2

R/W

0

–

TIFR2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – OCF2A: Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

16.10.6 ASSR – Asynchronous Status Register

Bit

(0xB6)

7

6

5

–

4

EXCLK

R/W

0

3

2

1

0

–

AS2

R/W

0

TCN2UB

OCR2UB

TCR2UB

ASSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 4 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input

buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead

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of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is

selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 3 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk_I/O. When AS2 is

written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-

lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and

TCCR2A might be corrupted.

• Bit 2 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.

When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

• Bit 1 – OCR2UB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.

When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.

When TCCR2A has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new

value.

If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading

TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the tem-

porary storage register is read.

16.10.7 GTCCR – General Timer/Counter Control Register

Bit

0x23 (0x43)

7

6

5

4

–

3

–

2

–

1

PSR2

R/W

0

PSR10

R/W

0

TSM

–

GTCCR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 1 – PSR2: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the ”Bit 7 – TSM: Timer/Counter Syn-

chronization Mode” on page 137 for a description of the Timer/Counter Synchronization mode.

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17. SPI – Serial Peripheral Interface

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega169P and peripheral devices or between several AVR devices. The ATmega169P SPI

includes the following features:

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

The PRSPI bit in ”PRR – Power Reduction Register” on page 44 must be written to zero to

enable SPI module.

Figure 17-1. SPI Block Diagram⁽¹⁾

DIVIDER

/2/4/8/16/32/64/128

Note:

1. Refer to Figure 1-1 on page 2, and Table 12-6 on page 74 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2. The sys-

tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and

Slave prepare the data to be sent in their respective shift Registers, and the Master generates

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the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-

ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In

– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling

high the Slave Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight

bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of

Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an

interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be

kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this state, software may update the contents of the SPI Data

Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin

until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission

Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt

is requested. The Slave may continue to place new data to be sent into SPDR before reading

the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 17-2. SPI Master-slave Interconnection

SHIFT

ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the minimum low and high periods should be:

Low period: longer than 2 CPU clock cycles

High period: longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden

according to Table 17-1. For more details on automatic port overrides, refer to ”Alternate Port

Functions” on page 71.

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Table 17-1. SPI Pin Overrides⁽¹⁾

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

1. See ”Alternate Functions of Port B” on page 74 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction

Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the

actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI

with DDB5 and DDR_SPI with DDRB.

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Assembly Code Example⁽¹⁾

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example⁽¹⁾

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

Note:

1. ”About Code Examples” on page 9

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The following code examples show how to initialize the SPI as a Slave and how to perform a

simple reception.

Assembly Code Example⁽¹⁾

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in

r16,SPDR

ret

C Code Example⁽¹⁾

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return Data Register */

return SPDR;

}

Note:

1. ”About Code Examples” on page 9.

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17.1 SS Pin Functionality

17.1.1

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

17.1.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is

set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

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17.2 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

17-3 and Figure 17-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 17-3 and Table 17-4, as done below:

Table 17-2. CPOL Functionality

Leading Edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing eDge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI Mode

CPOL=0, CPHA=0

CPOL=0, CPHA=1

CPOL=1, CPHA=0

CPOL=1, CPHA=1

0

1

2

3

Figure 17-3. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

Figure 17-4. SPI Transfer Format with CPHA = 1

SCK (CPOL = 0)

mode 1

SCK (CPOL = 1)

mode 3

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0)

LSB first (DORD = 1)

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

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17.3 SPI Register Description

17.3.1

SPCR – SPI Control Register

Bit

7

SPIE

R/W

0

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

SPR1

R/W

0

SPR0

R/W

0

0x2C (0x4C)

Read/Write

Initial Value

SPE

R/W

0

SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL functionality is sum-

marized below:

Table 17-3. CPOL Functionality

CPOL

Leading Edge

Rising

Trailing Edge

Falling

0

1

Falling

Rising

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 17-3 and Figure 17-4 for an example. The CPOL

functionality is summarized below:

Table 17-4. CPHA Functionality

CPHA

Leading Edge

Sample

Trailing Edge

Setup

0

1

Setup

Sample

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• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f_oscis

shown in the following table:

Table 17-5. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

f_osc/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f_osc/16

f_osc/64

f_osc/128

f_osc/2

f_osc/8

f_osc/32

f_osc/64

17.3.2

SPSR – SPI Status Register

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

SPI2X

R/W

0

0x2D (0x4D)

Read/Write

Initial Value

WCOL

SPSR

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 17-5). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_osc/4

or lower.

The SPI interface on the ATmega169P is also used for program memory and EEPROM down-

loading or uploading. See page 309 for serial programming and verification.

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17.3.3

SPDR – SPI Data Register

Bit

7

6

5

4

3

2

1

0

0x2E (0x4E)

Read/Write

Initial Value

MSB

R/W

X

LSB

R/W

X

SPDR

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

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18. USART

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device. The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

The PRUSART0 bit in ”PRR – Power Reduction Register” on page 44 must be written to zero to

enable USART0 module.

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18.1 Overview

A simplified block diagram of the USART Transmitter is shown in Figure 18-1. CPU accessible

I/O Registers and I/O pins are shown in bold.

Figure 18-1. USART Block Diagram⁽¹⁾

Clock Generator

UBRR[H:L]

OSC

BAUD RATE GENERATOR

SYNC LOGIC

XCK

CONTROL

Transmitter

TX

CONTROL

UDR (Transmit)

PARITY

GENERATOR

CONTROL

TRANSMIT SHIFT REGISTER

TxD

Receiver

CLOCK

RX

RECOVERY

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

RxD

PARITY

CHECKER

UDR (Receive)

UCSRA

UCSRB

UCSRC

Note:

1. Refer to Figure 1-1 on page 2, Table 12-13 on page 80, and Table 12-7 on page 76 for USART

pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only

used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial

Shift Register, Parity Generator and Control logic for handling different serial frame formats. The

write buffer allows a continuous transfer of data without any delay between frames. The

Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

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18.1.1

AVR USART vs. AVR UART – Compatibility

The USART is fully compatible with the AVR UART regarding:

• Bit locations inside all USART Registers.

• Baud Rate Generation.

• Transmitter Operation.

• Transmit Buffer Functionality.

• Receiver Operation.

However, the receive buffering has two improvements that will affect the compatibility in some

special cases:

• A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO

buffer. Therefore the UDRn must only be read once for each incoming data! More important is

the fact that the Error Flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered with

the data in the receive buffer. Therefore the status bits must always be read before the UDRn

Register is read. Otherwise the error status will be lost since the buffer state is lost.

• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the

received data to remain in the serial Shift Register (see Figure 18-1) if the Buffer Registers are

full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun

(DORn) error conditions.

The following control bits have changed name, but have same functionality and register location:

• CHR9 is changed to UCSZn2.

• OR is changed to DORn.

18.2 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCK pin is only active when using synchronous mode.

Figure 18-2 shows a block diagram of the clock generation logic.

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Figure 18-2. Clock Generation Logic, Block Diagram

UBRR

U2X

fosc

UBRR+1

Prescaling

Down-Counter

/2

/4

/2

0

1

0

OSC

txclk

1

DDR_XCK

Sync

Edge

Register

Detector

xcki

0

UMSEL

1

XCK

xcko

DDR_XCK

UCPOL

1

rxclk

0

Signal description:

txclk

Transmitter clock (Internal Signal).

Receiver base clock (Internal Signal).

rxclk

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

18.2.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 18-2.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(f_osc), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= f_osc/(UBRRn+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the Receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCK bits.

Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

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Table 18-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud

Rate⁽¹⁾

Equation for Calculating UBRRn

Operating Mode

Value

Asynchronous Normal

mode (U2Xn = 0)

f

OSC

f

OSC

BAUD = -----------------------------------------

UBRRn = ----------------------- – 1

16BAUD

16(UBRRn + 1)

Asynchronous Double

Speed mode (U2Xn = 1)

f

OSC

f

OSC

BAUD = --------------------------------------

UBRRn = -------------------- – 1

8(UBRRn + 1)

8BAUD

Synchronous Master

mode

f

OSC

f

OSC

BAUD = --------------------------------------

UBRRn = -------------------- – 1

2(UBRRn + 1)

2BAUD

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

f_OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRHn and UBRRLn Registers, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 18-9

(see page 195).

18.2.2

Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

18.2.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 18-2 for details.

External clock input from the XCK pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCK clock frequency

is limited by the following equation:

f

OSC

-----------

f

<

XCK

4

Note that f_oscdepends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

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18.2.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxD) is sampled at the

opposite XCK clock edge of the edge the data output (TxD) is changed.

Figure 18-3. Synchronous Mode XCK Timing.

UCPOL = 1

XCK

RxD / TxD

Sample

UCPOL = 0

XCK

RxD / TxD

The UCPOLn bit UCRSC selects which XCK clock edge is used for data sampling and which is

used for data change. As Figure 18-3 shows, when UCPOLn is zero the data will be changed at

rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at

falling XCK edge and sampled at rising XCK edge.

18.3 Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 18-4 on page 174 illustrates the possible combinations of the frame formats. Bits inside

brackets are optional.

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Figure 18-4. Frame Formats

FRAME

[5]

(IDLE)

St

0

1

2

3

4

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

Start bit, always low.

Data bits (0 to 8).

(n)

P

Parity bit. Can be odd or even.

Stop bit, always high.

Sp

IDLE

No transfers on the communication line (RxD or TxD). An IDLE line must

high.

be

The frame format used by the USART is set by the UCSZn2:0, UPM1n:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPM1n:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores

the second stop bit. An FEn (Frame Error FEn) will therefore only be detected in the cases

where the first stop bit is zero.

18.3.1

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

P

= d

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0

3 2 1 0

even

n – 1

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1

odd

3 2 1 0

P_even

P^odd

d_n

Parity bit using even parity

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

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18.4 USART Initialization

The USART has to be initialized before any communication can take place. The initialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no

ongoing transmissions during the period the registers are changed. The TXCn Flag can be used

to check that the Transmitter has completed all transfers, and the RXCn Flag can be used to

check that there are no unread data in the receive buffer. Note that the TXCn Flag must be

cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

Registers.

Assembly Code Example⁽¹⁾

USART_Init:

; Set baud rate

sts UBRRH0, r17

sts UBRRL0, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN0)|(1<<TXEN0)

sts UCSR0B,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBS0)|(3<<UCSZ00)

sts UCSR0C,r16

ret

C Code Example⁽¹⁾

#define FOSC 1843200// Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void main( void )

{

...

USART_Init ( MYUBRR );

...

}

void USART_Init( unsigned int ubrr)

{

/* Set baud rate */

UBRRH0 = (unsigned char)(ubrr>>8);

UBRRL0 = (unsigned char)ubrr;

/* Enable receiver and transmitter */

UCSR0B = (1<<RXEN0)|(1<<TXEN0);

/* Set frame format: 8data, 2stop bit */

UCSRnC = (1<<USBS0)|(3<<UCSZ00);

}

Note:

1. See ”About Code Examples” on page 9.

More advanced initialization routines can be made that include frame format as parameters, dis-

able interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed directly

in the main routine, or be combined with initialization code for other I/O modules.

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18.5 Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB

Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid-

den by the USART and given the function as the Transmitter’s serial output. The baud rate,

mode of operation and frame format must be set up once before doing any transmissions. If syn-

chronous operation is used, the clock on the XCK pin will be overridden and used as

transmission clock.

18.5.1

Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or

immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2Xn bit or by XCK depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-

nificant bits written to the UDRn are ignored. The USART has to be initialized before the function

can be used. For the assembly code, the data to be sent is assumed to be stored in Register

R16

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSR0A,UDREn

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

sts UDR0,r16

ret

C Code Example⁽¹⁾

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSR0A & (1<<UDRE0)) )

;

/* Put data into buffer, sends the data */

UDR0 = data;

}

Note:

1. See ”About Code Examples” on page 9.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,

the interrupt routine writes the data into the buffer.

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18.5.2

Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCS-

RnB before the low byte of the character is written to UDRn. The following code examples show

a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is

assumed to be stored in registers R17:R16.

Assembly Code Example⁽¹⁾⁽²⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSR0A,UDRE0

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB80

cbi UCSR0B,TXB80

sbrc r17,0

sbi UCSR0B,TXB80

; Put LSB data (r16) into buffer, sends the data

sts UDR0,r16

ret

C Code Example⁽¹⁾⁽²⁾

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSR0A & (1<<UDRE0))) )

;

/* Copy 9th bit to TXB8n */

UCSR0B &= ~(1<<TXB80);

if ( data & 0x0100 )

UCSR0B |= (1<<TXB80);

/* Put data into buffer, sends the data */

UDR0 = data;

}

Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of the UCSRnB is static. For example, only the TXB8n bit of the UCSRnB Register is

used after initialization.

2. See ”About Code Examples” on page 9.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for other protocol handling as for example synchronization.

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18.5.3

Transmitter Flags and Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty

(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.

The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that

global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift

Register has been shifted out and there are no new data currently present in the transmit buffer.

The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-

nication interfaces (like the RS-485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART

Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt

is executed.

18.5.4

18.5.5

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPM1n = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxD pin.

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18.6 Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB

Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is over-

ridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode

of operation and frame format must be set up once before any serial reception can be done. If

synchronous operation is used, the clock on the XCK pin will be used as transfer clock.

18.6.1

Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until

the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When

the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register,

the contents of the Shift Register will be moved into the receive buffer. The receive buffer can

then be read by reading the UDRn I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant

bits of the data read from the UDRn will be masked to zero. The USART has to be initialized

before the function can be used.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSR0A, RXC0

rjmp USART_Receive

; Get and return received data from buffer

in

r16, UDR0

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSR0A & (1<<RXC0)) )

;

/* Get and return received data from buffer */

return UDR0;

}

Note:

1. See ”About Code Examples” on page 9.

The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,

before reading the buffer and returning the value.

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18.6.2

Receiving Frames with 9 Data Bits

If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB

before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Sta-

tus Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O

location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,

DORn and UPEn bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both nine bit

characters and the status bits.

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Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSR0A, RXC0

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in

r18, UCSR0A

r17, UCSR0B

r16, UDR0

; If error, return -1

andi r18,(1<<FE0)|(1<<DOR0)|(1<<UPE0)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example⁽¹⁾

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSR0A;

resh = UCSR0B;

resl = UDR0;

/* If error, return -1 */

if ( status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

Note:

1. ”About Code Examples” on page 9

The receive function example reads all the I/O Registers into the Register File before any com-

putation is done. This gives an optimal receive buffer utilization since the buffer location read will

be free to accept new data as early as possible.

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18.6.3

Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),

the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive

Complete interrupt will be executed as long as the RXCn Flag is set (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

18.6.4

Receiver Error Flags

The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and

Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the

receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.

Another equality for the Error Flags is that they can not be altered by software doing a write to

the flag location. However, all flags must be set to zero when the UCSRnA is written for upward

compatibility of future USART implementations. None of the Error Flags can generate interrupts.

The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),

and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn

Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,

except for the first, stop bits. For compatibility with future devices, always set this bit to zero

when writing to UCSRnA.

The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A

Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-

ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there

was one or more serial frame lost between the frame last read from UDRn, and the next frame

read from UDRn. For compatibility with future devices, always write this bit to zero when writing

to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from

the Shift Register to the receive buffer.

The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more

details see ”Parity Bit Calculation” on page 174 and ”Parity Checker” on page 184.

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18.6.5

Parity Checker

The Parity Checker is active when the high USART Parity mode (UPM1n) bit is set. Type of Par-

ity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit from the serial frame. The result of the check is stored in the receive buffer together

with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software

to check if the frame had a Parity Error.

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPM1n = 1). This bit is

valid until the receive buffer (UDRn) is read.

18.6.6

18.6.7

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will

no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag

is cleared. The following code example shows how to flush the receive buffer.

Assembly Code Example⁽¹⁾

USART_Flush:

sbis UCSR0A, RXC0

ret

in

rjmp USART_Flush

C Code Example⁽¹⁾

r16, UDR0

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSR0A & (1<<RXC0) ) dummy = UDR0;

}

Note:

1. See ”About Code Examples” on page 9.

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18.7 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

18.7.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 18-5

on page 185 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed

mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-

cess. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of

operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communi-

cation activity).

Figure 18-5. Start Bit Sampling

RxD

IDLE

START

BIT 0

Sample

(U2X = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

Sample

(U2X = 1)

0

2

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

18.7.2

Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Speed mode. Figure 18-6 on page 186 shows the sampling of the

data bits and the parity bit. Each of the samples is given a number that is equal to the state of

the recovery unit.

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Figure 18-6. Sampling of Data and Parity Bit

RxD

BIT n

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

Figure 18-7 on page 186 shows the sampling of the stop bit and the earliest possible beginning

of the start bit of the next frame.

Figure 18-7. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxD

STOP 1

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2X = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 18-7 on page 186. For Double Speed mode the first low level must be

delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the

operational range of the Receiver.

18.7.3

Asynchronous Operational Range

The operational range of the Receiver is dependent on the mismatch between the received bit

rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too

slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 18-2 on page 187) base frequency, the Receiver will not be able to synchronize the

frames to the start bit.

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The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

(D + 1)S

S – 1 + D ⋅ S + S

(D + 2)S

(D + 1)S + S

R

= ------------------------------------------

R

= -----------------------------------

slow

fast

F

M

D

S

Sum of character size and parity size (D = 5 to 10 bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

S_F

First sample number used for majority voting. S_F= 8 for normal speed and S_F= 4

for Double Speed mode.

S_M

Middle sample number used for majority voting. S_M= 9 for normal speed and

S_M= 5 for Double Speed mode.

R_slow

is the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate. R_fastis the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 18-2 and Table 18-3 list the maximum receiver baud rate error that can be tolerated. Note

that Normal Speed mode has higher toleration of baud rate variations.

Table 18-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2Xn = 0)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R_slow(%)

93.20

94.12

94.81

95.36

95.81

96.17

R_fast(%)

106.67

105.79

105.11

104.58

104.14

103.78

Max Total Error (%)

+6.67/-6.8

5

6

3.0

2.5

2.0

1.5

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

7

8

9

10

Table 18-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2Xn = 1)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R_slow(%)

94.12

94.92

95.52

96.00

96.39

96.70

R_fast(%)

105.66

104.92

104,35

103.90

103.53

103.23

Max Total Error (%)

+5.66/-5.88

5

6

2.5

2.0

1.5

1.0

+4.92/-5.08

7

+4.35/-4.48

8

+3.90/-4.00

9

+3.53/-3.61

10

+3.23/-3.30

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The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator the system clock may differ more than 2ꢀ depending of the resonators tolerance. The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value

that gives an acceptable low error can be used if possible.

18.8 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering

function of incoming frames received by the USART Receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the Receiver is set up for frames with

nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When

the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the

frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

18.8.1

Using MPCMn

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ = 7). The

ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame

(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character

frame format.

The following procedure should be used to exchange data in Multi-processor Communication

mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is

set).

2. The Master MCU sends an address frame, and all slaves receive and read this frame. In

the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.

3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,

it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and

keeps the MPCMn setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.

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5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCMn bit and waits for a new address frame from master. The process then

repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes full-

duplex operation difficult since the Transmitter and Receiver uses the same character size set-

ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit

(USBSn = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The

MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be

cleared when using SBI or CBI instructions.

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18.9 USART Register Description

18.9.1

UDRn – USART I/O Data Register

Bit

7

6

5

4

3

2

1

0

RXB[7:0]

TXB[7:0]

UDRn (Read)

UDRn (Write)

(0xC6)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the

same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-

ister (TXB) will be the destination for data written to the UDRn Register location. Reading the

UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.

Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxD pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions

(SBIC and SBIS), since these also will change the state of the FIFO.

18.9.2

UCSRnA – USART Control and Status Register A

Bit

(0xC0)

7

6

5

4

FEn

R

3

DORn

R

2

UPEn

R

1

U2Xn

R/W

0

MPCMn

R/W

0

RXCn

TXCn

UDREn

UCSRnA

Read/Write

Initial Value

R

0

R/W

0

R

1

0

• Bit 7 – RXCn: USART Receive Complete n

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete n

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXC Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXC Flag can generate a Transmit Complete interrupt (see descrip-

tion of the TXCIE bit).

• Bit 5 – UDREn: USART Data Register Empty n

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIEn bit).

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UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error n

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun n

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error n

This bit is set if the next character in the receive buffer had a Parity Error when received and the

Parity Checking was enabled at that point (UPM1n = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed n

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode n

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed

information see ”Multi-processor Communication Mode” on page 188.

18.9.3

UCSRnB – USART Control and Status Register n B

Bit

(0xC1)

7

6

5

4

RXENn

R/W

0

3

TXENn

R/W

0

2

UCSZn2

R/W

1

0

TXB8n

R/W

0

RXCIEn

TXCIEn

UDRIEn

RXB8n

UCSRBn

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

• Bit 7 – RXCIEn: RX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt

will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ-

ten to one and the RXC bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

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• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXENn: Receiver Enable n

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxD pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

• Bit 3 – TXENn: Transmitter Enable n

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxD port.

• Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZ1n:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8 n

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8 n

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

18.9.4

UCSRnC – USART Control and Status Register n C

Bit

(0xC2)

7

6

5

4

UPM0n

R/W

0

3

USBSn

R/W

0

2

UCSZn1

R/W

1

UCSZn0

R/W

0

UCPOLn

R/W

–

UMSELn

UPM1n

UCSRnC

Read/Write

Initial Value

R

0

R/W

0

R/W

0

1

0

• Bit 6 – UMSELn: USART Mode Select n

This bit selects between asynchronous and synchronous mode of operation.

Table 18-4. UMSELn Bit Settings

UMSELn

Mode

0

1

Asynchronous Operation

Synchronous Operation

• Bit 5:4 – UPM1n:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

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Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

Table 18-5. UPM Bits Settings

UPM1n

UPM0n

Parity Mode

0

1

0

1

0

1

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Table 18-6. USBSn Bit Settings

USBSn

Stop Bit(s)

1-bit

0

1

2-bit

• Bit 2:1 – UCSZ1n:0: Character Size

The UCSZ1n:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Table 18-7. UCSZ Bits Settings

UCSZn2

UCSZ1n

UCSZ0n

Character Size

5-bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

Table 18-8. UCPOLn Bit Settings

Transmitted Data Changed

(Output of TxD Pin)

Received Data Sampled (Input on RxD

Pin)

UCPOLn

0

1

Rising XCK Edge

Falling XCK Edge

Rising XCK Edge

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18.9.5

UBRRLn and UBRRHn – USART Baud Rate Registers

Bit

15

14

13

12

11

10

9

8

(0xC5)

(0xC4)

–

UBRRn[11:8]

UBRRHn

UBRRLn

UBRRn[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRHn is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRHn contains the four

most significant bits, and the UBRRLn contains the eight least significant bits of the USART

baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud

rate is changed. Writing UBRRLn will trigger an immediate update of the baud rate prescaler.

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18.10 Examples of Baud Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-

chronous operation can be generated by using the UBRRn settings in Table 18-9. UBRRn

values which yield an actual baud rate differing less than 0.5ꢀ from the target baud rate, are

bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resis-

tance when the error ratings are high, especially for large serial frames (see ”Asynchronous

Operational Range” on page 186). The error values are calculated using the following equation:

BaudRate_{Closest Match}

⎛

⎞

Error[ꢀ] = ------------------------------------------------------- – 1 • 100ꢀ

⎝

⎠

BaudRate

Table 18-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies

f_osc= 1.0000 MHz f_osc= 1.8432 MHz

U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error

f_osc= 2.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

U2Xn = 1

UBRRn Error

2400

25

12

6

0.2ꢀ

-7.0ꢀ

8.5ꢀ

-18.6ꢀ

8.5ꢀ

–

51

25

12

8

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

-18.6ꢀ

8.5ꢀ

–

47

23

11

7

0.0ꢀ

-25.0ꢀ

0.0ꢀ

–

95

47

23

15

11

7

0.0ꢀ

–

51

25

12

8

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

-18.6ꢀ

8.5ꢀ

–

103

51

25

16

12

8

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

–

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

0

0.0ꢀ

Max.⁽¹⁾

62.5 kbps

1. UBRRn = 0, Error = 0ꢀ.

125 kbps

115.2 kbps

230.4 kbps

125 kbps

250 kbps

Note:

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Table 18-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 3.6864 MHz

U2Xn = 0

f_osc= 4.0000 MHz

U2Xn = 0

f_osc= 7.3728 MHz

U2Xn = 0

Baud

Rate

(bps)

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

0.0ꢀ

-7.8ꢀ

–

191

95

47

31

23

15

11

7

0.0ꢀ

-7.8ꢀ

–

103

51

25

16

12

8

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

0.0ꢀ

–

207

103

51

34

25

16

12

8

0.2ꢀ

-0.8ꢀ

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

0.0ꢀ

–

191

95

47

31

23

15

11

7

0.0ꢀ

-7.8ꢀ

–

383

191

95

63

47

31

23

15

11

7

0.0ꢀ

-7.8ꢀ

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

0.5M

–

0

–

0

1

1M

–

0

Max. ⁽¹⁾

230.4 kbps

460.8 kbps

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

1.

UBRRn = 0, Error = 0.0ꢀ

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Table 18-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 8.0000 MHz f_osc= 11.0592 MHz f_osc= 14.7456 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

0.2ꢀ

-0.8ꢀ

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

-7.0ꢀ

8.5ꢀ

0.0ꢀ

–

416

207

103

68

51

34

25

16

12

8

-0.1ꢀ

0.2ꢀ

0.6ꢀ

0.2ꢀ

-0.8ꢀ

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

8.5ꢀ

0.0ꢀ

287

143

71

47

35

23

17

11

8

0.0ꢀ

-7.8ꢀ

–

575

287

143

95

71

47

35

23

17

11

5

0.0ꢀ

-7.8ꢀ

–

383

191

95

63

47

31

23

15

11

7

0.0ꢀ

-7.8ꢀ

767

383

191

127

95

63

47

31

23

15

7

0.0ꢀ

5.3ꢀ

-7.8ꢀ

6

3

5

1

3

2

3

1

3

2

5

3

6

0.5M

0

1

–

2

1

3

1M

–

0

–

0

1

Max. ⁽¹⁾

0.5 Mbps

UBRRn = 0, Error = 0.0ꢀ

1 Mbps

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1.

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Table 18-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 16.0000 MHz f_osc= 18.4320 MHz f_osc= 20.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

416

207

103

68

51

34

25

16

12

8

-0.1ꢀ

0.2ꢀ

0.6ꢀ

0.2ꢀ

-0.8ꢀ

0.2ꢀ

2.1ꢀ

0.2ꢀ

-3.5ꢀ

8.5ꢀ

0.0ꢀ

832

416

207

138

103

68

51

34

25

16

8

0.0ꢀ

-0.1ꢀ

0.2ꢀ

-0.1ꢀ

0.2ꢀ

0.6ꢀ

0.2ꢀ

-0.8ꢀ

0.2ꢀ

2.1ꢀ

-3.5ꢀ

0.0ꢀ

479

239

119

79

59

39

29

19

14

9

0.0ꢀ

-7.8ꢀ

–

959

479

239

159

119

79

59

39

29

19

9

0.0ꢀ

2.4ꢀ

-7.8ꢀ

–

520

259

129

86

64

42

32

21

15

10

4

0.0ꢀ

0.2ꢀ

-0.2ꢀ

0.2ꢀ

0.9ꢀ

-1.4ꢀ

1.7ꢀ

-1.4ꢀ

8.5ꢀ

0.0ꢀ

–

1041

520

259

173

129

86

0.0ꢀ

0.2ꢀ

-0.2ꢀ

0.2ꢀ

-0.2ꢀ

0.2ꢀ

0.9ꢀ

-1.4ꢀ

0.0ꢀ

–

64

42

32

21

3

4

10

3

7

4

8

4

9

0.5M

1

3

–

4

–

4

1M

0

1

–

Max. ⁽¹⁾

1 Mbps

UBRRn = 0, Error = 0.0ꢀ

2 Mbps

1.152 Mbps

2.304 Mbps

1.25 Mbps

2.5 Mbps

1.

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ATmega169P

19. USI – Universal Serial Interface

The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial

communication. Combined with a minimum of control software, the USI allows significantly

higher transfer rates and uses less code space than solutions based on software only. Interrupts

are included to minimize the processor load. The main features of the USI are:

• Two-wire Synchronous Data Transfer (Master or Slave, f_SCLmax= f_CK/16)

• Three-wire Synchronous Data Transfer (Master or Slave f_SCKmax= f_CK/4)

• Data Received Interrupt

• Wakeup from Idle Mode

• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

• Two-wire Start Condition Detector with Interrupt Capability

19.1 Overview

A simplified block diagram of the USI is shown on Figure 19-1. For the actual placement of I/O

pins, refer to ”Pinout ATmega169P” on page 2. CPU accessible I/O Registers, including I/O bits

and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in

the ”USI Register Descriptions” on page 207.

Figure 19-1. Universal Serial Interface, Block Diagram

(Output only)

DO

D

Q

LE

(Input/Open Drain)

DI/SDA

3

2

USIDR

1

0

TIM0 COMP

3

2

0

1

(Input/Open Drain)

USCK/SCL

4-bit Counter

1

0

CLOCK

HOLD

[1]

Two-wire Clock

Control Unit

USISR

2

USICR

The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and

outgoing data. The register has no buffering so the data must be read as quickly as possible to

ensure that no data is lost. The most significant bit is connected to one of two output pins

depending of the wire mode configuration. A transparent latch is inserted between the Serial

Register Output and output pin, which delays the change of data output to the opposite clock

edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin

independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and can generate an overflow

interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock

source. This allows the counter to count the number of bits received or transmitted and generate

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an interrupt when the transfer is complete. Note that when an external clock source is selected

the counter counts both clock edges. In this case the counter counts the number of edges, and

not the number of bits. The clock can be selected from three different sources: The USCK pin,

Timer/Counter0 Compare Match or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on

the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-

dition is detected, or after the counter overflows.

19.2 Functional Descriptions

19.2.1

Three-wire Mode

The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

Figure 19-2. Three-wire Mode Operation, Simplified Diagram

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

SLAVE

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

MASTER

Figure 19-2 shows two USI units operating in Three-wire mode, one as Master and one as

Slave. The two Shift Registers are interconnected in such way that after eight USCK clocks, the

data in each register are interchanged. The same clock also increments the USI’s 4-bit counter.

The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a

transfer is completed. The clock is generated by the Master device software by toggling the

USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.

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Figure 19-3. Three-wire Mode, Timing Diagram

( Reference )

1

2

3

4

5

6

7

8

CYCLE

USCK

DO

MSB

6

5

4

3

2

1

LSB

6

5

4

3

2

1

DI

A

B

C

D

E

The Three-wire mode timing is shown in Figure 19-3. At the top of the figure is a USCK cycle ref-

erence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The

USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI

is sampled at positive edges, and DO is changed (Data Register is shifted by one) at negative

edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-

ples data at negative and changes the output at positive edges. The USI clock modes

corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 19-3.), a bus transfer involves the following steps:

1. The Slave device and Master device sets up its data output and, depending on the proto-

col used, enables its output driver (mark A and B). The output is set up by writing the

data to be transmitted to the Serial Data Register. Enabling of the output is done by set-

ting the corresponding bit in the port Data Direction Register. Note that point A and B

does not have any specific order, but both must be at least one half USCK cycle before

point C where the data is sampled. This must be done to ensure that the data setup

requirement is satisfied. The 4-bit counter is reset to zero.

2. The Master generates a clock pulse by software toggling the USCK line twice (C and D).

The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the

first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter

will count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer is completed. The data bytes transferred must now be processed before a

new transfer can be initiated. The overflow interrupt will wake up the processor if it is set

to Idle mode. Depending of the protocol used the slave device can now set its output to

high impedance.

19.2.2

SPI Master Operation Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts

ldi

sts

ldi

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

sts

USICR,r16

lds

r16, USISR

r16, USIOIF

sbrs

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rjmp

lds

SPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that

the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register

r16 prior to the function is called is transferred to the Slave device, and when the transfer is com-

pleted the data received from the Slave is stored back into the r16 Register.

The second and third instructions clears the USI Counter Overflow Flag and the USI counter

value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,

count at USITC strobe, and toggle USCK. The loop is repeated 16 times.

The following code demonstrates how to use the USI module as a SPI Master with maximum

speed (fsck = fck/4):

SPITransfer_Fast:

sts

ldi

USIDR,r16

r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

sts

USICR,r16 ; MSB

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16 ; LSB

USICR,r17

lds

r16,USIDR

ret

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19.2.3

SPI Slave Operation Example

The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi

sts

r16,(1<<USIWM0)|(1<<USICS1)

USICR,r16

...

SlaveSPITransfer:

sts

ldi

sts

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

SlaveSPITransfer_loop:

lds

r16, USISR

sbrs

rjmp

lds

r16, USIOIF

SlaveSPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that

the DO is configured as output and USCK pin is configured as input in the DDR Register. The

value stored in register r16 prior to the function is called is transferred to the master device, and

when the transfer is completed the data received from the Master is stored back into the r16

Register.

Note that the first two instructions is for initialization only and needs only to be executed

once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop

is repeated until the USI Counter Overflow Flag is set.

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19.2.4

Two-wire Mode

The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-

iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.

Figure 19-4. Two-wire Mode Operation, Simplified Diagram

VCC

SDA

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SCL

HOLD

SCL

Two-wire Clock

Control Unit

SLAVE

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PORTxn

MASTER

Figure 19-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave.

It is only the physical layer that is shown since the system operation is highly dependent of the

communication scheme used. The main differences between the Master and Slave operation at

this level, is the serial clock generation which is always done by the Master, and only the Slave

uses the clock control unit. Clock generation must be implemented in software, but the shift

operation is done automatically by both devices. Note that only clocking on negative edge for

shifting data is of practical use in this mode. The slave can insert wait states at start or end of

transfer by forcing the SCL clock low. This means that the Master must always check if the SCL

line was actually released after it has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that the

transfer is completed. The clock is generated by the master by toggling the USCK pin via the

PORT Register.

The data direction is not given by the physical layer. A protocol, like the one used by the TWI-

bus, must be implemented to control the data flow.

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ATmega169P

Figure 19-5. Two-wire Mode, Typical Timing Diagram

SDA

1 - 7

8

9

1 - 8

9

1 - 8

9

SCL

S

P

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

A

B

C

D

E

F

Referring to the timing diagram (Figure 19-5.), a bus transfer involves the following steps:

1. The a start condition is generated by the Master by forcing the SDA low line while the

SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift

Register, or by setting the corresponding bit in the PORT Register to zero. Note that the

Data Direction Register bit must be set to one for the output to be enabled. The slave

device’s start detector logic (Figure 19-6.) detects the start condition and sets the USISIF

Flag. The flag can generate an interrupt if necessary.

2. In addition, the start detector will hold the SCL line low after the Master has forced an

negative edge on this line (B). This allows the Slave to wake up from sleep or complete

its other tasks before setting up the Shift Register to receive the address. This is done by

clearing the start condition flag and reset the counter.

3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave

samples the data and shift it into the Serial Register at the positive edge of the SCL

clock.

4. After eight bits are transferred containing slave address and data direction (read or

write), the Slave counter overflows and the SCL line is forced low (D). If the slave is not

the one the Master has addressed, it releases the SCL line and waits for a new start

condition.

5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle

before holding the SCL line low again (i.e., the Counter Register must be set to 14 before

releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables its output. If

the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line)

The slave can hold the SCL line low after the acknowledge (E).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given

by the Master (F). Or a new start condition is given.

If the Slave is not able to receive more data it does not acknowledge the data byte it has last

received. When the Master does a read operation it must terminate the operation by force the

acknowledge bit low after the last byte transmitted.

Figure 19-6. Start Condition Detector, Logic Diagram

USISIF

CLOCK

HOLD

D Q

SDA

CLR

SCL

Write( USISIF)

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19.2.5

Start Condition Detector

The start condition detector is shown in Figure 19-6. The SDA line is delayed (in the range of 50

to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled

in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the processor

from the Power-down sleep mode. However, the protocol used might have restrictions on the

SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by

the CKSEL Fuses (see ”Clock Systems and their Distribution” on page 29) must also be taken

into the consideration. Refer to the USISIF bit description on page 207 for further details.

19.3 Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative tasks

due to its flexible design.

19.3.1

19.3.2

19.3.3

19.3.4

Half-duplex Asynchronous Data Transfer

By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact

and higher performance UART than by software only.

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will generate an increment.

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

19.3.5

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

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ATmega169P

19.4 USI Register Descriptions

19.4.1

USIDR – USI Data Register

Bit

7

6

5

4

3

2

1

0

(0xBA)

MSB

R/W

0

LSB

R/W

0

USIDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register

(USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the

register is written, the register will contain the value written and no shift is performed. A (left) shift

operation is performed depending of the USICS1..0 bits setting. The shift operation can be con-

trolled by an external clock edge, by a Timer/Counter0 Compare Match, or directly by software

using the USICLK strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0)

both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used

by the Shift Register.

The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch

to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-

ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),

and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB written as long as the latch is open. The latch ensures

that data input is sampled and data output is changed on opposite clock edges.

Note that the corresponding Data Direction Register to the pin must be set to one for enabling

data output from the Shift Register.

19.4.2

USISR – USI Status Register

Bit

7

6

USIOIF

R/W

0

5

USIPF

R/W

0

4

USIDC

R

3

USICNT3

R/W

2

USICNT2

R/W

1

USICNT1

R/W

0

USICNT0

R/W

USISIF

R/W

0

USISR

(0xB9)

Read/Write

Initial Value

0

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is

detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &

USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF

bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.

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A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.

The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is

useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag

is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire

bus master arbitration.

• Bits 3..0 – USICNT3:0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends of the setting of the USICS1:0 bits. For external clock operation

a special feature is added that allows the clock to be generated by writing to the USITC strobe

bit. This feature is enabled by write a one to the USICLK bit while setting an external clock

source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1:0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

19.4.3

USICR – USI Control Register

Bit

7

USISIE

R/W

0

6

USIOIE

R/W

0

5

USIWM1

R/W

4

USIWM0

R/W

3

USICS1

R/W

0

2

USICS0

R/W

0

1

0

USITC

W

(0xB8)

USICLK

USICR

Read/Write

Initial Value

W

0

The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,

and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-

rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be

executed. Refer to the USISIF bit description on page 207 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when

the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.

Refer to the USIOIF bit description on page 207 for further details.

• Bit 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the outputs are

affected by these bits. Data and clock inputs are not affected by the mode selected and will

always have the same function. The counter and Shift Register can therefore be clocked exter-

nally, and data input sampled, even when outputs are disabled. The relations between

USIWM1:0 and the USI operation is summarized in Table 19-1.

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Table 19-1. Relations between USIWM1:0 and the USI Operation

USIWM1

USIWM0

Description

Outputs, clock hold, and start detector disabled. Port pins operates as

normal.

0

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORT

Register in this mode. However, the corresponding DDR bit still controls the

data direction. When the port pin is set as input the pins pull-up is controlled

by the PORT bit.

0

1

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal

port operation. When operating as master, clock pulses are software

generated by toggling the PORT Register, while the data direction is set to

output. The USITC bit in the USICR Register can be used for this purpose.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins⁽¹⁾

.

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and

uses open-collector output drives. The output drivers are enabled by setting

the corresponding bit for SDA and SCL in the DDR Register.

When the output driver is enabled for the SDA pin, the output driver will force

the line SDA low if the output of the Shift Register or the corresponding bit in

the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is

released). When the SCL pin output driver is enabled the SCL line will be

forced low if the corresponding bit in the PORT Register is zero, or by the start

detector. Otherwise the SCL line will not be driven.

1

0

The SCL line is held low when a start detector detects a start condition and

the output is enabled. Clearing the Start Condition Flag (USISIF) releases the

line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-

ups on the SDA and SCL port pin are disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

Same operation as for the Two-wire mode described above, except that the

SCL line is also held low when a counter overflow occurs, and is held low until

the Counter Overflow Flag (USIOIF) is cleared.

1

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

• Bit 3:2 – USICS1:0: Clock Source Select

These bits set the clock source for the Shift Register and counter. The data output latch ensures

that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when

using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare

Match clock option is selected, the output latch is transparent and therefore the output is

changed immediately. Clearing the USICS1..0 bits enables software strobe option. When using

this option, writing a one to the USICLK bit clocks both the Shift Register and the counter. For

external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects

between external clocking and software clocking by the USITC strobe bit.

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Table 19-2 shows the relationship between the USICS1:0 and USICLK setting and clock source

used for the Shift Register and the 4-bit counter.

Table 19-2. Relations between the USICS1:0 and USICLK Setting

USICS1

USICS0

USICLK

Shift Register Clock Source

4-bit Counter Clock Source

0

No Clock

Software clock strobe

(USICLK)

Software clock strobe

(USICLK)

0

1

Timer/Counter0 Compare

Match

Timer/Counter0 Compare

Match

X

1

0

1

0

1

0

1

External, positive edge

External, negative edge

External, positive edge

External, negative edge

External, both edges

Software clock strobe (USITC)

• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the Shift Register to shift one step and the counter to

increment by one, provided that the USICS1..0 bits are set to zero and by doing so the software

clock strobe option is selected. The output will change immediately when the clock strobe is exe-

cuted, i.e., in the same instruction cycle. The value shifted into the Shift Register is sampled the

previous instruction cycle. The bit will be read as zero.

When an external clock source is selected (USICS1 = 1), the USICLK function is changed from

a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the

USITC strobe bit as clock source for the 4-bit counter (see Table 19-2).

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.

The toggling is independent of the setting in the Data Direction Register, but if the PORT value is

to be shown on the pin the DDRE4 must be set as output (to one). This feature allows easy clock

generation when implementing master devices. The bit will be read as zero.

When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-

ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of

when the transfer is done when operating as a master device.

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20. AC - Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger

the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate

interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on com-

parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is

shown in Figure 20-1.

The Power Reduction ADC bit, PRADC, in ”PRR – Power Reduction Register” on page 44 must

be disabled by writing a logical zero to be able to use the ADC input MUX.

Figure 20-1. Analog Comparator Block Diagram⁽²⁾

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

Notes: 1. See Table 20-1 on page 212.

2. Refer to Figure 1-1 on page 2 and Table 12-5 on page 74 for Analog Comparator pin

placement.

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20.1 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7:0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2:0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

20-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 20-1. Analog Comparator Multiplexed Input

ACME

ADEN

MUX2:0

xxx

Analog Comparator Negative Input

0

1

x

1

0

AIN1

xxx

AIN1

000

001

010

011

100

101

110

111

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

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20.2 Analog Comparator Register Description

20.2.1

ADCSRB – ADC Control and Status Register B

Bit

7

–

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

(0x7B)

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see ”Analog Comparator Multiplexed Input” on page 212.

20.2.2

ACSR – Analog Comparator Control and Status Register

Bit

0x30 (0x50)

7

6

5

4

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

ACD

ACBG

ACO

ACI

R/W

0

ACSR

Read/Write

Initial Value

R/W

0

R/W

0

R

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. See ”Internal Voltage Reference” on page 51.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

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Input Capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection

between the Analog Comparator and the Input Capture function exists. To make the comparator

trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

Register (TIMSK1) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 20-2 on page 214.

Table 20-2. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

20.2.3

DIDR1 – Digital Input Disable Register 1

Bit

(0x7F)

7

6

5

–

4

–

3

–

2

–

1

AIN1D

R/W

0

AIN0D

R/W

0

–

R

0

DIDR1

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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21. ADC - Analog to Digital Converter

21.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

•

2 LSB Absolute Accuracy

• 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock)

• Up to 15 kSPS at Maximum Resolution (200 kHz ADC clock)

• Eight Multiplexed Single Ended Input Channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

The ATmega169P features a 10-bit successive approximation ADC. The ADC is connected to

an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed

from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 21-1.

The ADC has a separate analog supply voltage pin, AVCC. AV_CCmust not differ more than

0.3V from V_CC. See the paragraph ”ADC Noise Canceler” on page 221 on how to connect this

pin.

Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

The Power Reduction ADC bit, PRADC, in ”PRR – Power Reduction Register” on page 44 must

be written to zero to enable the ADC module.

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Figure 21-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

INTERRUPT

FLAGS

ADTS[2:0]

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

ADC DATA REGISTER

(ADCH/ADCL)

TRIGGER

SELECT

MUX DECODER

PRESCALER

START

CONVERSION LOGIC

AVCC

INTERNAL

REFERENCE

SAMPLE & HOLD

COMPARATOR

AREF

GND

10-BIT DAC

-

+

BANDGAP

REFERENCE

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

SINGLE ENDED / DIFFERENTIAL SELECTION

POS.

INPUT

MUX

ADC MULTIPLEXER

OUTPUT

DIFFERENTIAL

AMPLIFIER

+

-

NEG.

INPUT

MUX

21.2 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be con-

nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve

noise immunity.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input

pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended

inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-

age reference and input channel selections will not go into effect until ADEN is set. The ADC

does not consume power when ADEN is cleared, so it is recommended to switch off the ADC

before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

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If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

21.3 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to

trigger a new conversion at the next interrupt event.

Figure 21-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADIF

ADATE

SOURCE 1

.

CONVERSION

LOGIC

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

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If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

21.4 Prescaling and Conversion Timing

Figure 21-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic. When using Differential mode, along

with Auto triggering from a source other than the ADC Conversion Complete, each conversion

will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after

every conversion.

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In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 21-1.

Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

LSB of Result

ADCH

ADCL

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

Sample & Hold

Figure 21-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

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Figure 21-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

Table 21-1. ADC Conversion Time

Sample & Hold (Cycles from

Start of Conversion)

Condition

Conversion Time (Cycles)

First conversion

13.5

1.5

2

25

13

Normal conversions, single ended

Auto Triggered conversions

13.5

21.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, minimum one ADC clock cycle after the trigger event.

c. After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

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21.5.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

21.5.2

ADC Voltage Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either AVCC, internal 1.1V reference, or external AREF pin.

AVCC is connected to the ADC through a passive switch. The internal 1.1V reference is gener-

ated from the internal bandgap reference (V_BG) through an internal buffer. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and ground. V_REFcan

also be measured at the AREF pin with a high impedant voltmeter. Note that V_REFis a high

impedant source, and only a capacitive load should be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as

reference selection. The first ADC conversion result after switching reference voltage source

may be inaccurate, and the user is advised to discard this result.

21.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

a. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be enabled.

b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If

another interrupt wakes up the CPU before the ADC conversion is complete, that

interrupt will be executed, and an ADC Conversion Complete interrupt request will be

generated when the ADC conversion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

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21.6.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 21-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 21-8. Analog Input Circuitry

I_IH

ADCn

1..100 kW

C_S/H= 14 pF

I_IL

V_CC/2

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21.6.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

a. Keep analog signal paths as short as possible. Make sure analog tracks run over the

analog ground plane, and keep them well away from high-speed switching digital

tracks.

b. The AVCC pin on the device should be connected to the digital V_CCsupply voltage

via an LC network as shown in Figure 21-9.

c. Use the ADC noise canceler function to reduce induced noise from the CPU.

d. If any ADC port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress.

Figure 21-9. ADC Power Connections

PA0 51

VCC

52

GND

53

(ADC7) PF7 54

(ADC6) PF6 55

(ADC5) PF5 56

(ADC4) PF4 57

(ADC3) PF3 58

(ADC2) PF2 59

(ADC1) PF1

(ADC0) PF0

60

61

10µΗ

62

63

64

AREF

GND

AVCC

100nF

1

Ground Plane

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21.6.3

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at

0.5 LSB). Ideal value: 0 LSB.

Figure 21-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 21-11. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

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Figure 21-12. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 21-13. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a

range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: 0.5 LSB.

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21.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 21-3 on page 228 and Table 21-4 on page 229). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

(V

– V

) ⋅ 512

NEG

POS

ADC = ----------------------------------------------------

V

REF

Figure 21-14. Differential Measurement Range

Output Code

0x1FF

0x000

0

Differential Input

Voltage (Volts)

- V_REF

V_REF

0x3FF

0x200

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Table 21-2. Correlation Between Input Voltage and Output Codes

V_ADCn

Read Code

0x1FF

0x1FE

...

Corresponding Decimal Value

V_ADCm+ V_REF

511

510

...

511

V_ADCm

...

+

/

₅₁₂V_REF

510

/₅₁₂V_REF

V

_ADCm+ ¹/₅₁₂V_REF

V_ADCm

_ADCm- ¹/₅₁₂V_REF

0x001

0x000

0x3FF

...

1

0

V

-1

...

511

V_ADCm

-

/

₅₁₂V_REF

0x201

0x200

-511

-512

V

_ADCm- V_REF

ADMUX = 0xFB (ADC3 - ADC2, 1.1V reference, left adjusted result)

Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.

ADCR = 512 * (300 - 500) / 1100 = -93 = 0x3A3.

ADCL will thus read 0xC0, and ADCH will read 0xD8. Writing zero to ADLAR right adjusts the

result: ADCL = 0xA3, ADCH = 0x03.

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21.8 ADC Register Description

21.8.1

ADMUX – ADC Multiplexer Selection Register

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

MUX4

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

(0x7C)

ADMUX

Read/Write

Initial Value

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 21-3. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

Table 21-3. Voltage Reference Selections for ADC

REFS1

REFS0

Voltage Reference Selection

0

1

0

1

0

1

AREF, Internal Vref turned off

AVCC with external capacitor at AREF pin

Reserved

Internal 1.1V Voltage Reference with external capacitor at AREF pin

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see ”ADCL and ADCH – ADC Data Register” on

page 231.

• Bits 4:0 – MUX4:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

See Table 21-4 for details. If these bits are changed during a conversion, the change will not go

in effect until this conversion is complete (ADIF in ADCSRA is set).

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Table 21-4. Input Channel Selections

MUX4..0

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Single Ended Input

ADC0

Positive Differential Input

Negative Differential Input

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

N/A

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC1

ADC2

N/A

1.1V (V_BG

)

N/A

0V (GND)

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21.8.2

ADCSRA – ADC Control and Status Register A

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADATE

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

(0x7A)

ADCSRA

Read/Write

Initial Value

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI

instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the

ADC.

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Table 21-5. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

21.8.3

ADCL and ADCH – ADC Data Register

21.8.3.1

ADLAR = 0

Bit

15

14

13

12

11

10

9

8

(0x79)

(0x78)

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

21.8.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers.When ADCL is

read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left

adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,

ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on

page 226.

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21.8.4

ADCSRB – ADC Control and Status Register B

Bit

7

–

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

(0x7B)

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use. To ensure compatibility with future devices, this bit must be

written to zero when ADCSRB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 21-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

Timer/Counter Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

21.8.5

DIDR0 – Digital Input Disable Register 0

Bit

7

ADC7D

R/W

0

6

ADC6D

R/W

0

5

ADC5D

R/W

0

4

3

ADC3D

R/W

0

2

ADC2D

R/W

0

1

ADC1D

R/W

0

ADC0D

R/W

0

(0x7E)

ADC4D

DIDR0

Read/Write

Initial Value

R/W

0

• Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

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22. LCD Controller

The LCD Controller/driver is intended for monochrome passive liquid crystal display (LCD) with

up to four common terminals and up to 25 segment terminals.

22.1 Features

• Display Capacity of 25 Segments and Four Common Terminals

• Support Static, 1/2, 1/3 and 1/4 Duty

• Support Static, 1/2, 1/3 Bias

• LCD Output Voltage (Contrast) Software Selectable from 2.6 to 3.35V for V_CCin the Entire

Operating Range

• On-chip LCD Power Supply, only One External Capacitor needed

• Display Possible in Power-save Mode for Low Power Consumption

• Software Selectable Low Power Waveform Capability

• Flexible Selection of Frame Frequency

• Software Selection between System Clock or an External Asynchronous Clock Source

• Equal Source and Sink Capability to maximize LCD Life Time

• LCD Interrupt Can be Used for Display Data Update or Wake-up from Sleep Mode

• Segment and Common Pins not Needed for Driving the Display Can be Used as Ordinary I/O Pins

• Latching of Display Data gives Full Freedom in Register Update

22.2 Overview

A simplified block diagram of the LCD Controller/Driver is shown in Figure 22-1. For the actual

placement of I/O pins, see ”Pinout ATmega169P” on page 2.

An LCD consists of several segments (pixels or complete symbols) which can be visible or non

visible. A segment has two electrodes with liquid crystal between them. When a voltage above a

threshold voltage is applied across the liquid crystal, the segment becomes visible.

The voltage must alternate to avoid an electrophoresis effect in the liquid crystal, which

degrades the display. Hence the waveform across a segment must not have a DC-component.

The PRLCD bit in ”PRR – Power Reduction Register” on page 44 must be written to zero to

enable the LCD module.

22.2.1

Definitions

Several terms are used when describing LCD. The definitions in Table 22-1 are used throughout

this document.

Table 22-1. Definitions

LCD

A passive display panel with terminals leading directly to a segment

The least viewing element (pixel) which can be on or off

Segment

Common

Duty

Denotes how many segments are connected to a segment terminal

1/(Number of common terminals on a actual LCD display)

1/(Number of voltage levels used driving a LCD display -1)

Number of times the LCD segments is energized per second.

Bias

Frame Rate

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Figure 22-1. LCD Module Block Diagram

clk_LCD

0

1

clk_i/o

12-bit Prescaler

TOSC

lcdcs

SEG0

SEG1

lcdps2:0

lcdcd2:0

Clock

Multiplexer

LCDFRR

SEG2

SEG3

SEG4

LCDCRA

LCDCRB

Divide by 1 to 8

SEG5

SEG6

SEG7

clk_{LCD_PS}

SEG8

SEG9

D

A

T

A

LCD

Timing

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

COM0

COM1

COM2

COM3

LCDDR 18 -15

LCDDR 13 -10

LCDDR 8 - 5

LCDDR 3 - 0

Analog

Switch

Array

B

U

S

25 x

4:1

MUX

LATCH

array

LCD Ouput

Decoder

LCD_voltage_ok

1/3 V_LCD

1/2 V_LCD

2/3 V_LCD

LCD Buffer/

Driver

Display

Configuration

V_LCD

Contrast Controller/

Power Supply

LCDCCR

lcdcc3:0

LCD

CAP

22.2.2

LCD Clock Sources

The LCD Controller can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk_LCDis by default equal to the system clock, clk_I/O. When the

LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the

TOSC1 pin.

The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage

offset across LCD segments.

22.2.3

LCD Prescaler

The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits

selects clk_LCDdivided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.

If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by

1 to 8.

Output from the clock divider clk_{LCD_PS}is used as clock source for the LCD timing.

22.2.4

LCD Memory

The display memory is available through I/O Registers grouped for each common terminal.

When a bit in the display memory is written to one, the corresponding segment is energized (on),

and non-energized when a bit in the display memory is written to zero.

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To energize a segment, an absolute voltage above a certain threshold must be applied. This is

done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase.

For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage lev-

els must be applied. Otherwise, non-energized segments on COM0 would be energized for all

non-selected common.

Addressing COM0 starts a frame by driving opposite phase with large amplitude out on COM0

compared to none addressed COM lines. Non-energized segments are in phase with the

addressed COM0, and energized segments have opposite phase and large amplitude. For

waveform figures refer to ”Mode of Operation” on page 236. Latched data from LCDDR4 -

LCDDR0 is multiplexed into the decoder. The decoder is controlled from the LCD timing and

sets up signals controlling the analog switches to produce an output waveform. Next, COM1 is

addressed, and latched data from LCDDR9 - LCDDR5 is input to decoder. Addressing continu-

ous until all COM lines are addressed according to number of common (duty). The display data

are latched before a new frame start.

22.2.5

22.2.6

LCD Contrast Controller/Power Supply

The peak value (V_LCD) on the output waveform determines the LCD Contrast. V_LCDis controlled

by software from 2.6V to 3.35V independent of V_CC. An internal signal inhibits output to the LCD

until V_LCDhas reached its target value.

LCDCAP

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 22-2. This capacitor acts as a reservoir for LCD power (V_LCD). A large capacitance reduces

ripple on V_LCDbut increases the time until V_LCDreaches its target value.

It is possible to use an external power supply. This power can be applied to LCDCAP before

V

_CC. Externally applied V_LCDcan be both above and below V_CC. Maximum V_LCDis 5.5V

Figure 22-2. LCDCAP Connection

62

63

64

1

2

3

LCDCAP

V_LCD

(Optional)

22.2.7

LCD Buffer Driver

Intermediate voltage levels are generated from buffers/drivers. The buffers are active the

amount of time specified by LCDDC[2:0] in ”LCDCCR – LCD Contrast Control Register” on page

248. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive time

will reduce power consumption, but displays with high internal resistance or capacitance may

need longer drive time to achieve sufficient contrast.

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22.3 Mode of Operation

22.3.1

Static Duty and Bias

If all segments on a LCD have one electrode common, then each segment must have a unique

terminal.

This kind of display is driven with the waveform shown in Figure 22-3. SEG0 - COM0 is the volt-

age across a segment that is on, and SEG1 - COM0 is the voltage across a segment that is off.

Figure 22-3. Driving a LCD with One Common Terminal

V

LCD

SEG0

COM0

SEG1

COM0

GND

V

LCD

GND

V

LCD

GND

SEG0 - COM0

GND

SEG1 - COM0

-V

LCD

Frame

22.3.2

1/2 Duty and 1/2 Bias

For LCD with two common terminals (1/2 duty) a more complex waveform must be used to indi-

vidually control segments. Although 1/3 bias can be selected 1/2 bias is most common for these

displays. Waveform is shown in Figure 22-4. SEG0 - COM0 is the voltage across a segment that

is on, and SEG0 - COM1 is the voltage across a segment that is off.

Figure 22-4. Driving a LCD with Two Common Terminals

V

LCD

SEG0

COM0

SEG0

COM1

GND

V

LCD

1

/ V

2

LCD

2 LCD

GND

V

LCD

1

/ V

2

LCD

2 LCD

GND

SEG0 - COM0

GND

SEG0 - COM1

-1

/ V

2

LCD

2

LCD

-V

Frame

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22.3.3

1/3 Duty and 1/3 Bias

1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is

shown in Figure 22-5. SEG0 - COM0 is the voltage across a segment that is on and SEG0-

COM1 is the voltage across a segment that is off.

Figure 22-5. Driving a LCD with Three Common Terminals

V

/ V

GND

LCD

2

1

2

1

/ V

3

SEG0

COM0

SEG0

COM1

/ V

3

GND

V

LCD

2

1

2

1

/ V

3

LCD

3

LCD

/ V

3

LCD

3

LCD

GND

V

LCD

2

1

2

1

/ V

3

LCD

3

LCD

/ V

3

LCD

3

LCD

SEG0 - COM0

SEG0 - COM1

GND

1

- / V

-V

3

LCD

3

LCD

2

- / V

3

-V

Frame

22.3.4

1/4 Duty and 1/3 Bias

1/3 bias is optimal for LCD displays with four common terminals (1/4 duty). Waveform is shown

in Figure 22-6. SEG0 - COM0 is the voltage across a segment that is on and SEG0 - COM1 is

the voltage across a segment that is off.

Figure 22-6. Driving a LCD with Four Common Terminals

V

LCD

2

1

2

1

/ V

3

/ V

3

GND

/ V

3

/ V

3

GND

SEG0

COM0

SEG0

COM1

V

/ V

LCD

2

1

2

1

/ V

3

LCD

3

LCD

/ V

3

/ V

3

LCD

GND

V

/ V

LCD

2

1

2

1

/ V

3

LCD

3

LCD

/ V

3

/ V

3

GND

LCD

SEG0 - COM0

SEG0 - COM1

GND

1

- / V

3

- / V

3

-V

- / V

3

- / V

3

-V

LCD

2

Frame

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22.3.5

Low Power Waveform

To reduce toggle activity and hence power consumption a low power waveform can be selected

by writing LCDAB to one. Low power waveform requires two subsequent frames with the same

display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set

every second frame. Default and low power waveform is shown in Figure 22-7 for 1/3 duty and

1/3 bias. For other selections of duty and bias, the effect is similar.

Figure 22-7. Default and Low Power Waveform

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

SEG0

COM0

SEG0

COM0

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

-¹/₃V_LCD

-²/₃V_LCD

-V_LCD

V_LCD

²/₃V_LCD

¹/₃V_LCD

GND

-¹/₃V_LCD

-²/₃V_LCD

-V_LCD

SEG0 - COM0

Frame

22.3.6

Operation in Sleep Mode

When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in Idle

mode and Power-save mode with any clock source.

An asynchronous clock from TOSC1 can be selected as LCD clock by writing the LCDCS bit to

one when Calibrated Internal RC Oscillator is selected as system clock source. The LCD will

then operate in Idle mode, ADC Noise Reduction mode and Power-save mode.

When EXCLK in ASSR Register is written to one, and asynchronous clock is selected, the exter-

nal clock input buffer is enabled and an external clock can be input on Timer Oscillator 1

(TOSC1) pin instead of a 32 kHz crystal. See ”Asynchronous operation of the Timer/Counter” on

page 150 for further details.

Before entering Power-down mode, Standby mode or ADC Noise Reduction mode with synchro-

nous LCD clock selected, the user have to disable the LCD. Refer to ”Disabling the LCD” on

page 242.

22.3.7

Display Blanking

When LCDBL is written to one, the LCD is blanked after completing the current frame. All seg-

ments and common pins are connected to GND, discharging the LCD. Display memory is

preserved. Display blanking should be used before disabling the LCD to avoid DC voltage

across segments, and a slowly fading image.

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22.3.8

Port Mask

For LCD with less than 25 segment terminals, it is possible to mask some of the unused pins

and use them as ordinary port pins instead. Refer to Table 22-3 for details. Unused common

pins are automatically configured as port pins.

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22.4 LCD Usage

The following section describes how to use the LCD.

22.4.1

LCD Initialization

Prior to enabling the LCD some initialization must be preformed. The initialization process nor-

mally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but

can also be adjusted during operation.

Consider the following LCD as an example:

Figure 22-8. LCD usage example.

LCD

2a

1b

1c

2f

2b

2c

2g

2d

2e

51

50

49

SEG2

SEG1

SEG0

2f

2g

2d

..

2e

COM3 48

SEG0 47

SEG1 46

SEG2 45

2c

1b,1c

COM0

2a

2b

COM1

COM2

ATmega329

Connection table

Display:

TN Positive, Reflective

Number of common terminals:

Number of segment terminals:

Bias system:

3

21

1/3 Bias

1/3 Duty

3.0 0.3 V

Drive system:

Operating voltage:

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Assembly Code Example⁽¹⁾

LCD_Init:

; Use 32 kHz crystal oscillator

; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins

ldi r16, (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2)

sts LCDCRB, r16

; Using 16 as prescaler selection and 7 as LCD Clock Divide

; gives a frame rate of 49 Hz

ldi r16, (1<<LCDCD2) | (1<<LCDCD1)

sts LCDFRR, r16

; Set segment drive time to 125 µs and output voltage to 3.3 V

ldi r16, (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1)

sts LCDCCR, r16

; Enable LCD, default waveform and no interrupt enabled

ldi r16, (1<<LCDEN)

sts LCDCRA, r16

ret

C Code Example⁽¹⁾

Void LCD_Init(void);

{

/* Use 32 kHz crystal oscillator */

/* 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins */

LCDCRB = (1<<LCDCS) | (1<<LCDMUX1)| (1<<LCDPM2);

/* Using 16 as prescaler selection and 7 as LCD Clock Divide */

/* gives a frame rate of 49 Hz */

LCDFRR = (1<<LCDCD2) | (1<<LCDCD1);

/* Set segment drive time to 125 µs and output voltage to 3.3 V*/

LCDCCR = (1<<LCDDC1) | (1<<LCDCC3) | (1<<LCDCC2) | (1<<LCDCC1);

/* Enable LCD, default waveform and no interrupt enabled */

LCDCRA = (1<<LCDEN);

}

Note:

1. See ”About Code Examples” on page 9.

Before a re-initialization is done, the LCD controller/driver should be disabled

Updating the LCD

22.4.2

Display memory (LCDDR0, LCDDR1, ..), LCD Blanking (LCDBL), Low power waveform

(LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no

restrictions on writing these LCD Register locations, but an LCD data update may be split

between two frames if data are latched while an update is in progress. To avoid this, an interrupt

routine can be used to update Display memory, LCD Blanking, Low power waveform, and con-

trast control, just after data are latched.

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In the example below we assume SEG10 and COM1 and SEG4 in COM0 are the only segments

changed from frame to frame. Data are stored in r20 and r21 for simplicity

Assembly Code Example⁽¹⁾

LCD_update:

; LCD Blanking and Low power waveform are unchanged.

; Update Display memory.

sts LCDDR0, r20

sts LCDDR6, r21

ret

C Code Example⁽¹⁾

Void LCD_update(unsigned char data1, data2);

{

/* LCD Blanking and Low power waveform are unchanged. */

/* Update Display memory. */

LCDDR0 = data1;

LCDDR6 = data2;

}

Note:

Disabling the LCD

1. See ”About Code Examples” on page 9.

22.4.3

In some application it may be necessary to disable the LCD. This is the case if the MCU enters

Power-down mode where no clock source is present.

The LCD should be completely discharged before being disabled. No DC voltage should be left

across any segment. The best way to achieve this is to use the LCD Blanking feature that drives

all segment pins and common pins to GND.

When the LCD is disabled, port function is activated again. Therefore, the user must check that

port pins connected to a LCD terminal are either tri-state or output low (sink).

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Assembly Code Example⁽¹⁾

LCD_disable:

; Wait until a new frame is started.

Wait_1:

lds r16, LCDCRA

sbrs r16, LCDIF

rjmp Wait_1

; Set LCD Blanking and clear interrupt flag

; by writing a logical one to the flag.

ldi r16, (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL)

sts LCDCRA, r16

; Wait until LCD Blanking is effective.

Wait_2:

lds r16, LCDCRA

sbrs r16, LCDIF

rjmp Wait_2

; Disable LCD.

ldi r16, (0<<LCDEN)

sts LCDCRA, r16

ret

C Code Example⁽¹⁾

Void LCD_disable(void);

{

/* Wait until a new frame is started. */

while ( !(LCDCRA & (1<<LCDIF)) )

;

/* Set LCD Blanking and clear interrupt flag */

/* by writing a logical one to the flag. */

LCDCRA = (1<<LCDEN)|(1<<LCDIF)|(1<<LCDBL);

/* Wait until LCD Blanking is effective. */

while ( !(LCDCRA & (1<<LCDIF)) )

;

/* Disable LCD */

LCDCRA = (0<<LCDEN);

}

Note:

1. See ”About Code Examples” on page 9.

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22.5 LCD Register Description

22.5.1

LCDCRA – LCD Control and Status Register A

Bit

7

LCDEN

R/W

0

6

LCDAB

R/W

0

5

–

4

LCDIF

R/W

0

3

LCDIE

R/W

0

2

LCDBD

R/W

0

1

LCDCCD

R/W

0

LCDBL

R/W

0

(0xE4)

LCDCRA

Read/Write

Initial Value

R

0

• Bit 7 – LCDEN: LCD Enable

Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned

off immediately. Turning the LCD Controller/Driver off while driving a display, enables ordinary

port function, and DC voltage can be applied to the display if ports are configured as output. It is

recommended to drive output to ground if the LCD Controller/Driver is disabled to discharge the

display.

• Bit 6 – LCDAB: LCD Low Power Waveform

When LCDAB is written logic zero, the default waveform is output on the LCD pins. When

LCDAB is written logic one, the Low Power Waveform is output on the LCD pins. If this bit is

modified during display operation the change takes place at the beginning of a new frame.

• Bit 5 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bit 4 – LCDIF: LCD Interrupt Flag

This bit is set by hardware at the beginning of a new frame, at the same time as the display data

is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I-bit in SREG

are set. LCDIF is cleared by hardware when executing the corresponding Interrupt Handling

Vector. Alternatively, writing a logical one to the flag clears LCDIF. Beware that if doing a Read-

Modify-Write on LCDCRA, a pending interrupt can be disabled. If Low Power Waveform is

selected the Interrupt Flag is set every second frame.

• Bit 3 – LCDIE: LCD Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the LCD Start of Frame Interrupt is

enabled.

• Bit 2 – LCDBD: LCD Buffer Disable

The intermediate voltage levels in the LCD are generated by an internal resistive voltage divider

and passed through buffer to increase the current driving capability. By writing this bit to one the

buffers are turned off and bypassed, resulting in decreased power consumption. The total resis-

tance of the voltage divider is nominally 400 kΩ between LCDCAP and GND.

• Bit 1 – LCDCCD: LCD Contrast Control Disable

Writing this bit to one disables the internal power supply for the LCD driver. The desired voltage

must be applied to the LCDCAP pin from an external power supply. To avoid conflict between

internal and external power supply, this bit must be written as '1' prior to or simultaneously with

writing '1' to the LCDEN bit.

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• Bit 0 – LCDBL: LCD Blanking

When this bit is written to one, the display will be blanked after completion of a frame. All seg-

ment and common pins will be driven to ground.

22.5.2

LCDCRB – LCD Control and Status Register B

Bit

7

6

5

4

LCDMUX0

R/W

3

–

2

LCDPM2

R/W

0

1

LCDPM1

R/W

0

LCDPM0

R/W

0

LCDCS

LCD2B

LCDMUX1

LCDCRB

(0xE5)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

• Bit 7 – LCDCS: LCD Clock Select

When this bit is written to zero, the system clock is used. When this bit is written to one, the

external asynchronous clock source is used. The asynchronous clock source is either

Timer/Counter Oscillator or external clock, depending on EXCLK in ASSR. See ”Asynchronous

operation of the Timer/Counter” on page 150 for further details.

• Bit 6 – LCD2B: LCD 1/2 Bias Select

When this bit is written to zero, 1/3 bias is used. When this bit is written to one, ½ bias is used.

Refer to the LCD Manufacture for recommended bias selection.

• Bit 5:4 – LCDMUX1:0: LCD Mux Select

The LCDMUX1:0 bits determine the duty cycle. Common pins that are not used are ordinary port

pins. The different duty selections are shown in Table 22-2.

Table 22-2. LCD Duty Select

LCDMUX1

LCDMUX0

Duty

Static

1/2

Bias

COM Pin

COM0

I/O Port Pin

COM1:3

COM2:3

COM3

0

1

0

1

0

1

Static

1/2 or 1/3⁽¹⁾

COM0:1

COM0:2

COM0:3

1/3

1/4

None

Note:

1. 1/2 bias when LCD2B is written to one and 1/3 otherwise.

• Bit 3 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 2:0 – LCDPM2:0: LCD Port Mask

The LCDPM2:0 bits determine the number of port pins to be used as segment drivers. The dif-

ferent selections are shown in Table 22-3. Unused pins can be used as ordinary port pins.

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Table 22-3. LCD Port Mask

I/O Port in Use as Segment

Driver

Maximum Number of

Segments

LCDPM2

LCDPM1

LCDPM0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SEG0:12

SEG0:14

SEG0:16

SEG0:18

SEG0:20

SEG0:22

SEG0:23

SEG0:24

13

15

17

19

21

23

24

25

22.5.3

LCDFRR – LCD Frame Rate Register

Bit

7

–

6

LCDPS2

R/W

0

5

LCDPS1

R/W

0

4

LCDPS0

R/W

0

3

–

2

LCDCD2

R/W

0

1

0

LCDCD1

R/W

0

LCDCD0

R/W

0

LCDFRR

(0xE6)

Read/Write

Initial Value

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 6:4 – LCDPS2:0: LCD Prescaler Select

The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further

divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in Table

22-4 on page 246. Together they determine the prescaled LCD clock (clk_{LCD_PS}), which is clock-

ing the LCD module.

Table 22-4. LCD Prescaler Select

Output from

Prescaler

clk_LCD/N

Applied Prescaled LCD Clock Frequency

when LCDCD2:0 = 0, Duty = 1/4, and

Frame Rate = 64 Hz

LCDPS2

LCDPS1

LCDPS0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

clk_LCD/16

clk_LCD/64

8.1 kHz

33 kHz

66 kHz

130 kHz

260 kHz

520 kHz

1 MHz

clk_LCD/128

clk_LCD/256

clk_LCD/512

clk_LCD/1024

clk_LCD/2048

clk_LCD/4096

2 MHz

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• Bit 3 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0

The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are

shown in Table 22-5 on page 247. This Clock Divider gives extra flexibility in frame rate

selection.

Table 22-5. LCD Clock Divide

Output from Prescaler

divided by (D):

clk_LCD= 32.768 kHz, N = 16, and

Duty = 1/4, gives a frame rate of:

LCDCD2

LCDCD1

LCDCD0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

256 Hz

128 Hz

85.3 Hz

64 Hz

51.2 Hz

42.7 Hz

36.6 Hz

32 Hz

The frame frequency can be calculated by the following equation:

f

clk_LCD

f

= -------------------------

frame

(K ⋅ N ⋅ D)

Where:

N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).

K = 8 for duty = 1/4, 1/2, and static.

K = 6 for duty = 1/3.

D = Division factor (see Table 22-5).

This is a very flexible scheme, and users are encouraged to calculate their own table to investi-

gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate

is increased with 33ꢀ when Frame Rate Register is constant. Example of frame rate calculation

is shown in Table 22-6.

Table 22-6. Example of frame rate calculation

clk_LCD

duty

1/4

K

N

LCDCD2:0

011

D

Frame Rate

4 MHz

8

6

8

2048

4

1

5

4000000/(8*2048*4) = 61 Hz

4000000/(6*2048*4) = 81 Hz

32768/(8*16*1) = 256 Hz

32768/(8*16*5) = 51 Hz

4 MHz

1/3

2048

16

011

32.768 kHz

Static

1/2

000

16

100

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22.5.4

LCDCCR – LCD Contrast Control Register

Bit

7

LCDDC2

R/W

0

6

LCDDC1

R/W

0

5

LCDDC0

R/W

0

4

LCDMDT

R/W

3

LCDCC3

R/W

0

2

LCDCC2

R/W

0

1

LCDCC1

R/W

0

LCDCC0

R/W

0

LCDCCR

(0xE7)

Read/Write

Initial Value

0

• Bits 7:5 – LCDDC2:0: LDC Display Configuration

The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-

age transition on segment and common pins. A short drive time will lead to lower power

consumption, but displays with high internal resistance may need longer drive time to achieve

satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD

clock period, even if the selected drive time is longer. When using static bias or blanking, drive

time will always be one half prescaled LCD clock period.

Table 22-7. LCD Display Configuration

LCDDC2

LCDDC1

LCDDC0

Nominal drive time

300 µs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

70 µs

150 µs

450 µs

575 µs

850 µs

1150 µs

50ꢀ of clk_{LCD_PS}

• Bit 4 – LCDMDT: LCD Maxium Drive Time

Writing this bit to one turns the LCD drivers on 100ꢀ on the time, regardless of the drive time

configured by LCDDC2:0.

• Bits 3:0 – LCDCC3:0: LCD Contrast Control

The LCDCC3:0 bits determine the maximum voltage V_LCDon segment and common pins. The

different selections are shown in Table 22-8. New values take effect every beginning of a new

frame.

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Table 22-8. LCD Contrast Control

LCDCC3

LCDCC2

LCDCC1

LCDCC0

Maximum Voltage V_LCD

2.60 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.65 V

2.70 V

2.75 V

2.80 V

2.85 V

2.90 V

2.95 V

3.00 V

3.05 V

3.10 V

3.15 V

3.20 V

3.25 V

3.30 V

3.35 V

22.5.5

LCD Memory Mapping

Write a LCD memory bit to one and the corresponding segment will be energized (visible).

Unused LCD Memory bits for the actual display can be used freely as storage.

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

Bit

–

LCDDR19

LCDDR18

LCDDR17

LCDDR16

LCDDR15

LCDDR14

LCDDR13

LCDDR12

LCDDR11

LCDDR10

LCDDR9

LCDDR8

LCDDR7

LCDDR6

LCDDR5

LCDDR4

LCDDR3

LCDDR2

LCDDR1

LCDDR0

–

SEG324

SEG316

SEG308

SEG300

–

COM3

SEG323

SEG315

SEG307

–

SEG322

SEG314

SEG306

–

SEG321

SEG313

SEG305

–

SEG320

SEG312

SEG304

–

SEG319

SEG311

SEG303

–

SEG318

SEG310

SEG302

–

SEG317

SEG309

SEG301

–

SEG224

SEG216

SEG208

SEG200

–

COM2

SEG223

SEG215

SEG207

–

SEG222

SEG214

SEG206

–

SEG221

SEG213

SEG205

–

SEG220

SEG212

SEG204

–

SEG219

SEG211

SEG203

–

SEG218

SEG210

SEG202

–

SEG217

SEG209

SEG201

–

SEG124

SEG116

SEG108

SEG100

–

COM1

SEG123

SEG115

SEG107

–

SEG122

SEG114

SEG106

–

SEG121

SEG113

SEG105

–

SEG120

SEG112

SEG104

–

SEG119

SEG111

SEG103

–

SEG118

SEG110

SEG102

–

SEG117

SEG109

SEG101

–

SEG024

SEG016

SEG008

SEG000

R/W

COM0

SEG023

SEG015

SEG007

R/W

SEG022

SEG014

SEG006

R/W

SEG021

SEG013

SEG005

R/W

SEG020

SEG012

SEG004

R/W

SEG019

SEG011

SEG003

R/W

SEG018

SEG010

SEG002

R/W

SEG017

SEG009

SEG001

R/W

COM0

Read/Write

Initial Value

0

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23. JTAG Interface and On-chip Debug System

23.0.1

Features

• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard

• Debugger Access to:

– All Internal Peripheral Units

– Internal and External RAM

– The Internal Register File

– Program Counter

– EEPROM and Flash Memories

• Extensive On-chip Debug Support for Break Conditions, Including

– AVR Break Instruction

– Break on Change of Program Memory Flow

– Single Step Break

– Program Memory Break Points on Single Address or Address Range

– Data Memory Break Points on Single Address or Address Range

• Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• On-chip Debugging Supported by AVR Studio^®

23.1 Overview

The AVR IEEE std. 1149.1 compliant JTAG interface can be used for

• Testing PCBs by using the JTAG Boundary-scan capability

• Programming the non-volatile memories, Fuses and Lock bits

• On-chip debugging

A brief description is given in the following sections. Detailed descriptions for Programming via

the JTAG interface, and using the Boundary-scan Chain can be found in the sections ”Program-

ming via the JTAG Interface” on page 314 and ”IEEE 1149.1 (JTAG) Boundary-scan” on page

257, respectively. The On-chip Debug support is considered being private JTAG instructions,

and distributed within ATMEL and to selected third party vendors only.

Figure 23-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The

TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller

selects either the JTAG Instruction Register or one of several Data Registers as the scan chain

(Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG

instructions controlling the behavior of a Data Register.

The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used

for board-level testing. The JTAG Programming Interface (actually consisting of several physical

and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal

Scan Chain and Break Point Scan Chain are used for On-chip debugging only.

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23.2 TAP – Test Access Port

The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins

constitute the Test Access Port – TAP. These pins are:

• TMS: Test mode select. This pin is used for navigating through the TAP-controller state

machine.

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register

(Scan Chains).

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not

provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the

TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP

pins are internally pulled high and the JTAG is enabled for Boundary-scan and programming.

The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-

tored by the debugger to be able to detect external reset sources. The debugger can also pull

the RESET pin low to reset the whole system, assuming only open collectors on the reset line

are used in the application.

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Figure 23-1. Block Diagram

I/O PORT 0

DEVICE BOUNDARY

BOUNDARY SCAN CHAIN

TDI

TDO

TCK

TMS

JTAG PROGRAMMING

INTERFACE

TAP

CONTROLLER

AVR CPU

INTERNAL

SCAN

CHAIN

FLASH

MEMORY

Address

Data

PC

Instruction

INSTRUCTION

REGISTER

ID

REGISTER

BREAKPOINT

UNIT

M

U

X

FLOW CONTROL

UNIT

BYPASS

REGISTER

DIGITAL

PERIPHERAL

UNITS

ANALOG

PERIPHERIAL

UNITS

Analog inputs

BREAKPOINT

SCAN CHAIN

JTAG / AVR CORE

COMMUNICATION

INTERFACE

ADDRESS

DECODER

OCD STATUS

AND CONTROL

Control & Clock lines

I/O PORT n

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Figure 23-2. TAP Controller State Diagram

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

Capture-IR

0

1

Capture-DR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

23.3 TAP Controller

The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-

scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions

depicted in Figure 23-2 depend on the signal present on TMS (shown adjacent to each state

transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-

Logic-Reset.

As a definition in this document, the LSB is shifted in and out first for all Shift Registers.

Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:

• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift

Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG

instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.

The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR

state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While

the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the

TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and

TDO and controls the circuitry surrounding the selected Data Register.

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• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched

onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-

IR, and Exit2-IR states are only used for navigating the state machine.

• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data

Register – Shift-DR state. While in this state, upload the selected Data Register (selected by

the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising

edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during

input of all bits except the MSB. The MSB of the data is shifted in when this state is left by

setting TMS high. While the Data Register is shifted in from the TDI pin, the parallel inputs to

the Data Register captured in the Capture-DR state is shifted out on the TDO pin.

• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data

Register has a latched parallel-output, the latching takes place in the Update-DR state. The

Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.

As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting

JTAG instruction and using Data Registers, and some JTAG instructions may select certain

functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.

Note:

Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be

entered by holding TMS high for five TCK clock periods.

For detailed information on the JTAG specification, refer to the literature listed in ”Bibliography”

on page 256.

23.4 Using the Boundary-scan Chain

A complete description of the Boundary-scan capabilities are given in the section ”IEEE 1149.1

(JTAG) Boundary-scan” on page 257.

23.5 Using the On-chip Debug System

As shown in Figure 23-1, the hardware support for On-chip Debugging consists mainly of

• A scan chain on the interface between the internal AVR CPU and the internal peripheral units.

• Break Point unit.

• Communication interface between the CPU and JTAG system.

All read or modify/write operations needed for implementing the Debugger are done by applying

AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O

memory mapped location which is part of the communication interface between the CPU and the

JTAG system.

The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two

Program Memory Break Points, and two combined Break Points. Together, the four Break

Points can be configured as either:

• 4 single Program Memory Break Points.

• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.

• 2 single Program Memory Break Points + 2 single Data Memory Break Points.

• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range

Break Point”).

• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break

Point”).

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A debugger, like the AVR Studio, may however use one or more of these resources for its inter-

nal purpose, leaving less flexibility to the end-user.

A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG

Instructions” on page 255.

The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the

OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system

to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or

LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door

into a secured device.

The AVR Studio enables the user to fully control execution of programs on an AVR device with

On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.

AVR Studio^®supports source level execution of Assembly programs assembled with Atmel Cor-

poration’s AVR Assembler and C programs compiled with third party vendors’ compilers.

AVR Studio runs under Microsoft^®Windows^®95/98/2000, Windows NT^®and Windows XP^®.

For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high-

lights are presented in this document.

All necessary execution commands are available in AVR Studio, both on source level and on

disassembly level. The user can execute the program, single step through the code either by

tracing into or stepping over functions, step out of functions, place the cursor on a statement and

execute until the statement is reached, stop the execution, and reset the execution target. In

addition, the user can have an unlimited number of code Break Points (using the BREAK

instruction) and up to two data memory Break Points, alternatively combined as a mask (range)

Break Point.

23.6 On-chip Debug Specific JTAG Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within

ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.

23.6.1

23.6.2

23.6.3

23.6.4

PRIVATE0; 0x8

PRIVATE1; 0x9

PRIVATE2; 0xA

PRIVATE3; 0xB

Private JTAG instruction for accessing On-chip debug system.

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23.7 On-chip Debug Related Register in I/O Memory

23.7.1

OCDR – On-chip Debug Register

Bit

7

6

5

4

3

2

1

0

0x31 (0x51)

Read/Write

Initial Value

MSB/IDRD

LSB

R/W

0

OCDR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The OCDR Register provides a communication channel from the running program in the micro-

controller to the debugger. The CPU can transfer a byte to the debugger by writing to this

location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate

to the debugger that the register has been written. When the CPU reads the OCDR Register the

7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the

IDRD bit when it has read the information.

In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR

Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables

access to the OCDR Register. In all other cases, the standard I/O location is accessed.

Refer to the debugger documentation for further information on how to use this register.

23.8 Using the JTAG Programming Capabilities

Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and

TDO. These are the only pins that need to be controlled/observed to perform JTAG program-

ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse

must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the

JTAG Test Access Port. See ”Boundary-scan Related Register in I/O Memory” on page 278.

The JTAG programming capability supports:

• Flash programming and verifying.

• EEPROM programming and verifying.

• Fuse programming and verifying.

• Lock bit programming and verifying.

The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are

programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a

security feature that ensures no back-door exists for reading out the content of a secured

device.

The details on programming through the JTAG interface and programming specific JTAG

instructions are given in the section ”Programming via the JTAG Interface” on page 314.

23.9 Bibliography

For more information about general Boundary-scan, the following literature can be consulted:

• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan

Architecture, IEEE, 1993.

• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992.

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24. IEEE 1149.1 (JTAG) Boundary-scan

24.1 Features

• JTAG (IEEE std. 1149.1 compliant) Interface

• Boundary-scan Capabilities According to the JTAG Standard

• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections

• Supports the Optional IDCODE Instruction

• Additional Public AVR_RESET Instruction to Reset the AVR

24.2 System Overview

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by

the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to

drive values at their output pins, and observe the input values received from other devices. The

controller compares the received data with the expected result. In this way, Boundary-scan pro-

vides a mechanism for testing interconnections and integrity of components on Printed Circuits

Boards by using the four TAP signals only.

The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-

LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be

used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the

ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to

have the AVR device in reset during test mode. If not reset, inputs to the device may be deter-

mined by the scan operations, and the internal software may be in an undetermined state when

exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high

impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction

can be issued to make the shortest possible scan chain through the device. The device can be

set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET

instruction with appropriate setting of the Reset Data Register.

The EXTEST instruction is used for sampling external pins and loading output pins with data.

The data from the output latch will be driven out on the pins as soon as the EXTEST instruction

is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for

setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST

instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the

external pins during normal operation of the part.

The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be

cleared to enable the JTAG Test Access Port.

When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher

than the internal chip frequency is possible. The chip clock is not required to run.

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24.3 Data Registers

The Data Registers relevant for Boundary-scan operations are:

• Bypass Register

• Device Identification Register

• Reset Register

• Boundary-scan Chain

24.3.1

24.3.2

Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is

selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR

controller state. The Bypass Register can be used to shorten the scan chain on a system when

the other devices are to be tested.

Device Identification Register

Figure 24-1 shows the structure of the Device Identification Register.

Figure 24-1. The Format of the Device Identification Register

LSB

MSB

Bit

31

28

27

12

11

1

0

Device ID

Version

Part Number

Manufacturer ID

1

4 bits

16 bits

11 bits

1-bit

24.3.2.1

24.3.2.2

Version

Version is a 4-bit number identifying the revision of the component. The JTAG version number

follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.

Part Number

The part number is a 16-bit code identifying the component. The JTAG Part Number for

ATmega169P is listed in Table 24-1.

Table 24-1. AVR JTAG Part Number

Part Number

JTAG Part Number (Hex)

ATmega169P

0x9405

24.3.2.3

Manufacturer ID

The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID

for ATMEL is listed in Table 24-2.

Table 24-2. Manufacturer ID

Manufacturer

JTAG Manufactor ID (Hex)

ATMEL

0x01F

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24.3.3

Reset Register

The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port

Pins when reset, the Reset Register can also replace the function of the unimplemented optional

JTAG instruction HIGHZ.

A high value in the Reset Register corresponds to pulling the external Reset low. The part is

reset as long as there is a high value present in the Reset Register. Depending on the fuse set-

tings for the clock options, the part will remain reset for a reset time-out period (refer to ”Clock

Sources” on page 30) after releasing the Reset Register. The output from this Data Register is

not latched, so the reset will take place immediately, as shown in Figure 24-2.

Figure 24-2. Reset Register

To

TDO

From Other Internal and

External Reset Sources

From

TDI

Internal reset

D

Q

ClockDR · AVR_RESET

24.3.4

Boundary-scan Chain

The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-

ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connections.

See ”Boundary-scan Chain” on page 261 for a complete description.

24.4 Boundary-scan Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the

JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction

is not implemented, but all outputs with tri-state capability can be set in high-impedant state by

using the AVR_RESET instruction, since the initial state for all port pins is tri-state.

As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

24.4.1

EXTEST; 0x0

Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing

circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output

Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip

connections, the interface between the analog and the digital logic is in the scan chain. The con-

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tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-

Register is loaded with the EXTEST instruction.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Internal Scan Chain is shifted by the TCK input.

• Update-DR: Data from the scan chain is applied to output pins.

24.4.2

IDCODE; 0x1

Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register

consists of a version number, a device number and the manufacturer code chosen by JEDEC.

This is the default instruction after power-up.

The active states are:

• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.

• Shift-DR: The IDCODE scan chain is shifted by the TCK input.

24.4.3

SAMPLE_PRELOAD; 0x2

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the

input/output pins without affecting the system operation. However, the output latches are not

connected to the pins. The Boundary-scan Chain is selected as Data Register.

The active states are:

• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.

• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.

• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However, the

output latches are not connected to the pins.

24.4.4

AVR_RESET; 0xC

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or

releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit

Reset Register is selected as Data Register. Note that the reset will be active as long as there is

a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

24.4.5

BYPASS; 0xF

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

• Capture-DR: Loads a logic “0” into the Bypass Register.

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.

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24.5 Boundary-scan Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-

tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having

off-chip connection.

24.5.1

Scanning the Digital Port Pins

Figure 24-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The

cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a

bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –

ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are

not used in the following description

The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a

simple digital port pin as described in the section ”I/O-Ports” on page 65. The Boundary-scan

details from Figure 24-3 replaces the dashed box in Figure 24-4.

When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-

ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output

Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-

responds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 24-4 to make the

scan chain read the actual pin value. For Analog function, there is a direct connection from the

external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-

tal logic and the analog circuitry.

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Figure 24-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.

ShiftDR

To Next Cell

EXTEST

Vcc

Pullup Enable (PUE)

0

1

FF2

Q

LD2

0

1

D

Q

G

Output Control (OC)

FF1

D Q

LD1

0

1

0

1

D

G

Q

Output Data (OD)

0

1

FF0

D

LD0

0

1

0

1

Q

D

G

Q

Input Data (ID)

From Last Cell

ClockDR

UpdateDR

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Figure 24-4. General Port Pin Schematic Diagram

See Boundary-scan

Description for Details!

PUExn

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

OCxn

Pxn

1

0

Q

D

PORTxn

ODxn

IDxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

CLK _I/O

PUD:

PULLUP DISABLE

WDx:

RDx:

WRx:

RRx:

RPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUExn:

OCxn:

ODxn:

IDxn:

PULLUP ENABLE for pin Pxn

OUTPUT CONTROL for pin Pxn

OUTPUT DATA to pin Pxn

INPUT DATA from pin Pxn

SLEEP CONTROL

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

I/O CLOCK

WPx:

CLK _I/O

SLEEP:

:

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24.5.2

Scanning the RESET Pin

The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high

logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 24-5 is

inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.

Figure 24-5. Observe-only Cell

To

Cell

From System Pin

To System Logic

FF1

0

1

D

Q

From

ClockDR

24.5.3

Scanning the Clock Pins

The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-

tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and

Ceramic Resonator.

Figure 24-6 shows how each Oscillator with external connection is supported in the scan chain.

The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-

put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is

scanned in the same way. The output from the internal RC Oscillator is not scanned, as this

Oscillator does not have external connections.

Figure 24-6. Boundary-scan Cells for Oscillators and Clock Options

XTAL1/TOSC1

XTAL2/TOSC2

To

ShiftDR

EXTEST

Oscillator

ShiftDR

From Digital Logic

0

1

To System Logic

ENABLE

OUTPUT

0

1

FF1

D

Q

D

G

Q

0

1

D

Q

From

ClockDR

UpdateDR

From

ClockDR

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Table 24-3 summaries the scan registers for the external clock pin XTAL1, oscillators with

XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.

Table 24-3. Scan Signals for the Oscillator^(1)(2)(3)

Scanned

Clock Line

Scanned Clock Line

when not Used

Enable Signal

Clock Option

EXTCLKEN

EXTCLK (XTAL1)

External Clock

0

1

External Crystal

OSCON

OSCCK

External Ceramic Resonator

OSC32EN

OSC32CK

Low Freq. External Crystal

Notes: 1. Do not enable more than one clock source as main clock at a time.

2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between

the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is

preferred.

3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock

configuration is considered fixed for a given application. The user is advised to scan the same

clock option as to be used in the final system. The enable signals are supported in the scan

chain because the system logic can disable clock options in sleep modes, thereby disconnect-

ing the Oscillator pins from the scan path if not provided.

24.5.4

Scanning the Analog Comparator

The relevant Comparator signals regarding Boundary-scan are shown in Figure 24-7. The

Boundary-scan cell from Figure 24-8 is attached to each of these signals. The signals are

described in Table 24-4.

The Comparator need not be used for pure connectivity testing, since all analog inputs are

shared with a digital port pin as well.

Figure 24-7. Analog Comparator

BANDGAP

REFERENCE

ACBG

ACD

ACO

AC_IDLE

ACME

ADCEN

ADC MULTIPLEXER

OUTPUT

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Figure 24-8. General Boundary-scan cell Used for Signals for Comparator and ADC

To

Cell

EXTEST

From Digital Logic/

From Analog Ciruitry

0

1

To Analog Circuitry/

To Digital Logic

0

1

D

Q

D

G

Q

From

ClockDR

UpdateDR

Table 24-4. Boundary-scan Signals for the Analog Comparator

Direction as

Seen from the

Comparator

Recommended

Input when Not

in Use

Output Values when

Recommended Inputs

are Used

Signal

Name

Description

Turns off Analog

Comparator when

true

Depends upon µC code

being executed

AC_IDLE

ACO

input

1

Will become input

to µC code being

executed

Analog Comparator

Output

output

0

Uses output signal

from ADC mux when

true

Depends upon µC code

being executed

ACME

ACBG

input

0

Bandgap Reference

enable

Depends upon µC code

being executed

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24.5.5

Scanning the ADC

Figure 24-9 shows a block diagram of the ADC with all relevant control and observe signals. The

Boundary-scan cell from Figure 24-5 is attached to each of these signals. The ADC need not be

used for pure connectivity testing, since all analog inputs are shared with a digital port pin as

well.

Figure 24-9. Analog to Digital Converter

VCCREN

AREF

IREFEN

1.11V

ref

To Comparator

PASSEN

MUXEN_7

ADC_7

MUXEN_6

ADC_6

MUXEN_5

ADC_5

MUXEN_4

ADC_4

ADCBGEN

SCTEST

1.22V

ref

EXTCH

MUXEN_3

ADC_3

PRECH

AREF

DACOUT

COMP

MUXEN_2

ADC_2

MUXEN_1

ADC_1

MUXEN_0

ADC_0

DAC_9..0

ADCEN

10-bit DAC

+

-

COMP

ACTEN

+

NEGSEL_2

NEGSEL_1

NEGSEL_0

1x

-

HOLD

ADC_2

ADC_1

GNDEN

ST

ACLK

AMPEN

ADC_0

The signals are described briefly in Table 24-5.

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Table 24-5. Boundary-scan Signals for the ADC⁽¹⁾

Direction

as Seen

from the

ADC

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

Signal

Name

Description

COMP

Output

Comparator Output

0

Clock signal to

differential amplifier

implemented as Switch-

cap filters

ACLK

Input

0

Enable path from

differential amplifier to

the comparator

ACTEN

Input

0

Enable Band-gap

reference as negative

input to comparator

ADCBGEN

Power-on signal to the

ADC

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

DAC_3

DAC_2

DAC_1

DAC_0

Input

0

1

0

1

0

Power-on signal to the

differential amplifier

Bit 9 of digital value to

DAC

Bit 8 of digital value to

DAC

Bit 7 of digital value to

DAC

Bit 6 of digital value to

DAC

Bit 5 of digital value to

DAC

Bit 4 of digital value to

DAC

Bit 3 of digital value to

DAC

Bit 2 of digital value to

DAC

Bit 1 of digital value to

DAC

Bit 0 of digital value to

DAC

Connect ADC channels 0

- 3 to by-pass path

around differential

amplifier

EXTCH

GNDEN

Input

1

0

1

0

Ground the negative

input to comparator when

true

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Table 24-5. Boundary-scan Signals for the ADC⁽¹⁾(Continued)

Direction

as Seen

from the

ADC

Recommen-

ded Input

when not

in Use

Output Values when

Recommended Inputs

are Used, and CPU is

not Using the ADC

Signal

Name

Description

Sample & Hold signal.

Sample analog signal

when low. Hold signal

when high. If differential

amplifier is used, this

signal must go active

when ACLK is high.

HOLD

Input

1

Enables Band-gap

reference as AREF

signal to DAC

IREFEN

Input

0

MUXEN_7

MUXEN_6

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

Input

Input Mux bit 7

Input Mux bit 6

Input Mux bit 5

Input Mux bit 4

Input Mux bit 3

Input Mux bit 2

Input Mux bit 1

Input Mux bit 0

0

1

0

1

Input Mux for negative

input for differential

signal, bit 2

NEGSEL_2

NEGSEL_1

NEGSEL_0

Input

0

Input Mux for negative

input for differential

signal, bit 1

Input Mux for negative

input for differential

signal, bit 0

Enable pass-gate of

differential amplifier.

PASSEN

PRECH

Input

1

Precharge output latch of

comparator. (Active low)

Switch-cap TEST enable.

Output from differential

amplifier is sent out to

Port Pin having ADC_4

SCTEST

Input

0

Output of differential

amplifier will settle faster

if this signal is high first

two ACLK periods after

AMPEN goes high.

ST

Input

0

Selects Vcc as the ACC

reference voltage.

VCCREN

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Note:

1. Incorrect setting of the switches in Figure 24-9 will make signal contention and may damage

the part. There are several input choices to the S&H circuitry on the negative input of the out-

put comparator in Figure 24-9. Make sure only one path is selected from either one ADC pin,

Bandgap reference source, or Ground.

If the ADC is not to be used during scan, the recommended input values from Table 24-5 should

be used. The user is recommended not to use the Differential Amplifier during scan. Switch-Cap

based differential amplifier requires fast operation and accurate timing which is difficult to obtain

when used in a scan chain. Details concerning operations of the differential amplifier is therefore

not provided.

The AVR ADC is based on the analog circuitry shown in Figure 24-9 with a successive approxi-

mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is

usually to ensure that an applied analog voltage is measured within some limits. This can easily

be done without running a successive approximation algorithm: apply the lower limit on the digi-

tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit

on the digital DAC[9:0] lines, and verify the output from the comparator to be high.

The ADC need not be used for pure connectivity testing, since all analog inputs are shared with

a digital port pin as well.

When using the ADC, remember the following

• The port pin for the ADC channel in use must be configured to be an input with pull-up disabled

to avoid signal contention.

• In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when

enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before

controlling/observing any ADC signal, or perform a dummy conversion before using the first

result.

• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low

(Sample mode).

As an example, consider the task of verifying a 1.5V 5ꢀ input signal at ADC channel 3 when

the power supply is 5.0V and AREF is externally connected to V_CC

.

The lower limit is:

The upper limit is:

1024 ⋅ 1,5V ⋅ 0,95 ⁄ 5V = 291 = 0x123

1024 ⋅ 1,5V ⋅ 1,05 ⁄ 5V = 323 = 0x143

The recommended values from Table 24-5 are used unless other values are given in the algo-

rithm in Table 24-6. Only the DAC and port pin values of the Scan Chain are shown. The column

“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register

with the succeeding columns. The verification should be done on the data scanned out when

scanning in the data on the same row in the table.

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Table 24-6. Algorithm for Using the ADC

PA3.

Data

PA3.

Control

Pull-up_

Enable

Step

Actions

ADCEN

DAC

MUXEN

HOLD

PRECH

SAMPLE_P

RELOAD

1

0x200

0x08

1

0

2

3

4

5

EXTEST

1

0x200

0x123

0x08

0

1

0

Verify the

COMP bit

scanned out

to be 0

6

1

0x200

0x08

1

0

7

1

0x200

0x143

0x08

0

1

0

8

9

10

Verify the

COMP bit

scanned out

to be 1

11

1

0x200

0x08

1

0

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-

quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at

least five times the number of scan bits divided by the maximum hold time, t_hold,max

24.6 Boundary-scan Order

Table 24-7 shows the Scan order between TDI and TDO when the Boundary-scan chain is

selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The

scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in

the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the

analog circuits, which constitute the most significant bits of the scan chain regardless of which

physical pin they are connected to. In Figure 24-3, PXn. Data corresponds to FF0, PXn. Control

corresponds to FF1, and PXn. Pull-up_enable corresponds to FF2. Bit 4, 5, 6, and 7of Port F is

not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

Table 24-7. ATmega169P Boundary-scan Order

Bit Number

197

Signal Name

AC_IDLE

ACO

Module

196

Comparator

195

ACME

194

AINBG

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

Signal Name

COMP

Module

ACLK

ACTEN

PRIVATE_SIGNAL1⁽¹⁾

ADCBGEN

ADCEN

AMPEN

DAC_9

DAC_8

DAC_7

DAC_6

DAC_5

DAC_4

ADC

DAC_3

DAC_2

DAC_1

DAC_0

EXTCH

GNDEN

HOLD

IREFEN

MUXEN_7

MUXEN_6

MUXEN_5

MUXEN_4

MUXEN_3

MUXEN_2

MUXEN_1

MUXEN_0

NEGSEL_2

NEGSEL_1

NEGSEL_0

PASSEN

PRECH

ADC

ST

VCCREN

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

Signal Name

PE0.Data

Module

Port E

Port B

PE0.Control

PE0.Pull-up_Enable

PE1.Data

PE1.Control

PE1.Pull-up_Enable

PE2.Data

PE2.Control

PE2.Pull-up_Enable

PE3.Data

PE3.Control

PE3.Pull-up_Enable

PE4.Data

PE4.Control

PE4.Pull-up_Enable

PE5.Data

PE5.Control

PE5.Pull-up_Enable

PE6.Data

PE6.Control

PE6.Pull-up_Enable

PE7.Data

PE7.Control

PE7.Pull-up_Enable

PB0.Data

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

Signal Name

PB0.Control

PB0.Pull-up_Enable

PB1.Data

Module

PB1.Control

PB1.Pull-up_Enable

PB2.Data

PB2.Control

PB2.Pull-up_Enable

PB3.Data

PB3.Control

PB3.Pull-up_Enable

PB4.Data

Port B

PB4.Control

PB4.Pull-up_Enable

PB5.Data

PB5.Control

PB5.Pull-up_Enable

PB6.Data

PB6.Control

PB6.Pull-up_Enable

PB7.Data

PB7.Control

PB7.Pull-up_Enable

PG3.Data

PG3.Control

PG3.Pull-up_Enable

PG4.Data

Port G

PG4.Control

PG4.Pull-up_Enable

PG5

(Observe Only)

RSTT

Reset Logic

(Observe-only)

RSTHV

EXTCLKEN

OSCON

Enable signals for main Clock/Oscillators

98

RCOSCEN

97

OSC32EN

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

96

Signal Name

EXTCLK (XTAL1)

OSCCK

Module

95

Clock input and Oscillators for the main clock

(Observe-only)

94

RCCK

93

OSC32CK

92

PD0.Data

91

PD0.Control

90

PD0.Pull-up_Enable

PD1.Data

89

88

PD1.Control

87

PD1.Pull-up_Enable

PD2.Data

86

85

PD2.Control

84

PD2.Pull-up_Enable

PD3.Data

83

82

PD3.Control

81

PD3.Pull-up_Enable

PD4.Data

Port D

80

79

PD4.Control

78

PD4.Pull-up_Enable

PD5.Data

77

76

PD5.Control

75

PD5.Pull-up_Enable

PD6.Data

74

73

PD6.Control

72

PD6.Pull-up_Enable

PD7.Data

71

70

PD7.Control

69

PD7.Pull-up_Enable

PG0.Data

68

67

PG0.Control

PG0.Pull-up_Enable

PG1.Data

66

Port G

Port C

65

64

PG1.Control

PG1.Pull-up_Enable

PC0.Data

63

62

61

PC0.Control

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

60

Signal Name

PC0.Pull-up_Enable

PC1.Data

Module

59

58

PC1.Control

57

PC1.Pull-up_Enable

PC2.Data

56

55

PC2.Control

54

PC2.Pull-up_Enable

PC3.Data

53

52

PC3.Control

51

PC3.Pull-up_Enable

PC4.Data

50

Port C

49

PC4.Control

48

PC4.Pull-up_Enable

PC5.Data

47

46

PC5.Control

45

PC5.Pull-up_Enable

PC6.Data

44

43

PC6.Control

42

PC6.Pull-up_Enable

PC7.Data

41

40

PC7.Control

39

PC7.Pull-up_Enable

PG2.Data

38

37

PG2.Control

Port G

36

PG2.Pull-up_Enable

PA7.Data

35

34

PA7.Control

33

PA7.Pull-up_Enable

PA6.Data

32

31

PA6.Control

30

PA6.Pull-up_Enable

PA5.Data

Port A

29

28

PA5.Control

27

PA5.Pull-up_Enable

PA4.Data

26

25

PA4.Control

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Table 24-7. ATmega169P Boundary-scan Order (Continued)

Bit Number

Signal Name

PA4.Pull-up_Enable

PA3.Data

Module

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

PA3.Control

PA3.Pull-up_Enable

PA2.Data

PA2.Control

PA2.Pull-up_Enable

PA1.Data

Port A

PA1.Control

PA1.Pull-up_Enable

PA0.Data

PA0.Control

PA0.Pull-up_Enable

PF3.Data

PF3.Control

PF3.Pull-up_Enable

PF2.Data

8

7

PF2.Control

6

PF2.Pull-up_Enable

PF1.Data

Port F

5

4

PF1.Control

3

PF1.Pull-up_Enable

PF0.Data

2

1

PF0.Control

0

PF0.Pull-up_Enable

Note:

1. PRIVATE_SIGNAL1 should always be scanned in as zero.

24.7 Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in

a standard format used by automated test-generation software. The order and function of bits in

the Boundary-scan Data Register are included in this description. A BSDL file for ATmega169P

is available.

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24.8 Boundary-scan Related Register in I/O Memory

24.8.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for general MCU functions.

Bit

7

6

-

5

-

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

0x35 (0x55)

Read/Write

Initial Value

JTD

R/W

0

PUD

R/W

0

MCUCR

R

0

R

0

R

0

R

0

• Bit 7 – JTD: JTAG Interface Disable

When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this

bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of

the JTAG interface, a timed sequence must be followed when changing this bit: The application

software must write this bit to the desired value twice within four cycles to change its value. Note

that this bit must not be altered when using the On-chip Debug system.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to

one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.

24.8.2

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

6

–

5

–

4

3

2

BORF

1

0

0x34 (0x54)

Read/Write

Initial Value

JTRF

R/W

WDRF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R/W

See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

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25. Boot Loader Support – Read-While-Write Self-Programming

The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for

downloading and uploading program code by the MCU itself. This feature allows flexible applica-

tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The

Boot Loader program can use any available data interface and associated protocol to read code

and write (program) that code into the Flash memory, or read the code from the program mem-

ory. The program code within the Boot Loader section has the capability to write into the entire

Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it

can also erase itself from the code if the feature is not needed anymore. The size of the Boot

Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot

Lock bits which can be set independently. This gives the user a unique flexibility to select differ-

ent levels of protection.

25.1 Boot Loader Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page⁽¹⁾Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note:

1. A page is a section in the Flash consisting of several bytes (see Table 26-6 on page 298) used

during programming. The page organization does not affect normal operation.

25.2 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 25-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 25-6 on page 291 and Figure 25-2. These two sections can

have different level of protection since they have different sets of Lock bits.

25.2.1

25.2.2

Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the application Boot Lock bits

(Boot Lock bits 0), see Table 25-2 on page 283. The Application section can never store any

Boot Loader code since the SPM instruction is disabled when executed from the Application

section.

BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 25-3 on page 283.

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25.3 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is dependent on which address that is being programmed. In addition to the two

sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 25-

7 on page 292 and Figure 25-2 on page 282. The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted during the

entire operation.

Note that the user software can never read any code that is located inside the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

25.3.1

RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by a

call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown

state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-

tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy

bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read

as logical one as long as the RWW section is blocked for reading. After a programming is com-

pleted, the RWWSB must be cleared by software before reading code located in the RWW

section. See ”SPMCSR – Store Program Memory Control and Status Register” on page 293. for

details on how to clear RWWSB.

25.3.2

NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire Page Erase or Page Write operation.

Table 25-1. Read-While-Write Features

Which Section does the Z-pointer

Address During the Programming?

Which Section Can be

Read During Programming?

Is the

CPU Halted?

Read-While-Write

Supported?

RWW Section

NRWW Section

None

No

Yes

No

NRWW Section

Yes

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Figure 25-1. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

Z-pointer

Addresses NRWW

Section

Z-pointer

No Read-While-Write

(NRWW) Section

Addresses RWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 25-2. Memory Sections

Program Memory

BOOTSZ = '10'

Program Memory

BOOTSZ = '11'

0x0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

Application Flash Section

Boot Loader Flash Section

End Application

Start Boot Loader

Flashend

Start Boot Loader

Flashend

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

0x0000

Application Flash Section

End RWW, End Application

End RWW

Start NRWW, Start Boot Loader

Start NRWW

Application Flash Section

Boot Loader Flash Section

End Application

Boot Loader Flash Section

Start Boot Loader

Flashend

Note:

1. The parameters in the figure above are given in Table 25-6 on page 291.

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25.4 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives

the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a software update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

• Allow software update in the entire Flash.

See Table 25-2 and Table 25-3 for further details. The Boot Lock bits and general Lock bits can

be set in software and in Serial or Parallel Programming mode, but they can be cleared by a

Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the pro-

gramming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock

(Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted.

Table 25-2. Boot Lock Bit0 Protection Modes (Application Section)⁽¹⁾

BLB0 Mode

BLB02

BLB01

Protection

No restrictions for SPM or LPM accessing the Application

section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 25-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)⁽¹⁾

BLB1 Mode

BLB12

BLB11

Protection

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

3

4

0

1

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

Note:

1. “1” means unprogrammed, “0” means programmed

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25.5 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,

the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash

start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-

tion code is loaded, the program can start executing the application code. Note that the fuses

cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial or parallel programming interface.

Table 25-4. Boot Reset Fuse⁽¹⁾

BOOTRST

Reset Address

1

0

Reset Vector = Application Reset (address 0x0000)

Reset Vector = Boot Loader Reset (see Table 25-6 on page 291)

Note:

1. “1” means unprogrammed, “0” means programmed

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25.6 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 26-6 on page 298), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 25-3. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the Boot Loader software

addresses the same page in both the Page Erase and Page Write operation. Once a program-

ming operation is initiated, the address is latched and the Z-pointer can be used for other

operations.

The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.

The content of the Z-pointer is ignored and will have no effect on the operation. The LPM

instruction does also use the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 25-3. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 25-3 are listed in Table 25-8 on page 292.

2. PCPAGE and PCWORD are listed in Table 26-6 on page 298.

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25.7 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the same

page. See ”Boot Loader: Simple Assembly Code Example” on page 290 for an assembly code

example.

25.7.1

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

25.7.2

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

25.7.3

286

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

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The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

25.7.4

25.7.5

25.7.6

Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling

the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should

be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is

blocked for reading. How to move the interrupts is described in ”Interrupts” on page 56.

Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS

as described in ”Interrupts” on page 56, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

RWWSB by writing the RWWSRE. See ”Boot Loader: Simple Assembly Code Example” on

page 290 for an example.

25.7.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write

“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.

Bit

7

6

5

4

3

2

1

0

R0

1

BLB12

BLB11

BLB02

BLB01

LB2

LB1

See Table 25-2 and Table 25-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an

SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility

it is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When pro-

gramming the Lock bits the entire Flash can be read during the operation.

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25.7.8

25.7.9

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN

bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-

SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 26-5 on page 297 for a

detailed description and mapping of the Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table 26-4 on page 297 for detailed description and mapping of the Fuse High byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction

is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the

value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.

Refer to Table 26-3 on page 296 for detailed description and mapping of the Extended Fuse

byte.

Bit

Rd

7

6

5

4

3

2

1

0

–

EFB3

EFB2

EFB1

EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

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25.7.10 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock

bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V_CCreset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

25.7.11 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 25-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 25-5. SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

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25.7.12 Boot Loader: Simple Assembly Code Example

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

Write_page:

;PAGESIZEB is page size in BYTES, not words

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcrval, (1<<SPMEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

; execute Page Write

subi ZL, low(PAGESIZEB)

sbci ZH, high(PAGESIZEB)

;restore pointer

;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

Rdloop:

;restore pointer

lpm r0, Z+

ld

r1, Y+

cpse r0, r1

jmp Error

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sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

in

temp1, SPMCSR

sbrs temp1, RWWSB

ret

; If RWWSB is set, the RWW section is not ready yet

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in

temp1, SPMCSR

sbrc temp1, SPMEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

25.7.13 ATmega169P Boot Loader Parameters

In Table 25-6 through Table 25-8, the parameters used in the description of the Self-Program-

ming are given.

Table 25-6. Boot Size Configuration⁽¹⁾

Boot Reset

Address

Boot Loader

Flash

Section

End

Application

Section

(Start Boot

Loader

Section)

Application Flash

Section

128

words

1

0

1

0

2

4

0x0000 - 0x1F7F

0x0000 - 0x1EFF

0x0000 - 0x1DFF

0x0000 - 0x1BFF

0x1F80 - 0x1FFF

0x1F00 - 0x1FFF

0x1E00 - 0x1FFF

0x1C00 - 0x1FFF

0x1F7F

0x1EFF

0x1DFF

0x1BFF

0x1F80

0x1F00

0x1E00

0x1C00

256

words

1

512

words

0

8

1024

words

16

Note:

1. The different BOOTSZ Fuse configurations are shown in Figure 25-2

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Table 25-7. Read-While-Write Limit⁽¹⁾

Section

Pages

112

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

0x0000 - 0x1BFF

0x1C00 - 0x1FFF

16

Note:

1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page

280 and ”RWW – Read-While-Write Section” on page 280.

Table 25-8. Explanation of different variables used in Figure 25-3 and the mapping to the Z-

pointer⁽¹⁾

Corresponding

Variable

Z-value

Description

Most significant bit in the Program Counter. (The

Program Counter is 13 bits PC[12:0])

PCMSB

12

5

Most significant bit which is used to address the words

within one page (64 words in a page requires six bits PC

[5:0]).

PAGEMSB

Bit in Z-register that is mapped to PCMSB. Because Z0

is not used, the ZPCMSB equals PCMSB + 1.

ZPCMSB

ZPAGEMSB

PCPAGE

Z13

Z6

Bit in Z-register that is mapped to PAGEMSB. Because

Z0 is not used, the ZPAGEMSB equals PAGEMSB + 1.

Program Counter page address: Page select, for Page

Erase and Page Write

PC[12:6]

PC[5:0]

Z13:Z7

Program Counter word address: Word select, for filling

temporary buffer (must be zero during Page Write

operation)

PCWORD

Z6:Z1

Note:

1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See ”Addressing the Flash During Self-Programming” on page 285 for details about the use of

Z-pointer during Self-Programming.

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25.8 Register Description

25.8.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

Bit

7

SPMIE

R/W

0

6

5

–

4

RWWSRE

R/W

3

BLBSET

R/W

0

2

PGWRT

R/W

0

1

PGERS

R/W

0

SPMEN

R/W

0

RWWSB

SPMCSR

0x37 (0x57)

Read/Write

Initial Value

R

0

R

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN

bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega169P and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SPMEN will be cleared). Then, if

the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within

four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while

the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ-

ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will

be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles sets Boot Lock bits and general Lock bits, according to the data in R0. The data in R1 and

the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon

completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg-

ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See ”Reading the Fuse and Lock Bits from Software” on page 288 for

details.

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• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is

addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation if the NRWW section is addressed.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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26. Memory Programming

26.1 Program And Data Memory Lock Bits

The ATmega169P provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 26-2. The Lock bits can only be

erased to “1” with the Chip Erase command.

Table 26-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

–

Default Value

7

6

5

4

3

2

1

0

1 (unprogrammed)

–

BLB12

Boot Lock bit

Lock bit

BLB11

BLB02

BLB01

LB2

LB1

Lock bit

Note:

Table 26-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

1. “1” means unprogrammed, “0” means programmed

LB Mode

LB2

LB1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

Parallel and Serial Programming mode. The Fuse bits are

locked in both Serial and Parallel Programming mode.⁽¹⁾

2

1

0

Further programming and verification of the Flash and EEPROM

is disabled in Parallel and Serial Programming mode. The Boot

Lock bits and Fuse bits are locked in both Serial and Parallel

Programming mode.⁽¹⁾

3

BLB0 Mode

BLB02

BLB01

No restrictions for SPM or LPM accessing the Application

section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

3

0

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

4

0

1

BLB1 Mode

BLB12

BLB11

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Table 26-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾(Continued)

Memory Lock Bits

Protection Type

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

3

0

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

4

0

1

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

26.2 Fuse Bits

The ATmega169P has three Fuse bytes. Table 26-3 - Table 26-5 describe briefly the functional-

ity of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as

logical zero, “0”, if they are programmed.

Table 26-3. Extended Fuse Byte

Fuse Low Byte

Bit No

Description

Default Value

–

7

6

5

4

3

2

1

0

–

1

–

1

–

1

–

1

BODLEVEL2⁽¹⁾

BODLEVEL1⁽¹⁾

BODLEVEL0⁽¹⁾

RSTDISBL⁽²⁾

Brown-out Detector trigger level

External Reset Disable

1 (unprogrammed)

Notes: 1. See Table 9-2 on page 49 for BODLEVEL Fuse decoding.

2. Port G, PG5 is input only. Pull-up is always on. See ”Alternate Functions of Port G” on page

85.

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Table 26-4. Fuse High Byte

Fuse High Byte

OCDEN⁽⁴⁾

Bit No

Description

Enable OCD

Enable JTAG

Default Value

7

6

1 (unprogrammed, OCD disabled)

0 (programmed, JTAG enabled)

JTAGEN⁽⁵⁾

Enable Serial Program and Data

Downloading

0 (programmed, SPI prog.

enabled)

SPIEN⁽¹⁾

WDTON⁽³⁾

EESAVE

5

4

3

Watchdog Timer always on

1 (unprogrammed)

EEPROM memory is preserved

through the Chip Erase

1 (unprogrammed, EEPROM not

preserved)

Select Boot Size (see Table 25-6

for details)

BOOTSZ1

2

0 (programmed)⁽²⁾

Select Boot Size (see Table 25-6

for details)

BOOTSZ0

BOOTRST

1

0

0 (programmed)⁽²⁾

1 (unprogrammed)

Select Reset Vector

Note:

1. The SPIEN Fuse is not accessible in serial programming mode.

2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 25-6 on page 291

for details.

3. See ”WDTCR – Watchdog Timer Control Register” on page 54 for details.

4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits

and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to

be running in all sleep modes. This may increase the power consumption.

5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This

to avoid static current at the TDO pin in the JTAG interface.

Table 26-5. Fuse Low Byte

Fuse Low Byte

CKDIV8⁽⁴⁾

CKOUT⁽³⁾

SUT1

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

Clock output

0 (programmed)

1 (unprogrammed)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

0 (programmed)⁽²⁾

Select start-up time

Select Clock source

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Note:

1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 9-1 on page 47 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 7-9 on

page 34 for details.

3. The CKOUT Fuse allow the system clock to be output on PORTE7. See ”Clock Output Buffer”

on page 36 for details.

4. See ”System Clock Prescaler” on page 36 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

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26.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

26.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space.

For the ATmega169P the signature bytes are:

1. 0x000: 0x1E (indicates manufactured by Atmel).

2. 0x001: 0x94 (indicates 16KB Flash memory).

3. 0x002: 0x05 (indicates ATmega169P device when 0x001 is 0x94).

26.4 Calibration Byte

The ATmega169P has a byte calibration value for the internal RC Oscillator. This byte resides in

the high byte of address 0x000 in the signature address space. During reset, this byte is auto-

matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC

Oscillator.

26.5 Page Size

Table 26-6. No. of Words in a Page and No. of Pages in the Flash

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

8K words (16K bytes)

64 words

PC[5:0]

128

PC[12:6]

12

Table 26-7. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM Size

Page Size

PCWORD

No. of Pages

PCPAGE

EEAMSB

512 bytes

4 bytes

EEA[1:0]

128

EEA[8:2]

8

26.6 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATmega169P. Pulses are assumed to be

at least 250 ns unless otherwise noted.

26.6.1

Signal Names

In this section, some pins of the ATmega169P are referenced by signal names describing their

functionality during parallel programming, see Figure 26-1 and Table 26-8. Pins not described in

the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 26-10.

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When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 26-11.

Figure 26-1. Parallel Programming

+5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VCC

+5V

WR

AVCC

BS1

PB7 - PB0

DATA

XA0

XA1

PAGEL

+12 V

BS2

RESET

PA0

XTAL1

GND

Table 26-8. Pin Name Mapping

Signal Name

in Programming Mode

Pin Name

I/O Function

0: Device is busy programming, 1: Device is ready for

new command.

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (Active low).

Write Pulse (Active low).

WR

Byte Select 1 (“0” selects low byte, “1” selects high

byte).

BS1

PD4

I

XA0

XA1

PD5

PD6

PD7

I

XTAL Action Bit 0

XTAL Action Bit 1

PAGEL

Program Memory and EEPROM data Page Load.

Byte Select 2 (“0” selects low byte, “1” selects 2’nd high

byte).

BS2

PA0

I

DATA

PB7-0

I/O Bi-directional Data bus (Output when OE is low).

Table 26-9. Pin Values Used to Enter Programming Mode

PAGEL

XA1

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

XA0

BS1

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Table 26-10. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

Load Flash or EEPROM Address (High or low address byte determined by

BS1).

0

1

0

1

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 26-11. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

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26.7 Parallel Programming

26.7.1

26.7.2

26.7.3

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V between V_CCand GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 26-9 on page 299 to “0000” and wait at least 100

ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V

has been applied to RESET, will cause the device to fail entering programming mode.

5. Wait at least 50 µs before sending a new command.

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Note:

1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

26.7.4

Programming the Flash

The Flash is organized in pages, see Table 26-6 on page 298. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

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A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 26-3 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address

the pages within the FLASH. This is illustrated in Figure 26-2 on page 303. Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)

in the address low byte are used to address the page when performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY

goes low.

2. Wait until RDY/BSY goes high (See Figure 26-3 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

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J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

reset.

Figure 26-2. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PROGRAM

COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 26-6 on page 298.

Figure 26-3. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW DATA LOW

DATA HIGH

ADDR. HIGH

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

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26.7.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 26-7 on page 298. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to ”Programming the Flash” on page 301 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure 26-4 for

signal waveforms).

Figure 26-4. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

26.7.6

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on

page 301 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

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26.7.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash”

on page 301 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

26.7.8

26.7.9

Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash”

on page 301 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the

Flash” on page 301 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high fuse byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

26.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to ”Programming the

Flash” on page 301 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended fuse byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

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Figure 26-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

26.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on

page 301 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

26.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash”

on page 301 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

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Figure 26-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

0

DATA

BS2

BS1

Fuse High Byte

1

BS2

26.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on

page 301 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

26.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on

page 301 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

26.7.15 Parallel Programming Characteristics

Figure 26-7. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBXt_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

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Figure 26-8. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 26-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to load-

ing operation.

Figure 26-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BVDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 26-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-

ing operation.

Table 26-12. Parallel Programming Characteristics, V_CC= 5V 10ꢀ

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

µA

ns

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

67

200

150

67

ns

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

ns

0

ns

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Table 26-12. Parallel Programming Characteristics, V_CC= 5V 10ꢀ (Continued)

Symbol

t_XLPH

Parameter

Min

0

Typ

Max

Units

ns

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

BS1 Valid to WR Low

t_PLXH

150

67

150

67

150

0

ns

t_BVPH

t_PHPL

ns

t_PLBX

ns

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

t_XLOL

ns

WR Pulse Width Low

ns

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

XTAL1 Low to OE Low

1

4.5

9

µs

ms

ns

3.7

7.5

0

t_BVDV

t_OLDV

t_OHDZ

BS1 Valid to DATA valid

OE Low to DATA Valid

0

250

ns

OE High to DATA Tri-stated

ns

Notes: 1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. t_{WLRH_CE}is valid for the Chip Erase command.

26.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 26-13 on page 309, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

26.8.1

Serial Programming Pin Mapping

Table 26-13. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB2

PB3

PB1

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

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Figure 26-10. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

+1.8 - 5.5V⁽²⁾

MOSI

MISO

AVCC

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V_CC- 0.3V < AVCC < V_CC+ 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

26.8.2

Serial Programming Algorithm

When writing serial data to the ATmega169P, data is clocked on the rising edge of SCK.

When reading data from the ATmega169P, data is clocked on the falling edge of SCK. See Fig-

ure 26-11 for timing details.

To program and verify the ATmega169P in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 26-15):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The page size is found in Table 26-6 on

page 298. The memory page is loaded one byte at a time by supplying the 6 LSB of the

address and data together with the Load Program Memory Page instruction. To ensure

correct loading of the page, the data low byte must be loaded before data high byte is

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applied for a given address. The Program Memory Page is stored by loading the Write

Program Memory Page instruction with the 7 MSB of the address. If polling (RDY/BSY) is

not used, the user must wait at least t_{WD_FLASH}before issuing the next page. (See Table

26-14.) Accessing the serial programming interface before the Flash write operation

completes can result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling (RDY/BSY) is not used, the

user must wait at least t_{WD_EEPROM}before issuing the next byte (See Table 26-14). In a

chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the Load

EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading

the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using

EEPROM page access only byte locations loaded with the Load EEPROM Memory Page

instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is

not used, the user must wait at least t_{WD_EEPROM}before issuing the next page (See Table

26-14). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off

Table 26-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FUSE}

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

4.5 ms

9.0 ms

Figure 26-11. Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

(MISO)

MSB

SERIAL CLOCK INPUT

(SCK)

SAMPLE

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26.8.3

Serial Programming Instruction set

Table 26-15 and Figure 26-12 on page 313 describes the Instruction set.

Table 26-15. Serial Programming Instruction Set

Instruction Format

Instruction/Operation

Byte 1

$AC

Byte 2

Byte 3

$00

Byte4

$00

Programming Enable

$53

$80

$00

Chip Erase (Program Memory/EEPROM)

Poll RDY/BSY

$AC

$00

$F0

$00

data byte out

Load Instructions

Load Extended Address byte⁽¹⁾

Load Program Memory Page, High byte

Load Program Memory Page, Low byte

Load EEPROM Memory Page (page access)

Read Instructions

$4D

$48

$40

$C1

$00

Extended adr

adr LSB

$00

high data byte in

low data byte in

data byte in

adr LSB

0000 00aa

Read Program Memory, High byte

Read Program Memory, Low byte

Read EEPROM Memory

Read Lock bits

$28

$20

$A0

$58

$30

$50

$58

$50

$38

adr MSB

0000 00aa

$00

adr LSB

aaaa aaaa

$00

high data byte out

low data byte out

data byte out

Read Signature Byte

$00

0000 00aa

$00

Read Fuse bits

$00

Read Fuse High bits

$08

$00

Read Extended Fuse Bits

Read Calibration Byte

$08

$00

Write Instructions

Write Program Memory Page

Write EEPROM Memory

Write EEPROM Memory Page (page access)

Write Lock bits

$4C

$C0

$C2

$AC

adr MSB

0000 00aa

$E0

adr LSB

aaaa aaaa

aaaa aa00

$00

data byte in

$00

data byte in

Write Fuse bits

$A0

$00

Write Fuse High bits

$A8

$00

Write Extended Fuse Bits

$A4

$00

Notes: 1. Not all instructions are applicable for all parts

2. a = address

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and

Page size.

6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

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Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 26-12.

Figure 26-12. Serial Programming Instruction example

Serial Programming Instruction

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Write Program Memory Page/

Write EEPROM Memory Page

Byte 1

Byte 2

Byte 3

Byte 4

Byte 1

Byte 2

Byte 3

Byte 4

Adr MSB

Adr LSB

Adr MSB

Adr LSB

Bit 15 B

0

Bit 15 B

0

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

26.8.4

SPI Serial Programming Characteristics

For characteristics of the SPI module see “SPI Timing Characteristics” on page 331.

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26.9 Programming via the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,

TMS, TDI, and TDO. Control of the reset and clock pins is not required.

To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is

default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.

Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be

cleared after two chip clocks, and the JTAG pins are available for programming. This provides a

means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-

tem Programming via the JTAG interface. Note that this technique can not be used when using

the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-

icated for this purpose.

During programming the clock frequency of the TCK Input must be less than the maximum fre-

quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input

into a sufficiently low frequency.

As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.

26.9.1

Programming Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions

useful for programming are listed below.

The OPCODE for each instruction is shown behind the instruction name in hex format. The text

describes which Data Register is selected as path between TDI and TDO for each instruction.

The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be

used as an idle state between JTAG sequences. The state machine sequence for changing the

instruction word is shown in Figure 26-13.

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Figure 26-13. State Machine Sequence for Changing the Instruction Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

Capture-IR

0

1

Capture-DR

0

Shift-DR

0

Shift-IR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-IR

1

Pause-DR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

26.9.2

AVR_RESET (0xC)

The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking

the device out from the Reset mode. The TAP controller is not reset by this instruction. The one

bit Reset Register is selected as Data Register. Note that the reset will be active as long as there

is a logic “one” in the Reset Chain. The output from this chain is not latched.

The active states are:

• Shift-DR: The Reset Register is shifted by the TCK input.

26.9.3

PROG_ENABLE (0x4)

The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-

bit Programming Enable Register is selected as Data Register. The active states are the

following:

• Shift-DR: The programming enable signature is shifted into the Data Register.

• Update-DR: The programming enable signature is compared to the correct value, and

Programming mode is entered if the signature is valid.

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26.9.4

PROG_COMMANDS (0x5)

The AVR specific public JTAG instruction for entering programming commands via the JTAG

port. The 15-bit Programming Command Register is selected as Data Register. The active

states are the following:

• Capture-DR: The result of the previous command is loaded into the Data Register.

• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous

command and shifting in the new command.

• Update-DR: The programming command is applied to the Flash inputs

• Run-Test/Idle: One clock cycle is generated, executing the applied command (not always

required, see Table 26-16 below).

26.9.5

PROG_PAGELOAD (0x6)

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

• Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A

write sequence is initiated that within 11 TCK cycles loads the content of the temporary

register into the Flash page buffer. The AVR automatically alternates between writing the low

and the high byte for each new Update-DR state, starting with the low byte for the first Update-

DR encountered after entering the PROG_PAGELOAD command. The Program Counter is

pre-incremented before writing the low byte, except for the first written byte. This ensures that

the first data is written to the address set up by PROG_COMMANDS, and loading the last

location in the page buffer does not make the program counter increment into the next page.

26.9.6

PROG_PAGEREAD (0x7)

The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.

An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs

of the Programming Command Register. The active states are the following:

• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte

Register. The AVR automatically alternates between reading the low and the high byte for each

new Capture-DR state, starting with the low byte for the first Capture-DR encountered after

entering the PROG_PAGEREAD command. The Program Counter is post-incremented after

reading each high byte, including the first read byte. This ensures that the first data is captured

from the first address set up by PROG_COMMANDS, and reading the last location in the page

makes the program counter increment into the next page.

• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.

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26.9.7

Data Registers

The Data Registers are selected by the JTAG instruction registers described in section ”Pro-

gramming Specific JTAG Instructions” on page 314. The Data Registers relevant for

programming operations are:

• Reset Register

• Programming Enable Register

• Programming Command Register

• Flash Data Byte Register

26.9.8

Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is

required to reset the part before entering Programming mode.

A high value in the Reset Register corresponds to pulling the external reset low. The part is reset

as long as there is a high value present in the Reset Register. Depending on the Fuse settings

for the clock options, the part will remain reset for a Reset Time-out period (refer to ”Clock

Sources” on page 30) after releasing the Reset Register. The output from this Data Register is

not latched, so the reset will take place immediately, as shown in Figure 24-2 on page 259.

26.9.9

Programming Enable Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared

to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con-

tents of the register is equal to the programming enable signature, programming via the JTAG

port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when

leaving Programming mode.

Figure 26-14. Programming Enable Register

TDI

0xA370

D

Q

A

T

A

Programming Enable

=

ClockDR & PROG_ENABLE

TDO

26.9.10 Programming Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in

programming commands, and to serially shift out the result of the previous command, if any. The

JTAG Programming Instruction Set is shown in Table 26-16. The state sequence when shifting

in the programming commands is illustrated in Figure 26-16.

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Figure 26-15. Programming Command Register

TDI

S

T

R

O

B

E

S

Flash

EEPROM

Fuses

A

D

R

E

S

/

Lock Bits

D

A

T

A

TDO

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Table 26-16. JTAG Programming Instruction

Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

Instruction

TDI Sequence

TDO Sequence

Notes

0100011_10000000

0110001_10000000

0110011_10000000

xxxxxxx_xxxxxxxx

1a. Chip Erase

1b. Poll for Chip Erase Complete

2a. Enter Flash Write

0110011_10000000

0100011_00010000

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(9)

2b. Load Address High Byte

2c. Load Address Low Byte

2d. Load Data Low Byte

2e. Load Data High Byte

0010111_iiiiiiii

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

2f. Latch Data

(1)

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

2g. Write Flash Page

2h. Poll for Page Write Complete

3a. Enter Flash Read

0110111_00000000

0100011_00000010

0000111_aaaaaaaa

0000011_bbbbbbbb

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(9)

3b. Load Address High Byte

3c. Load Address Low Byte

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

3d. Read Data Low and High Byte

Low byte

High byte

4a. Enter EEPROM Write

4b. Load Address High Byte

4c. Load Address Low Byte

4d. Load Data Byte

0100011_00010001

0000111_aaaaaaaa

0000011_bbbbbbbb

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(9)

0110111_00000000

1110111_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

4e. Latch Data

(1)

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

4f. Write EEPROM Page

4g. Poll for Page Write Complete

5a. Enter EEPROM Read

0110011_00000000

0100011_00000011

0000111_aaaaaaaa

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(9)

5b. Load Address High Byte

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Table 26-16. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x

Instruction

TDI Sequence

TDO Sequence

Notes

5c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

0110011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

5d. Read Data Byte

6a. Enter Fuse Write

0100011_01000000

xxxxxxx_xxxxxxxx

6b. Load Data Low Byte⁽⁶⁾

0010011_iiiiiiii

(3)

(1)

0111011_00000000

0111001_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

6c. Write Fuse Extended Byte

6d. Poll for Fuse Write Complete

6e. Load Data Low Byte⁽⁷⁾

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110111_00000000

0110101_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

6f. Write Fuse High Byte

(1)

6g. Poll for Fuse Write Complete

6h. Load Data Low Byte⁽⁷⁾

0110111_00000000

xxxxxox_xxxxxxxx

(2)

(3)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

6i. Write Fuse Low Byte

(1)

6j. Poll for Fuse Write Complete

7a. Enter Lock Bit Write

7b. Load Data Byte⁽⁹⁾

0110011_00000000

0100011_00100000

0010011_11iiiiii

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

(2)

(4)

0110011_00000000

0110001_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

7c. Write Lock Bits

(1)

(2)

7d. Poll for Lock Bit Write complete

8a. Enter Fuse/Lock Bit Read

0110011_00000000

0100011_00000100

xxxxxox_xxxxxxxx

xxxxxxx_xxxxxxxx

0111010_00000000

0111011_00000000

xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte⁽⁶⁾

8c. Read Fuse High Byte⁽⁷⁾

8d. Read Fuse Low Byte⁽⁸⁾

8e. Read Lock Bits⁽⁹⁾

xxxxxxx_oooooooo

0111110_00000000

0111111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

(5)

xxxxxxx_xxoooooo

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Table 26-16. JTAG Programming Instruction (Continued)

Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x

Instruction

TDI Sequence

TDO Sequence

Notes

0111010_00000000

0111110_00000000

0110010_00000000

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

xxxxxxx_oooooooo

(5)

Fuse Ext. byte

Fuse High byte

Fuse Low byte

Lock bits

8f. Read Fuses and Lock Bits

9a. Enter Signature Byte Read

9b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

0110010_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

9c. Read Signature Byte

xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

10b. Load Address Byte

0100011_00001000

xxxxxxx_xxxxxxxx

0000011_bbbbbbbb

0110110_00000000

0110111_00000000

xxxxxxx_xxxxxxxx

10c. Read Calibration Byte

xxxxxxx_oooooooo

0100011_00000000

0110011_00000000

xxxxxxx_xxxxxxxx

11a. Load No Operation Command

Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is

normally the case).

2. Repeat until o = “1”.

3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse.

4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged.

5. “0” = programmed, “1” = unprogrammed.

6. The bit mapping for Fuses Extended byte is listed in Table 26-3 on page 296

7. The bit mapping for Fuses High byte is listed in Table 26-4 on page 297

8. The bit mapping for Fuses Low byte is listed in Table 26-5 on page 297

9. The bit mapping for Lock bits byte is listed in Table 26-1 on page 295

10. Address bits exceeding PCMSB and EEAMSB (Table 26-6 and Table 26-7) are don’t care

11. All TDI and TDO sequences are represented by binary digits (0b...).

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Figure 26-16. State Machine Sequence for Changing/Reading the Data Word

1

Test-Logic-Reset

0

1

0

Run-Test/Idle

Select-DR Scan

Select-IR Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

1

Shift-DR

0

1

Exit1-DR

0

1

Exit1-IR

0

Pause-DR

1

0

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

26.9.11 Flash Data Byte Register

The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer

before executing Page Write, or to read out/verify the content of the Flash. A state machine sets

up the control signals to the Flash and senses the strobe signals from the Flash, thus only the

data words need to be shifted in/out.

The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg-

ister. During page load, the Update-DR state copies the content of the scan chain over to the

temporary register and initiates a write sequence that within 11 TCK cycles loads the content of

the temporary register into the Flash page buffer. The AVR automatically alternates between

writing the low and the high byte for each new Update-DR state, starting with the low byte for the

first Update-DR encountered after entering the PROG_PAGELOAD command. The Program

Counter is pre-incremented before writing the low byte, except for the first written byte. This

ensures that the first data is written to the address set up by PROG_COMMANDS, and loading

the last location in the page buffer does not make the Program Counter increment into the next

page.

During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte

Register during the Capture-DR state. The AVR automatically alternates between reading the

low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap-

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ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is

post-incremented after reading each high byte, including the first read byte. This ensures that

the first data is captured from the first address set up by PROG_COMMANDS, and reading the

last location in the page makes the program counter increment into the next page.

Figure 26-17. Flash Data Byte Register

STROBES

State

Machine

TDI

ADDRESS

Flash

EEPROM

Fuses

Lock Bits

D

A

T

A

TDO

The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal

operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate

through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis-

ter with sufficient number of clock pulses to complete its operation transparently for the user.

However, if too few bits are shifted between each Update-DR state during page load, the TAP

controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at

least 11 TCK cycles between each Update-DR state.

26.9.12 Programming Algorithm

All references below of type “1a”, “1b”, and so on, refer to Table 26-16 on page 319.

26.9.13 Entering Programming Mode

1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program-

ming Enable Register.

26.9.14 Leaving Programming Mode

1. Enter JTAG instruction PROG_COMMANDS.

2. Disable all programming instructions by using no operation instruction 11a.

3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program-

ming Enable Register.

4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

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26.9.15 Performing Chip Erase

1. Enter JTAG instruction PROG_COMMANDS.

2. Start Chip Erase using programming instruction 1a.

3. Poll for Chip Erase complete using programming instruction 1b, or wait for t_{WLRH_CE}(refer

to Table 26-12 on page 308).

26.9.16 Programming the Flash

Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase”

on page 324.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load address High byte using programming instruction 2b.

4. Load address Low byte using programming instruction 2c.

5. Load data using programming instructions 2d, 2e and 2f.

6. Repeat steps 4 and 5 for all instruction words in the page.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer to

Table 26-12 on page 308).

9. Repeat steps 3 to 7 until all data have been programmed.

A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash write using programming instruction 2a.

3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to

Table 26-6 on page 298) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGELOAD.

5. Load the entire page by shifting in all instruction words in the page byte-by-byte, starting

with the LSB of the first instruction in the page and ending with the MSB of the last

instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte Reg-

ister into the Flash page location and to auto-increment the Program Counter before

each new word.

6. Enter JTAG instruction PROG_COMMANDS.

7. Write the page using programming instruction 2g.

8. Poll for Flash write complete using programming instruction 2h, or wait for t_WLRH(refer to

Table 26-12 on page 308).

9. Repeat steps 3 to 8 until all data have been programmed.

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26.9.17 Reading the Flash

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load address using programming instructions 3b and 3c.

4. Read data using programming instruction 3d.

5. Repeat steps 3 and 4 until all data have been read.

A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Flash read using programming instruction 3a.

3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to

Table 26-6 on page 298) is used to address within one page and must be written as 0.

4. Enter JTAG instruction PROG_PAGEREAD.

5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash),

starting with the LSB of the first instruction in the page (Flash) and ending with the MSB

of the last instruction in the page (Flash). The Capture-DR state both captures the data

from the Flash, and also auto-increments the program counter after each word is read.

Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is

shifted out contains valid data.

6. Enter JTAG instruction PROG_COMMANDS.

7. Repeat steps 3 to 6 until all data have been read.

26.9.18 Programming the EEPROM

Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip

Erase” on page 324.

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM write using programming instruction 4a.

3. Load address High byte using programming instruction 4b.

4. Load address Low byte using programming instruction 4c.

5. Load data using programming instructions 4d and 4e.

6. Repeat steps 4 and 5 for all data bytes in the page.

7. Write the data using programming instruction 4f.

8. Poll for EEPROM write complete using programming instruction 4g, or wait for t_WLRH

(refer to Table 26-12 on page 308).

9. Repeat steps 3 to 8 until all data have been programmed.

Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM.

26.9.19 Reading the EEPROM

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable EEPROM read using programming instruction 5a.

3. Load address using programming instructions 5b and 5c.

4. Read data using programming instruction 5d.

5. Repeat steps 3 and 4 until all data have been read.

Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.

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26.9.20 Programming the Fuses

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse write using programming instruction 6a.

3. Load data high byte using programming instructions 6b. A bit value of “0” will program the

corresponding fuse, a “1” will unprogram the fuse.

4. Write Fuse High byte using programming instruction 6c.

5. Poll for Fuse write complete using programming instruction 6d, or wait for t_WLRH(refer to

Table 26-12 on page 308).

6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1”

will unprogram the fuse.

7. Write Fuse low byte using programming instruction 6f.

8. Poll for Fuse write complete using programming instruction 6g, or wait for t_WLRH(refer to

Table 26-12 on page 308).

26.9.21 Programming the Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Lock bit write using programming instruction 7a.

3. Load data using programming instructions 7b. A bit value of “0” will program the corre-

sponding lock bit, a “1” will leave the lock bit unchanged.

4. Write Lock bits using programming instruction 7c.

5. Poll for Lock bit write complete using programming instruction 7d, or wait for t_WLRH(refer

to Table 26-12 on page 308).

26.9.22 Reading the Fuses and Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Fuse/Lock bit read using programming instruction 8a.

3. To read all Fuses and Lock bits, use programming instruction 8e.

To only read Fuse High byte, use programming instruction 8b.

To only read Fuse Low byte, use programming instruction 8c.

To only read Lock bits, use programming instruction 8d.

26.9.23 Reading the Signature Bytes

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Signature byte read using programming instruction 9a.

3. Load address 0x00 using programming instruction 9b.

4. Read first signature byte using programming instruction 9c.

5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third

signature bytes, respectively.

26.9.24 Reading the Calibration Byte

1. Enter JTAG instruction PROG_COMMANDS.

2. Enable Calibration byte read using programming instruction 10a.

3. Load address 0x00 using programming instruction 10b.

4. Read the calibration byte using programming instruction 10c.

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27. Electrical Characteristics

27.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 400.0 mA

27.2 DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

(1)

Input Low Voltage except

XTAL1 and RESET pins

V

_CC= 1.8V - 2.4V

-0.5

0.2V_CC

0.3V_CC

V_IL

V

V_CC= 2.4V - 5.5V

(2)

Input High Voltage except

XTAL1 and RESET pins

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

V_CC+ 0.5

V_IH

V

(2)

Input Low Voltage

XTAL1 pins

(1)

V_IL1

V_IH1

V_IL2

V_IH2

V_OL

V_OL1

V_OH

V_OH1

I_IL

V

_CC= 1.8V - 5.5V

-0.5

0.1V_CC

(2)

Input High Voltage,

XTAL1 pin

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.8V_CC

0.7V_CC

V_CC+ 0.5

V

(1)

0.1V_CC

Input Low Voltage,

RESET pins

V_CC= 1.8V - 5.5V

-0.5

V

(1)

0.2V_CC

Input High Voltage,

RESET pins

(2)

V_CC= 1.8V - 5.5V

0.9V_CC

V_CC+ 0.5

V

Output Low Voltage⁽³⁾

Port A, C, D, E, F, G

,

I_OL= 10 mA, V_CC= 5V

I_OL= 5 mA, V_CC= 3V

0.7

0.5

V

Output Low Voltage⁽³⁾

Port B

I_OL= 20 mA, V_CC= 5V

0.7

0.5

V

I

_OL= 10 mA, V_CC= 3V

Output High Voltage⁽⁴⁾

Port A, C, D, E, F, G

,

I_OH= -10 mA, V_CC= 5V

I_OH= -5 mA, V_CC= 3V

4.2

2.3

V

Output High Voltage⁽⁴⁾

Port B

I_OH= -20 mA, V_CC= 5V

I_OH= -10 mA, V_CC= 3V

4.2

2.3

V

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin low

(absolute value)

1

µA

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin high

(absolute value)

I_IH

R_RST

R_PU

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

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T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

0.44

2.5

Units

mA

Active 1 MHz, V_CC= 2V

Active 4 MHz, V_CC= 3V

Active 8 MHz, V_CC= 5V

Idle 1 MHz, V_CC= 2V

Idle 4 MHz, V_CC= 3V

Idle 8 MHz, V_CC= 5V

9.5

Power Supply Current⁽⁵⁾

0.2

0.8

3.3

I_CC

32 kHz TOSC enabled,

V_CC= 1.8V

0.55

0.8

1.6

2.6

µA

Power-save mode⁽⁶⁾

Power-down mode⁽⁶⁾

32 kHz TOSC enabled,

V_CC= 3V

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

6

10

2

µA

0.2

V_CC= 5V

Analog Comparator

Input Offset Voltage

V_ACIO

I_ACLK

t_ACPD

<10

40

50

mV

nA

ns

V_in= V_CC/2

Analog Comparator

Input Leakage Current

V_CC= 5V

V_in= V_CC/2

-50

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750

500

Note:

1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V for Port B and 10 mA

at V_CC= 5V, 5 mA at V_CC= 3V for all other ports) under steady state conditions (non-transient), the following must be

observed:

TQFP and QFN/MLF Package:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.

3] The sum of all IOL, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.

4] The sum of all IOL, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.

5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V for Port B and 10mA

at V_CC= 5V, 5 mA at V_CC= 3V for all other ports) under steady state conditions (non-transient), the following must be

observed:

TQFP and QFN/MLF Package:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0 - A7, C4 - C7, G2 should not exceed 100 mA.

3] The sum of all IOH, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100 mA.

4] The sum of all IOH, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100 mA.

5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

5. All bits set in the “Power Reduction Register” on page 34.

6. Typical values at 25 °C. Maximum values are characterized values and not test limits in production.

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27.3 External Clock Drive Waveforms

Figure 27-1. External Clock Drive Waveforms

V

IH1

V

IL1

27.4 External Clock Drive

Table 27-1. External Clock Drive

V_CC=1.8-5.5V

V_CC=2.7-5.5V

V_CC=4.5-5.5V

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

Oscillator

Frequency

1/t_CLCL

0

1

0

8

0

16

MHz

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

Clock Period

High Time

Low Time

Rise Time

Fall Time

1000

400

125

50

62.5

25

ns

µs

400

50

25

2.0

1.6

0.5

Change in period

from one clock

cycle to the next

∆t_CLCL

2

ꢀ

27.5 Maximum Speed vs. V_CC

Maximum frequency is depending on V_CC.As shown in Figure 27-2 and Figure 27-3, the Maxi-

mum Frequency vs. V_CCcurve is linear between 1.8V < V_CC< 4.5V. To calculate the maximum

frequency at a given voltage in this interval, use this equation:

Frequency = a • (V – Vx) + Fy

To calculate required voltage for a given frequency, use this equation::

Voltage = b • (F – Fy) + Vx

Table 27-2. Constants used to calculate maximum speed vs. V_CC

Voltage and Frequency range

2.7 < V_CC< 4.5 or 8 < Frq < 16

1.8 < V_CC< 2.7 or 4 < Frq < 8

a

b

Vx

2.7

1.8

Fy

8

8/1.8

1.8/8

4

8

1,8

-------

At 3 Volt, this gives:Frequency =

• (3 – 2,7) + 8 = 9,33

Thus, when V_CC= 3V, maximum frequency will be 9.33 MHz.

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1,8

8

-------

At 6 MHz this gives:Voltage =

• (6 – 4) + 1,8 = 2,25

Thus, a maximum frequency of 6 MHz requires V_CC= 2.25V.

Figure 27-2. Maximum Frequency vs. V_CC, ATmega169PV

8 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 27-3. Maximum Frequency vs. V_CC, ATmega169P

16 MHz

8 MHz

Safe Operating Area

2.7V

4.5V

5.5V

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27.6 SPI Timing Characteristics

See Figure 27-4 and Figure 27-5 for details.

Table 27-3. SPI Timing Parameters

Description

SCK period

SCK high/low

Rise/Fall time

Setup

Mode

Min

Typ

Max

1

2

Master

Slave

See Table 17-5

50ꢀ duty cycle

3

3.6

10

4

5

Hold

10

ns

6

Out to SCK

SCK to out

SCK to out high

SS low to out

SCK period

SCK high/low⁽¹⁾

Rise/Fall time

Setup

0.5 • t_sck

10

7

8

10

9

15

10

11

12

13

14

15

16

17

18

Slave

4 • t_ck

2 • t_ck

Slave

1.6

µs

ns

Slave

10

t_ck

Hold

Slave

SCK to out

SCK to SS high

SS high to tri-state

SS low to SCK

Slave

15

10

Slave

20

Slave

20 • t_ck

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

- 2 t_CLCLfor f_CK< 12 MHz

- 3 t_CLCLfor f_CK> 12 MHz

Figure 27-4. SPI Interface Timing Requirements (Master Mode)

SS

6

1

SCK

(CPOL = 0)

2

SCK

(CPOL = 1)

4

5

3

MISO

(Data Input)

MSB

...

LSB

7

8

MOSI

(Data Output)

MSB

...

LSB

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Figure 27-5. SPI Interface Timing Requirements (Slave Mode)

SS

10

16

9

SCK

(CPOL = 0)

11

SCK

(CPOL = 1)

13

14

12

MOSI

(Data Input)

MSB

...

LSB

15

17

MISO

(Data Output)

MSB

...

LSB

X

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ATmega169P

27.7 ADC Characteristics – Preliminary Data

Table 27-4. ADC Characteristics

Symbol

Parameter

Condition

Min

Typ

10

8

Max

Units

Bits

Single Ended Conversion

Differential Conversion

Single Ended Conversion

Resolution

Bits

V

_REF= 4V, V_CC= 4V,

2

2.5

LSB

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

4.5

ADC clock = 1 MHz

Absolute accuracy

(Including INL, DNL,

quantization error, gain and

offset error)

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

2

LSB

ADC clock = 200 kHz

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

4.5

ADC clock = 1 MHz

Noise Reduction Mode

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Integral Non-Linearity (INL)

Differential Non-Linearity (DNL)

Gain Error

0.5

0.25

2

LSB

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Single Ended Conversion

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Single Ended Conversion

Offset Error

V_REF= 4V, V_CC= 4V,

2

ADC clock = 200 kHz

Conversion Time

Free Running Conversion

Single Ended Conversion

13

50

260

1000

µs

kHz

V

Clock Frequency

AVCC

V_REF

Analog Supply Voltage

V

_CC- 0.3

1.0

V_CC+ 0.3

AVCC

Single Ended Conversion

Differential Conversion

Single ended channels

Differential Conversion

Single Ended Channels

Differential Channels

V

Reference Voltage

Input Voltage

1.0

AVCC - 0.5

V

GND

0

V_REF

V

V_IN

AVCC⁽¹⁾

V

38,5

4

kHz

V

Input Bandwidth

V_INT

R_REF

R_AIN

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

1.0

1.1

32

1.2

kΩ

MΩ

100

Note:

1. V_DIFFmust be below V_REF

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27.8 LCD Controller Characteristics – Preliminary Data

Table 27-5. LCD Controller Characteristics

Symbol

I_LCD

Parameter

Condition

Min

Typ

100

10

Max

Units

µA

LCD Driver Current

LCD Driver Output Resistance

Total for All COM and SEG pins

Per COM or SEG pin

R_LCD

kΩ

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28. Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock

source.

All Active- and Idle current consumption measurements are done with all bits in the PRR register

set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is dis-

abled during these measurements. Table 28-1 and Table 28-2 on page 340 show the additional

current consumption compared to I_CCActive and I_CCIdle for every I/O module controlled by the

Power Reduction Register. See ”Power Reduction Register” on page 41 for details.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f where

C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

28.1 Active Supply Current

Figure 28-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

1.6

5.5 V

5.0 V

1.4

1.2

1

4.5 V

4.0 V

0.8

0.6

0.4

0.2

0

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

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Figure 28-2. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

25

5.5 V

20

15

10

5.0 V

4.5 V

4.0 V

3.3 V

5

2.7 V

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 28-3. Active Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

10

85 ˚C

25 ˚C

-40 ˚C

9

8

7

6

5

4

3

2

1

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

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Figure 28-4. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

2

1.8

1.6

1.4

1.2

1

85 ˚C

25 ˚C

-40 ˚C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-5. Active Supply Current vs. V_CC(32 kHz Watch Crystal)

ACTIVE SUPPLY CURRENT vs. V_CC

32 kHz WATCH CRYSTAL

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

25 ˚C

0.0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

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28.2 Idle Supply Current

Figure 28-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

0.5

0.45

0.4

5.5 V

5.0 V

0.35

0.3

4.5 V

4.0 V

0.25

0.2

3.3 V

2.7 V

0.15

0.1

1.8 V

0.05

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 28-7. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

10

9

8

7

6

5

4

3

2

1

0

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

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ATmega169P

Figure 28-8. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

4

3.5

3

85 ˚C

25 ˚C

-40 ˚C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 28-9. Idle Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

0.7

85 ˚C

25 ˚C

-40 ˚C

0.6

0.5

0.4

0.3

0.2

0.1

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

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Figure 28-10. Idle Supply Current vs. V_CC(32 kHz Watch Crystal)

IDLE SUPPLY CURRENT vs. V_CC

32 kHz WATCH CRYSTAL

14

25 ˚C

12

10

8

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

28.3 Supply Current of I/O modules

The tables and formulas below can be used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Power Reduction Register. See ”Power Reduction Register” on page 41 for

details.

Table 28-1. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit

Typical numbers

V_CC= 2V, F = 1MHz

18 µA

V_CC= 3V, F = 4MHz

116 µA

V_CC= 5V, F = 8MHz

495 µA

PRADC

PRUSART0

PRSPI

11µA

79 µA

72 µA

117 µA

32 µA

313 µA

283 µA

481 µA

105 µA

10 µA

PRTIM1

PRLCD

19 µA

4 µA

Table 28-2. Additional Current Consumption (percentage) in Active and Idle mode

Additional Current consumption

compared to Active with external clock

(see Figure 28-1 and Figure 28-2)

Additional Current consumption

compared to Idle with external clock

(see Figure 28-6 and Figure 28-7)

PRR bit

PRADC

5.6ꢀ

3.7ꢀ

18.7ꢀ

12.4ꢀ

PRUSART0

340

ATmega169P

8018A–AVR–03/06

ATmega169P

Table 28-2. Additional Current Consumption (percentage) in Active and Idle mode

Additional Current consumption

compared to Active with external clock

(see Figure 28-1 and Figure 28-2)

Additional Current consumption

compared to Idle with external clock

(see Figure 28-6 and Figure 28-7)

PRR bit

PRSPI

3.2ꢀ

5.6ꢀ

10.8ꢀ

18.6ꢀ

41.7ꢀ

PRTIM1

PRLCD

12.5ꢀ

It is possible to calculate the typical current consumption based on the numbers from Table 28-2

for other V_CCand frequency settings than listed in Table 28-1.

28.3.0.1

Example 1

Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI

enabled at V_CC= 3.0V and F = 1MHz. From Table 28-2, second column, we see that we need to

add 12.4ꢀ for the USART0, 10.8ꢀ for the SPI, and 18.6ꢀ for the TIMER1 module. Reading

from Figure 28-6, we find that the idle current consumption is ~0.18mA at V_CC= 3.0V and F =

1MHz. The total current consumption in idle mode with USART0, TIMER1, and SPI enabled,

gives:

ICCtotal ≈ 0,18mA • (1 + 0,124 + 0,108 + 0,186) ≈ 0,26mA

28.4 Power-down Supply Current

Figure 28-11. Power-down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

85˚C

-40˚C

25˚C

1.5

2.0

2.5

3.0

3.5

_CC(V)

4.0

4.5

5.0

5.5

V

341

8018A–AVR–03/06

Figure 28-12. Power-down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

20

18

16

14

12

10

8

85°C

-40°C

25°C

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

28.5 Power-save Supply Current

Figure 28-13. Power-save Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-SAVE SUPPLY CURRENT vs. V_CC

WATCHDIG TIMER DISABLED

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

85 ˚C

-40 ˚C

25 ˚C

1.5

2.0

2.5

3.0

3.5

_CC(V)

4.0

4.5

5.0

5.5

V

The differential current consumption between Power-save with WD disabled and 32 kHz TOSC

represents the current drawn by Timer/Counter2.

342

ATmega169P

8018A–AVR–03/06

ATmega169P

28.6 Standby Supply Current

Figure 28-14. Standby Supply Current vs. V_CC(32 kHz Watch Crystal, Watchdog Timer

Disabled)

STANDBY CURRENT vs. V_CC

32 kHz WATCH CRYSTAL, WATCHDOG TIMER DISABLED

2.50

2.00

1.50

1.00

0.50

0.00

85˚C

25˚C

-40˚C

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V_CC(V)

Figure 28-15. Standby Supply Current vs. V_CC(455 kHz Resonator, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

CC

455 kHz RESONATOR, WATCHDOG TIMER DISABLED

70

60

50

40

30

20

10

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

343

8018A–AVR–03/06

Figure 28-16. Standby Supply Current vs. V_CC(1 MHz Resonator, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

CC

1 MHz RESONATOR, WATCHDOG TIMER DISABLED

60

50

40

30

20

10

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

Figure 28-17. Standby Supply Current vs. V_CC(2 MHz Resonator, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V_CC

2 MHz RESONATOR, WATCHDOG TIMER DISABLED

90

80

70

60

50

40

30

20

10

0

1.5

2

2.5

3

3.5

_CC(V)

4

4.5

5

5.5

V

344

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-18. Standby Supply Current vs. V_CC(2 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V_CC

2 MHz XTAL, WATCHDOG TIMER DISABLED

80

70

60

50

40

30

20

10

0

1.5

2

2.5

3

3.5

_CC(V)

4

4.5

5

5.5

V

Figure 28-19. Standby Supply Current vs. V_CC(4 MHz Resonator, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V

CC

4 MHz RESONATOR, WATCHDOG TIMER DISABLED

140

120

100

80

60

40

20

0

1.5

2

2.5

3

3.5

_CC(V)

4

4.5

5

5.5

V

345

8018A–AVR–03/06

Figure 28-20. Standby Supply Current vs. V_CC(4 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V_CC

4 MHz XTAL, WATCHDOG TIMER DISABLED

140

120

100

80

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-21. Standby Supply Current vs. V_CC(6 MHz Resonator, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V_CC

6 MHz RESONATOR, WATCHDOG TIMER DISABLED

160

140

120

100

80

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V^CC(V)

346

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-22. Standby Supply Current vs. V_CC(6 MHz Xtal, Watchdog Timer Disabled)

STANDBY SUPPLY CURRENT vs. V_CC

6 MHz XTAL, WATCHDOG TIMER DISABLED

180

160

140

120

100

80

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

28.7 Pin Pull-up

Figure 28-23. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5V

160

85°C

140

25°C

120

-40°C

100

80

60

40

20

0

1

2

3

4

5

V_IO(V)

347

8018A–AVR–03/06

Figure 28-24. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2.7V

90

80

85°C

25°C

70

-40°C

60

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_IO(V)

Figure 28-25. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 1.8V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 1.8V

60

50

85°C

25°C

40

-40°C

30

20

10

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OP(V)

348

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 5V

120

-40°C

25°C

100

80

60

40

20

0

85°C

0

1

2

3

4

5

V_RESET(V)

Figure 28-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 2.7V

70

60

-40°C

25°C

50

85°C

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V

_RESET(V)

349

8018A–AVR–03/06

Figure 28-28. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 1.8V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

Vcc = 1.8V

40

-40°C

35

25°C

30

85°C

25

20

15

10

5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_RESET(V)

28.8 Pin Driver Strength

Figure 28-29. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 5V

70

60

-40°C

50

25°C

85°C

40

30

20

10

0

1

2

3

4

5

6

V_OH(V)

350

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-30. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 2.7V

25

-40°C

20

25°C

85°C

15

10

5

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 28-31. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 1.8V

8

-40°C

7

25°C

6

85°C

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

351

8018A–AVR–03/06

Figure 28-32. I/O Pin Source Current vs. Output Voltage, Port B (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 5V

80

-40°C

70

25°C

60

85°C

50

40

30

20

10

0

1

2

3

4

V

_OH(V)

Figure 28-33. I/O Pin Source Current vs. Output Voltage, Port B (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 2.7V

35

30

-40°C

25°C

25

85°C

20

15

10

5

0

0.5

1

1.5

2

2.5

3

V

_OH(V)

352

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-34. I/O Pin Source Current vs. Output Voltage, Port B (V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 1.8V

10

9

-40°C

85°C

25°C

8

7

6

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

Figure 28-35. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 5V

50

-40°C

45

40

25°C

35

85°C

30

25

20

15

10

5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

353

8018A–AVR–03/06

Figure 28-36. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 2.7V

Vcc = 5V

20

50

-40°C

18

45

16

40

14

25°C

85°C

25°C

85°C

35

12

30

10

25

8

20

6

15

4

2

10

0

5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.4

1.8

1.6

2

V_OL(V)

0

0.4

0.6

0.8

1

1.2

1.8

2

V_OL(V)

Figure 28-37. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G (V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G

Vcc = 1.8V

7

-40°C

6

25°C

5

85°C

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

354

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-38. I/O Pin Sink Current vs. Output Voltage, Port B (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 5V

90

80

70

60

50

40

30

20

10

0

-40°C

25°C

85°C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V

_OL(V)

Figure 28-39. I/O Pin Sink Current vs. Output Voltage, Port B (V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 2.7V

35

30

25

20

15

10

5

-40°C

25°C

85°C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

355

8018A–AVR–03/06

Figure 28-40. I/O Pin Sink Current vs. Output Voltage, Port B (V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B

Vcc = 1.8V

12

-40°C

10

8

25°C

85°C

6

4

2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

28.9 Pin Thresholds and Hysteresis

Figure 28-41. I/O Pin Input Threshold Voltage vs. V_CC(V_IH, I/O Pin Read as “1”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, I/O PIN READ AS '1'

3

85°C

25°C

-40°C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

356

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-42. I/O Pin Input Threshold Voltage vs. V_CC(V_IL, I/O Pin Read as “0”)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, I/O PIN READ AS '0'

3

2.5

2

85°C

25°C

-40°C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-43. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V_CC

0.6

0.5

0.4

0.3

0.2

0.1

0

-40°C

25°C

85°C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

357

8018A–AVR–03/06

Figure 28-44. Reset Input Threshold Voltage vs. V_CC(V_IH,Reset Pin Read as “1”)

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, RESET PIN READ AS '1'

2.5

2

1.5

-40°C

25°C

85°C

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-45. Reset Input Threshold Voltage vs. V_CC(V_IL,Reset Pin Read as “0”)

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, RESET PIN READ AS '0'

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

2.5

85°C

25°C

-40°C

VIH, RESET PIN READ AS '1'

2.5

2

1.5

-40°C

25°C

85°C

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0

V_CC(V)

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

358

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-46. Reset Input Pin Hysteresis vs. V_CC

RESET INPUT PIN HYSTERESIS vs. V_CC

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-40°C

25°C

85°C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

28.10 BOD Thresholds and Analog Comparator Offset

Figure 28-47. BOD Thresholds vs. Temperature (BOD Level is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3V

4.6

4.5

Rising V_CC

4.4

Falling V

CC

4.3

4.2

4.1

4

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature (˚C)

359

8018A–AVR–03/06

Figure 28-48. BOD Thresholds vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

3

2.9

Rising V

CC

2.8

2.7

2.6

2.5

2.4

Falling V

CC

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature (˚C)

Figure 28-49. BOD Thresholds vs. Temperature (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8V

2.1

2

Rising V

Falling V

CC

1.9

1.8

1.7

1.6

1.5

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature (˚C)

360

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-50. Bandgap Voltage vs. V_CC

BANDGAP VOLTAGE vs. V _CC

1.14

1.13

1.12

1.11

1.1

85°C

25°C

-40°C

1.09

1.08

1.5

2

2.5

3

3.5

4

4.5

5

5.5

Vcc (V)

Figure 28-51. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC= 5V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

V_CC= 5V

0.008

85°C

25°C

0.006

0.004

0.002

0

-40°C

-0.002

-0.004

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Common Mode Voltage (V)

361

8018A–AVR–03/06

Figure 28-52. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC= 2.7V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

V_CC= 2.7V

0.003

85°C

0.002

25°C

0.001

-40°C

0

-0.001

-0.002

-0.003

-0.004

0

0.5

1

1.5

2

2.5

3

Common Mode Voltage (V)

28.11 Internal Oscillator Speed

Figure 28-53. Oscillator Current vs. V_CC(32 kHz Watch Crystal)

OSCILLATOR CURRENT vs. V_CC

32 kHz WATCH CRYSTAL

1.00

0.90

0.80

0.70

0.60

0.50

0.40

0.30

0.20

0.10

0.00

85˚C

25˚C

-40˚C

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V_CC(V)

362

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-54. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

1200

1150

1100

1050

1000

950

-40°C

25°C

85°C

900

850

800

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-55. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

8.8

8.6

8.4

8.2

8

7.8

7.6

7.4

7.2

1.8V

2.7V

4.0V

5.5V

-60

-40

-20

0

20

40

60

80

100

T_a(˚C)

363

8018A–AVR–03/06

Figure 28-56. Calibrated 8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V_CC

10

9.5

9

8.5

8

85°C

25°C

7.5

7

-40°C

6.5

6

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-57. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

16

14

12

10

8

85 ˚C

25 ˚C

-40 ˚C

6

4

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

OSCCAL VALUE

364

ATmega169P

8018A–AVR–03/06

ATmega169P

28.12 Current Consumption of Peripheral Units

Figure 28-58. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. V_CC

30

25

20

15

10

5

-40°C

85°C

25°C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-59. ADC Current vs. V_CC(AREF = AVCC)

ADC CURRENT vs. V_CC

AREF = AV_CC

350

300

250

200

150

100

50

-40°C

25°C

85°C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

365

8018A–AVR–03/06

Figure 28-60. AREF External Reference Current vs. V_CC

AREF EXTERNAL REFERENCE CURRENT vs. V_CC

160

140

120

100

80

85°C

25°C

-40°C

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-61. 32 kHZ TOSC Current vs. V_CC(Watchdog Timer Disabled) - TBD

The differential current consumption between Power-save with WD disabled and 32 kHz TOSC

represents the current drawn by Timer/Counter2.

366

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-62. Watchdog Timer Current vs. V_CC

WATCHDOG TIMER CURRENT vs. V_CC

16

14

12

10

8

85°C

25°C

-40°C

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 28-63. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V_CC

120

100

80

60

40

20

0

-40°C

25°C

85°C

1.5

2

2.5

3

3.5

_CC(V)

4

4.5

5

5.5

V

367

8018A–AVR–03/06

Figure 28-64. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. Vcc

25

20

15

10

5

-40°C

25°C

85°C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

28.13 Current Consumption in Reset and Reset Pulsewidth

Figure 28-65. Reset Supply Current vs. V_CC(0.1 - 1.0 MHz, Excluding Current Through The

Reset Pull-up)

RESET SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0.18

5.5V

0.16

5.0V

0.14

4.5V

0.12

4.0V

0.1

3.3V

2.7V

0.08

0.06

0.04

0.02

0

1.8V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

368

ATmega169P

8018A–AVR–03/06

ATmega169P

Figure 28-66. Reset Supply Current vs. V_CC(1 - 20 MHz, Excluding Current Through The Reset

Pull-up)

RESET SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

3.5

3

5.5V

2.5

2

5.0V

4.5V

4.0V

1.5

1

3.3V

0.5

0

2.7V

1.8V

0

2

4

6

8 10

12

14

16

18

20

Frequency (MHz)

Figure 28-67. Minimum Reset Pulse Width vs. V_CC

MINIMUM RESET PULSE WIDTH vs. V_CC

2500

2000

1500

1000

500

85°C

25°C

-40°C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

_CC(V)

369

8018A–AVR–03/06

29. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

Reserved

LCDDR18

LCDDR17

LCDDR16

LCDDR15

Reserved

LCDDR13

LCDDR12

LCDDR11

LCDDR10

Reserved

LCDDR8

LCDDR7

LCDDR6

LCDDR5

Reserved

LCDDR3

LCDDR2

LCDDR1

LCDDR0

Reserved

LCDCCR

LCDFRR

LCDCRB

LCDCRA

Reserved

UDR0

–

SEG324

249

SEG323

SEG322

SEG321

SEG320

SEG319

SEG318

SEG317

SEG316

SEG315

SEG314

SEG313

SEG312

SEG311

SEG310

SEG309

SEG308

SEG307

SEG306

SEG305

SEG304

SEG303

SEG302

SEG301

SEG300

–

SEG224

249

SEG223

SEG222

SEG221

SEG220

SEG219

SEG218

SEG217

SEG216

SEG215

SEG214

SEG213

SEG212

SEG211

SEG210

SEG209

SEG208

SEG207

SEG206

SEG205

SEG204

SEG203

SEG202

SEG201

SEG200

–

SEG124

249

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

–

SEG024

249

SEG023

SEG022

SEG021

SEG020

SEG019

SEG018

SEG017

SEG016

SEG015

SEG014

SEG013

SEG012

SEG011

SEG010

SEG09

SEG008

SEG007

SEG006

SEG005

SEG004

SEG003

SEG002

SEG001

SEG000

–

LCDCD2

LCDCD1

LCDCC0

LCDMDT

LCDCC3

LCDCC2

LCDCC1

LCDCC0

248

246

245

244

–

LCDPS2

LCDPS1

LCDPS0

–

LCDCD2

LCDCD1

LCDCD0

LCDCS

LCD2B

LCDMUX1

LCDMUX0

–

LCDPM2

LCDPM1

LCDPM0

LCDEN

LCDAB

–

LCDIF

LCDIE

LCDBD

LCDCCD

LCDBL

–

USART0 I/O Data Register

190

194

UBRRH0

UBRRL0

Reserved

UCSR0C

UCSR0B

UCSR0A

USART0 Baud Rate Register High

USART0 Baud Rate Register Low

–

UMSEL0

TXCIE0

TXC0

UPM10

UDRIE0

UDRE0

UPM00

RXEN0

FE0

USBS0

TXEN0

DOR0

UCSZ01

UCSZ02

UPE0

UCSZ00

RXB80

U2X0

UCPOL0

TXB80

MPCM0

190

RXCIE0

RXC0

370

ATmega169P

8018A–AVR–03/06

ATmega169P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

Reserved

USIDR

–

USI Data Register

207

208

USISR

USISIF

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USICR

USISIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

Reserved

ASSR

–

AS2

–

EXCLK

TCN2UB

OCR2UB

TCR2UB

156

Reserved

OCR2A

–

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8-bit)

155

TCNT2

Reserved

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

–

CS22

–

CS21

–

CS20

–

FOC2A

WGM20

COM2A1

COM2A0

WGM21

153

–

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

132

133

132

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

WGM12

–

CS12

–

131

130

128

214

232

–

WGM13

COM1B0

–

CS11

WGM11

AIN1D

ADC1D

CS10

WGM10

AIN0D

ADC0D

COM1B1

–

DIDR0

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

371

8018A–AVR–03/06

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7D)

(0x7C)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

–

MUX4

–

MUX3

–

REFS1

–

REFS0

ACME

ADSC

ADLAR

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

228

213, 232

230

(0x7B)

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

231

(0x78)

ADCL

231

(0x77)

Reserved

TIMSK2

TIMSK1

TIMSK0

Reserved

PCMSK1

PCMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

OCIE2A

OCIE1A

OCIE0A

–

(0x70)

–

TOIE2

TOIE1

TOIE0

–

156

133

104

(0x6F)

–

ICIE1

–

OCIE1B

(0x6E)

–

(0x6D)

–

(0x6C)

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

PCINT9

PCINT1

–

PCINT8

PCINT0

–

63

64

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

(0x6A)

–

(0x69)

ISC01

–

ISC00

–

62

(0x68)

Reserved

OSCCAL

Reserved

PRR

(0x67)

–

(0x66)

Oscillator Calibration Register

37

44

(0x65)

–

PRSPI

–

PRADC

–

(0x64)

–

PRLCD

PRTIM1

PRUSART0

(0x63)

Reserved

CLKPR

–

(0x62)

–

CLKPS3

WDE

V

–

(0x61)

CLKPCE

–

CLKPS2

WDP2

N

CLKPS1

WDP1

Z

CLKPS0

WDP0

C

37

54

12

14

(0x60)

WDTCR

SREG

–

I

–

WDCE

S

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

T

H

SPH

–

SP10

SP2

SP9

SP1

SP8

SP0

SPL

SP7

SP6

SP5

SP4

SP3

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

SPMIE

RWWSB

–

RWWSRE

BLBSET

PGWRT

PGERS

–

SPMEN

–

293

–

PUD

JTRF

–

JTD

–

IVSEL

EXTRF

SM0

–

IVCE

PORF

SE

60, 88, 278

–

WDRF

SM2

–

BORF

SM1

–

278

44

–

Reserved

OCDR

–

IDRD/OCDR7

OCDR6

ACBG

–

OCDR5

ACO

–

OCDR4

ACI

–

OCDR3

ACIE

–

OCDR2

ACIC

–

OCDR1

ACIS1

–

OCDR0

ACIS0

–

256

213

ACSR

ACD

–

Reserved

SPDR

SPI Data Register

167

166

165

28

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

28

–

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit)

104

Reserved

TCCR0A

GTCCR

EEARH

EEARL

–

FOC0A

TSM

–

CS02

–

WGM00

COM0A1

COM0A0

WGM01

CS01

PSR2

–

CS00

PSR10

EEAR8

102

137, 157

26

–

EEPROM Address Register Low Byte

EEPROM Data Register

26

EEDR

26

EECR

–

EERIE

EEMWE

EEWE

EERE

26

GPIOR0

EIMSK

General Purpose I/O Register 0

28

PCIE1

PCIF1

PCIE0

PCIF0

–

INT0

62

EIFR

INTF0

63

372

ATmega169P

8018A–AVR–03/06

ATmega169P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved

TIFR2

–

OCF2A

OCF1A

OCF0A

PORTG1

DDG1

PING1

PORTF1

DDF1

TOV2

TOV1

TOV0

PORTG0

DDG0

PING0

PORTF0

DDF0

PINF0

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

156

134

105

90

89

90

89

88

TIFR1

–

ICF1

–

OCF1B

–

TIFR0

–

PORTG

DDRG

PING

–

PORTG4

DDG4

PING4

PORTF4

DDF4

PINF4

PORTE4

DDE4

PINE4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTG3

DDG3

PING3

PORTF3

DDF3

PINF3

PORTE3

DDE3

PINE3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTG2

DDG2

PING2

PORTF2

DDF2

PINF2

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

–

PORTF

DDRF

PORTF7

DDF7

PINF7

PORTE7

DDE7

PINE7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PORTF5

DDF5

PINF5

PORTE5

DDE5

PINE5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PINF

PINF1

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

PORTE

DDRE

PINE

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com-

plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN

and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

373

8018A–AVR–03/06

30. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

k

374

ATmega169P

8018A–AVR–03/06

ATmega169P

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Enabled

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rd ← P

1

OUT

Out Port

P ← Rr

375

8018A–AVR–03/06

Mnemonics

Operands

Description

Operation

Flags

#Clocks

PUSH

POP

Rr

Rd

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

None

2

None

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

376

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ATmega169P

31. Ordering Information

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾⁽²⁾

Operation Range

ATmega169PV-8AU

ATmega169PV-8MU

64A

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

64M1

ATmega169P-16AU

ATmega169P-16MU

64A

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

64M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC, see Figure 27-2 on page 330 and Figure 27-3 on page 330.

Package Type

64A

64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1

64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

377

8018A–AVR–03/06

32. Packaging Information

32.1 64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

14.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64A

B

R

378

ATmega169P

8018A–AVR–03/06

ATmega169P

32.2 64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

NOM

0.90

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.02

0.18

0.25

D

9.00 BSC

5.40

D2

E

5.20

5.60

K

Pin #1

Notch

(0.20 R)

9.00 BSC

5.40

e

b

E2

e

BOTTOM VIEW

0.50 BSC

0.40

L

0.35

0.45

1.55

K

1.25

1.40

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Note:

7/19/05

DRAWING NO. REV.

64M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

F

R

379

8018A–AVR–03/06

33. Errata

33.1 ATmega169P Rev. G

No known errata.

33.2 ATmega169P Rev. A to F

Not sampled.

380

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ATmega169P

34. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document. The

referring revision in this section are referring to the document revision.

34.1 Rev. A 03/06

1.

Initial revision.

381

8018A–AVR–03/06

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8018A–AVR–03/06

ATmega169P

Table of Contents

Features..................................................................................................... 1

1

2

Pin Configurations ................................................................................... 2

1.1 Disclaimer .................................................................................................................2

Overview ................................................................................................... 3

2.1 Block Diagram ..........................................................................................................3

2.2 Pin Descriptions .......................................................................................................5

3

4

5

Resources ................................................................................................. 8

About Code Examples ............................................................................. 9

AVR CPU Core ........................................................................................ 10

5.1 Introduction .............................................................................................................10

5.2 Architectural Overview ...........................................................................................10

5.3 ALU – Arithmetic Logic Unit ...................................................................................11

5.4 Status Register .......................................................................................................12

5.5 General Purpose Register File ...............................................................................13

5.6 Stack Pointer ..........................................................................................................14

5.7 Instruction Execution Timing ..................................................................................15

5.8 Reset and Interrupt Handling .................................................................................16

6

AVR Memories ........................................................................................ 18

6.1 In-System Reprogrammable Flash Program Memory ............................................18

6.2 SRAM Data Memory ..............................................................................................19

6.3 EEPROM Data Memory .........................................................................................21

6.4 EEPROM Register Description ...............................................................................26

6.5 I/O Memory .............................................................................................................28

6.6 General Purpose I/O Registers ..............................................................................28

7

System Clock and Clock Options ......................................................... 29

7.1 Clock Systems and their Distribution ......................................................................29

7.2 Clock Sources ........................................................................................................30

7.3 Default Clock Source ..............................................................................................31

7.4 Calibrated Internal RC Oscillator ............................................................................31

7.5 Crystal Oscillator ....................................................................................................32

7.6 Low-frequency Crystal Oscillator ............................................................................33

7.7 External Clock ........................................................................................................35

i

8018A–AVR–03/06

7.8 Timer/Counter Oscillator ........................................................................................36

7.9 Clock Output Buffer ................................................................................................36

7.10 System Clock Prescaler .......................................................................................36

7.11 Register Description .............................................................................................37

8

Power Management and Sleep Modes ................................................. 39

8.1 Sleep Modes ..........................................................................................................39

8.2 Idle Mode ................................................................................................................40

8.3 ADC Noise Reduction Mode ..................................................................................40

8.4 Power-down Mode .................................................................................................40

8.5 Power-save Mode ..................................................................................................41

8.6 Standby Mode ........................................................................................................41

8.7 Power Reduction Register ......................................................................................41

8.8 Minimizing Power Consumption .............................................................................42

8.9 Register Description ...............................................................................................44

9

System Control and Reset .................................................................... 46

9.1 Resetting the AVR ..................................................................................................46

9.2 Reset Sources ........................................................................................................46

9.3 Internal Voltage Reference .....................................................................................51

9.4 Watchdog Timer .....................................................................................................51

9.5 Register Description ...............................................................................................54

10 Interrupts ................................................................................................ 56

10.1 Interrupt Vectors in ATmega169P ........................................................................56

10.2 Moving Interrupts Between Application and Boot Space .....................................59

11 External Interrupts ................................................................................. 61

11.1 Pin Change Interrupt Timing ................................................................................61

11.2 Register Description .............................................................................................62

12 I/O-Ports .................................................................................................. 65

12.1 Introduction ...........................................................................................................65

12.2 Ports as General Digital I/O ..................................................................................66

12.3 Alternate Port Functions .......................................................................................71

12.4 Register Description for I/O-Ports .........................................................................88

13 8-bit Timer/Counter0 with PWM ............................................................ 91

13.1 Overview ..............................................................................................................91

13.2 Timer/Counter Clock Sources ..............................................................................92

ii

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ATmega169P

13.3 Counter Unit .........................................................................................................92

13.4 Output Compare Unit ...........................................................................................93

13.5 Compare Match Output Unit .................................................................................95

13.6 Modes of Operation ..............................................................................................96

13.7 Timer/Counter Timing Diagrams ........................................................................100

13.8 8-bit Timer/Counter Register Description ...........................................................102

14 16-bit Timer/Counter1 .......................................................................... 106

14.1 Overview ............................................................................................................106

14.2 Accessing 16-bit Registers .................................................................................109

14.3 Timer/Counter Clock Sources ............................................................................111

14.4 Counter Unit .......................................................................................................112

14.5 Input Capture Unit ..............................................................................................113

14.6 Output Compare Units ........................................................................................115

14.7 Compare Match Output Unit ...............................................................................117

14.8 Modes of Operation ............................................................................................118

14.9 Timer/Counter Timing Diagrams ........................................................................126

14.10 16-bit Timer/Counter Register Description .......................................................128

15 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 135

15.1 Prescaler Reset ..................................................................................................135

15.2 Internal Clock Source .........................................................................................135

15.3 External Clock Source ........................................................................................135

15.4 Register Description ...........................................................................................137

16 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 138

16.1 Overview ............................................................................................................138

16.2 Timer/Counter Clock Sources ............................................................................139

16.3 Counter Unit .......................................................................................................139

16.4 Output Compare Unit .........................................................................................140

16.5 Compare Match Output Unit ...............................................................................142

16.6 Modes of Operation ............................................................................................143

16.7 Timer/Counter Timing Diagrams ........................................................................148

16.8 Asynchronous operation of the Timer/Counter ...................................................150

16.9 Timer/Counter Prescaler ....................................................................................152

16.10 8-bit Timer/Counter Register Description .........................................................153

17 SPI – Serial Peripheral Interface ......................................................... 158

17.1 SS Pin Functionality ...........................................................................................163

iii

8018A–AVR–03/06

17.2 Data Modes ........................................................................................................164

17.3 SPI Register Description ....................................................................................165

18 USART ................................................................................................... 168

18.1 Overview ............................................................................................................169

18.2 Clock Generation ................................................................................................170

18.3 Frame Formats ...................................................................................................173

18.4 USART Initialization ...........................................................................................175

18.5 Data Transmission – The USART Transmitter ...................................................177

18.6 Data Reception – The USART Receiver ............................................................180

18.7 Asynchronous Data Reception ...........................................................................185

18.8 Multi-processor Communication Mode ...............................................................188

18.9 USART Register Description ..............................................................................190

18.10 Examples of Baud Rate Setting .......................................................................195

19 USI – Universal Serial Interface .......................................................... 199

19.1 Overview ............................................................................................................199

19.2 Functional Descriptions ......................................................................................200

19.3 Alternative USI Usage ........................................................................................206

19.4 USI Register Descriptions ..................................................................................207

20 AC - Analog Comparator ..................................................................... 211

20.1 Analog Comparator Multiplexed Input ................................................................212

20.2 Analog Comparator Register Description ...........................................................213

21 ADC - Analog to Digital Converter ..................................................... 215

21.1 Features .............................................................................................................215

21.2 Operation ............................................................................................................216

21.3 Starting a Conversion .........................................................................................217

21.4 Prescaling and Conversion Timing .....................................................................218

21.5 Changing Channel or Reference Selection ........................................................220

21.6 ADC Noise Canceler ..........................................................................................221

21.7 ADC Conversion Result .....................................................................................226

21.8 ADC Register Description ..................................................................................228

22 LCD Controller ..................................................................................... 233

22.1 Features .............................................................................................................233

22.2 Overview ............................................................................................................233

22.3 Mode of Operation ..............................................................................................236

iv

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ATmega169P

22.4 LCD Usage .........................................................................................................240

22.5 LCD Register Description ...................................................................................244

23 JTAG Interface and On-chip Debug System ..................................... 250

23.1 Overview ............................................................................................................250

23.2 TAP – Test Access Port .....................................................................................251

23.3 TAP Controller ....................................................................................................253

23.4 Using the Boundary-scan Chain .........................................................................254

23.5 Using the On-chip Debug System ......................................................................254

23.6 On-chip Debug Specific JTAG Instructions ........................................................255

23.7 On-chip Debug Related Register in I/O Memory ................................................256

23.8 Using the JTAG Programming Capabilities ........................................................256

23.9 Bibliography ........................................................................................................256

24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 257

24.1 Features .............................................................................................................257

24.2 System Overview ...............................................................................................257

24.3 Data Registers ....................................................................................................258

24.4 Boundary-scan Specific JTAG Instructions ........................................................259

24.5 Boundary-scan Chain .........................................................................................261

24.6 Boundary-scan Order .........................................................................................271

24.7 Boundary-scan Description Language Files .......................................................277

24.8 Boundary-scan Related Register in I/O Memory ................................................278

25 Boot Loader Support – Read-While-Write Self-Programming ......... 279

25.1 Boot Loader Features .........................................................................................279

25.2 Application and Boot Loader Flash Sections ......................................................279

25.3 Read-While-Write and No Read-While-Write Flash Sections .............................280

25.4 Boot Loader Lock Bits ........................................................................................283

25.5 Entering the Boot Loader Program .....................................................................284

25.6 Addressing the Flash During Self-Programming ................................................285

25.7 Self-Programming the Flash ...............................................................................286

25.8 Register Description ...........................................................................................293

26 Memory Programming ......................................................................... 295

26.1 Program And Data Memory Lock Bits ................................................................295

26.2 Fuse Bits ............................................................................................................296

26.3 Signature Bytes ..................................................................................................298

26.4 Calibration Byte ..................................................................................................298

v

8018A–AVR–03/06

26.5 Page Size ...........................................................................................................298

26.6 Parallel Programming Parameters, Pin Mapping, and Commands ....................298

26.7 Parallel Programming .........................................................................................301

26.8 Serial Downloading ............................................................................................309

26.9 Programming via the JTAG Interface .................................................................314

27 Electrical Characteristics .................................................................... 327

27.1 Absolute Maximum Ratings* ..............................................................................327

27.2 DC Characteristics .............................................................................................327

27.3 External Clock Drive Waveforms ........................................................................329

27.4 External Clock Drive ...........................................................................................329

27.5 Maximum Speed vs. V_{CC ...........................................................................................................................329}

27.6 SPI Timing Characteristics .................................................................................331

27.7 ADC Characteristics – Preliminary Data .............................................................333

27.8 LCD Controller Characteristics – Preliminary Data ............................................334

28 Typical Characteristics ........................................................................ 335

28.1 Active Supply Current .........................................................................................335

28.2 Idle Supply Current .............................................................................................338

28.3 Supply Current of I/O modules ...........................................................................340

28.4 Power-down Supply Current ..............................................................................341

28.5 Power-save Supply Current ...............................................................................342

28.6 Standby Supply Current .....................................................................................343

28.7 Pin Pull-up ..........................................................................................................347

28.8 Pin Driver Strength .............................................................................................350

28.9 Pin Thresholds and Hysteresis ...........................................................................356

28.10 BOD Thresholds and Analog Comparator Offset .............................................359

28.11 Internal Oscillator Speed ..................................................................................362

28.12 Current Consumption of Peripheral Units .........................................................365

28.13 Current Consumption in Reset and Reset Pulsewidth .....................................368

29 Register Summary ............................................................................... 370

30 Instruction Set Summary .................................................................... 374

31 Ordering Information ........................................................................... 377

32 Packaging Information ........................................................................ 378

32.1 64A .....................................................................................................................378

32.2 64M1 ..................................................................................................................379

vi

ATmega169P

8018A–AVR–03/06

ATmega169P

33 Errata ..................................................................................................... 380

33.1 ATmega169P Rev. G .........................................................................................380

33.2 ATmega169P Rev. A to F ..................................................................................380

34 Datasheet Revision History ................................................................ 381

34.1 Rev. A 03/06 .......................................................................................................381

Table of Contents....................................................................................... i

vii

8018A–AVR–03/06

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Printed on recycled paper.

8018A–AVR–03/06


型号：	ATMEGA169PV-8MU
厂家：	ATMEL
描述：	Microcontroller with 16K Bytes In-System Programmable Flash 微控制器，带有16K字节的系统内可编程闪存闪存微控制器外围集成电路时钟
文件：	总390页 (文件大小：3485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA169PV-8MU [ATMEL]

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