ATMEGA325P_08_技术文档

Features

• High Performance, Low Power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 4 MIPS Throughput at 4 MHz

• High Endurance Non-volatile Memorie segments

– 8K/16K Bytes of In-System Self-Programmable Flash Program

Memory(ATmega8HVA/16HVA)

8-bit

– 256 Bytes EEPROM

Microcontroller

with 8K/16K

Bytes In-System

Programmable

Flash

– 512 Bytes Internal SRAM

– Write/Erase cycles: 10,000 Flash/100,000 EEPROM

– Data Retention: 20 years at 85°C /100 years at 25°C⁽¹⁾

– Programming Lock for Software Security

• Battery Management Features

– One or Two Cells in Series

– Over-current Protection (Charge and Discharge)

– Short-circuit Protection (Discharge)

– High Voltage Outputs to Drive N-Channel Charge/Discharge FETs

• Peripheral Features

– Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input

Capture (IC), Compare Mode and CTC

– SPI - Serial Programmable Interface

– 12-bit Voltage ADC, Four External and One Internal ADC Inputs

– High Resolution Coulomb Counter ADC for Current Measurements

– Programmable Watchdog Timer

ATmega8HVA

ATmega16HVA

Preliminary

Summary

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI ports

– Power-on Reset

– On-chip Voltage Regulator with Short-circuit Monitoring Interface

– External and Internal Interrupt Sources

– Sleep Modes:

Idle, ADC Noise Reduction, Power-save, and Power-off

• Additional Secure Authentication Features available only under NDA

• Packages

– 36-pad LGA

– 28-lead TSOP

• Operating Voltage: 1.8 - 9V

• Maximum Withstand Voltage (High-voltage pins): 28V

• Temperature Range: - 20°C to 85°C

• Speed Grade: 1-4 MHz

8024AS–AVR–04/08

1. Pin Configurations

1.1

LGA

Figure 1-1. LGA - Pinout ATmega8HVA/16HVA

1 2 3 4 5 6 7 8

A

B

C

D

E

Figure 1-2. LGA - pinout ATmega8HVA/16HVA

1

2

3

4

5

6

7

8

A

B

C

D

E

DNC

CF2P

VREF

PI

PV2

PV1

VFET

VREG

GND

PA1

NV

GND

VCC

GND

PB1

OC

OD

DNC

GND

BATT

GND

DNC

CF2N

VREFGND

NI

CF1P

CF1N

GND

PA0

PC0

GND

PB2

PB0

DNC

GND

PB3

RESET

DNC

2

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

1.2

TSOP

Figure 1-3. TSOP - pinout ATmega8HVA/16HVA

1

2

3

28

27

26

25

24

23

22

21

20

19

18

PV2

PV1

OD

OC

NV

GND

VFET

CF1P

CF1N

4

5

6

7

8

BATT

PC0 (RXD/TXD/INT0)

VCC

GND

CF2P

CF2N

VREG

VREF

PB3 (MISO/INT2)

9

PB2 (MOSI/INT1)

PB1 (SCK)

10

11

12

PB0 (SS/CKOUT)

PA2 (RESET/dW)

PA1 (ADC1/SGND/T1)

PA0 (ADC0/SGND/T0)

17

16

15

VREFGND

13

14

PI

NI

1.3

Pin Descriptions

1.3.1

VFET

Input to the internal voltage regulator.

1.3.2

1.3.3

1.3.4

VCC

Digital supply voltage. Normally connected to VREG.

Output from the internal voltage regulator.

VREG

CF1P/CF1N/CF2P/CF2N

CF1P/CF1N/CF2P/CF2N are the connection pins for connecting external fly capacitors to the

step-up regulator.

1.3.5

1.3.6

VREF

Internal Voltage Reference for external decoupling.

VREFGND

Ground for decoupling of Internal Voltage Reference. Do not connect to GND or SGND on PCB.

3

8024AS–AVR–04/08

1.3.7

1.3.8

GND

Ground

Port A (PA1..PA0)

Port A serves as a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected

for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port A also serves the functions of various special features of the ATmega8HVA/16HVA as

listed in ”Alternate Functions of Port A” on page 70.

1.3.9

Port B (PB3..PB0)

Port B is a low-voltage 4-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega8HVA/16HVA as

listed in ”Alternate Functions of Port B” on page 71.

1.3.10

PC0

Port C serves the functions of various special features of the ATmega8HVA/16HVA as listed in

”Alternate Functions of Port C” on page 61.

1.3.11

1.3.12

1.3.13

1.3.14

1.3.15

1.3.16

1.3.17

OC

High voltage output to drive Charge FET.

OD

High voltage output to drive Discharge FET.

NI

NI is the filtered negative input from the current sense resistor.

PI is the filtered positive input from the current sense resistor.

NV, PV1, and PV2 are the inputs for battery cells 1 and 2.

Input for detecting when a charger is connected.

PI

NV/PV1/PV2

BATT

RESET/dw

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page

38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE

communication pin.

4

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

2. Overview

The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion appli-

cations with focus on high security/authentication, accurate monitoring, low cost and high

utilization of the cell energy. The device contains secure authentication features as well as

autonomous battery protection during charging and discharging. The chip allows very accurate

accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV. The fea-

ture set makes the ATmega8HVA/16HVA a key component in any system focusing on high

security, battery protection, accurate monitoring, high system utilization and low cost.

Figure 2-1. Block Diagram

PB3..0

PC0

PB0

OC

OD

Oscillator

Circuits /

Clock

FET

Control

PORTB (4)

PORTC (1)

Generation

Oscillator

Sampling

Interface

Watchdog

Oscillator

Battery

Protection

SPI

8/16-bit T/C0

8/16-bit T/C1

EEPROM

VCC

Program

Logic

Watchdog

Timer

PV2

PV1

NV

Voltage

ADC

Flash

SRAM

Power

Supervision

POR &

debugWIRE

RESET/dW

VPTAT

RESET

VREF

CPU

Voltage

Reference

VREFGND

Security

Module

GND

BATT

Coulumb

Counter ADC

PI

NI

Charger

Detect

DATA BUS

VFET

VREG

Voltage

Regulator

Voltage Regulator

Monitor Interface

PORTA (2)

PA1..0

CF1N

CF2N

PA1..0

CF1P CF2P

A combined step-up and linear voltage regulator ensures that the chip can operate with supply

voltages as low as 1.8V for 1-cell applications. The regulator automatically switches to linear

mode when the input voltage is sufficiently high, thereby ensuring a minimum power consump-

tion at all times. For 2-cell applications, only linear regulation is enabled. The regulator

capabilities, combined with an extremely low power consumption in the power saving modes,

greatly enhances the cell energy utilization compared to existing solutions.

The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports

pre-charging of deeply discharged battery cells without using a separate Pre-charge FET.

5

8024AS–AVR–04/08

The ATmega8HVA/16HVA contains a 12-bit ADC that can be used to measure the voltage of

each cell individually. The ADC can also be used to monitor temperature, either on-chip temper-

ature using the built-in temperature sensor, external temperature using thermistors connected to

dedicated ADC inputs. The ATmega8HVA/16HVA contains a high-voltage tolerant, open-drain

IO pin that supports serial communication. Programming can be done in-system using the 4

General Purpose IO ports that support SPI programming.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The MCU includes 8K/16K bytes of In-System Programmable Flash with Read-While-Write

capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 6

general purpose I/O lines, debugWIRE for On-chip debugging and SPI for In-system Program-

ming, two flexible Timer/Counters with Input Capture and compare modes, internal and external

interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolu-

tion Sigma Delta ADC for Coulomb Counting and instantaneous current measurements,

Additional Secure Authentication Features, an authonomous Battery Protection module, a pro-

grammable Watchdog Timer with wake-up capabilities, and software selectable power saving

modes.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two indepdent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The device is manufactured using Atmel’s high voltage high density non-volatile memory tech-

nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System,

through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-

chip Boot program running on the AVR core. By combining an 8-bit RISC CPU with In-System

Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, and a volt-

age regulator on a monolithic chip, the ATmega8HVA/16HVA is a powerful microcontroller that

provides a highly flexible and cost effective solution for Li-ion Smart Battery applications.

The ATmega8HVA/16HVA AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-

chip Debugger.

The ATmega8HVA/16HVA is a low-power CMOS 8-bit microcontroller based on the AVR archi-

tecture. It is part of the AVR Smart Battery family that provides secure authentication, highly

accurate monitoring and autonomous protection for Lithium-ion battery cells.

6

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

2.1

Comparison Between ATmega8HVA and ATmega16HVA

The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size.

Table 2-1 summarizes the different configuration for the two devices.

Table 2-1.

Configuration summary

Device

Flash

8K

Interrupt vector size

1 Word

ATmega8HVA

ATmega16HVA

16K

2 Word

3. Disclaimer

4. Resources

All Min, Typ and Max values contained in this datasheet are preliminary estimates based on sim-

ulations and characterization of other AVR microcontrollers manufactured on the same process

technology. Final values will be available after the device is characterized.

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note:

1.

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

7

8024AS–AVR–04/08

6. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

Reserved

BPPLR

–

BPPLE

DHCD

BPPL

CHCD

127

130

129

128

132

131

BPCR

SCD

DOCD

COCD

BPHCTR

BPOCTR

BPSCTR

BPCHCD

BPDHCD

BPCOCD

BPDOCD

BPSCD

HCPT[5:0]

OCPT[5:0]

SCPT[6:0]

CHCDL[7:0]

DHCDL[7:0]

COCDL[7:0]

DOCDL[7:0]

SCDL[7:0]

Reserved

BPIFR

–

SCIF

DOCIF

COCIF

DHCIF

CHCIF

134

133

BPIMSK

Reserved

FCSR

SCIE

DOCIE

COCIE

DHCIE

CHCIE

–

CPS

–

DFE

–

CFE

–

DUVRD

138

Reserved

CADICH

CADICL

–

CADIC[15:8]

110

CADIC[7:0]

Reserved

CADRC

–

CADRC[7:0]

111

109

107

110

CADCSRB

CADCSRA

CADAC3

CADAC2

CADAC1

CADAC0

Reserved

BGCRR

–

CADACIE

CADPOL

–

CADICIE

CADAS[1:0]

CADACIF

CADRCIF

CADICIF

CADSE

CADEN

CADUB

CADSI[1:0]

CADAC[31:24]

CADAC[23:16]

CADAC[15:8]

CADAC[7:0]

–

BGCR[7:0]

119

118

BGCCR

BGD

–

BGCC[5:0]

Reserved

ROCR

–

ROCS

ROCWIF

ROCWIE

123

Reserved

–

Reserved

–

8

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

Reserved

OCR1B

–

Timer/Counter1 – Output Compare Register B

Timer/Counter1 – Output Compare Register A

92

91

OCR1A

Reserved

TCNT1H

TCNT1L

–

Timer/Counter1 (8 Bit) High Byte

Timer/Counter1 (8 Bit) Low Byte

91

Reserved

TCCR1B

TCCR1A

Reserved

DIDR0

–

CS11

–

CS12

CS10

WGM10

–

76

90

TCW1

ICEN1

ICNC1

ICES1

ICS1

–

PA1DID

PA0DID

116

9

8024AS–AVR–04/08

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7D)

(0x7C)

Reserved

VADMUX

Reserved

VADCSR

VADCH

VADCL

–

VADMUX[3:0]

114

(0x7B)

–

(0x7A)

VADEN

VADSC

VADCCIF

VADCCIE

114

115

(0x79)

VADC Data Register High byte

(0x78)

VADC Data Register Low byte

(0x77)

Reserved

TIMSK1

TIMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

(0x6F)

–

ICIE1

OCIE1B

OCIE1A

TOIE1

92

(0x6E)

–

ICIE0

OCIE0B

OCIE0A

TOIE0

(0x6D)

–

(0x6C)

–

(0x6B)

–

(0x6A)

–

(0x69)

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

56

(0x68)

Reserved

FOSCCAL

Reserved

PRR0

–

(0x67)

(0x66)

Fast Oscillator Calibration Register

30

39

(0x65)

–

(0x64)

–

PRVRM

–

PRSPI

PRTIM1

PRTIM0

PRVADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS1

CLKPS0

31

49

9

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

I

T

H

S

V

N

Z

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

12

SPL

SP7

–

SP6

–

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

CTPB

–

RFLB

–

PGERS

–

SIGRD

PGWRT

SPMEN

147

–

CKOE

PUD

OCDRF

–

73/31

49

–

WDRF

BODRF

SM[2:0]

–

EXTRF

PORF

SE

–

39

Reserved

DWDR

–

debugWIRE Data Register

140

Reserved

SPDR

–

SPI Data Register

103

102

101

23

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

OCR0B

OCR0A

TCNT0H

TCNT0L

TCCR0B

TCCR0A

GTCCR

Reserved

EEAR

General Purpose I/O Register 2

General Purpose I/O Register 1

23

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit) High Byte

92

91

Timer/Counter0 (8 Bit) Low Byte

91

–

TCW0

TSM

–

ICS0

–

CS02

CS01

CS00

WGM00

PSRSYNC

–

76

ICEN0

ICNC0

ICES0

–

90

–

EEPROM Address Register Low Byte

EEPROM Data Register

19

23

57

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

EIMSK

General Purpose I/O Register 0

–

INT2

INT1

INT0

EIFR

INTF2

INTF1

INTF0

10

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved

OSICSR

TIFR1

–

OSISEL0

–

OSIST

OSIEN

32

93

–

ICF1

OCF1B

OCF1A

TOV1

TIFR0

ICF0

OCF0B

OCF0A

TOV0

Reserved

PORTC

Reserved

PINC

–

PORTC0

–

62

–

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

62

73

PORTB

DDRB

PORTB3

PORTB2

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

DDB3

DDB2

PINB

PINB3

PINB2

PORTA

DDRA

–

PINA

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-

ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega8HVA/16HVA is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

11

8024AS–AVR–04/08

7. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP⁽¹⁾

RCALL

ICALL

CALL⁽¹⁾

RET

k

Direct Jump

PC ← k

3

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

12

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

7. Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

Rd ← P

1

13

8024AS–AVR–04/08

7. Instruction Set Summary (Continued)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

OUT

P, Rr

Out Port

P ← Rr

None

1

2

PUSH

POP

Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

None

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

Note:

1. These instructions are only available in ATmega16HVA.

14

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

8. Ordering Information

8.1

ATmega8HVA

Speed (MHz)

1 - 4

Power Supply

Ordering Code

Package⁽¹⁾

Operation Range

ATmega8HVA-4CKU

ATmega8HVA-4TU

36CK1

28T

1.8 - 9.0V

-20 to +85°C

Notes: 1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

Package Type

36CK1

28T

36-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package.

28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP)

15

8024AS–AVR–04/08

8.2

ATmega16HVA

Speed (MHz)

1 - 4

Power Supply

1.8 - 9.0V

Ordering Code

Package⁽¹⁾

Operation Range

ATmega16HVA-4CKU

ATmega16HVA-4TU

36CK1

28T

-20 to +85°C

Notes: 1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

Package Type

36CK1

28T

36-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package.

28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP)

16

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

9. Packaging Information

9.1

36CK1

D

Marked A1 ID

E

A1 (Substrate)

A (Total PKG HGT)

0.08

Top View

Side View

A1 BALL PAD CORNER

8

7

6

5

4

3

2

1

A

B

C

D

E

COMMON DIMENSIONS

(Unit of Measure = mm)

e

MIN

6.40

3.40

0.59

0.17

NOM

6.50

MAX

6.60

3.60

0.73

0.25

NOTE

SYMBOL

D

b

E

3.50

e2

A

0.66

L1

Øb

A1

L

0.21

e1

L

e

0.70 REF

0.35 REF

0.35

2

L1

b

Bottom View

2

Øb

e

0.32

0.38

0.60 TYP

0.80 REF

0.55 REF

Notes: 1. This drawing is for general information only.

2. Metal pad dimensions.

e1

e2

3.

= > Dummy pad.

3/15/07

TITLE

DRAWING NO. REV.

36CK1

2325 Orchard Parkway

San Jose, CA 95131

36CK1, 36-Pad, 6.50 x 3.50 x 0.73 mm Body,

0.60 mm Pitch, Land Grid Array (LGA) Package

D

R

17

8024AS–AVR–04/08

9.2

28T

PIN 1

0º ~ 5º

c

Pin 1 Identifier Area

D1

D

L

b

L1

e

A2

E

GAGE PLANE

A

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

A1

MIN

–

MAX

1.20

0.15

1.05

13.60

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.90

13.20

11.70

7.90

0.50

–

1.00

Notes:

1. This package conforms to JEDEC reference MO-183.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

13.40

11.80

8.00

D1

E

11.90 Note 2

8.10

0.70

Note 2

L

0.60

L1

b

0.25 BASIC

0.22

0.17

0.10

0.27

0.21

c

–

e

0.55 BASIC

12/06/02

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline

Package, Type I (TSOP)

28T

C

R

18

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

10. Errata

10.1 ATmega8HVA

10.1.1

Rev. A

No known errata.

10.2 ATmega16HVA

10.2.1

Rev. A

19

8024AS–AVR–04/08

11. Datasheet Revision History

11.1 Rev. 8024A – 04/08

1.

Initial revision

20

ATmega8HVA/16HVA

8024AS–AVR–04/08

ATmega8HVA/16HVA

21

8024AS–AVR–04/08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8024AS–AVR–04/08


型号：	ATMEGA325P_08
厂家：	ATMEL
描述：	8-bit Microcontroller with 32K Bytes In-System Programmable Flash 8位微控制器，带有32K字节的系统内可编程闪存闪存微控制器
文件：	总22页 (文件大小：320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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