ATMEGA325V-8MUR_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– In-System Self-programmable Flash Program Memory

• 32K Bytes (ATmega325/ATmega3250)

• 64K Bytes (ATmega645/ATmega6450)

– EEPROM

8-bit

• 1K bytes (ATmega325/ATmega3250)

• 2K bytes (ATmega645/ATmega6450)

– Internal SRAM

• 2K bytes (ATmega325/ATmega3250)

• 4K bytes (ATmega645/ATmega6450)

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

Microcontroller

with In-System

Programmable

Flash

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

ATmega325/V

ATmega3250/V

ATmega645/V

ATmega6450/V

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Preliminary

Summary

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 53/68 Programmable I/O Lines

– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:

• 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega325/3250/645/6450:

• 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 350 µA

32 kHz, 1.8V: 20 µA (including Oscillator)

– Power-down Mode:

100 nA at 1.8V

1. Pin Configurations

Figure 1-1. Pinout ATmega3250/6450

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DNC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

PA3

2

PA4

INDEX CORNER

3

PA5

4

PA6

5

PA7

6

PG2

7

PC7

8

PC6

9

DNC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PH3 (PCINT19)

GND

PH2 (PCINT18)

DNC

PH1 (PCINT17)

PH0 (PCINT16)

DNC

(PCINT24) PJ0

(PCINT25) PJ1

DNC

ATmega3250/6450

DNC

PC5

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

PC4

PC3

PC2

PC1

PC0

PG1

PG0

2

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

Figure 1-2. Pinout ATmega325/645

DNC

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

PA3

48

1

2

3

PA4

PA5

PA6

47

46

45

INDEX CORNER

(XCK/AIN0/PCINT2) PE2

4

(AIN1/PCINT3) PE3

5

6

PA7

PG2

PC7

PC6

PC5

44

43

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

7

8

9

42

41

40

ATmega325/645

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0 10

(SCK/PCINT9) PB1 11

(MOSI/PCINT10) PB2 12

(MISO/PCINT11) PB3 13

39 PC4

PC3

PC2

PC1

PC0

38

37

36

(OC0A/PCINT12) PB4 14

(OC1A/PCINT13) PB5 15

(OC1B/PCINT14) PB6 16

35

34

33

PG1

PG0

Note:

The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If

the center pad is left unconnected, the package might loosen from the board.

2. Disclaimer

3. Overview

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

3

2570LS–AVR–08/07

3.1

Block Diagram

Figure 3-1. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

GND

VCC

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC

AGND

AREF

ADC

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

JTAG TAP

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

AVR CPU

UNIVERSAL

SERIAL INTERFACE

SPI

USART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

4

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte

SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface

for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters

with compare modes, internal and external interrupts, a serial programmable USART, Universal

Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable

Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power

saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI

port, and interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or

hardware reset. In Power-save mode, the asynchronous timer will continue to run, allowing the

user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction

mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize

switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is

running while the rest of the device is sleeping. This allows very fast start-up combined with low-

power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip In-System re-Programmable (ISP) Flash allows the program memory to be repro-

grammed In-System through an SPI serial interface, by a conventional non-volatile memory

programmer, or by an On-chip Boot program running on the AVR core. The Boot program can

use any interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is updated,

providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System

Self-Programmable Flash on a monolithic chip, the Atmel ATmega325/3250/645/6450 is a pow-

erful microcontroller that provides a highly flexible and cost effective solution to many embedded

control applications.

The ATmega325/3250/645/6450 AVR is supported with a full suite of program and system

development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,

In-Circuit Emulators, and Evaluation kits.

3.2

Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450

The ATmega325, ATmega3250, ATmega645, and ATmega6450 differs only in memory sizes,

pin count and pinout. Table 3-1 on page 5 summarizes the different configurations for the four

devices.

Table 3-1.

Configuration Summary

General Purpose

I/O Pins

Device

Flash

EEPROM

RAM

ATmega325

ATmega3250

ATmega645

ATmega6450

32K bytes

64K bytes

1K bytes

2K bytes

4K bytes

54

69

54

69

3.3

Pin Descriptions

The following section describes the I/O-pin special functions.

5

2570LS–AVR–08/07

3.3.1

3.3.2

3.3.3

V_CC

Digital supply voltage.

Ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port A output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

3.3.4

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega325/3250/645/6450

as listed on page 67.

3.3.5

3.3.6

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325/3250/645/6450

as listed on page 70.

3.3.7

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port E also serves the functions of various special features of the ATmega325/3250/645/6450

as listed on page 71.

6

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

3.3.8

Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-

metrical drive characteristics with both high sink and source capability. As inputs, Port F pins

that are externally pulled low will source current if the pull-up resistors are activated. The Port F

pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the

JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will

be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

3.3.9

Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port G output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port G also serves the functions of various special features of the ATmega325/3250/645/6450

as listed on page 71.

3.3.10

Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port H output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250/6450 as listed

on page 71.

3.3.11

Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port J output buffers have symmetrical drive characteristics with both high sink and source capa-

bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250/6450 as listed on

page 71.

3.3.12

3.3.13

RESET

XTAL1

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page

300. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

7

2570LS–AVR–08/07

3.3.14

3.3.15

XTAL2

AVCC

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-

nected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

3.3.16

AREF

This is the analog reference pin for the A/D Converter.

4. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note:

1.

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

8

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

6. Register Summary

Note:

Registers with bold type only available in ATmega3250/6450.

Address

Name

Reserved

PORTJ

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

-

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

-

PORTJ6

PORTJ5

PORTJ4

PORTJ3

PORTJ2

PORTJ1

PORTJ0

83

DDRJ

-

DDJ6

DDJ5

DDJ4

DDJ3

DDJ2

DDJ1

DDJ0

PINJ

-

PINJ6

PINJ5

PINJ4

PINJ3

PINJ2

PINJ1

PINJ0

PORTH

PORTH7

PORTH6

PORTH5

PORTH4

PORTH3

PORTH2

PORTH1

PORTH0

DDRH

DDH7

DDH6

DDH5

DDH4

DDH3

DDH2

DDH1

DDH0

PINH

PINH7

PINH6

PINH5

PINH4

PINH3

PINH2

PINH1

PINH0

Reserved

UDR0

-

USART0 Data Register

178

183

UBRR0H

UBRR0L

USART0 Baud Rate Register High

USART0 Baud Rate Register Low

9

2570LS–AVR–08/07

Address

Name

Reserved

UCSR0C

UCSR0B

UCSR0A

Reserved

USIDR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

-

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

-

UMSEL0

UPM01

UPM00

USBS0

UCSZ01

UCSZ00

UCPOL0

181

180

179

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

-

USI Data Register

191

192

193

USISR

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USICR

USISIE

USIOIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

Reserved

ASSR

-

EXCLK

AS2

TCN2UB

OCR2UB

TCR2UB

144

Reserved

OCR2A

-

Timer/Counter 2 Output Compare Register A

Timer/Counter2

144

TCNT2

Reserved

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

-

FOC2A

WGM20

COM2A1

COM2A0

WGM21

CS22

CS21

CS20

142

-

Timer/Counter1 Output Compare Register B High

Timer/Counter1 Output Compare Register B Low

Timer/Counter1 Output Compare Register A High

Timer/Counter1 Output Compare Register A Low

Timer/Counter1 Input Capture Register High

Timer/Counter1 Input Capture Register Low

Timer/Counter1 High

126

ICR1L

TCNT1H

10

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

Address

Name

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Timer/Counter1 Low

126

(0x84)

(0x83)

-

FOC1A

ICNC1

COM1A1

-

FOC1B

ICES1

COM1A0

-

CS12

-

125

124

122

199

216

(0x82)

-

WGM13

WGM12

CS11

WGM11

AIN1D

ADC1D

-

CS10

WGM10

AIN0D

ADC0D

-

(0x81)

COM1B1

COM1B0

-

(0x80)

-

ADC4D

-

ADC3D

-

(0x7F)

DIDR0

ADC7D

-

ADC6D

-

ADC5D

-

ADC2D

-

(0x7E)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

(0x7D)

REFS1

-

REFS0

ACME

ADSC

ADLAR

-

MUX4

-

MUX3

-

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

212

197/216

214

(0x7C)

(0x7B)

ADEN

ADATE

ADIF

ADIE

(0x7A)

ADC Data Register High

ADC Data Register Low

215

(0x79)

ADCL

215

(0x78)

Reserved

PCMSK3

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

-

(0x77)

-

(0x76)

-

(0x75)

-

(0x74)

-

PCINT30

PCINT29

PCINT28

PCINT27

PCINT26

PCINT25

PCINT24

57

(0x73)

-

(0x72)

-

(0x71)

-

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

-

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

-

145

127

98

(0x70)

-

ICIE1

-

OCIE1B

(0x6F)

-

(0x6E)

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT18

57

(0x6D)

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

58

(0x6C)

PCINT7

PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

58

(0x6B)

-

(0x6A)

ISC01

-

ISC00

-

55

(0x69)

Reserved

OSCCAL

Reserved

PRR

(0x68)

-

(0x67)

Oscillator Calibration Register [CAL7..0]

31

39

(0x66)

-

(0x65)

-

PRTIM1

PRSPI

PSUSART0

PRADC

(0x64)

Reserved

CLKPR

-

(0x63)

-

CLKPS3

WDE

V

-

(0x62)

CLKPCE

-

WDCE

S

CLKPS2

WDP2

N

CLKPS1

WDP1

Z

CLKPS0

WDP0

C

31

46

11

13

(0x61)

WDTCR

SREG

-

I

-

(0x60)

T

H

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

SPH

Stack Pointer High

Stack Pointer Low

SPL

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

-

SPMIE

RWWSB

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

262

JTD

-

PUD

-

WDRF

SM2

-

BORF

SM1

-

IVSEL

EXTRF

SM0

-

IVCE

PORF

SE

52/80/226

-

JTRF

46

34

-

Reserved

OCDR

-

OCDR5

ACO

-

OCDR4

ACI

-

IDRD/OCDR7

OCDR6

ACBG

-

OCDR3

ACIE

-

OCDR2

ACIC

-

OCDR1

ACIS1

-

OCDR0

ACIS0

-

222

197

ACSR

ACD

-

Reserved

SPDR

-

SPI Data Register

155

153

24

SPSR

SPIF

SPIE

WCOL

SPE

-

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0A

TCNT0

General Purpose I/O Register

24

-

Timer/Counter0 Output Compare A

Timer/Counter0

97

11

2570LS–AVR–08/07

Address

Name

Reserved

TCCR0A

GTCCR

EEARH

EEARL

EEDR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

-

Bit 0

-

Page

-

FOC0A

TSM

-

CS02

-

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

WGM00

COM0A1

COM0A0

WGM01

CS01

PSR2

CS00

PSR10

95

100/146

21

-

EEPROM Address Register High

EEPROM Address Register Low

EEPROM Data Register

21

EECR

-

EERIE

EEMWE

EEWE

EERE

21

GPIOR0

EIMSK

EIFR

General Purpose I/O Register

24

PCIE3

PCIF3

-

PCIE2

PCIF2

-

PCIE1

PCIF1

-

PCIE0

PCIF0

-

INT0

INTF0

-

56

-

56

Reserved

TIFR2

-

OCF2A

OCF1A

OCF0A

PORTG1

DDG1

PING1

PORTF1

DDF1

PINF1

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

TOV2

TOV1

TOV0

PORTG0

DDG0

PING0

PORTF0

DDF0

PINF0

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

146

127

98

82

83

82

81

82

81

80

TIFR1

-

ICF1

-

OCF1B

-

TIFR0

-

PORTG

DDRG

PING

-

PORTG4

DDG4

PING4

PORTF4

DDF4

PINF4

PORTE4

DDE4

PINE4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTG3

DDG3

PING3

PORTF3

DDF3

PINF3

PORTE3

DDE3

PINE3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTG2

DDG2

PING2

PORTF2

DDF2

PINF2

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

-

PING5

PORTF5

DDF5

PINF5

PORTE5

DDE5

PINE5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PORTF

DDRF

PORTF7

DDF7

PINF7

PORTE7

DDE7

PINE7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PINF

PORTE

DDRE

PINE

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64

location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only

the ST/STS/STD and LD/LDS/LDD instructions can be used.

12

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

7. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

13

2570LS–AVR–08/07

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRTC

BRVS

BRVC

BRIE

k

Branch if T Flag Cleared

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

None

BRID

Branch if Interrupt Disabled

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

14

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

Mnemonics

Operands

Description

Operation

Flags

#Clocks

IN

Rd, P

In Port

Rd ← P

None

1

2

OUT

P, Rr

Rr

Out Port

P ← Rr

None

PUSH

POP

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

15

2570LS–AVR–08/07

8. Ordering Information

8.1

ATmega325

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega325V-8AI

ATmega325V-8AU⁽²⁾

ATmega325V-8MI

ATmega325V-8MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

ATmega325-16AI

ATmega325-16AU⁽²⁾

ATmega325-16MI

ATmega325-16MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.

16

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

17

2570LS–AVR–08/07

8.2

ATmega3250

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega3250V-8AI

100A

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

2.7 - 5.5V

ATmega3250V-8AU⁽²⁾

ATmega3250-16AI

100A

Industrial

(-40°C to 85°C)

16

ATmega3250-16AU⁽²⁾

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

18

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

8.3

ATmega645

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega645V-8AI

ATmega645V-8AU⁽²⁾

ATmega645V-8MI

ATmega645V-8MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

ATmega645-16AI

ATmega645-16AU⁽²⁾

ATmega645-16MI

ATmega645-16MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

19

2570LS–AVR–08/07

8.4

ATmega6450

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega6450V-8AI

100A

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

2.7 - 5.5V

ATmega6450V-8AU⁽²⁾

ATmega6450-16AI

100A

Industrial

(-40°C to 85°C)

16

ATmega6450-16AU⁽²⁾

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed Grades see Figure 28-1 on page 298 and Figure 28-2 on page 298.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

20

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

9. Packaging Information

9.1

64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

–

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

E1

B

14.10 Note 2

0.45

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64A

B

R

21

2570LS–AVR–08/07

9.2

64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

9.10

NOM

0.90

0.02

0.25

9.00

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.18

8.90

D

D2

E

5.20

5.40

9.00

5.60

9.10

K

Pin #1

Notch

(0.20 R)

8.90

e

b

E2

e

5.20

5.40

0.50 BSC

0.40

5.60

BOTTOM VIEW

L

0.35

1.25

0.45

1.55

K

1.40

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Note:

5/25/06

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

64M1

G

R

22

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

9.3

100A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.17

0.09

0.45

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

14.10 Note 2

0.27

C

–

0.20

3. Lead coplanarity is 0.08 mm maximum.

L

–

0.75

e

0.50 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

100A

C

R

23

2570LS–AVR–08/07

10. Errata

10.1 Errata ATmega325

The revision letter in this section refers to the revision of the ATmega325 device.

10.1.1

ATmega325 Rev. C

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

10.1.2

10.1.3

ATmega325 Rev. B

Not sampled.

ATmega325 Rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

10.2 Errata ATmega3250

The revision letter in this section refers to the revision of the ATmega3250 device.

10.2.1

ATmega3250 Rev. C

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

10.2.2

ATmega3250 Rev. B

Not sampled.

24

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

10.2.3

ATmega3250 Rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

10.3 Errata ATmega645

The revision letter in this section refers to the revision of the ATmega645 device.

10.3.1

ATmega645 Rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

10.4 Errata ATmega6450

The revision letter in this section refers to the revision of the ATmega6450 device.

10.4.1

ATmega6450 Rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/ Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

25

2570LS–AVR–08/07

11. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document. The

referring revision in this section are referring to the document revision.

11.1 Rev. 2570L – 08/07

1.

Updated “Features” on page 1.

2.

3.

4.

5.

6.

Added “Data Retention” on page 8.

Updated “Serial Programming Algorithm” on page 280.

Updated “Speed Grades” on page 298.

Updated “System and Reset Characteristics” on page 300.

Updated the Register Description at the end of each chapter.

11.2 Rev. 2570K – 04/07

1.

Updated “Errata” on page 24.

11.3 Rev. 2570J – 11/06

1.

2.

Updated Table 28-7 on page 303.

Updated note in Table 28-7 on page 303.

11.4 Rev. 2570I – 07/06

1.

2.

Updated Table 15-6 on page 91.

Updated Table 15-2 on page 96, Table 15-4 on page 96, Table 17-3 on page

123, Table 17-5 on page 124, Table 18-2 on page 142 and Table 18-4 on page

143.

3.

4.

5.

6.

Updated “Fast PWM Mode” on page 114.

Updated Features in “USI – Universal Serial Interface” on page 184.

Added “Clock speed considerations.” on page 190.

Updated “Errata” on page 24.

11.5 Rev. 2570H – 06/06

1.

2.

3.

Updated “Calibrated Internal RC Oscillator” on page 28.

Updated “OSCCAL – Oscillator Calibration Register” on page 31.

Added Table 28-2 on page 299.

26

ATmega325/3250/645/6450

2570LS–AVR–08/07

ATmega325/3250/645/6450

11.6 Rev. 2570G – 04/06

1.

Updated “Calibrated Internal RC Oscillator” on page 28.

11.7 Rev. 2570F – 03/06

1.

Updated “Errata” on page 24.

11.8 Rev. 2570E – 03/06

1.

2.

3.

4.

5.

6.

7.

8.

9.

Added Addresses in Register Descriptions.

Updated number of Genearl Purpose I/O pins.

Correction of Bitnames in “Register Summary” on page 9.

Added “Resources” on page 8.

Updated “Power Management and Sleep Modes” on page 34.

Updated “Bit 0 – IVCE: Interrupt Vector Change Enable” on page 53.

Updated Introduction in “I/O-Ports” on page 59.

Updated 19.“SPI – Serial Peripheral Interface” on page 147.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 198.

10 Updated Features in “Analog to Digital Converter” on page 200.

11. Updated “Prescaling and Conversion Timing” on page 203.

12. Updated “ATmega325/3250/645/6450 Boot Loader Parameters” on page 261.

13. Updated “DC Characteristics” on page 296.

11.9 Rev. 2570D – 05/05

1.

MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame

Package QFN/MLF”.

2.

3.

4.

5.

6.

7.

8.

9.

Added “Pin Change Interrupt Timing” on page 54.

Updated “Signature Bytes” on page 267.

Updated Table 27-15 on page 281.

Added Figure 27-12 on page 283.

Updated Figure 23-9 on page 208 and Figure 27-5 on page 275.

Updated algorithm “Enter Programming Mode” on page 270.

Added “Supply Current of I/O modules” on page 310.

Updated “Ordering Information” on page 16.

11.10 Rev. 2570C – 11/04

1.

2.

3.

“0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V” on page 1 updated.

Table 9-8 on page 29 updated.

COM01:0 renamed COM0A1:0 in “8-bit Timer/Counter0 with PWM” on page

84.

27

2570LS–AVR–08/07

4.

PRR-bit descripton added to “16-bit Timer/Counter1” on page 101, “SPI –

Serial Peripheral Interface” on page 147, and “USART0” on page 156.

“Part Number” on page 224 updated.

5.

6.

7.

8.

“Typical Characteristics” on page 305 updated.

“DC Characteristics” on page 296 updated.

“Alternate Functions of Port G” on page 75 updated.

11.11 Rev. 2570B – 09/04

1.

Updated “Ordering Information” on page 16.

11.12 Rev. 2570A – 09/04

1.

Initial revision.

28

ATmega325/3250/645/6450

2570LS–AVR–08/07

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

2570LS–AVR–08/07


型号：	ATMEGA325V-8MUR
厂家：	ATMEL
描述：	暂无描述微控制器
文件：	总29页 (文件大小：780K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA325V-8MUR [ATMEL]

相关型号：

ATMEGA325_06

ATMEGA325_0611

ATMEGA325_07

ATMEGA325_14

ATMEGA328

ATMEGA328-AU

ATMEGA328-AUR

ATMEGA328-MMHR

ATMEGA328-MMHR

ATMEGA328-MU

ATMEGA328-MUR

ATMEGA328-PU