ATMEGA32U4-16MU_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 135 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

8-bit

– 16/32K Bytes of In-System Self-Programmable Flash

• Endurance: 100,000 Write/Erase Cycles

Microcontroller

with

16/32K Bytes of

ISP Flash

and USB

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program hardware activated after

reset

• True Read-While-Write Operation

• All supplied parts are preprogramed with a default USB bootloader

– 1.25/2.5K Bytes Internal SRAM

– 512Bytes/1K Bytes Internal EEPROM

• Endurance: 100,000 Write/Erase Cycles

– Programming Lock for Software Security

Controller

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification Rev 2.0

– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s

– Endpoint 0 for Control Transfers: up to 64-bytes

– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

ATmega16U4

ATmega32U4

– Configurable Endpoints size up to 256 bytes in double bank mode

– Fully independent 832 bytes USB DPRAM for endpoint memory allocation

– Suspend/Resume Interrupts

Preliminary

Summary

– CPU Reset possible on USB Bus Reset detection

– 48 MHz from PLL for Full-speed Bus Operation

– USB Bus Connection/Disconnection on Microcontroller Request

• Peripheral Features

– On-chip PLL for USB and High Speed Timer: 32 up to 96 MHz operation

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode

– One 10-bit High-Speed Timer/Counter with PLL (64 MHz) and Compare Mode

– Four 8-bit PWM Channels

– Four PWM Channels with Programmable Resolution from 2 to 16 Bits

– Six PWM Channels for High Speed Operation, with Programmable Resolution from

2 to 11 Bits

– Output Compare Modulator

– 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain)

– Programmable Serial USART with Hardware Flow Control

– Master/Slave SPI Serial Interface

7766BS–AVR–07/08

– Byte Oriented 2-wire Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change (8xPCINT + 5xINT sources)

– On-chip Temperature Sensor (see A/D Converter section)

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal 8 MHz Calibrated Oscillator

– Internal clock prescaler & On-the-fly Clock Switching (Int RC / Ext Osc)

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– All I/O combine CMOS outputs and LVTTL inputs

– 26 Programmable I/O Lines

– 44-lead TQFP Package, 10x10mm

– 44-lead QFN Package, 7x7mm

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range

– 16 MHz at 4.5V - Industrial range

2

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

1. Pin Configurations

Figure 1-1. Pinout ATmega16U4/ATmega32U4

PE2 (HWB)

33

32

31

30

29

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

(INT.6/AIN.0) PE6

PC7 (ICP3/CLK0/OC4A)

PC6 (OC3A/OC4A)

PB6 (PCINT6/OC1B/OC4B/ADC13)

PB5 (PCINT5/OC1A/OC4B/ADC12)

PB4 (PCINT4/OC2A/ADC11)

PD7 (T0/OC4D/ADC10)

PD6 (T1/OC4D/ADC9)

PD4 (ICP1/ADC8)

UVcc

INDEX CORNER

D-

D+

UGnd

UCap

AT90USB324

44-pin QFN/TQFP

VBus

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

AVCC

(PDI/PCINT2/MOSI) PB2 10

(PDO/PCINT3/MISO) PB3 11

GND

1.1

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

2. Overview

The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega16U4/ATmega32U4 achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

3

7766BS–AVR–07/08

2.1

Block Diagram

Figure 2-1. Block Diagram

PF7 - PF4

PF0

PC7

PC6

PF1

VCC

GND

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DA TA BUS

POR - BOD

RESET

INTERNAL

OSCILLATOR

CALIB. OSC

OSCILLATOR

WATCHDOG

TIMER

PROGRAM

COUNTER

STACK

POINTER

JTAG TAP

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

TIMERS/

COUNTERS

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

UVcc

UCap

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

ON-CHIP

USB PAD 3V

REGULATOR

EEPROM

TEMPERATURE

SENSOR

CONTROL

LINES

ALU

1uF

PLL

AVCC

HIGH SPEED

TIMER/PWM

ADC

AGND

AREF

STATUS

REGISTER

VBUS

DP

USB 2.0

DM

ANALOG

COMPARATOR

TWO-WIRE SERIAL

INTERFACE

USART0

SPI

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PORTE DRIVERS

PE2

PE6

PB7 - PB0

PD7 - PD0

- Subject to changes -

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega16U4/ATmega32U4 provides the following features: 16/32K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 512Bytes/1K bytes EEPROM,

1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32

general purpose working registers, four flexible Timer/Counters with compare modes and PWM,

one more high-speed Timer/Counter with compare modes and PLL adjustable source, one

USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12-

4

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip

calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI

serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip

Debug system and programming and six software selectable power saving modes. The Idle

mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system

to continue functioning. The Power-down mode saves the register contents but freezes the

Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC

Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching

noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running

while the rest of the device is sleeping. This allows very fast start-up combined with low power

consumption.

The device is manufactured using ATMEL’s high-density nonvolatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI

serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The boot program can use any interface to download the

application program in the application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the ATMEL ATmega16U4/ATmega32U4 is a powerful microcontroller that pro-

vides a highly flexible and cost effective solution to many embedded control applications.

The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system

development tools including: C compilers, macro assemblers, program debugger/simulators, in-

circuit emulators, and evaluation kits.

2.2

Pin Descriptions

2.2.1

VCC

Digital supply voltage.

2.2.2

2.2.3

GND

Ground.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega16U4/ATmega32U4

as listed on page 70.

2.2.4

Port C (PC7,PC6)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

5

7766BS–AVR–07/08

Only bits 6 and 7 are present on the product pinout.

Port C also serves the functions of special features of the ATmega16U4/ATmega32U4 as listed

on page 73.

2.2.5

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4

as listed on page 75.

2.2.6

Port E (PE6,PE2)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port E output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Only bits 2 and 6 are present on the product pinout.

Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4

as listed on page 78.

2.2.7

Port F (PF7..PF4, PF1,PF0)

Port F serves as analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers

have symmetrical drive characteristics with both high sink and source capability. As inputs, Port

F pins that are externally pulled low will source current if the pull-up resistors are activated. The

Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Bits 2 and 3 are not present on the product pinout.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-

up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

2.2.8

2.2.9

2.2.10

D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-

connector pin with a serial 22 Ohms resistor.

D+

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+

connector pin with a serial 22 Ohms resistor.

UGND

USB Pads Ground.

6

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

2.2.11

2.2.12

UVCC

UCAP

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac-

itor (1µF).

2.2.13

2.2.14

VBUS

USB VBUS monitor input.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

48. Shorter pulses are not guaranteed to generate a reset.

2.2.15

2.2.16

2.2.17

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used,

it should be externally connected to V_CC. If the ADC is used, it should be connected to V_CC

through a low-pass filter.

2.2.18

AREF

This is the analog reference pin (input) for the A/D Converter.

3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

These code examples assume that the part specific header file is included before compilation.

For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"

instructions must be replaced with instructions that allow access to extended I/O. Typically

"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

7

7766BS–AVR–07/08

8

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

4. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

Reserved

UEINT

-

EPINT6:0

-

UEBCHX

UEBCLX

UEDATX

UEIENX

UESTA1X

UESTA0X

UECFG1X

UECFG0X

UECONX

UERST

-

BYCT10:8

BYCT7:0

DAT7:0

RXSTPE

FLERRE

-

NAKINE

-

NAKOUTE

RXOUTE

CTRLDIR

STALLEDE

TXINE

-

CURRBK1:0

NBUSYBK1:0

ALLOC

CFGOK

OVERFI

UNDERFI

EPSIZE2:0

-

DTSEQ1:0

EPBK1:0

-

EPTYPE1:0

-

EPDIR

EPEN

-

STALLRQ

STALLRQC

RSTDT

-

EPRST6:0

UENUM

UEINTX

Reserved

UDMFN

-

EPNUM2:0

STALLEDI

FIFOCON

NAKINI

RWAL

NAKOUTI

RXSTPI

RXOUTI

TXINI

-

FNCERR

-

UDFNUMH

UDFNUML

UDADDR

UDIEN

FNUM10:8

FNUM7:0

ADDEN

UADD6:0

EORSTE

EORSTI

-

UPRSME

UPRSMI

-

EORSME

EORSMI

-

WAKEUPE

WAKEUPI

-

SOFE

SOFI

LSM

MSOFE

MSOFI

SUSPE

SUSPI

UDINT

UDCON

Reserved

USBINT

USBSTA

USBCON

UHWCON

Reserved

DT4

RSTCPU

RMWKUP

DETACH

-

ID

-

VBUSTI

VBUS

-

USBE

-

FRZCLK

-

OTGPADE

-

VBUSTE

UVREGE

-

DT4H3

DT4H2

DT4H1

DT4H0

DT4L3

DT4L2

DT4L1

DT4L0

Reserved

OCR4D

Timer/Counter4 - Output Compare Register D

Timer/Counter4 - Output Compare Register C

Timer/Counter4 - Output Compare Register B

Timer/Counter4 - Output Compare Register A

USART1 I/O Data Register

OCR4C

OCR4B

OCR4A

UDR1

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

CLKSTA

CLKSEL1

CLKSEL0

TCCR4E

TCCR4D

TCCR4C

TCCR4B

TCCR4A

TC4H

-

USART1 Baud Rate Register High Byte

USART1 Baud Rate Register Low Byte

-

USBS1

TXEN1

DOR1

-

UMSEL11

RXCIE1

RXC1

UMSEL10

TXCIE1

TXC1

UPM11

UDRIE1

UDRE1

-

UPM10

RXEN1

FE1

UCSZ11

UCSZ12

PE1

UCSZ10

RXB81

U2X1

UCPOL1

TXB81

MPCM1

EXTON

EXCKSEL0

CLKS

-

RCON

EXCKSEL1

-

RCCKSEL3

RCSUT1

TLOCK4

FPIE4

RCCKSEL2

RCSUT0

ENHC4

FPEN4

COM4A0S

PSR4

RCCKSEL1

EXSUT1

OC4OE5

FPNC4

COM4B1S

DTPS41

COM4B1

-

RCCKSEL0

EXSUT0

OC4OE4

FPES4

COM4B0S

DTPS40

COM4B0

-

EXCKSEL3

RCE

EXCKSEL2

EXTE

OC4OE3

FPAC4

COM4D1S

CS43

OC4OE2

FPF4

OC4OE1

WGM41

FOC4D

CS41

OC4OE0

WGM40

PWM4D

CS40

COM4A1S

PWM4X

COM4A1

-

COM4D0S

CS42

COM4A0

-

FOC4A

-

FOC4B

PWM4A

PWM4B

Timer/Counter4 High Byte

9

7766BS–AVR–07/08

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

TCNT4

TWAMR

TWCR

Timer/Counter4 - Counter Register Low Byte

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWAM0

-

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

-

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

OCR3CH

OCR3CL

OCR3BH

OCR3BL

OCR3AH

OCR3AL

ICR3H

-

Timer/Counter3 - Output Compare Register C High Byte

Timer/Counter3 - Output Compare Register C Low Byte

Timer/Counter3 - Output Compare Register B High Byte

Timer/Counter3 - Output Compare Register B Low Byte

Timer/Counter3 - Output Compare Register A High Byte

Timer/Counter3 - Output Compare Register A Low Byte

Timer/Counter3 - Input Capture Register High Byte

Timer/Counter3 - Input Capture Register Low Byte

Timer/Counter3 - Counter Register High Byte

ICR3L

TCNT3H

TCNT3L

Reserved

TCCR3C

TCCR3B

TCCR3A

Reserved

OCR1CH

OCR1CL

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

Timer/Counter3 - Counter Register Low Byte

-

FOC3A

-

ICNC3

ICES3

-

WGM33

WGM32

CS32

CS31

CS30

COM3A1

COM3A0

COM3B1

COM3B0

COM3C1

COM3C0

WGM31

WGM30

-

Timer/Counter1 - Output Compare Register C High Byte

Timer/Counter1 - Output Compare Register C Low Byte

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

-

FOC1A

ICNC1

COM1A1

-

FOC1B

ICES1

COM1A0

-

FOC1C

-

WGM13

COM1B0

-

WGM12

CS12

CS11

WGM11

-

CS10

WGM10

AIN0D

ADC0D

ADC8D

COM1B1

-

COM1C1

COM1C0

-

DIDR0

ADC7D

-

ADC6D

-

ADC5D

ADC13D

ADC4D

ADC12D

-

ADC1D

ADC9D

DIDR2

ADC11D

ADC10D

10

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7C)

(0x7B)

ADMUX

ADCSRB

ADCSRA

ADCH

REFS1

ADHSM

ADEN

REFS0

ACME

ADSC

ADLAR

MUX5

MUX4

-

MUX3

ADTS3

ADIE

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

(0x7A)

ADATE

ADIF

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

TIMSK4

TIMSK3

TIMSK2

TIMSK1

TIMSK0

Reserved

PCMSK0

EICRB

-

(0x76)

-

(0x75)

-

(0x74)

-

(0x73)

-

(0x72)

OCIE4D

OCIE4A

OCIE4B

-

TOIE4

-

(0x71)

-

ICIE3

-

OCIE3C

OCIE3B

OCIE3A

TOIE3

TOIE2

TOIE1

TOIE0

-

(0x70)

-

OCIE2B

OCIE2A

(0x6F)

-

ICIE1

-

OCIE1C

OCIE1B

OCIE1A

(0x6E)

-

OCIE0B

OCIE0A

(0x6D)

-

(0x6C)

-

PCINT5

ISC61

ISC21

-

PCINT4

ISC60

ISC20

-

(0x6B)

PCINT7

PCINT6

PCINT3

PCINT2

PCINT1

PCINT0

-

(0x6A)

-

(0x69)

EICRA

ISC31

ISC30

ISC11

ISC10

ISC01

ISC00

PCIE0

RCFREQ

(0x68)

PCICR

-

(0x67)

RCCTRL

OSCCAL

PRR1

-

(0x66)

RC Oscillator Calibration Register

(0x65)

PRUSB

-

PRTIM4

PRTIM3

-

PRUSART1

(0x64)

PRR0

PRTWI

PRTIM2

PRTIM0

-

PRTIM1

PRSPI

-

PRADC

(0x63)

Reserved

CLKPR

-

(0x62)

-

CLKPS1

WDP1

Z

-

(0x61)

CLKPCE

-

CLKPS3

CLKPS2

CLKPS0

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

I

T

H

S

V

N

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP1

-

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP0

Reserved

RAMPZ

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

-

RAMPZ1

-

RAMPZ0

-

RWWSRE

-

SPMIE

RWWSB

SIGRD

BLBSET

-

PGWRT

-

PGERS

-

SPMEN

-

JTD

-

PUD

-

IVSEL

EXTRF

SM0

PDIV1

OCDR1

IVCE

PORF

SE

-

USBRF

-

JTRF

-

WDRF

SM2

PDIV3

OCDR3

BORF

SM1

PDIV2

OCDR2

-

PLLFRQ

PINMUX

OCDR7

PLLUSB

OCDR6

PLLTM1

OCDR5

PLLTM0

OCDR4

PDIV0

OCDR0

OCDR/

MONDR

0x31 (0x51)

Monitor Data Register

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

ACSR

Reserved

SPDR

ACD

-

ACBG

-

ACO

-

ACI

-

ACIE

-

ACIC

-

ACIS1

-

ACIS0

-

SPI Data Register

-

SPSR

SPIF

SPIE

WCOL

SPE

-

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

PLLCSR

OCR0B

OCR0A

TCNT0

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

EEDR

General Purpose I/O Register 2

General Purpose I/O Register 1

-

PINDIV

-

PLLE

PLOCK

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit)

FOC0A

COM0A1

TSM

FOC0B

-

WGM02

CS02

CS01

CS00

COM0A0

COM0B1

COM0B0

-

WGM01

PSRASY

WGM00

-

PSRSYNC

-

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

EECR

-

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

EIMSK

EIFR

General Purpose I/O Register 0

-

INT6

-

INT3

INT2

INT1

INT0

INTF6

INTF3

INTF2

INTF1

INTF0

11

7766BS–AVR–07/08

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

PCIFR

Reserved

TIFR4

-

PCIF0

-

OCF4D

OCF4A

OCF4B

-

TOV4

-

TIFR3

-

ICF3

-

OCF3C

OCF3B

OCF3A

TOV3

TIFR2

-

OCF2B

OCF2A

TOV2

TIFR1

-

ICF1

-

OCF1C

OCF1B

OCF1A

TOV1

TIFR0

-

OCF0B

OCF0A

TOV0

Reserved

PORTF

DDRF

-

PORTF7

DDF7

PINF7

-

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

-

PORTF5

PORTF4

-

PORTF1

PORTF0

DDF5

DDF4

-

DDF1

DDF0

PINF

PINF5

PINF4

-

PINF1

PINF0

PORTE

DDRE

-

PORTE2

-

DDE2

-

PINE

-

PINE2

-

PORTD

DDRD

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

-

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

PIND

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

PORTC

DDRC

-

PINC

-

PORTB

DDRB

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

PINB

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

-

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O reg-

isters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega16U4/ATmega32U4

is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for

the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

12

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

5. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Clear Register

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

PC ← PC + k + 1

PC ← Z

None

I

2

PC ←(EIND:Z)

EIJMP

JMP

Extended Indirect Jump to (Z)

Direct Jump

2

k

PC ← k

PC ← PC + k + 1

PC ← Z

3

RCALL

ICALL

EICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

4

PC ←(EIND:Z)

Extended Indirect Call to (Z)

Direct Subroutine Call

Subroutine Return

4

k

PC ← k

5

PC ← STACK

5

RETI

Interrupt Return

PC ← STACK

5

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

k

13

7766BS–AVR–07/08

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

k

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd ← (X)

LD

Rd, X

Load Indirect

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

ELPM

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Extended Load Program Memory

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (Z)

Rd, Z

Rd, Z+

Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1

14

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SPM

IN

Store Program Memory

In Port

(Z) ← R1:R0

Rd ← P

None

-

Rd, P

P, Rr

Rr

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

No Operation

Sleep

None

1

(see specific description for Sleep function)

(see specific description for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

15

7766BS–AVR–07/08

16

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

6. Ordering Information

Table 6-1.

Possible Order Entries

USB

interface

Speed

(MHz)

Power Supply

(V)

Ordering Code

Package

Operation Range

Product Marking

Device

only

Industrial (-40° to +85°C)

Green

8-16

2.7 - 5.5

TQFP44

mega32U4-16AU

ATmega32U4-16AU

ATmega32U4-16MU

Device

only

Industrial (-40° to +85°C)

Green

QFN44

mega32U4-16MU

7. Package Information

Package Type

ML

ML, 44 - Lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

PW, 44 - Lead 7.0 x 7.0 mm Body, 0.50 mm Pitch

Quad Flat No Lead Package (QFN)

PW

17

7766BS–AVR–07/08

7.1

TQFP44

18

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

19

7766BS–AVR–07/08

7.2

QFN44

20

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

ATmega16U4/ATmega32U4

8. Errata

The revision letter in this section refers to the revision of the ATmega16U4/ATmega32U4

device.

8.1

ATmega16U4/ATmega32U4 Rev A

1. Spike on TWI pins when TWI is enabled

100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.

Problem Fix/work around

No known work around, enable ATmega16U4/ATmega32U4 TWI first versus the others

nodes of the TWI network.

2. High current consumption in sleep mode

If a pending interrupt cannot wake the part up from the selected mode, the current consump-

tion will increase during sleep when executing the SLEEP instruction directly after a SEI

instruction.

Problem Fix/work around

Before entering sleep, interrupts not used to wake up the part from the sleep mode should

be disabled.

3. Extra power comsumption

The typical power comsumption is increased by about 30µA in power-down mode.

Problem Fix/work around

None.

4. Internal RC oscillator start up issue.

When the part is configured to start on internal RC, the oscillator may not start properly after

power-on.

Problem Fix/work around

Do not configure the part to start with the internal oscillator (default part configuration is to

start with the external crystal oscillator).

5. Internal RC oscillator calibration issue.

The default internal RC oscillator frequency may be lower that 8MHz.

Problem Fix/work around

Parts are configured so that the internal RC oscillator frequency is as close as possible to

the 8MHz default target frequency.

21

7766BS–AVR–07/08

9. Datasheet Revision History for ATmega16U4/ATmega32U4

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

9.1

9.2

Revision A.

Revision B.

1. Initial document version.

1. Added ATmega16U4 device.

2. Created errata section and added ATmega16U4.

3. Update High Speed Timer, asynchronous description Section 15. on page 139.

22

ATmega16U4/ATmega32U4

7766BS–AVR–07/08

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7766BS–AVR–07/08


型号：	ATMEGA32U4-16MU
厂家：	ATMEL
描述：	8-bit Microcontroller with 16/32K Bytes of ISP Flash and USB Controller 8位微控制器具有ISP功能的Flash和USB控制器16 / 32K字节闪存微控制器和处理器外围集成电路异步传输模式 ATM 时钟
文件：	总23页 (文件大小：557K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA32U4-16MU [ATMEL]

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