ATMEGA48P-20MMUR_技术文档

Features

• High Performance, Low Power Atmel^®AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 4/8/16KBytes of In-System Self-Programmable Flash progam memory

– 256/512/512Bytes EEPROM

– 512/1K/1KBytes Internal SRAM

8-bit Atmel

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 4/8/16K

Bytes In-System

Programmable

Flash

– Programming Lock for Software Security

• QTouch^®library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

Temperature Measurement

ATmega48P/V

ATmega88P/V

ATmega168P/V

– 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I²C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

Summary

• I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating Voltage:

– 1.8 - 5.5V for ATmega48P/88P/168PV

– 2.7 - 5.5V for ATmega48P/88P/168P

• Temperature Range:

– -40°C to 85°C

• Speed Grade:

– ATmega48P/88P/168PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V

– ATmega48P/88P/168P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

• Low Power Consumption at 1MHz, 1.8V, 25°C:

– Active Mode: 0.3mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.8µA (Including 32kHz RTC)

Note:

1. See ”Data Retention” on page 8 for details.

Rev. 8025MS–AVR–6/11

ATmega48P/88P/168P

1. Pin Configurations

Figure 1-1. Pinout ATmega48P/88P/168P

PDIP

TQFP Top View

(PCINT14/RESET) PC6

(PCINT16/RXD) PD0

(PCINT17/TXD) PD1

(PCINT18/INT0) PD2

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

1

2

3

4

5

6

7

8

9

28 PC5 (ADC5/SCL/PCINT13)

27 PC4 (ADC4/SDA/PCINT12)

26 PC3 (ADC3/PCINT11)

25 PC2 (ADC2/PCINT10)

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 GND

(PCINT19/OC2B/INT1) PD3

1

2

3

4

5

6

7

8

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 ADC7

(PCINT20/XCK/T0) PD4

GND

VCC

GND

21 GND

20 AREF

GND

21 AREF

VCC

19 ADC6

(PCINT6/XTAL1/TOSC1) PB6

20 AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

18 AVCC

(PCINT7/XTAL2/TOSC2) PB7 10

(PCINT21/OC0B/T1) PD5 11

(PCINT22/OC0A/AIN0) PD6 12

(PCINT23/AIN1) PD7 13

19 PB5 (SCK/PCINT5)

18 PB4 (MISO/PCINT4)

17 PB3 (MOSI/OC2A/PCINT3)

16 PB2 (SS/OC1B/PCINT2)

15 PB1 (OC1A/PCINT1)

17 PB5 (SCK/PCINT5)

(PCINT0/CLKO/ICP1) PB0 14

32 MLF Top View

28 MLF Top View

(PCINT19/OC2B/INT1) PD3

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

1

2

3

4

5

6

7

21

20

19

18

17

16

15

(PCINT20/XCK/T0) PD4

GND

VCC

GND

AREF

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

AREF

VCC

ADC6

AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

2

8025MS–AVR–6/11

ATmega48P/88P/168P

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page

80 and ”System Clock and Clock Options” on page 27.

1.1.4

1.1.5

Port C (PC5:0)

PC6/RESET

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5:0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 29-3 on page 314. Shorter pulses are not guaran-

teed to generate a Reset.

The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page

83.

1.1.6

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

3

8025MS–AVR–6/11

ATmega48P/88P/168P

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page

86.

1.1.7

AV_CC

AV_CCis the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally

connected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter. Note that PC6:4 use digital supply voltage, V_CC

.

1.1.8

1.1.9

AREF

AREF is the analog reference pin for the A/D Converter.

ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

2. Overview

The ATmega48P/88P/168P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48P/88P/168P achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

4

8025MS–AVR–6/11

ATmega48P/88P/168P

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

PROGRAM

LOGIC

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

AVCC

AREF

GND

2

8bit T/C 0

8bit T/C 2

16bit T/C 1

A/D Conv.

Analog

Comp.

Internal

Bandgap

6

USART 0

PORT D (8)

PD[0..7]

SPI

PORT B (8)

PB[0..7]

TWI

PORT C (7)

PC[0..6]

RESET

XTAL[1..2]

ADC[6..7]

5

8025MS–AVR–6/11

ATmega48P/88P/168P

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48P/88P/168P provides the following features: 4K/8K/16Kbytes of In-System Pro-

grammable Flash with Read-While-Write capabilities, 256/512/512bytes EEPROM,

512/1K/1Kbytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers,

three flexible Timer/Counters with compare modes, internal and external interrupts, a serial pro-

grammable USART, a byte-oriented, 2-wire Serial Interface, an SPI serial port, a 6-channel 10-

bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with

internal Oscillator, and five software selectable power saving modes. The Idle mode stops the

CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.

In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise dur-

ing ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest

of the device is sleeping. This allows very fast start-up combined with low power consumption.

Atmel offers the QTouch^®library for embedding capacitive touch buttons, sliders and wheels

functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers

robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key

Suppression^®(AKS™) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48P/88P/168P is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications.

The ATmega48P/88P/168P AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit

Emulators, and Evaluation kits.

6

8025MS–AVR–6/11

ATmega48P/88P/168P

2.2

Comparison Between ATmega48P, ATmega88P and ATmega168P

The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader sup-

port, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector

sizes for the three devices.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

RAM

Interrupt Vector Size

1 instruction word/vector

2 instruction words/vector

ATmega48P

ATmega88P

ATmega168P

4KBytes

8KBytes

16KBytes

256Bytes

512Bytes

1KBytes

ATmega88P and ATmega168P support a real Read-While-Write Self-Programming mechanism.

There is a separate Boot Loader Section, and the SPM instruction can only execute from there.

In ATmega48P, there is no Read-While-Write support and no separate Boot Loader Section.

The SPM instruction can execute from the entire Flash.

7

8025MS–AVR–6/11

ATmega48P/88P/168P

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

6. Capacitive touch sensing

The Atmel^®QTouch^®Library provides a simple to use solution to realize touch sensitive inter-

faces on most Atmel AVR^®microcontrollers. The QTouch Library includes support for the

QTouch and QMatrix^®acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library

for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-

nels and sensors, and then calling the touch sensing API’s to retrieve the channel information

and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the

Atmel QTouch Library User Guide - also available for download from the Atmel website.

8

8025MS–AVR–6/11

ATmega48P/88P/168P

7. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

Reserved

UDR0

–

USART I/O Data Register

193

197

UBRR0H

UBRR0L

Reserved

UCSR0C

USART Baud Rate Register High

USART Baud Rate Register Low

–

UCSZ01 /UDORD0

UCSZ00 / UCPHA0

UMSEL01

UMSEL00

UPM01

UPM00

USBS0

UCPOL0

195/210

9

8025MS–AVR–6/11

ATmega48P/88P/168P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xC1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

UCSR0B

UCSR0A

Reserved

TWAMR

TWCR

RXCIE0

RXC0

–

TXCIE0

TXC0

–

UDRIE0

UDRE0

–

RXEN0

FE0

TXEN0

DOR0

–

UCSZ02

UPE0

–

RXB80

TXB80

194

193

U2X0

MPCM0

–

TWAM0

–

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

–

242

239

241

242

241

239

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

–

AS2

–

TCN2UB

–

OCR2AUB

–

OCR2BUB

–

TCR2AUB

–

TCR2BUB

–

EXCLK

–

162

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8-bit)

160

159

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

–

WGM22

CS22

–

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

156

–

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

136

137

136

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

Timer/Counter1 - Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

FOC1B

ICES1

COM1A0

–

WGM12

–

135

134

132

WGM13

COM1B0

CS12

–

CS11

WGM11

CS10

WGM10

COM1B1

10

8025MS–AVR–6/11

ATmega48P/88P/168P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7F)

(0x7E)

DIDR1

DIDR0

–

ADC3D

–

AIN1D

ADC1D

–

AIN0D

ADC0D

–

247

264

–

ADC5D

–

ADC4D

ADC2D

–

(0x7D)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

–

(0x7C)

REFS1

–

REFS0

ACME

ADSC

ADLAR

–

MUX3

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

260

263

261

263

(0x7B)

–

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

–

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

–

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

–

161

137

109

72

(0x6F)

–

ICIE1

–

(0x6E)

–

PCINT19

PCINT11

PCINT3

–

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

(0x6C)

–

PCINT14

PCINT13

PCINT12

72

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

72

(0x6A)

–

(0x69)

ISC11

–

ISC10

PCIE2

–

ISC01

PCIE1

–

ISC00

PCIE0

–

69

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

–

(0x66)

Oscillator Calibration Register

38

43

(0x65)

–

(0x64)

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

38

55

10

13

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

I

T

H

S

V

N

Z

C

SPH

–

(SP10) ^5.

SP9

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

PGERS

–

SPMIE

(RWWSB)^5.

–

(RWWSRE)^5.

BLBSET

PGWRT

SELFPRGEN

289

–

PUD

–

IVCE

PORF

SE

BODS

BODSE

IVSEL

EXTRF

SM0

–

45/66/90

55

–

WDRF

SM2

–

BORF

SM1

–

41

Reserved

ACSR

–

ACBG

–

ACD

–

ACO

–

ACI

–

ACIE

–

ACIC

–

ACIS1

–

ACIS0

–

245

Reserved

SPDR

SPI Data Register

173

172

171

26

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

26

–

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8-bit)

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

COM0A0

–

COM0B1

–

COM0B0

–

WGM02

CS02

CS01

CS00

–

WGM01

PSRASY

WGM00

PSRSYNC

141/163

22

(EEPROM Address Register High Byte) ^5.

EEPROM Address Register Low Byte

EEPROM Data Register

22

EEDR

22

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

22

GPIOR0

General Purpose I/O Register 0

26

11

8025MS–AVR–6/11

ATmega48P/88P/168P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x0 (0x20)

EIMSK

EIFR

–

INT1

INT0

70

–

INTF1

INTF0

PCIFR

–

PCIF2

PCIF1

PCIF0

Reserved

TIFR2

–

OCF2B

OCF2A

TOV2

161

138

TIFR1

–

ICF1

–

OCF1B

OCF1A

TOV1

TIFR0

–

OCF0B

OCF0A

TOV0

Reserved

PORTD

DDRD

–

PORTD7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

91

90

DDD7

PIND

PIND7

PORTC

DDRC

–

PINC

–

PORTB

DDRB

PORTB7

DDB7

PINB

PINB7

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48P/88P/168P

is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for

the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

5. Only valid for ATmega88P/168P.

12

8025MS–AVR–6/11

ATmega48P/88P/168P

8. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

IJMP

Indirect Jump to (Z)

PC ← Z

JMP⁽¹⁾

RCALL

ICALL

CALL⁽¹⁾

RET

k

Direct Jump

PC ← k

3

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

13

8025MS–AVR–6/11

ATmega48P/88P/168P

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

Out Port

P ← Rr

Push Register on Stack

STACK ← Rr

14

8025MS–AVR–6/11

ATmega48P/88P/168P

Mnemonics

Operands

Description

Operation

Flags

#Clocks

POP

Rd

Pop Register from Stack

Rd ← STACK

None

2

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

Note:

1. These instructions are only available in ATmega168P.

15

8025MS–AVR–6/11

ATmega48P/88P/168P

9. Ordering Information

9.1

ATmega48P

Speed (MHz)

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega48PV-10AU

32A

ATmega48PV-10AUR⁽⁴⁾

ATmega48PV-10MMU

ATmega48PV-10MMUR⁽⁴⁾

ATmega48PV-10MU

ATmega48PV-10MUR⁽⁴⁾

ATmega48PV-10PU

32A

28M1

32M1-A

28P3

10⁽³⁾

1.8 - 5.5

Industrial

(-40°C to 85°C)

ATmega48P-20AU

32A

ATmega48P-20AUR⁽⁴⁾

ATmega48P-20MMU

ATmega48P-20MMUR⁽⁴⁾

ATmega48P-20MU

ATmega48P-20MUR⁽⁴⁾

ATmega48P-20PU

28M1

32M1-A

28P3

20⁽³⁾

2.7 - 5.5

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 29-1 on page 312 and Figure 29-2 on page 312.

4. Tape & Reel

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

16

8025MS–AVR–6/11

ATmega48P/88P/168P

9.2

ATmega88P

Speed (MHz)

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega88PV-10AU

ATmega88PV-10AUR⁽⁴⁾

ATmega88PV-10MU

ATmega88PV-10MUR⁽⁴⁾

ATmega88PV-10PU

32A

32M1-A

28P3

10⁽³⁾

1.8 - 5.5

Industrial

(-40°C to 85°C)

ATmega88P-20AU

ATmega88P-20AUR⁽⁴⁾

ATmega88P-20MU

ATmega88P-20MUR⁽⁴⁾

ATmega88P-20PU

32A

32M1-A

28P3

20⁽³⁾

2.7 - 5.5

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 29-1 on page 312 and Figure 29-2 on page 312.

4. Taper & Reel.

Package Type

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32A

28P3

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

17

8025MS–AVR–6/11

ATmega48P/88P/168P

9.3

ATmega168P

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega168PV-10AU

ATmega168PV-10AUR⁽⁴⁾

ATmega168PV-10MU

ATmega168PV-10MUR⁽⁴⁾

ATmega168PV-10PU

32A

32M1-A

28P3

10

20

1.8 - 5.5

Industrial

(-40°C to 85°C)

ATmega168P-20AU

ATmega168P-20AUR⁽⁴⁾

ATmega168P-20MU

ATmega168P-20MUR⁽⁴⁾

ATmega168P-20PU

32A

32M1-A

28P3

2.7 - 5.5

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 29-1 on page 312 and Figure 29-2 on page 312.

4. Taper & Reel.

Package Type

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32A

28P3

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

18

8025MS–AVR–6/11

ATmega48P/88P/168P

10. Packaging Information

10.1 32A

PIN 1 IDENTIFIER

PIN 1

e

B

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

E1

B

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

3. Lead coplanarity is 0.10 mm maximum.

L

–

e

0.80 TYP

2010-10-20

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

C

R

19

8025MS–AVR–6/11

ATmega48P/88P/168P

10.2 28M1

D

C

1

2

3

Pin 1 ID

E

SIDE VIEW

A1

TOP VIEW

A

y

K

D2

0.45

E2

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

3

R 0.20

MIN

MAX

NOM

NOTE

SYMBOL

A

0.80

0.90

1.00

A1

b

0.00

0.17

0.02

0.22

0.20 REF

4.00

2.40

4.00

2.40

0.45

0.40

–

0.05

0.27

b

C

D

D2

E

3.95

2.35

3.95

2.35

4.05

2.45

4.05

2.45

L

e

E2

e

0.4 Ref

(4x)

BOTTOM VIEW

L

0.35

0.00

0.20

0.45

0.08

–

y

K

–

The terminal #1 ID is a Laser-marked Feature.

Note:

10/24/08

GPC

DRAWING NO.

TITLE

REV.

28M1, 28-pad,4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 x 2.4 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

ZBV

28M1

B

20

8025MS–AVR–6/11

ATmega48P/88P/168P

10.3 32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

0.08

C

(Unit of Measure = mm)

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

21

8025MS–AVR–6/11

ATmega48P/88P/168P

10.4 28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

22

8025MS–AVR–6/11

ATmega48P/88P/168P

11. Errata

11.1 Errata ATmega48P

The revision letter in this section refers to the revision of the ATmega48P device.

11.1.1

11.1.2

11.1.3

Rev. C

Rev. B

Rev. A

No known errata.

Not Sampled.

11.2 Errata ATmega88P

The revision letter in this section refers to the revision of the ATmega88P device.

11.2.1

11.2.2

11.2.3

Rev. C

Rev. B

Rev. A

Not sampled.

No known errata.

11.3 Errata ATmega168P

The revision letter in this section refers to the revision of the ATmega168P device.

11.3.1

11.3.2

Rev B

Rev A

No known errata.

23

8025MS–AVR–6/11

ATmega48P/88P/168P

12. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

12.1 Rev. 8025M-06/11

1.

Added Atmel QTouch Library Support and QTouch Sensing Capability Features.

Updated “Ordering Information” to include Tape and Reel devices.

2.

3.

Updated the datasheet with Atmel new style guide.

12.2 Rev. 8025L-07/10

1.

2.

Removed from the front page, the note “Not recommended for new design”.

Editorial updates.

12.3 Rev. 8025K-10/09

1.

2.

Updated “Low Frequency Crystal Oscillator” with the Table 9-8 on page 33.

Editorial updates.

12.4 Rev. 8025J-05/09

1.

2.

3.

Removed the “About” section.

Removed ATmega328P device and its reference from the data sheet.

Editorial updates.

12.5 Rev. 8025I-02/09

1.

Removed “preliminary” from ATmega48P/88P/168P.

12.6 Rev. 8025H-02/09

1.

2.

3.

Added Power-save Maximum values and footnote to ”ATmega48P DC Characteris-

tics” on page 310.

Added Power-save Maximum values and footnote to ”ATmega88P DC Characteris-

tics” on page 311.

Added Power-save Maximum values and footnote to ”ATmega168P DC Characteris-

tics” on page 311.

4.

5.

Added Power-save Maximum values and footnote to ”” on page 312.

Added errata for revision A, ”” on page 23.

24

8025MS–AVR–6/11

ATmega48P/88P/168P

12.7 Rev. 8025G-01/09

1

ATmega48P/88P not recommended for new designs.

2.

3.

4.

5.

6.

Updated the footnote Note1 of the Table 9-3 on page 30.

Updated the Table 9-5 on page 31 by removing a footnote Note1.

Updated the Table 9-11 on page 34 by removing a footnote Note1.

Updated the footnote Note1 of the Table 9-13 on page 35.

Updated the footnote Note2 of the ”ATmega48P DC Characteristics” on page 310

and removed TBD from the table.

7.

8.

Updated the footnote Note2 of the ”ATmega88P DC Characteristics” on page 311

and removed TBD from the table.

Updated the footnote Note2 of the ”ATmega168P DC Characteristics” on page 311

and removed TBD from the table.

9.

Updated the footnote Note2 of the ”” on page 312 and removed TBD from the table.

Updated the footnote Note1 of the Table 29-4 on page 314.

Replaced the Figure 30-69 on page 358 by a correct one.

Replaced the Figure 29-173 on page 419 by a correct one.

Updated ”Errata” on page 23.

10.

11.

12.

13.

14.

15.

Updated ”MCUCR – MCU Control Register” on page 44.

Updated ”TCCR2B – Timer/Counter Control Register B” on page 159.

12.8 Rev. 8025F-08/08

1.

2.

Updated ”Register Summary” on page 9 with Power-save numbers.

Added ATmega328P ”Standby Supply Current” on page 408.

12.9 Rev. 8025E-08/08

1.

2.

Updated description of ”Stack Pointer” on page 13.

Updated description of use of external capacitors in ”Low Frequency Crystal Oscilla-

tor” on page 33.

3.

4.

5.

6.

Updated Table 9-10 in ”Low Frequency Crystal Oscillator” on page 33.

Added note to ”Address Match Unit” on page 220.

Added section ”Reading the Signature Row from Software” on page 283.

Updated ”Program And Data Memory Lock Bits” on page 291 to include

ATmega328P in the description.

7.

8.

9.

Added ”” on page 312.

Updated ”Speed Grades” on page 312 for ATmega328P.

Removed note 6 and 7 from the table ”2-wire Serial Interface Characteristics” on

page 317.

10.

11.

12.

13.

14.

Added figure ”Minimum Reset Pulse width vs. V_CC.” on page 346 for ATmega48P.

Added figure ”Minimum Reset Pulse width vs. V_CC.” on page 370 for ATmega88P.

Added figure ”Minimum Reset Pulse width vs. V_CC.” on page 394 for ATmega168P.

Added ”Register Summary” on page 9.

Updated Ordering Information for ”Packaging Information” on page 19.

25

8025MS–AVR–6/11

ATmega48P/88P/168P

12.10 Rev. 8025D-03/08

1.

2.

3.

Updated figures in ”Speed Grades” on page 312.

Updated note in Table 29-4 in ”System and Reset Characteristics” on page 314.

Ordering codes for ”Packaging Information” on page 19 updated.

- ATmega328P is offered in 20 MHz option only.

4.

Added Errata for ATmega328P rev. B, ”” on page 23.

12.11 Rev. 8025C-01/08

1.

Power-save Maximum values removed form ”ATmega48P DC Characteristics” on

page 310, ”ATmega88P DC Characteristics” on page 311, and ”ATmega168P DC

Characteristics” on page 311.

12.12 Rev. 8025B-01/08

Updated ”Features” on page 1.

Added ”Data Retention” on page 8.

Updated Table 9-2 on page 29.

1.

2.

3.

Removed “Low-frequency Crystal Oscillator Internal Load Capacitance“ table

from”Low Frequency Crystal Oscillator” on page 33.

Removed JTD bit from ”MCUCR – MCU Control Register” on page 45.

4.

5.

Updated typical and general program setup for Reset and Interrupt Vector Addresses

in ”Interrupt Vectors in ATmega168P” on page 63 and ”Interrupt Vectors in

ATmega328P” on page 65.

Updated Interrupt Vectors Start Address in Table 12-5 on page 64 and Table 11-7 on

page 66.

6.

7.

Updated ”Temperature Measurement” on page 259.

8.

9.

Updated ATmega328P ”Fuse Bits” on page 292.

Removed V_OL3/V_OH3rows from ”DC Characteristics” on page 309.

Updated condition for V_OLin ”DC Characteristics” on page 309.

Updated max value for V_IL2in ”DC Characteristics” on page 309.

10.

11.

Added ”ATmega48P DC Characteristics” on page 310, ”ATmega88P DC Characteris-

tics” on page 311, and ”ATmega168P DC Characteristics” on page 311.

Updated ”System and Reset Characteristics” on page 314.

12.

13.

Added ”ATmega48P Typical Characteristics” on page 322, ”ATmega88P Typical

Characteristics” on page 346, and ”ATmega168P Typical Characteristics” on page

370.

14.

15.

Updated note in ”Instruction Set Summary” on page 13.

12.13 Rev. 8025A-07/07

1.

Initial revision.

26

8025MS–AVR–6/11

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: (+1)(408) 441-0311

Fax: (+1)(408) 487-2600

www.atmel.com

Atmel Asia Limited

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

HONG KONG

Atmel Munich GmbH

Business Campus

Parkring 4

D-85748 Garching b. Munich

GERMANY

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

JAPAN

Tel: (+81)(3) 3523-3551

Fax: (+81)(3) 3523-7581

Tel: (+49) 89-31970-0

Fax: (+49) 89-3194621

Tel: (+852) 2245-6100

Fax: (+852) 2722-1369

Atmel^®, Atmel logo and combinations thereof, AVR^®, QTouch^®, QMatrix^®, AVR Studio^®and others are registered trademarks or trade-

marks of Atmel Corporation or its subsidiaries. Windows^®and others are registered trademarks of Microsoft Corporation in U.S. and

other countries. Other terms and product names may be trademarks of others.

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to

any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL

TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY

EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF

MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,

INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROF-

ITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL

HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or com-

pleteness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.

Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suit-

able for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applica-

tions intended to support or sustain life.

8025MS–AVR–6/11


型号：	ATMEGA48P-20MMUR
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28 时钟微控制器外围集成电路闪存
文件：	总27页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA48P-20MMUR [ATMEL]

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