ATMEGA48V-10MMU-SL383

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 4/8/16K Bytes of In-System Self-programmable Flash program memory

– 256/512/512 Bytes EEPROM

8-bit

– 512/1K/1K Bytes Internal SRAM

– Write/Erase cyles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

– 6-channel 10-bit ADC in PDIP Package

– Programmable Serial USART

ATmega48/V

ATmega88/V

ATmega168/V

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I²C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby

• I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating Voltage:

– 1.8 - 5.5V for ATmega48V/88V/168V

– 2.7 - 5.5V for ATmega48/88/168

• Temperature Range:

– -40°C to 85°C

• Speed Grade:

– ATmega48V/88V/168V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega48/88/168: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Low Power Consumption

– Active Mode:

250 µA at 1 MHz, 1.8V

15 µA at 32 kHz, 1.8V (including Oscillator)

– Power-down Mode:

0.1µA at 1.8V

Rev. 2545M–AVR–09/07

1. Pin Configurations

Figure 1-1. Pinout ATmega48/88/1682545M

PDIP

TQFP Top View

(PCINT14/RESET) PC6

(PCINT16/RXD) PD0

(PCINT17/TXD) PD1

(PCINT18/INT0) PD2

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

1

2

3

4

5

6

7

8

9

28 PC5 (ADC5/SCL/PCINT13)

27 PC4 (ADC4/SDA/PCINT12)

26 PC3 (ADC3/PCINT11)

25 PC2 (ADC2/PCINT10)

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 GND

(PCINT19/OC2B/INT1) PD3

1

2

3

4

5

6

7

8

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 ADC7

(PCINT20/XCK/T0) PD4

GND

VCC

GND

21 GND

20 AREF

GND

21 AREF

VCC

19 ADC6

(PCINT6/XTAL1/TOSC1) PB6

20 AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

18 AVCC

(PCINT7/XTAL2/TOSC2) PB7 10

(PCINT21/OC0B/T1) PD5 11

(PCINT22/OC0A/AIN0) PD6 12

(PCINT23/AIN1) PD7 13

19 PB5 (SCK/PCINT5)

18 PB4 (MISO/PCINT4)

17 PB3 (MOSI/OC2A/PCINT3)

16 PB2 (SS/OC1B/PCINT2)

15 PB1 (OC1A/PCINT1)

17 PB5 (SCK/PCINT5)

(PCINT0/CLKO/ICP1) PB0 14

32 MLF Top View

28 MLF Top View

(PCINT19/OC2B/INT1) PD3

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

1

2

3

4

5

6

7

21

20

19

18

17

16

15

(PCINT20/XCK/T0) PD4

GND

VCC

GND

AREF

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

AREF

VCC

ADC6

AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

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ATmega48/88/168

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

79 and “System Clock and Clock Options” on page 28.

1.1.4

1.1.5

Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5..0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 28-3 on page 308. Shorter pulses are not guaran-

teed to generate a Reset.

The various special features of Port C are elaborated in “Alternate Functions of Port C” on page

82.

1.1.6

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

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2545M–AVR–09/07

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

The various special features of Port D are elaborated in “Alternate Functions of Port D” on page

85.

1.1.7

AV_CC

AV_CCis the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally

connected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter. Note that PC6..4 use digital supply voltage, V_CC

.

1.1.8

1.1.9

AREF

AREF is the analog reference pin for the A/D Converter.

ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

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ATmega48/88/168

2. Overview

The ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

PROGRAM

LOGIC

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

AVCC

AREF

GND

2

8bit T/C 0

8bit T/C 2

16bit T/C 1

A/D Conv.

Analog

Comp.

Internal

Bandgap

6

USART 0

PORT D (8)

PD[0..7]

SPI

PORT B (8)

PB[0..7]

TWI

PORT C (7)

PC[0..6]

RESET

XTAL[1..2]

ADC[6..7]

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

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architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Program-

mable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes

SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial programmable

USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8

channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal

Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and inter-

rupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset.

In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a

timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the

CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise dur-

ing ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest

of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48/88/168 is a powerful microcontroller that provides a highly

flexible and cost effective solution to many embedded control applications.

The ATmega48/88/168 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-

lators, and Evaluation kits.

2.2

Comparison Between ATmega48, ATmega88, and ATmega168

The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support,

and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes

for the three devices.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

RAM

Interrupt Vector Size

1 instruction word/vector

2 instruction words/vector

ATmega48

ATmega88

ATmega168

4K Bytes

8K Bytes

16K Bytes

256 Bytes

512 Bytes

1K Bytes

ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism.

There is a separate Boot Loader Section, and the SPM instruction can only execute from there.

In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The

SPM instruction can execute from the entire Flash.

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ATmega48/88/168

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

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2545M–AVR–09/07

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATmega48/88/168

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

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6. AVR CPU Core

6.1

Overview

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

6.2

Architectural Overview

Figure 6-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

Interrupt

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

SPI

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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ATmega48/88/168

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

ATmega48/88/168 has Extended I/O space from 0x60 - 0xFF in SRAM where only the

ST/STS/STD and LD/LDS/LDD instructions can be used.

6.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

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2545M–AVR–09/07

6.4

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

6.4.1

SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

0x3F (0x5F)

Read/Write

Initial Value

SREG

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

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ATmega48/88/168

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

6.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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6.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 6-3.

Figure 6-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

6.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when data

is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the

return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is

incremented by one when data is popped from the Stack with the POP instruction, and it is incre-

mented by two when data is popped from the Stack with return from subroutine RET or return

from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

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ATmega48/88/168

6.6.1

SPH and SPL – Stack Pointer High and Stack Pointer Low Register

Bit

15

SP15

SP7

14

SP14

SP6

13

SP13

SP5

12

SP12

SP4

11

SP11

SP3

10

SP10

SP2

9

SP9

8

SP8

0x3E (0x5E)

0x3D (0x5D)

SPH

SPL

SP1

SP0

7

6

5

4

3

2

1

0

Read/Write

Initial Value

R/W

RAMEND

6.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 6-5. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

15

2545M–AVR–09/07

6.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 286 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 57. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 57 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming, ATmega88

and ATmega168” on page 270.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

16

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Assembly Code Example

in r16, SREG

; store SREG value

cli

; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

6.8.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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2545M–AVR–09/07

7. AVR Memories

7.1

Overview

This section describes the different memories in the ATmega48/88/168. The AVR architecture

has two main memory spaces, the Data Memory and the Program Memory space. In addition,

the ATmega48/88/168 features an EEPROM Memory for data storage. All three memory spaces

are linear and regular.

7.2

In-System Reprogrammable Flash Program Memory

The ATmega48/88/168 contains 4/8/16K bytes On-chip In-System Reprogrammable Flash

memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two

sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168.

ATmega48 does not have separate Boot Loader and Application Program sections, and the

SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section

“SPMCSR – Store Program Memory Control and Status Register” on page 268 and page 284for

more details.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega48/88/168 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K pro-

gram memory locations. The operation of Boot Program section and associated Boot Lock bits

for software protection are described in detail in “Self-Programming the Flash, ATmega48” on

page 263 and “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168” on page 270. “Memory Programming” on page 286 contains a detailed description

on Flash Programming in SPI- or Parallel Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

18

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 7-1. Program Memory Map, ATmega48

Program Memory

0x0000

Application Flash Section

0x7FF

Figure 7-2. Program Memory Map, ATmega88 and ATmega168

Program Memory

0x0000

Application Flash Section

Boot Flash Section

0x0FFF/0x1FFF

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2545M–AVR–09/07

7.3

SRAM Data Memory

Figure 7-3 shows how the ATmega48/88/168 SRAM Memory is organized.

The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-

tions can be used.

The lower 768/1280/1280 data memory locations address both the Register File, the I/O mem-

ory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the

Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O

memory, and the next 512/1024/1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 512/1024/1024 bytes of internal data SRAM in the ATmega48/88/168 are all accessible

through all these addressing modes. The Register File is described in “General Purpose Regis-

ter File” on page 13.

Figure 7-3. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

32 Registers

64 I/O Registers

160 Ext I/O Reg.

0x0100

Internal SRAM

(512/1024/1024 x 8)

0x02FF/0x04FF/0x04FF

7.3.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 7-4.

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ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 7-4. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

7.4

EEPROM Data Memory

The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is organized

as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

“Memory Programming” on page 286 contains a detailed description on EEPROM Programming

in SPI or Parallel Programming mode.

7.4.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 7-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, V_CCis likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 21 for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

7.4.2

Preventing EEPROM Corruption

During periods of low V_CC,the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

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2545M–AVR–09/07

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.5

I/O Memory

The I/O space definition of the ATmega48/88/168 is shown in “Register Summary” on page 343.

All ATmega48/88/168 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses. The ATmega48/88/168 is a

complex microcontroller with more peripheral units than can be supported within the 64 location

reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -

0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.5.1

General Purpose I/O Registers

The ATmega48/88/168 contains three General Purpose I/O Registers. These registers can be

used for storing any information, and they are particularly useful for storing global variables and

Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

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ATmega48/88/168

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ATmega48/88/168

7.6

Register Description

7.6.1

EEARH and EEARL – The EEPROM Address Register

Bit

15

14

13

12

11

10

9

8

EEAR8

EEAR0

0

0x22 (0x42)

0x21 (0x41)

–

EEARH

EEARL

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

7

R

6

R

5

R

4

R

3

R

2

R

1

R

Read/Write

Initial Value

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0

and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before

the EEPROM may be accessed.

EEAR8 is an unused bit in ATmega48 and must always be written to zero.

7.6.2

EEDR – The EEPROM Data Register

Bit

0x20 (0x40)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

EEDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3

EECR – The EEPROM Control Register

Bit

0x1F (0x3F)

7

6

–

5

EEPM1

R/W

X

4

EEPM0

R/W

X

3

EERIE

R/W

0

2

EEMPE

R/W

0

1

EEPE

R/W

X

0

EERE

R/W

0

–

EECR

Read/Write

Initial Value

R

0

R

0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be trig-

gered when writing EEPE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 7-1. While EEPE

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2545M–AVR–09/07

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

Table 7-1.

EEPROM Mode Bits

Programming

EEPM1

EEPM0

Time

Operation

0

1

0

1

0

1

3.4 ms

1.8 ms

–

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMPE: EEPROM Master Write Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.

When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the

selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Write Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEPE bit must be written to one to write the value into the

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 270 for

details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

24

ATmega48/88/168

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ATmega48/88/168

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-2 lists the typical pro-

gramming time for EEPROM access from the CPU.

Table 7-2.

Symbol

EEPROM Programming Time

Number of Calibrated RC Oscillator Cycles

Typ Programming Time

EEPROM write

(from CPU)

26,368

3.3 ms

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-

bally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

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2545M–AVR–09/07

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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ATmega48/88/168

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ATmega48/88/168

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

7.6.4

7.6.5

7.6.6

GPIOR2 – General Purpose I/O Register 2

Bit

0x2B (0x4B)

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

GPIOR2

GPIOR1

GPIOR0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR1 – General Purpose I/O Register 1

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2A (0x4A)

Read/Write

Initial Value

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

GPIOR0 – General Purpose I/O Register 0

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x1E (0x3E)

Read/Write

Initial Value

LSB

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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2545M–AVR–09/07

8. System Clock and Clock Options

8.1

Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 40. The clock systems are detailed below.

Figure 8-1. Clock Distribution

Asynchronous

Timer/Counter

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_ADC

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_ASY

clk_FLASH

System Clock

Prescaler

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Clock

Multiplexer

Watchdog

Oscillator

Timer/Counter

Oscillator

Crystal

Oscillator

Low-frequency

Crystal Oscillator

Calibrated RC

Oscillator

External Clock

8.1.1

8.1.2

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also note that start condition detection in the USI module is carried out asynchro-

nously when clk_I/Ois halted, TWI address recognition in all sleep modes.

8.1.3

28

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

8.1.4

8.1.5

Asynchronous Timer Clock – clk_ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows

using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

8.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 8-1.

Device Clocking Options Select⁽¹⁾

Device Clocking Option

Low Power Crystal Oscillator

Full Swing Crystal Oscillator

Low Frequency Crystal Oscillator

Internal 128 kHz RC Oscillator

Calibrated Internal RC Oscillator

External Clock

CKSEL3..0

1111 - 1000

0111 - 0110

0101 - 0100

0011

0010

0000

Reserved

0001

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

8.2.1

8.2.2

Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-

grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out

period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that

all users can make their desired clock source setting using any available programming interface.

Clock Startup Sequence

Any clock source needs a sufficient V_CCto start oscillating and a minimum number of oscillating

cycles before it can be considered stable.

To ensure sufficient V_CC, the device issues an internal reset with a time-out delay (t_TOUT) after

the device reset is released by all other reset sources. “System Control and Reset” on page 46

describes the start conditions for the internal reset. The delay (t_TOUT) is timed from the Watchdog

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

29

2545M–AVR–09/07

selectable delays are shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage

dependent as shown in “Typical Characteristics” on page 316.

Table 8-2.

Typ Time-out (V_CC= 5.0V)

0 ms

Number of Watchdog Oscillator Cycles

Typ Time-out (V_CC= 3.0V)

0 ms

Number of Cycles

0

4.1 ms

65 ms

4.3 ms

69 ms

4K (4,096)

8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V_CC. The

delay will not monitor the actual voltage and it will be required to select a delay longer than the

V

_CCrise time. If this is not possible, an internal or external Brown-Out Detection circuit should be

used. A BOD circuit will ensure sufficient V_CCbefore it releases the reset, and the time-out delay

can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is

not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-

ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal

reset active for a given number of clock cycles. The reset is then released and the device will

start to execute. The recommended oscillator start-up time is dependent on the clock type, and

varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when

the device starts up from reset. When starting up from Power-save or Power-down mode, V_CCis

assumed to be at a sufficient level and only the start-up time is included.

8.3

Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be

configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a

ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out-

put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and

may be more susceptible to noise in noisy environments. In these cases, refer to the “Full Swing

Crystal Oscillator” on page 32.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

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ATmega48/88/168

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ATmega48/88/168

Figure 8-2. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Low Power Oscillator can operate in three different modes, each optimized for a specific fre-

quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3

on page 31.

Table 8-3.

Low Power Crystal Oscillator Operating Modes⁽³⁾

Frequency Range

Recommended Range for

Capacitors C1 and C2 (pF)

(MHz)

CKSEL3..1⁽¹⁾

100⁽²⁾

101

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 - 16.0

–

12 - 22

110

111

Notes: 1. This is the recommended CKSEL settings for the different frequency ranges.

2. This option should not be used with crystals, only with ceramic resonators.

3. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured

that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

Table 8-4.

Start-up Times for the Low Power Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Oscillator Source /

Power Conditions

(V_CC= 5.0V)

CKSEL0

SUT1..0

Ceramic resonator, fast

rising power

258 CK

1K CK

14CK + 4.1 ms⁽¹⁾

14CK + 65 ms⁽¹⁾

14CK⁽²⁾

0

00

Ceramic resonator, slowly

rising power

0

1

01

10

11

00

Ceramic resonator, BOD

enabled

Ceramic resonator, fast

rising power

14CK + 4.1 ms⁽²⁾

14CK + 65 ms⁽²⁾

Ceramic resonator, slowly

rising power

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2545M–AVR–09/07

Table 8-4.

Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued)

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Oscillator Source /

Power Conditions

(V_CC= 5.0V)

CKSEL0

SUT1..0

Crystal Oscillator, BOD

enabled

16K CK

14CK

1

01

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

1

10

11

Crystal Oscillator, slowly

rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

8.4

Full Swing Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be

configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a

ceramic resonator may be used.

This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is

useful for driving other clock inputs and in noisy environments. The current consumption is

higher than the “Low Power Crystal Oscillator” on page 30. Note that the Full Swing Crystal

Oscillator will only operate for V_CC= 2.7 - 5.5 volts.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 8-6. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-5.

Table 8-5.

Full Swing Crystal Oscillator operating modes⁽¹⁾

Recommended Range for

Frequency Range (MHz)

Capacitors C1 and C2 (pF)

CKSEL3..1

011

0.4 - 20

12 - 22

Notes: 1. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured

that the resulting divided clock meets the frequency specification of the device.

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ATmega48/88/168

Figure 8-3. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

Table 8-6.

Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Oscillator Source /

Power Conditions

(V_CC= 5.0V)

CKSEL0

SUT1..0

Ceramic resonator, fast

rising power

258 CK

1K CK

14CK + 4.1 ms⁽¹⁾

14CK + 65 ms⁽¹⁾

14CK⁽²⁾

0

00

Ceramic resonator, slowly

rising power

0

1

01

10

11

00

01

10

11

Ceramic resonator, BOD

enabled

Ceramic resonator, fast

rising power

1K CK

14CK + 4.1 ms⁽²⁾

14CK + 65 ms⁽²⁾

14CK

Ceramic resonator, slowly

rising power

1K CK

Crystal Oscillator, BOD

enabled

16K CK

Crystal Oscillator, fast

rising power

14CK + 4.1 ms

14CK + 65 ms

Crystal Oscillator, slowly

rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

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2545M–AVR–09/07

8.5

Low Frequency Crystal Oscillator

The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre-

quency Crystal Oscillator. The crystal should be connected as shown in Figure 8-2. When this

Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in

Table 8-7.

Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

Power Conditions

BOD enabled

(V_CC= 5.0V)

CKSEL0

SUT1..0

00

1K CK

14CK⁽¹⁾

0

1

Fast rising power

Slowly rising power

14CK + 4.1 ms⁽¹⁾

14CK + 65 ms⁽¹⁾

01

1K CK

10

Reserved

32K CK

Reserved

11

BOD enabled

14CK

00

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms

01

10

11

Note:

1. These options should only be used if frequency stability at start-up is not important for the

application.

8.6

Calibrated Internal RC Oscillator

By default, the Internal RC OScillator provides an approximate 8.0 MHz clock. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. The device

is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 37 for

more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 8-8. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed calibration value into the OSCCAL Register and thereby automatically cal-

ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in

Table 28-1 on page 307.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 38, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 28-1 on page 307.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section “Calibration Byte” on page 289.

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ATmega48/88/168

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ATmega48/88/168

Table 8-8.

Internal Calibrated RC Oscillator Operating Modes⁽¹⁾⁽²⁾

Frequency Range (MHz)

CKSEL3..0

7.3 - 8.1

0010

Notes: 1. The device is shipped with this option selected.

2. If 8 MHz frequency exceeds the specification of the device (depends on V_CC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-9 on page 35.

Table 8-9.

Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK⁽¹⁾

Fast rising power

Slowly rising power

14CK + 4.1 ms

14CK + 65 ms⁽²⁾

01

6 CK

10

Reserved

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1 ms to ensure programming mode can be entered.

2. The device is shipped with this option selected.

8.7

128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming the CKSEL Fuses to “11” as shown in Table 8-10.

Table 8-10. 128 kHz Internal Oscillator Operating Modes

Nominal Frequency

CKSEL3..0

128 kHz

0011

Note:

1. Note that the 128 kHz oscillator is a very low power clock source, and is not designed for a

high accuracy.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-11.

Table 8-11. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK⁽¹⁾

Fast rising power

14CK + 4 ms

14CK + 64 ms

01

Slowly rising power

6 CK

10

Reserved

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1 ms to ensure programming mode can be entered.

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2545M–AVR–09/07

8.8

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

8-4 on page 36. To run the device on an external clock, the CKSEL Fuses must be programmed

to “0000” (see Table 8-12).

Table 8-12. Crystal Oscillator Clock Frequency

Frequency

CKSEL3..0

0 - 20 MHz

0000

Figure 8-4. External Clock Drive Configuration

NC

XTAL2

EXTERNAL

CLOCK

XTAL1

GND

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-13.

Table 8-13. Start-up Times for the External Clock Selection

Start-up Time from Power-

down and Power-save

Additional Delay from

Reset (V_CC= 5.0V)

Power Conditions

BOD enabled

SUT1..0

00

6 CK

14CK

Fast rising power

14CK + 4.1 ms

14CK + 65 ms

01

Slowly rising power

6 CK

10

Reserved

11

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

37 for details.

8.9

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

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ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

8.10 Timer/Counter Oscillator

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a exter-

nal clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared with

XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when an

internal RC Oscillator is selected as system clock source. See Figure 8-2 on page 31 for crystal

connection.

Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to

logic one. See “Asynchronous Operation of Timer/Counter2” on page 152 for further description

on selecting external clock as input instead of a 32 kHz crystal.

8.11 System Clock Prescaler

The ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by

setting the “CLKPR – Clock Prescale Register” on page 387. This feature can be used to

decrease the system clock frequency and the power consumption when the requirement for pro-

cessing power is low. This can be used with all clock source options, and it will affect the clock

frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASHare

divided by a factor as shown in Table 28-3 on page 308.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting. The ripple counter that implements the prescaler runs at the

frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it

is not possible to determine the state of the prescaler - even if it were readable, and the exact

time it takes to switch from one clock division to the other cannot be exactly predicted. From the

time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the pre-

vious clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must befollowed to

change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

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2545M–AVR–09/07

8.12 Register Description

8.12.1

OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

(0x66)

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration value is

automatically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 28-1 on page 307. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 28-

1 on page 307. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range.

8.12.2

CLKPR – Clock Prescale Register

Bit

7

6

–

5

–

4

–

3

2

1

0

CLKPCE

R/W

0

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

(0x61)

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 8-14.

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ATmega48/88/168

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ATmega48/88/168

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock

source has a higher frequency than the maximum frequency of the device at the present operat-

ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8

Fuse setting. The Application software must ensure that a sufficient division factor is chosen if

the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 8-14. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

39

2545M–AVR–09/07

9. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

9.1

Sleep Modes

Figure 8-1 on page 28 presents the different clock systems in the ATmega48/88/168, and their

distribution. The figure is helpful in selecting an appropriate sleep mode. Table 9-1 shows the

different sleep modes and their wake up sources.

Table 9-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

Sleep Mode

Idle

X

X⁽²⁾

X

ADC Noise

Reduction

X⁽³⁾

X⁽²⁾

Power-down

Power-save

Standby⁽¹⁾

X⁽³⁾

X

X⁽²⁾

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT1 and INT0, only level interrupt.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be

activated by the SLEEP instruction. See Table 9-2 on page 44 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

9.2

Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial

Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk_CPUand clk_FLASH, while allowing the other clocks to run.

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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

9.3

ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-

wire Serial Interface address watch, Timer/Counter2⁽¹⁾, and the Watchdog to continue operating

(if enabled). This sleep mode basically halts clk_I/O, clk_CPU, and clk_FLASH, while allowing the other

clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a

Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0

or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

Note:

1. Timer/Counter2 will only keep running in asynchronous mode, see “8-bit Timer/Counter2 with

PWM and Asynchronous Operation” on page 141 for details.

9.4

Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an

External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire

Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change

interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing

operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 67

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 29.

9.5

Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from

either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding

Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in

SREG is set.

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2545M–AVR–09/07

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save

mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is

stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is

stopped during sleep. Note that even if the synchronous clock is running in Power-save, this

clock is only available for Timer/Counter2.

9.6

9.7

Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 45, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. See “Power-Down Supply Current” on page 324 for examples. In all other

sleep modes, the clock is already stopped.

9.8

Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an

AVR controlled system. In general, sleep modes should be used as much as possible, and the

sleep mode should be selected so that as few as possible of the device’s functions are operat-

ing. All functions not needed should be disabled. In particular, the following modules may need

special consideration when trying to achieve the lowest possible power consumption.

9.8.1

9.8.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 245

for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep

mode. Refer to “Analog Comparator” on page 242 for details on how to configure the Analog

Comparator.

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ATmega48/88/168

9.8.3

9.8.4

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to “Brown-out Detection” on page 48 for details

on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 49 for details on the start-up time.

9.8.5

9.8.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 50 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 76 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page 244 and “DIDR0 – Digital

Input Disable Register 0” on page 260 for details.

9.8.7

On-chip Debug System

If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the

main clock source is enabled and hence always consumes power. In the deeper sleep modes,

this will contribute significantly to the total current consumption.

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2545M–AVR–09/07

9.9

Register Description

9.9.1

SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

SE

R/W

0

0x33 (0x53)

Read/Write

Initial Value

SM2

R/W

0

SM1

R/W

0

SM0

R/W

0

SMCR

R

0

R

0

R

0

R

0

• Bits 7..4 Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Table 9-2.

Sleep Mode Select

SM2

0

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

0

1

0

1

0

1

0

ADC Noise Reduction

Power-down

Power-save

Reserved

0

1

Reserved

1

Standby⁽¹⁾

1

Reserved

Note:

1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

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ATmega48/88/168

9.9.2

PRR – Power Reduction Register

Bit

7

PRTWI

R/W

0

6

PRTIM2

R/W

0

5

PRTIM0

R/W

0

4

–

3

PRTIM1

R/W

0

2

PRSPI

R/W

0

1

PRUSART0

R/W

0

PRADC

R/W

0

(0x64)

PRR

Read/Write

Initial Value

R

0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2

is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved in ATmega48/88/168 and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

If using debugWIRE On-chip Debug System, this bit should not be written to one.

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re initialized to ensure proper

operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When

waking up the USART again, the USART should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

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10. System Control and Reset

10.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a

JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and

ATmega88, the instruction placed at the Reset Vector must be an RJMP – Relative Jump –

instruction to the reset handling routine. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in

the Boot section or vice versa (ATmega88/168 only). The circuit diagram in Figure 10-1 shows

the reset logic. Table 28-3 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 29.

10.2 Reset Sources

The ATmega48/88/168 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than

the minimum pulse length.

• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog System Reset mode is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out Reset

threshold (V_BOT) and the Brown-out Detector is enabled.

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ATmega48/88/168

Figure 10-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

RSTDISBL

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

10.3 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in “System and Reset Characteristics” on page 308. The POR is activated whenever

V

_CCis below the detection level. The POR circuit can be used to trigger the start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

Figure 10-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

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Figure 10-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

10.4 External Reset

An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see “System and Reset Characteristics” on page 308) will generate a

reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

When the applied signal reaches the Reset Threshold Voltage – V_RST– on its positive edge, the

delay counter starts the MCU after the Time-out period – t_TOUT– has expired. The External Reset

can be disabled by the RSTDISBL fuse, see Table 27-6 on page 288.

Figure 10-4. External Reset During Operation

CC

10.5 Brown-out Detection

ATmega48/88/168 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CC

level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can

be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

=

V

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.When the BOD is enabled, and V_CCdecreases to a

value below the trigger level (V_BOT-in Figure 10-5), the Brown-out Reset is immediately acti-

vated. When V_CCincreases above the trigger level (V_BOT+in Figure 10-5), the delay counter

starts the MCU after the Time-out period t_TOUThas expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in “System and Reset Characteristics” on page 308.

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ATmega48/88/168

Figure 10-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

10.6 Watchdog System Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

page 50 for details on operation of the Watchdog Timer.

Figure 10-6. Watchdog System Reset During Operation

CC

CK

10.7 Internal Voltage Reference

ATmega48/88/168 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

10.7.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 308. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

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2545M–AVR–09/07

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

10.8 Watchdog Timer

10.8.1

Features

• Clocked from separate On-chip Oscillator

• 3 Operating modes

– Interrupt

– System Reset

– Interrupt and System Reset

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 10-7. Watchdog Timer

128kHz

OSCILLATOR

WDP0

WDP1

WATCHDOG

WDP2

RESET

WDP3

WDE

MCU RESET

WDIF

INTERRUPT

WDIE

ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting

cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset

when the counter reaches a given time-out value. In normal operation mode, it is required that

the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the

time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset

will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used

to wake the device from sleep-modes, and also as a general system timer. One example is to

limit the maximum time allowed for certain operations, giving an interrupt when the operation

has run longer than expected. In System Reset mode, the WDT gives a reset when the timer

expires. This is typically used to prevent system hang-up in case of runaway code. The third

mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-

rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown

by saving critical parameters before a system reset.

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The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alter-

ations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE

and changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and

WDE. A logic one must be written to WDE regardless of the previous value of the WDE

bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watch-

dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts

globally) so that no interrupts will occur during the execution of these functions.

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Assembly Code Example⁽¹⁾

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

r16, MCUSR

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

lds r16, WDTCSR

ori

r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; Turn off WDT

ldi

r16, (0<<WDE)

sts WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note:

1. See ”About Code Examples” on page 9.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out

condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not

set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this

situation, the application software should always clear the Watchdog System Reset Flag

(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

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The following code example shows one assembly and one C function for changing the time-out

value of the Watchdog Timer.

Assembly Code Example⁽¹⁾

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

lds r16, WDTCSR

ori

r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

sts WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note:

1. See ”About Code Examples” on page 9.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change

in the WDP bits can result in a time-out when switching to a shorter time-out period.

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10.9 Register Description

10.9.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

0x35 (0x55)

Read/Write

Initial Value

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

R

0

R

0

R

0

R

0

See Bit Description

• Bit 7..4: Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 3 – WDRF: Watchdog System Reset Flag

This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

10.9.2

WDTCSR – Watchdog Timer Control Register

Bit

(0x60)

7

6

5

WDP3

R/W

0

4

WDCE

R/W

0

3

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

WDIF

WDIE

WDE

R/W

X

WDTCSR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

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If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE

and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

Table 10-1. Watchdog Timer Configuration

WDTON⁽¹⁾

WDE

WDIE

Mode

Action on Time-out

None

1

0

1

0

1

0

Stopped

Interrupt Mode

System Reset Mode

Interrupt

Reset

Interrupt and System Reset

Mode

Interrupt, then go to System

Reset Mode

1

0

1

x

1

x

System Reset Mode

Reset

Note:

1. WDTON Fuse set to “0“ means programmed and “1“ means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

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• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 10-2 on page 56.

Table 10-2. Watchdog Timer Prescale Select

Number of WDT Oscillator

Cycles

Typical Time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

4K (4096) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

8K (8192) cycles

16K (16384) cycles

32K (32768) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

Reserved

56

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

11. Interrupts

11.1 Overview

This section describes the specifics of the interrupt handling as performed in ATmega48/88/168.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 16.

The interrupt vectors in ATmega48, ATmega88 and ATmega168 are generally the same, with

the following differences:

• Each Interrupt Vector occupies two instruction words in ATmega168, and one instruction word

in ATmega48 and ATmega88.

• ATmega48 does not have a separate Boot Loader Section. In ATmega88 and ATmega168, the

Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is

affected by the IVSEL bit in MCUCR.

11.2 Interrupt Vectors in ATmega48

Table 11-1. Reset and Interrupt Vectors in ATmega48

Vector No. Program Address Source

Interrupt Definition

1

2

0x000

0x001

0x002

0x003

0x004

0x005

0x006

0x007

0x008

0x009

0x00A

0x00B

0x00C

0x00D

0x00E

0x00F

0x010

0x011

0x012

0x013

0x014

RESET

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

External Interrupt Request 0

External Interrupt Request 1

Pin Change Interrupt Request 0

Pin Change Interrupt Request 1

Pin Change Interrupt Request 2

Watchdog Time-out Interrupt

Timer/Counter2 Compare Match A

Timer/Counter2 Compare Match B

Timer/Counter2 Overflow

INT0

3

INT1

4

PCINT0

5

PCINT1

6

PCINT2

7

WDT

8

TIMER2 COMPA

TIMER2 COMPB

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 OVF

TIMER0 COMPA

TIMER0 COMPB

TIMER0 OVF

SPI, STC

9

10

11

12

13

14

15

16

17

18

19

20

21

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Coutner1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART Rx Complete

USART, RX

USART, UDRE

USART, TX

USART, Data Register Empty

USART, Tx Complete

57

2545M–AVR–09/07

Table 11-1. Reset and Interrupt Vectors in ATmega48 (Continued)

Vector No. Program Address Source Interrupt Definition

22

23

24

25

26

0x015

0x016

0x017

0x018

0x019

ADC

ADC Conversion Complete

EEPROM Ready

EE READY

ANALOG COMP

TWI

Analog Comparator

2-wire Serial Interface

Store Program Memory Ready

SPM READY

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega48 is:

Address Labels Code

Comments

0x000

0x001

0x002

0x003

0x004

0x005

0x006

0x007

0x008

0x009

0x00A

0x00B

0x00C

0x00D

0x00E

0x00F

0x010

0x011

0x012

0x013

0x014

0x015

0x016

0x017

0x018

0x019

;

rjmp

RESET

; Reset Handler

EXT_INT0

EXT_INT1

PCINT0

; IRQ0 Handler

; IRQ1 Handler

; PCINT0 Handler

PCINT1

; PCINT1 Handler

PCINT2

; PCINT2 Handler

WDT

; Watchdog Timer Handler

; Timer2 Compare A Handler

; Timer2 Compare B Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 Compare A Handler

; Timer1 Compare B Handler

; Timer1 Overflow Handler

; Timer0 Compare A Handler

; Timer0 Compare B Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; USART, RX Complete Handler

; USART, UDR Empty Handler

; USART, TX Complete Handler

; ADC Conversion Complete Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; 2-wire Serial Interface Handler

; Store Program Memory Ready Handler

TIM2_COMPA

TIM2_COMPB

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_COMPA

TIM0_COMPB

TIM0_OVF

SPI_STC

USART_RXC

USART_UDRE

USART_TXC

ADC

EE_RDY

ANA_COMP

TWI

SPM_RDY

0x01ARESET:

0x01B

0x01C

0x01D

0x01E

0x01F

ldi

out

ldi

out

sei

r16, high(RAMEND); Main program start

SPH,r16

; Set Stack Pointer to top of RAM

r16, low(RAMEND)

SPL,r16

; Enable interrupts

<instr> xxx

... ...

...

58

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

11.3 Interrupt Vectors in ATmega88

Table 11-2. Reset and Interrupt Vectors in ATmega88

Program

Vector No.

Address⁽²⁾

0x000⁽¹⁾

0x001

0x002

0x003

0x004

0x005

0x006

0x007

0x008

0x009

0x00A

0x00B

0x00C

0x00D

0x00E

0x00F

0x010

0x011

0x012

0x013

0x014

0x015

0x016

0x017

0x018

0x019

Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

External Interrupt Request 0

External Interrupt Request 1

Pin Change Interrupt Request 0

Pin Change Interrupt Request 1

Pin Change Interrupt Request 2

Watchdog Time-out Interrupt

Timer/Counter2 Compare Match A

Timer/Counter2 Compare Match B

Timer/Counter2 Overflow

1

RESET

2

INT0

3

INT1

4

PCINT0

5

PCINT1

6

PCINT2

7

WDT

8

TIMER2 COMPA

TIMER2 COMPB

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 OVF

TIMER0 COMPA

TIMER0 COMPB

TIMER0 OVF

SPI, STC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Coutner1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART Rx Complete

USART, RX

USART, UDRE

USART, TX

ADC

USART, Data Register Empty

USART, Tx Complete

ADC Conversion Complete

EE READY

ANALOG COMP

TWI

EEPROM Ready

Analog Comparator

2-wire Serial Interface

SPM READY

Store Program Memory Ready

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

reset, see “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168” on page 270.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot

Flash Section. The address of each Interrupt Vector will then be the address in this table

added to the start address of the Boot Flash Section.

Table 11-3 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt

Vectors are not used, and regular program code can be placed at these locations. This is also

the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the

Boot section or vice versa.

59

2545M–AVR–09/07

Table 11-3. Reset and Interrupt Vectors Placement in ATmega88⁽¹⁾

BOOTRST

IVSEL

Reset Address

0x000

Interrupt Vectors Start Address

0x001

1

0

1

0

1

0x000

Boot Reset Address + 0x001

0x001

Boot Reset Address

Boot Reset Address + 0x001

Note:

1. The Boot Reset Address is shown in Table 26-6 on page 282. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega88 is:

Address Labels Code

Comments

0x000

0x001

0x002

0x003

0x004

0x005

0x006

0x007

0X008

0x009

0x00A

0x00B

0x00C

0x00D

0x00E

0x00F

0x010

0x011

0x012

0x013

0x014

0x015

0x016

0x017

0x018

0x019

;

rjmp

RESET

; Reset Handler

EXT_INT0

EXT_INT1

PCINT0

; IRQ0 Handler

; IRQ1 Handler

; PCINT0 Handler

PCINT1

; PCINT1 Handler

PCINT2

; PCINT2 Handler

WDT

; Watchdog Timer Handler

; Timer2 Compare A Handler

; Timer2 Compare B Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 Compare A Handler

; Timer1 Compare B Handler

; Timer1 Overflow Handler

; Timer0 Compare A Handler

; Timer0 Compare B Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; USART, RX Complete Handler

; USART, UDR Empty Handler

; USART, TX Complete Handler

; ADC Conversion Complete Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; 2-wire Serial Interface Handler

; Store Program Memory Ready Handler

TIM2_COMPA

TIM2_COMPB

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_COMPA

TIM0_COMPB

TIM0_OVF

SPI_STC

USART_RXC

USART_UDRE

USART_TXC

ADC

EE_RDY

ANA_COMP

TWI

SPM_RDY

0x01ARESET:

0x01B

0x01C

ldi

out

ldi

r16, high(RAMEND); Main program start

SPH,r16

; Set Stack Pointer to top of RAM

r16, low(RAMEND)

0x01D

0x01E

out

sei

SPL,r16

; Enable interrupts

0x01F

<instr> xxx

60

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in ATmega88 is:

Address Labels Code

Comments

0x000

0x001

0x002

RESET: ldi

out

r16,high(RAMEND); Main program start

SPH,r16

; Set Stack Pointer to top of RAM

ldi

r16,low(RAMEND)

SPL,r16

0x003

0x004

out

sei

; Enable interrupts

0x005

;

<instr> xxx

.org 0xC01

0xC01

rjmp

...

EXT_INT0

EXT_INT1

...

; IRQ0 Handler

0xC02

; IRQ1 Handler

...

;

0xC19

rjmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88

is:

Address Labels Code

.org 0x001

Comments

0x001

0x002

...

rjmp

...

EXT_INT0

EXT_INT1

...

; IRQ0 Handler

; IRQ1 Handler

;

0x019

;

rjmp

SPM_RDY

; Store Program Memory Ready Handler

.org 0xC00

0xC00

0xC01

0xC02

RESET: ldi

r16,high(RAMEND); Main program start

out

SPH,r16

; Set Stack Pointer to top of RAM

ldi

r16,low(RAMEND)

SPL,r16

0xC03

0xC04

out

sei

; Enable interrupts

0xC05

<instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in ATmega88 is:

Address Labels Code

Comments

;

.org 0xC00

0xC00

0xC01

0xC02

...

rjmp

...

RESET

; Reset handler

EXT_INT0

EXT_INT1

...

; IRQ0 Handler

; IRQ1 Handler

;

0xC19

;

rjmp

SPM_RDY

; Store Program Memory Ready Handler

0xC1A

RESET: ldi

r16,high(RAMEND); Main program start

61

2545M–AVR–09/07

0xC1B

0xC1C

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

; Enable interrupts

r16,low(RAMEND)

SPL,r16

0xC1D

0xC1E

out

sei

0xC1F

<instr> xxx

11.4 Interrupt Vectors in ATmega168

Table 11-4. Reset and Interrupt Vectors in ATmega168

Program

VectorNo.

Address⁽²⁾

0x0000⁽¹⁾

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

0x002E

0x0030

0x0032

Source

Interrupt Definition

External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

External Interrupt Request 0

External Interrupt Request 1

Pin Change Interrupt Request 0

Pin Change Interrupt Request 1

Pin Change Interrupt Request 2

Watchdog Time-out Interrupt

Timer/Counter2 Compare Match A

Timer/Counter2 Compare Match B

Timer/Counter2 Overflow

1

RESET

2

INT0

3

INT1

4

PCINT0

5

PCINT1

6

PCINT2

7

WDT

8

TIMER2 COMPA

TIMER2 COMPB

TIMER2 OVF

TIMER1 CAPT

TIMER1 COMPA

TIMER1 COMPB

TIMER1 OVF

TIMER0 COMPA

TIMER0 COMPB

TIMER0 OVF

SPI, STC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Timer/Counter1 Capture Event

Timer/Counter1 Compare Match A

Timer/Coutner1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

Timer/Counter0 Overflow

SPI Serial Transfer Complete

USART Rx Complete

USART, RX

USART, UDRE

USART, TX

ADC

USART, Data Register Empty

USART, Tx Complete

ADC Conversion Complete

EE READY

ANALOG COMP

TWI

EEPROM Ready

Analog Comparator

2-wire Serial Interface

SPM READY

Store Program Memory Ready

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

reset, see “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168” on page 270.

62

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot

Flash Section. The address of each Interrupt Vector will then be the address in this table

added to the start address of the Boot Flash Section.

Table 11-5 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt

Vectors are not used, and regular program code can be placed at these locations. This is also

the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the

Boot section or vice versa.

Table 11-5. Reset and Interrupt Vectors Placement in ATmega168⁽¹⁾

BOOTRST

IVSEL

Reset Address

0x000

Interrupt Vectors Start Address

0x001

1

0

1

0

1

0x000

Boot Reset Address + 0x0002

0x001

Boot Reset Address

Boot Reset Address + 0x0002

Note:

1. The Boot Reset Address is shown in Table 26-6 on page 282. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega168 is:

Address Labels Code

Comments

0x0000

0x0002

0x0004

0x0006

0x0008

0x000A

0x000C

0x000E

0x0010

0x0012

0x0014

0x0016

0x0018

0x001A

0x001C

0x001E

0x0020

0x0022

0x0024

0x0026

0x0028

0x002A

0x002C

0x002E

0x0030

0x0032

jmp

RESET

; Reset Handler

EXT_INT0

EXT_INT1

PCINT0

; IRQ0 Handler

; IRQ1 Handler

; PCINT0 Handler

PCINT1

; PCINT1 Handler

PCINT2

; PCINT2 Handler

WDT

; Watchdog Timer Handler

; Timer2 Compare A Handler

; Timer2 Compare B Handler

; Timer2 Overflow Handler

; Timer1 Capture Handler

; Timer1 Compare A Handler

; Timer1 Compare B Handler

; Timer1 Overflow Handler

; Timer0 Compare A Handler

; Timer0 Compare B Handler

; Timer0 Overflow Handler

; SPI Transfer Complete Handler

; USART, RX Complete Handler

; USART, UDR Empty Handler

; USART, TX Complete Handler

; ADC Conversion Complete Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; 2-wire Serial Interface Handler

; Store Program Memory Ready Handler

TIM2_COMPA

TIM2_COMPB

TIM2_OVF

TIM1_CAPT

TIM1_COMPA

TIM1_COMPB

TIM1_OVF

TIM0_COMPA

TIM0_COMPB

TIM0_OVF

SPI_STC

USART_RXC

USART_UDRE

USART_TXC

ADC

EE_RDY

ANA_COMP

TWI

SPM_RDY

63

2545M–AVR–09/07

;

0x0033RESET:

0x0034

0x0035

0x0036

0x0037

0x0038

ldi

out

ldi

out

sei

r16, high(RAMEND); Main program start

SPH,r16

; Set Stack Pointer to top of RAM

r16, low(RAMEND)

SPL,r16

; Enable interrupts

<instr> xxx

... ...

...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in ATmega168 is:

Address Labels Code

0x0000 RESET: ldi

Comments

r16,high(RAMEND); Main program start

0x0001

0x0002

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x0003

0x0004

out

sei

; Enable interrupts

0x0005

;

<instr> xxx

.org 0xC02

0x1C02

0x1C04

...

jmp

...

jmp

EXT_INT0

; IRQ0 Handler

EXT_INT1

...

; IRQ1 Handler

;

0x1C32

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168

is:

Address Labels Code

.org 0x0002

Comments

0x0002

0x0004

...

jmp

...

jmp

EXT_INT0

EXT_INT1

...

; IRQ0 Handler

; IRQ1 Handler

;

0x0032

;

SPM_RDY

; Store Program Memory Ready Handler

.org 0x1C00

0x1C00 RESET: ldi

r16,high(RAMEND); Main program start

0x1C01

0x1C02

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x1C03

0x1C04

out

sei

; Enable interrupts

0x1C05

<instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in ATmega168 is:

64

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Address Labels Code

Comments

;

.org 0x1C00

0x1C00

0x1C02

0x1C04

...

jmp

...

jmp

RESET

; Reset handler

EXT_INT0

EXT_INT1

...

; IRQ0 Handler

; IRQ1 Handler

;

0x1C32

;

SPM_RDY

; Store Program Memory Ready Handler

0x1C33 RESET: ldi

r16,high(RAMEND); Main program start

0x1C34

0x1C35

out

ldi

SPH,r16

; Set Stack Pointer to top of RAM

r16,low(RAMEND)

SPL,r16

0x1C36

0x1C37

out

sei

; Enable interrupts

0x1C38

<instr> xxx

11.4.1

Moving Interrupts Between Application and Boot Space, ATmega88 and ATmega168

The MCU Control Register controls the placement of the Interrupt Vector table.

11.5 Register Description

11.5.1

MCUCR – MCU Control Register

Bit

7

–

6

–

5

–

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

0x35 (0x55)

Read/Write

Initial Value

PUD

R/W

0

MCUCR

R

0

R

0

R

0

R

0

R

0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming, ATmega88 and ATmega168” on page 270 for details. To avoid unintentional

changes of Interrupt Vector tables, a special write procedure must be followed to change the

IVSEL bit:

a. Write the Interrupt Vector Change Enable (IVCE) bit to one.

b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Register is unaffected by the automatic disabling.

Note:

If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-

Write Self-Programming, ATmega88 and ATmega168” on page 270 for details on Boot Lock bits.

This bit is not available in ATmega48.

65

2545M–AVR–09/07

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explained in the IVSEL description above. See Code Example below.

Assembly Code Example

Move_interrupts:

; Get MCUCR

in r16, MCUCR

mov r17, r16

; Enable change of Interrupt Vectors

ori r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r17, (1<<IVSEL)

out MCUCR, r17

ret

C Code Example

void Move_interrupts(void)

{

uchar temp;

/* Get MCUCR*/

temp = MCUCR

/* Enable change of Interrupt Vectors */

MCUCR = temp|(1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = temp|(1<<IVSEL);

}

This bit is not available in ATmega48.

66

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

12. External Interrupts

The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins

are configured as outputs. This feature provides a way of generating a software interrupt. The

pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change

interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0

will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-

ters control which pins contribute to the pin change interrupts. Pin change interrupts on

PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for

waking the part also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is

set up as indicated in the specification for the External Interrupt Control Register A – EICRA.

When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-

rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge

interrupts on INT0 or INT1 requires the presence of an I/O clock, described in “Clock Systems

and their Distribution” on page 28. Low level interrupt on INT0 and INT1 is detected asynchro-

nously. This implies that this interrupt can be used for waking the part also from sleep modes

other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in “System Clock and Clock Options” on page 28.

12.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 12-1.

Figure 12-1. Timing of pin change interrupts

pin_lat

pcint_in_(0)

PCINT(0)

0

x

D

Q

pcint_syn

pcint_setflag

PCIF

pin_sync

PCINT(0) in PCMSK(x)

LE

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF

67

2545M–AVR–09/07

12.2 Register Description

12.2.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit

7

–

6

–

5

–

4

–

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

(0x69)

EICRA

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7..4 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the

interrupt are defined in Table 12-1. The value on the INT1 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

Table 12-1. Interrupt 1 Sense Control

ISC11

ISC10

Description

0

1

0

1

0

1

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 12-2. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

Table 12-2. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

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ATmega48/88/168

12.2.2

EIMSK – External Interrupt Mask Register

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

0

0x1D (0x3D)

Read/Write

Initial Value

INT1

R/W

0

INT0

R/W

0

EIMSK

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 1 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT1 is configured as an output. The corresponding interrupt of External

Interrupt Request 1 is executed from the INT1 Interrupt Vector.

• Bit 0 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT0 is configured as an output. The corresponding interrupt of External

Interrupt Request 0 is executed from the INT0 Interrupt Vector.

12.2.3

EIFR – External Interrupt Flag Register

Bit

0x1C (0x3C)

7

6

–

5

–

4

–

3

–

2

–

1

INTF1

R/W

0

INTF0

R/W

0

–

EIFR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set

(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

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2545M–AVR–09/07

12.2.4

PCICR – Pin Change Interrupt Control Register

Bit

7

–

6

–

5

–

4

–

3

–

2

PCIE2

R/W

0

1

PCIE1

R/W

0

PCIE0

R/W

0

(0x68)

PCICR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 - PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2

Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

• Bit 1 - PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an inter-

rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT14..8 pins are enabled individually by the PCMSK1 Register.

• Bit 0 - PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

12.2.5

PCIFR – Pin Change Interrupt Flag Register

Bit

0x1B (0x3B)

7

6

5

–

4

–

3

–

2

PCIF2

R/W

0

1

PCIF1

R/W

0

PCIF0

R/W

0

–

PCIFR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 - PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 1 - PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

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ATmega48/88/168

• Bit 0 - PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

12.2.6

PCMSK2 – Pin Change Mask Register 2

Bit

7

6

5

PCINT21

R/W

0

4

PCINT20

R/W

0

3

PCINT19

R/W

0

2

PCINT18

R/W

0

1

PCINT17

R/W

0

PCINT16

R/W

0

PCINT23

R/W

0

PCINT22

R/W

0

PCMSK2

(0x6D)

Read/Write

Initial Value

• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16

Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on

the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

12.2.7

PCMSK1 – Pin Change Mask Register 1

Bit

7

6

PCINT14

R/W

0

5

PCINT13

R/W

0

4

PCINT12

R/W

0

3

PCINT11

R/W

0

2

PCINT10

R/W

0

1

PCINT9

R/W

0

PCINT8

R/W

0

–

R

0

PCMSK1

(0x6C)

Read/Write

Initial Value

• Bit 7 – Res: Reserved Bit

This bit is an unused bit in the ATmega48/88/168, and will always read as zero.

• Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8

Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on

the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

12.2.8

PCMSK0 – Pin Change Mask Register 0

Bit

(0x6B)

7

6

5

4

3

2

1

0

PCINT7

PCINT6

R/W

0

PCINT5

R/W

0

PCINT4

R/W

0

PCINT3

R/W

0

PCINT2

R/W

0

PCINT1

R/W

0

PCINT0

R/W

0

PCMSK0

Read/Write

Initial Value

R/W

0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin

is disabled.

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2545M–AVR–09/07

13. I/O-Ports

13.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 13-1. Refer to “Electrical Char-

acteristics” on page 304 for a complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description” on page 88.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

73. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 77. Refer to the individual module sections for a full description of the alter-

nate functions.

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ATmega48/88/168

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

13.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

SLEEP:

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

13.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description” on page 88, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

73

2545M–AVR–09/07

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

13.2.2

13.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedance environment will not notice the difference between a strong high

driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to dis-

able all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

Table 13-1. Port Pin Configurations

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

No

Comment

0

1

0

1

0

1

X

0

Input

Tri-state (Hi-Z)

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

1

Input

X

Output

No

Output Low (Sink)

Output High (Source)

No

13.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 13-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 13-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

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ATmega48/88/168

Figure 13-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

XXX

in r17, PINx

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

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2545M–AVR–09/07

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

13.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the

Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 77.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

13.2.6

76

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

13.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5

shows how the port pin control signals from the simplified Figure 13-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 13-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RESET

WRx

1

0

RRx

RPx

SYNCHRONIZER

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

I/O CLOCK

DIGITAL INPUT PIN n ON PORTx

ANALOG INPUT/OUTPUT PIN n ON PORTx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

DIxn:

AIOxn:

:

SLEEP:

SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

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2545M–AVR–09/07

Table 13-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 13-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 13-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up Override

Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the Schmitt Trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

DI

Digital Input

This is the Analog Input/output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

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ATmega48/88/168

13.3.1

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 13-3.

Table 13-3. Port B Pins Alternate Functions

Port Pin

Alternate Functions

XTAL2 (Chip Clock Oscillator pin 2)

TOSC2 (Timer Oscillator pin 2)

PCINT7 (Pin Change Interrupt 7)

PB7

XTAL1 (Chip Clock Oscillator pin 1 or External clock input)

TOSC1 (Timer Oscillator pin 1)

PB6

PCINT6 (Pin Change Interrupt 6)

SCK (SPI Bus Master clock Input)

PCINT5 (Pin Change Interrupt 5)

PB5

PB4

MISO (SPI Bus Master Input/Slave Output)

PCINT4 (Pin Change Interrupt 4)

MOSI (SPI Bus Master Output/Slave Input)

OC2A (Timer/Counter2 Output Compare Match A Output)

PCINT3 (Pin Change Interrupt 3)

PB3

SS (SPI Bus Master Slave select)

PB2

PB1

PB0

OC1B (Timer/Counter1 Output Compare Match B Output)

PCINT2 (Pin Change Interrupt 2)

OC1A (Timer/Counter1 Output Compare Match A Output)

PCINT1 (Pin Change Interrupt 1)

ICP1 (Timer/Counter1 Input Capture Input)

CLKO (Divided System Clock Output)

PCINT0 (Pin Change Interrupt 0)

The alternate pin configuration is as follows:

• XTAL2/TOSC2/PCINT7 – Port B, Bit 7

XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency

crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as chip

clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the

AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asynchronous clock-

ing of Timer/Counter2 using the Crystal Oscillator, pin PB7 is disconnected from the port, and

becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is con-

nected to this pin, and the pin cannot be used as an I/O pin.

PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.

If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.

• XTAL1/TOSC1/PCINT6 – Port B, Bit 6

XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC

Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip

clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the

79

2545M–AVR–09/07

AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis-

connected from the port, and becomes the input of the inverting Oscillator amplifier. In this

mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin.

PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.

If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.

• SCK/PCINT5 – Port B, Bit 5

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.

PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.

• MISO/PCINT4 – Port B, Bit 4

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.

PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.

• MOSI/OC2/PCINT3 – Port B, Bit 3

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.

OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the

Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output (DDB3 set

(one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer

function.

PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.

• SS/OC1B/PCINT2 – Port B, Bit 2

SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input

regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is driven low.

When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When

the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the

Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set

(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer

function.

PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.

• OC1A/PCINT1 – Port B, Bit 1

OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the

Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set

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ATmega48/88/168

(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer

function.

PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.

• ICP1/CLKO/PCINT0 – Port B, Bit 0

ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.

CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTB0 and DDB0 settings. It will also be output during reset.

PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.

Table 13-4 and Table 13-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 13-5 on page 77. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the

MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Table 13-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name

PB7/XTAL2/

PB6/XTAL1/

PB5/SCK/

PCINT5

PB4/MISO/

PCINT4

TOSC2/PCINT7⁽¹⁾

TOSC1/PCINT6⁽¹⁾

INTRC • EXTCK+

AS2

PUOE

PUOV

DDOE

INTRC + AS2

0

SPE • MSTR

PORTB5 • PUD

SPE • MSTR

PORTB4 • PUD

SPE • MSTR

0

INTRC • EXTCK+

AS2

INTRC + AS2

DDOV

PVOE

0

SPE • MSTR

SPI SLAVE

OUTPUT

PVOV

0

SCK OUTPUT

PCINT5 • PCIE0

1

INTRC • EXTCK +

AS2 + PCINT7 •

PCIE0

INTRC + AS2 +

PCINT6 • PCIE0

DIEOE

PCINT4 • PCIE0

1

(INTRC + EXTCK) •

AS2

DIEOV

DI

INTRC • AS2

PCINT5 INPUT

SCK INPUT

PCINT4 INPUT

PCINT7 INPUT

Oscillator Output

PCINT6 INPUT

SPI MSTR INPUT

Oscillator/Clock

Input

AIO

–

81

2545M–AVR–09/07

Notes: 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),

EXTCK means that external clock is selected (by the CKSEL fuses).

Table 13-5. Overriding Signals for Alternate Functions in PB3..PB0

Signal

Name

PB3/MOSI/

OC2/PCINT3

PB2/SS/

OC1B/PCINT2

PB1/OC1A/

PCINT1

PB0/ICP1/

PCINT0

PUOE

PUOV

DDOE

DDOV

SPE • MSTR

PORTB3 • PUD

SPE • MSTR

0

SPE • MSTR

PORTB2 • PUD

SPE • MSTR

0

SPE • MSTR +

OC2A ENABLE

PVOE

PVOV

OC1B ENABLE

OC1B

OC1A ENABLE

OC1A

0

SPI MSTR OUTPUT

+ OC2A

DIEOE

DIEOV

PCINT3 • PCIE0

1

PCINT2 • PCIE0

1

PCINT1 • PCIE0

1

PCINT0 • PCIE0

1

PCINT3 INPUT

PCINT2 INPUT

SPI SS

PCINT0 INPUT

ICP1 INPUT

DI

PCINT1 INPUT

–

SPI SLAVE INPUT

AIO

–

13.3.2

Alternate Functions of Port C

The Port C pins with alternate functions are shown in Table 13-6.

Table 13-6. Port C Pins Alternate Functions

Port Pin

Alternate Function

RESET (Reset pin)

PCINT14 (Pin Change Interrupt 14)

PC6

ADC5 (ADC Input Channel 5)

PC5

PC4

SCL (2-wire Serial Bus Clock Line)

PCINT13 (Pin Change Interrupt 13)

ADC4 (ADC Input Channel 4)

SDA (2-wire Serial Bus Data Input/Output Line)

PCINT12 (Pin Change Interrupt 12)

ADC3 (ADC Input Channel 3)

PCINT11 (Pin Change Interrupt 11)

PC3

PC2

PC1

PC0

ADC2 (ADC Input Channel 2)

PCINT10 (Pin Change Interrupt 10)

ADC1 (ADC Input Channel 1)

PCINT9 (Pin Change Interrupt 9)

ADC0 (ADC Input Channel 0)

PCINT8 (Pin Change Interrupt 8)

The alternate pin configuration is as follows:

• RESET/PCINT14 – Port C, Bit 6

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ATmega48/88/168

RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O

pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.

When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the

pin can not be used as an I/O pin.

If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.

PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt

source.

• SCL/ADC5/PCINT13 – Port C, Bit 5

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-

wire Serial Interface, pin PC5 is disconnected from the port and becomes the Serial Clock I/O

pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress

spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with

slew-rate limitation.

PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital

power.

PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt

source.

• SDA/ADC4/PCINT12 – Port C, Bit 4

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire

Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for

the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes

shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-

rate limitation.

PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital

power.

PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt

source.

• ADC3/PCINT11 – Port C, Bit 3

PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog

power.

PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt

source.

• ADC2/PCINT10 – Port C, Bit 2

PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog

power.

PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt

source.

• ADC1/PCINT9 – Port C, Bit 1

PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog

power.

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PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.

• ADC0/PCINT8 – Port C, Bit 0

PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog

power.

PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.

Table 13-7 and Table 13-8 relate the alternate functions of Port C to the overriding signals

shown in Figure 13-5 on page 77.

Table 13-7. Overriding Signals for Alternate Functions in PC6..PC4⁽¹⁾

Signal

Name

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PC6/RESET/PCINT14

PC5/SCL/ADC5/PCINT13

PC4/SDA/ADC4/PCINT12

RSTDISBL

TWEN

1

PORTC5 • PUD

TWEN

PORTC4 • PUD

TWEN

RSTDISBL

0

SCL_OUT

TWEN

SDA_OUT

TWEN

0

RSTDISBL + PCINT14 •

PCIE1

DIEOE

PCINT13 • PCIE1 + ADC5D

PCINT12 • PCIE1 + ADC4D

DIEOV

DI

RSTDISBL

PCINT13 • PCIE1

PCINT12 • PCIE1

PCINT14 INPUT

RESET INPUT

PCINT13 INPUT

PCINT12 INPUT

AIO

ADC5 INPUT / SCL INPUT

ADC4 INPUT / SDA INPUT

Note:

1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4

and PC5. This is not shown in the figure. In addition, spike filters are connected between the

AIO outputs shown in the port figure and the digital logic of the TWI module.

Table 13-8. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name

PC3/ADC3/

PCINT11

PC2/ADC2/

PCINT10

PC1/ADC1/

PCINT9

PC0/ADC0/

PCINT8

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

0

PCINT11 • PCIE1 +

ADC3D

PCINT10 • PCIE1 +

ADC2D

PCINT9 • PCIE1 +

ADC1D

PCINT8 • PCIE1 +

ADC0D

DIEOE

DIEOV

DI

PCINT11 • PCIE1

PCINT11 INPUT

ADC3 INPUT

PCINT10 • PCIE1

PCINT10 INPUT

ADC2 INPUT

PCINT9 • PCIE1

PCINT9 INPUT

ADC1 INPUT

PCINT8 • PCIE1

PCINT8 INPUT

ADC0 INPUT

AIO

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ATmega48/88/168

13.3.3

Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 13-9.

Table 13-9. Port D Pins Alternate Functions

Port Pin

Alternate Function

AIN1 (Analog Comparator Negative Input)

PCINT23 (Pin Change Interrupt 23)

PD7

AIN0 (Analog Comparator Positive Input)

OC0A (Timer/Counter0 Output Compare Match A Output)

PCINT22 (Pin Change Interrupt 22)

PD6

PD5

PD4

PD3

T1 (Timer/Counter 1 External Counter Input)

OC0B (Timer/Counter0 Output Compare Match B Output)

PCINT21 (Pin Change Interrupt 21)

XCK (USART External Clock Input/Output)

T0 (Timer/Counter 0 External Counter Input)

PCINT20 (Pin Change Interrupt 20)

INT1 (External Interrupt 1 Input)

OC2B (Timer/Counter2 Output Compare Match B Output)

PCINT19 (Pin Change Interrupt 19)

INT0 (External Interrupt 0 Input)

PCINT18 (Pin Change Interrupt 18)

PD2

PD1

PD0

TXD (USART Output Pin)

PCINT17 (Pin Change Interrupt 17)

RXD (USART Input Pin)

PCINT16 (Pin Change Interrupt 16)

The alternate pin configuration is as follows:

• AIN1/OC2B/PCINT23 – Port D, Bit 7

AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt

source.

• AIN0/OC0A/PCINT22 – Port D, Bit 6

AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

OC0A, Output Compare Match output: The PD6 pin can serve as an external output for the

Timer/Counter0 Compare Match A. The PD6 pin has to be configured as an output (DDD6 set

(one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer

function.

PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt

source.

85

2545M–AVR–09/07

• T1/OC0B/PCINT21 – Port D, Bit 5

T1, Timer/Counter1 counter source.

OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the

Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an output (DDD5 set

(one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer

function.

PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt

source.

• XCK/T0/PCINT20 – Port D, Bit 4

XCK, USART external clock.

T0, Timer/Counter0 counter source.

PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt

source.

• INT1/OC2B/PCINT19 – Port D, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.

OC2B, Output Compare Match output: The PD3 pin can serve as an external output for the

Timer/Counter0 Compare Match B. The PD3 pin has to be configured as an output (DDD3 set

(one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer

function.

PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt

source.

• INT0/PCINT18 – Port D, Bit 2

INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.

PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt

source.

• TXD/PCINT17 – Port D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled,

this pin is configured as an output regardless of the value of DDD1.

PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt

source.

• RXD/PCINT16 – Port D, Bit 0

RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this

pin is configured as an input regardless of the value of DDD0. When the USART forces this pin

to be an input, the pull-up can still be controlled by the PORTD0 bit.

PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt

source.

Table 13-10 and Table 13-11 relate the alternate functions of Port D to the overriding signals

shown in Figure 13-5 on page 77.

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ATmega48/88/168

Table 13-10. Overriding Signals for Alternate Functions PD7..PD4

Signal

Name

PD7/AIN1

/PCINT23

PD6/AIN0/

OC0A/PCINT22

PD5/T1/OC0B/

PCINT21

PD4/XCK/

T0/PCINT20

PUOE

PUO

0

DDOE

DDOV

PVOE

PVOV

DIEOE

DIEOV

0

OC0A ENABLE

OC0B ENABLE

UMSEL

0

OC0A

OC0B

XCK OUTPUT

PCINT20 • PCIE2

1

PCINT23 • PCIE2

1

PCINT22 • PCIE2

1

PCINT21 • PCIE2

1

PCINT20 INPUT

XCK INPUT

T0 INPUT

PCINT21 INPUT

T1 INPUT

DI

PCINT23 INPUT

AIN1 INPUT

PCINT22 INPUT

AIN0 INPUT

AIO

–

Table 13-11. Overriding Signals for Alternate Functions in PD3..PD0

Signal

Name

PD3/OC2B/INT1/

PCINT19

PD2/INT0/

PCINT18

PD1/TXD/

PCINT17

PD0/RXD/

PCINT16

PUOE

PUO

0

TXEN

0

RXEN

0

PORTD0 • PUD

DDOE

DDOV

PVOE

PVOV

0

TXEN

1

RXEN

0

OC2B ENABLE

OC2B

TXEN

TXD

INT1 ENABLE +

PCINT19 • PCIE2

INT0 ENABLE +

PCINT18 • PCIE1

DIEOE

DIEOV

DI

PCINT17 • PCIE2

PCINT16 • PCIE2

1

PCINT19 INPUT

INT1 INPUT

PCINT18 INPUT

INT0 INPUT

PCINT16 INPUT

RXD

PCINT17 INPUT

–

AIO

–

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2545M–AVR–09/07

13.4 Register Description

13.4.1

MCUCR – MCU Control Register

Bit

7

–

6

–

5

–

4

3

–

2

–

1

IVSEL

R/W

0

IVCE

R/W

0

0x35 (0x55)

Read/Write

Initial Value

PUD

R/W

0

MCUCR

R

0

R

0

R

0

R

0

R

0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 73 for more details about this feature.

13.4.2

13.4.3

13.4.4

13.4.5

13.4.6

13.4.7

PORTB – The Port B Data Register

Bit

7

6

PORTB6

R/W

0

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

PORTB7

R/W

0

PORTB

DDRB

PINB

0x05 (0x25)

Read/Write

Initial Value

DDRB – The Port B Data Direction Register

Bit

7

DDB7

R/W

0

6

DDB6

R/W

0

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

0x04 (0x24)

Read/Write

Initial Value

PINB – The Port B Input Pins Address

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

0x03 (0x23)

Read/Write

Initial Value

N/A

PORTC – The Port C Data Register

Bit

7

–

6

PORTC6

R/W

0

5

PORTC5

R/W

0

4

PORTC4

R/W

0

3

PORTC3

R/W

0

2

PORTC2

R/W

0

1

PORTC1

R/W

0

PORTC0

R/W

0

PORTC

DDRC

PINC

0x08 (0x28)

Read/Write

Initial Value

R

0

DDRC – The Port C Data Direction Register

Bit

7

–

6

DDC6

R/W

0

5

DDC5

R/W

0

4

DDC4

R/W

0

3

DDC3

R/W

0

2

DDC2

R/W

0

1

DDC1

R/W

0

DDC0

R/W

0

0x07 (0x27)

Read/Write

Initial Value

R

0

PINC – The Port C Input Pins Address

Bit

7

–

6

PINC6

R

5

PINC5

R

4

PINC4

R

3

PINC3

R

2

PINC2

R

1

PINC1

R

0

PINC0

R

0x06 (0x26)

Read/Write

Initial Value

R

0

N/A

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13.4.8

13.4.9

PORTD – The Port D Data Register

Bit

7

PORTD7

R/W

0

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

0x0B (0x2B)

Read/Write

Initial Value

DDRD – The Port D Data Direction Register

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

0x0A (0x2A)

Read/Write

Initial Value

13.4.10 PIND – The Port D Input Pins Address

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

0x09 (0x29)

Read/Write

Initial Value

N/A

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14. 8-bit Timer/Counter0 with PWM

14.1 Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

14.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units, and with PWM support. It allows accurate program execution timing (event man-

agement) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual

placement of I/O pins, refer to “Pinout ATmega48/88/1682545M” on page 2. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “Register Description” on page 102.

The PRTIM0 bit in “Minimizing Power Consumption” on page 42 must be written to zero to

enable Timer/Counter0 module.

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Figure 14-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Direction

Clock Select

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

0

OCnA

(Int.Req.)

Waveform

OCnA

=

Generation

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

OCnB

=

Generation

OCRnB

TCCRnA

TCCRnB

14.2.1

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the document.

Table 14-1. Definitions

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x00.

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is depen-

dent on the mode of operation.

14.2.2

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

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The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See “Using the Output Compare Unit” on page 119. for details. The compare match

event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Out-

put Compare interrupt request.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-

caler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 138.

14.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

top

bottom

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

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The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

Control Register B (TCCR0B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 95.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

14.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation (“Modes of Operation” on page 95).

Figure 14-3 shows a block diagram of the Output Compare unit.

Figure 14-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnx1:0

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare

Registers to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

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The OCR0x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly.

14.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0x) bit. Forcing compare match will not set the

OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare

match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

14.5.2

14.5.3

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when

changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

14.6 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses

the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match.

Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 shows a simplified

schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR

and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x

state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur,

the OC0x Register is reset to “0”.

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Figure 14-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 102.

14.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 14-2 on page 102. For fast PWM mode, refer to Table 14-3 on

page 102, and for phase correct PWM refer to Table 14-4 on page 103.

A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

14.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output

mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See “Compare Match Output Unit” on page 94.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 100.

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14.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

14.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 14-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

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the pin is set to output. The waveform generated will have a maximum frequency of f_OC0

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

14.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match

between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0x and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

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In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows

the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available

for the OC0B pin (see Table 14-6 on page 103). The actual OC0x value will only be visible on

the port pin if the data direction for the port pin is set as output. The PWM waveform is gener-

ated by setting (or clearing) the OC0x Register at the compare match between OCR0x and

TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is

cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

14.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match

between TCNT0 and OCR0x while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x

and TCNT0.

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Figure 14-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (see Table 14-7 on page 104). The actual OC0x value will only be

visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is

generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and

TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare

match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 OCnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCRnx changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

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symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCRnx, and for that reason

misses the Compare Match and hence the OCnx change that would have happened on the

way up.

14.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 14-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 14-9 shows the same timing data, but with the prescaler enabled.

Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

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Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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14.9 Register Description

14.9.1

TCCR0A – Timer/Counter Control Register A

Bit

7

COM0A1

R/W

6

COM0A0

R/W

5

COM0B1

R/W

4

COM0B0

R/W

3

–

2

–

1

WGM01

R/W

0

WGM00

R/W

0

TCCR0A

0x24 (0x44)

Read/Write

Initial Value

R

0

R

0

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 14-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 14-2. Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Table 14-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match, set OC0A at BOTTOM,

(non-inverting mode)

Set OC0A on Compare Match, clear OC0A at BOTTOM,

(inverting mode)

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on

page 97 for more details.

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Table 14-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 14-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match when up-counting. Set OC0A on

Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 124 for more details.

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0

bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin

must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the

WGM02:0 bit setting. Table 14-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 14-5. Compare Output Mode, non-PWM Mode

COM0B1

COM0B0

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Toggle OC0B on Compare Match

Clear OC0B on Compare Match

Set OC0B on Compare Match

Table 14-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 14-6. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0B1

COM0B0

Description

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at BOTTOM,

(non-inverting mode)

1

0

1

Set OC0B on Compare Match, clear OC0B at BOTTOM,

(inverting mode)

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Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 97

for more details.

Table 14-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 14-7. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0B1

COM0B0

Description

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on

Compare Match when down-counting.

1

0

1

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 98 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-8. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 95).

Table 14-8. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Operation

Update of

OCRx at

TOV Flag

Mode

WGM02

WGM01

WGM00

TOP

Set on⁽¹⁾⁽²⁾

0

Normal

0xFF

Immediate

TOP

MAX

PWM, Phase

Correct

1

0

1

0xFF

BOTTOM

2

3

4

0

1

0

1

0

CTC

OCRA

0xFF

–

Immediate

BOTTOM

–

MAX

–

Fast PWM

Reserved

PWM, Phase

Correct

5

1

0

1

OCRA

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCRA

BOTTOM

TOP

Notes: 1. MAX

= 0xFF

2. BOTTOM = 0x00

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14.9.2

TCCR0B – Timer/Counter Control Register B

Bit

7

FOC0A

W

6

FOC0B

W

5

–

4

–

3

WGM02

R/W

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

TCCR0B

0x25 (0x45)

Read/Write

Initial Value

R

0

R

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “TCCR0A – Timer/Counter Control Register A” on page 102.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

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Table 14-9. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.9.3

TCNT0 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

0x26 (0x46)

Read/Write

Initial Value

TCNT0[7:0]

TCNT0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

14.9.4

OCR0A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

0x27 (0x47)

Read/Write

Initial Value

OCR0A[7:0]

OCR0A

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

14.9.5

OCR0B – Output Compare Register B

Bit

7

6

5

4

3

2

1

0

0x28 (0x48)

Read/Write

Initial Value

OCR0B[7:0]

OCR0B

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0B pin.

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14.9.6

TIMSK0 – Timer/Counter Interrupt Mask Register

Bit

7

–

6

–

5

–

4

–

3

–

2

OCIE0B

R/W

0

1

OCIE0A

R/W

0

TOIE0

R/W

0

(0x6E)

TIMSK0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

14.9.7

TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bit

0x15 (0x35)

7

6

5

–

4

–

3

–

2

OCF0B

R/W

0

1

OCF0A

R/W

0

TOV0

R/W

0

–

TIFR0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

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• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-8, “Waveform

Generation Mode Bit Description” on page 104.

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15. 16-bit Timer/Counter1 with PWM

15.1 Features

• True 16-bit Design (i.e., Allows 16-bit PWM)

• Two independent Output Compare Units

• Double Buffered Output Compare Registers

• One Input Capture Unit

• Input Capture Noise Canceler

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• External Event Counter

• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

15.2 Overview

The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement.

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a program, the precise form must be

used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1. For the actual

placement of I/O pins, refer to “Pinout ATmega48/88/1682545M” on page 2. CPU accessible I/O

Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the “Register Description” on page 131.

The PRTIM1 bit in “PRR – Power Reduction Register” on page 45 must be written to zero to

enable Timer/Counter1 module.

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Figure 15-1. 16-bit Timer/Counter Block Diagram⁽¹⁾

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

OCnB

(Int.Req.)

Fixed

TOP

Values

Waveform

Generation

=

OCRnB

( From Analog

Comparator Ouput )

ICFn (Int.Req.)

Edge

Detector

Noise

Canceler

ICRn

ICPn

TCCRnA

TCCRnB

Note:

1. Refer to Figure 1-1 on page 2, Table 13-3 on page 79 and Table 13-9 on page 85 for

Timer/Counter1 pin placement and description.

15.2.1

Registers

The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section “Accessing 16-bit Registers” on

page 111. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with

the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk ).

1

T

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-

ator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See

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“Output Compare Units” on page 118.. The compare match event will also set the Compare

Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See

“Analog Comparator” on page 242.) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using

OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used

as an alternative, freeing the OCR1A to be used as PWM output.

15.2.2

Definitions

The following definitions are used extensively throughout the section:

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x0000.

The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is

dependent of the mode of operation.

TOP

15.3 Accessing 16-bit Registers

The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via

the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.

Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers within each 16-bit

timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a

16-bit register is written by the CPU, the high byte stored in the temporary register, and the low

byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of

a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-

rary register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-

bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit

access.

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Assembly Code Examples⁽¹⁾

...

; Set TCNT1 to 0x01FF

ldir17,0x01

ldir16,0xFF

outTCNT1H,r17

outTCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples⁽¹⁾

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

Note:

1. See ”About Code Examples” on page 9.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

the main code and the interrupt code update the temporary register, the main code must disable

the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNT1 Register contents.

Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

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Assembly Code Example⁽¹⁾

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

Note:

1. See ”About Code Examples” on page 9.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example returns the TCNT1 value in the r17:r16 register pair.

The following code examples show how to do an atomic write of the TCNT1 Register contents.

Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

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Assembly Code Example⁽¹⁾

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

outTCNT1H,r17

outTCNT1L,r16

; Restore global interrupt flag

outSREG,r18

ret

C Code Example⁽¹⁾

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

Note:

1. See ”About Code Examples” on page 9.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

15.3.1

Reusing the Temporary High Byte Register

If writing to more than one 16-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

15.4 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits

located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and

prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 138.

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15.5 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 15-2 shows a block diagram of the counter and its surroundings.

Figure 15-2. Counter Unit Block Diagram

DATA BUS (8-bit)

TOVn

(Int.Req.)

TEMP (8-bit)

Clock Select

Count

Clear

Edge

Detector

Tn

TCNTnH (8-bit)

TCNTnL (8-bit)

clk_Tn

Control Logic

Direction

TCNTn (16-bit Counter)

( From Prescaler )

TOP

BOTTOM

Signal description (internal signals):

Count

Increment or decrement TCNT1 by 1.

Direction

Clear

Select between increment and decrement.

Clear TCNT1 (set all bits to zero).

clk_T

Timer/Counter clock.

1

TOP

Signalize that TCNT1 has reached maximum value.

BOTTOM

Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-

taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight

bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an

access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).

The temporary register is updated with the TCNT1H value when the TCNT1L is read, and

TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk ). The clk ₁can be generated from an external or internal clock source,

1

T

selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the

timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of

whether clk_Tis present or not. A CPU write overrides (has priority over) all counter clear or

1

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).

There are close connections between how the counter behaves (counts) and how waveforms

are generated on the Output Compare outputs OC1x. For more details about advanced counting

sequences and waveform generation, see “Modes of Operation” on page 121.

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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by

the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

15.6 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-

tiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of

the block diagram that are not directly a part of the Input Capture unit are gray shaded. The

small “n” in register and bit names indicates the Timer/Counter number.

Figure 15-3. Input Capture Unit Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

ICRnH (8-bit)

ICRnL (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

ICRn (16-bit Register)

TCNTn (16-bit Counter)

WRITE

ACO*

ACIC*

ICNC

ICES

Analog

Comparator

Noise

Canceler

Edge

Detector

ICFn (Int.Req.)

ICPn

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively

on the Analog Comparator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at

the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),

the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically

cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software

by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low

byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied

into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will

access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes

the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-

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tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1

Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location

before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 111.

15.6.1

Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the T1 pin (Figure 16-1 on page 138). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICR1 to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

15.6.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in

Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

15.6.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dependent on the maximum number of clock

cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during operation, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICR1

Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be

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cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICF1 Flag is not required (if an interrupt handler is used).

15.7 Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register

(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output

Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-

pare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared

when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See “Modes of Operation” on page 121.)

A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 15-4 shows a block diagram of the Output Compare unit. The small “n” in the register and

bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output

Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output

Compare unit are gray shaded.

Figure 15-4. Output Compare Unit, Block Diagram

DATA BUS (8-bit)

TEMP (8-bit)

OCRnxH Buf. (8-bit)

OCRnxL Buf. (8-bit)

TCNTnH (8-bit)

TCNTnL (8-bit)

OCRnx Buffer (16-bit Register)

TCNTn (16-bit Counter)

OCRnxH (8-bit)

OCRnxL (8-bit)

OCRnx (16-bit Register)

=

(16-bit Comparator )

OCFnx (Int.Req.)

TOP

OCnx

Waveform Generator

BOTTOM

WGMn3:0

COMnx1:0

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the

double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

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prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-

put glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)

Register is only changed by a write operation (the Timer/Counter does not update this register

automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte

temporary register (TEMP). However, it is a good practice to read the low byte first as when

accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare

Register in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”

on page 111.

15.7.1

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the

OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare

match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or

toggled).

15.7.2

15.7.3

Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the

same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT1 when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-

pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

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15.8 Compare Match Output Unit

The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses

the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified

schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the

OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset

occur, the OC1x Register is reset to “0”.

Figure 15-5. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform

Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visi-

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 15-1, Table 15-2 and Table 15-3 for

details.

The design of the Output Compare pin logic allows initialization of the OC1x state before the out-

put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 131.

The COM1x1:0 bits have no effect on the Input Capture unit.

15.8.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OC1x Register is to be performed on the next compare match. For compare output actions in the

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non-PWM modes refer to Table 15-1 on page 131. For fast PWM mode refer to Table 15-2 on

page 131, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on

page 132.

A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

15.9 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output

mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare

match (See “Compare Match Output Unit” on page 120.)

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 128.

15.9.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in

the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maximum

interval between the external events must not exceed the resolution of the counter. If the interval

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

15.9.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register

are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when

the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =

12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This

mode allows greater control of the compare match output frequency. It also simplifies the opera-

tion of counting external events.

The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT1)

increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)

is cleared.

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Figure 15-6. CTC Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnA

(Toggle)

(COMnA1:0 = 1)

1

2

3

4

Period

An interrupt can be generated at each time the counter value reaches the TOP value by either

using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-

ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a

low prescaler value must be done with care since the CTC mode does not have the double buff-

ering feature. If the new value written to OCR1A or ICR1 is lower than the current value of

TCNT1, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-

quency of f_{OC A}= f_{clk_I/O}/2 when OCR1A is set to zero (0x0000). The waveform frequency is

1

defined by the following equation:

f

clk_I/O

f

= --------------------------------------------------

OCnA

2 ⋅ N ⋅ (1 + OCRnA)

The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x0000.

15.9.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation option. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared

on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare

Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope

operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-

rect and phase and frequency correct PWM modes that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or

OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-

imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be

calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

FPWM

log(2)

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =

14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure

shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the

timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1

slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will

be set when a compare match occurs.

Figure 15-7. Fast PWM Mode, Timing Diagram

OCRnx/BOTTOM Update

and TOVn Interrupt Flag Set

and OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

1

2

3

4

5

6

7

8

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition

the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A

or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP

value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low

value when the counter is running with none or a low prescaler value, there is a risk that the new

ICR1 value written is lower than the current value of TCNT1. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location

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to be written anytime. When the OCR1A I/O location is written the value written will be put into

the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done

at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM1x1:0 to three (see Table on page 131). The actual OC1x

value will only be visible on the port pin if the data direction for the port pin is set as output

(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at

the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ----------------------------------

OCnxPWM

N ⋅ (1 + TOP)

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only

if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have

a maximum frequency of f_{OC A}= f_{clk_I/O}/2 when OCR1A is set to zero (0x0000). This feature is

1

similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-

pare unit is enabled in the fast PWM mode.

15.9.4

Phase Correct PWM Mode

The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is

cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is

inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

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0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

log(TOP + 1)

R

= ----------------------------------

PCPWM

log(2)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1

(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-8. The figure

shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter-

rupt Flag will be set when a compare match occurs.

Figure 15-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When

either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-

ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer

value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCR1x Registers are written. As the third period shown in Figure 15-8 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an

unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg-

ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This

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implies that the length of the falling slope is determined by the previous TOP value, while the

length of the rising slope is determined by the new TOP value. When these two values differ the

two slopes of the period will differ in length. The difference in length gives the unsymmetrical

result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changing the TOP value while the Timer/Counter is running. When using a static

TOP value there are practically no differences between the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM1x1:0 to three (See Table on page 132). The

actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as

output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Regis-

ter at the compare match between OCR1x and TCNT1 when the counter increments, and

clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when

the counter decrements. The PWM frequency for the output when using phase correct PWM can

be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If

OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output

will toggle with a 50% duty cycle.

15.9.5

Phase and Frequency Correct PWM Mode

The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM

mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while

upcounting, and set on the compare match while downcounting. In inverting Compare Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM modes, these modes are preferred for motor control applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 15-

8 and Figure 15-9).

The PWM resolution for the phase and frequency correct PWM mode can be defined by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and

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the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can

be calculated using the following equation:

log(TOP + 1)

R

= ----------------------------------

PFCPWM

log(2)

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 15-9. The figure shows phase and frequency correct

PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre-

sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a

compare match occurs.

Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

4

Period

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x

Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1

is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.

The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the

TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table on

page 132). The actual OC1x value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)

the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-

ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and

TCNT1 when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ---------------------------

OCnxPFCPWM

2 ⋅ N ⋅ TOP

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A

is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle

with a 50% duty cycle.

15.10 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for

modes utilizing double buffering). Figure 15-10 shows a timing diagram for the setting of OCF1x.

Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 15-11 shows the same timing data, but with the prescaler enabled.

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Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and

frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.

The same renaming applies for modes that set the TOV1 Flag at BOTTOM.

Figure 15-12. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

New OCRnx Value

Old OCRnx Value

Figure 15-13 shows the same timing data, but with the prescaler enabled.

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Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk

I/O

clk

Tn

(clk /8)

I/O

TCNTn

TOP - 1

TOP

BOTTOM

TOP - 1

BOTTOM + 1

TOP - 2

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOVn(FPWM)

and ICFn(if used

as TOP)

OCRnx

(Update at TOP)

Old OCRnx Value

New OCRnx Value

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15.11 Register Description

15.11.1 TCCR1A – Timer/Counter1 Control Register A

Bit

7

COM1A1

R/W

6

COM1A0

R/W

5

COM1B1

R/W

4

COM1B0

R/W

3

–

2

–

1

WGM11

R/W

0

WGM10

R/W

0

TCCR1A

(0x80)

Read/Write

Initial Value

R

0

R

0

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-

tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OC1A or OC1B pin must be set in order to enable the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-

dent of the WGM13:0 bits setting. Table 15-1 shows the COM1x1:0 bit functionality when the

WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

Table 15-1. Compare Output Mode, non-PWM

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

1

Normal port operation, OC1A/OC1B disconnected.

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set output to

low level).

1

0

1

Set OC1A/OC1B on Compare Match (Set output to

high level).

Table 15-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast

PWM mode.

Table 15-2. Compare Output Mode, Fast PWM⁽¹⁾

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 14 or 15: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

0

1

Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at BOTTOM (non-inverting mode)

1

0

1

Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at BOTTOM (invertiong mode)

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Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In

this case the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast

PWM Mode” on page 122. for more details.

Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase

correct or the phase and frequency correct, PWM mode.

Table 15-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM⁽¹⁾

COM1A1/COM1B1

COM1A0/COM1B0

Description

0

Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 9 or 11: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

0

1

Clear OC1A/OC1B on Compare Match when up-

counting. Set OC1A/OC1B on Compare Match when

downcounting.

1

0

1

Set OC1A/OC1B on Compare Match when up-

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

Note:

1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See

“Phase Correct PWM Mode” on page 124. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 15-4. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 121.).

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Table 15-4. Waveform Generation Mode Bit Description⁽¹⁾

WGM12

(CTC1)

WGM11

WGM10

Timer/Counter Mode of

Update of

OCR1x at

TOV1 Flag

Set on

Mode

WGM13

(PWM11) (PWM10) Operation

TOP

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal

0xFFFF

0x00FF

0x01FF

0x03FF

OCR1A

0x00FF

0x01FF

0x03FF

Immediate

TOP

MAX

PWM, Phase Correct, 8-bit

PWM, Phase Correct, 9-bit

PWM, Phase Correct, 10-bit

CTC

BOTTOM

MAX

TOP

Immediate

BOTTOM

Fast PWM, 8-bit

TOP

Fast PWM, 9-bit

TOP

Fast PWM, 10-bit

TOP

PWM, Phase and Frequency

Correct

8

9

1

0

1

ICR1

BOTTOM

PWM, Phase and Frequency

Correct

OCR1A

10

11

12

13

14

15

1

0

1

0

1

0

1

0

1

0

1

PWM, Phase Correct

CTC

ICR1

OCR1A

ICR1

–

TOP

BOTTOM

MAX

TOP

Immediate

–

(Reserved)

–

Fast PWM

ICR1

OCR1A

BOTTOM

TOP

Fast PWM

TOP

Note:

1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

15.11.2 TCCR1B – Timer/Counter1 Control Register B

Bit

7

ICNC1

R/W

0

6

ICES1

R/W

0

5

–

4

WGM13

R/W

0

3

WGM12

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

(0x81)

TCCR1B

Read/Write

Initial Value

R

0

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four

successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this

can be used to cause an Input Capture Interrupt, if this interrupt is enabled.

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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure

15-10 and Figure 15-11.

Table 15-5. Clock Select Bit Description

CS12

CS11

CS10

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_I/O/1 (No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T1 pin. Clock on falling edge.

External clock source on T1 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

15.11.3 TCCR1C – Timer/Counter1 Control Register C

Bit

(0x82)

7

6

5

–

4

–

3

–

2

–

1

–

0

–

FOC1A

FOC1B

TCCR1C

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – FOC1A: Force Output Compare for Channel A

• Bit 6 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode..

When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on

the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0

bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the

value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCR1A as TOP.

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The FOC1A/FOC1B bits are always read as zero.

15.11.4 TCNT1H and TCNT1L – Timer/Counter1

Bit

7

6

5

4

3

2

1

0

(0x85)

TCNT1[15:8]

TCNT1[7:0]

TCNT1H

TCNT1L

(0x84)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 111.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-

pare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock

for all compare units.

15.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A

Bit

7

6

5

4

3

2

1

0

(0x89)

OCR1A[15:8]

OCR1A[7:0]

OCR1AH

OCR1AL

(0x88)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

15.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B

Bit

7

6

5

4

3

2

1

0

(0x8B)

OCR1B[15:8]

OCR1B[7:0]

OCR1BH

OCR1BL

(0x8A)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See “Accessing 16-bit Registers” on page 111.

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15.11.7 ICR1H and ICR1L – Input Capture Register 1

Bit

7

6

5

4

3

2

1

0

(0x87)

ICR1[15:8]

ICR1[7:0]

ICR1H

ICR1L

(0x86)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 111.

15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register

Bit

(0x6F)

7

6

5

4

–

3

–

2

OCIE1B

R/W

0

1

OCIE1A

R/W

0

TOIE1

R/W

0

–

ICIE1

TIMSK1

Read/Write

Initial Value

R

0

R

0

R/W

0

R

0

R

0

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 57) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Interrupts” on page 57) is executed when the TOV1 Flag, located in TIFR1, is set.

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15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register

Bit

7

–

6

–

5

4

–

3

–

2

OCF1B

R/W

0

1

OCF1A

R/W

0

TOV1

R/W

0

0x16 (0x36)

Read/Write

Initial Value

ICF1

R/W

0

TIFR1

R

0

R

0

R

0

R

0

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the

counter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,

the TOV1 Flag is set when the timer overflows. Refer to Table 15-4 on page 133 for the TOV1

Flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

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16. Timer/Counter0 and Timer/Counter1 Prescalers

“8-bit Timer/Counter0 with PWM” on page 90 and “16-bit Timer/Counter1 with PWM” on page

109 share the same prescaler module, but the Timer/Counters can have different prescaler set-

tings. The description below applies to both Timer/Counter1 and Timer/Counter0.

16.0.1

16.0.2

Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024.

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is

not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications

for situations where a prescaled clock is used. One example of prescaling artifacts occurs when

the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock

cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system

clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

16.0.3

External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk_T1/clk_T0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-1

shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector

logic. The registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch

is transparent in the high period of the internal system clock.

The edge detector generates one clk_T1/clk_Tpulse for each positive (CSn2:0 = 7) or negative

0

(CSn2:0 = 6) edge it detects.

Figure 16-1. T1/T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1⁽¹⁾

clk_I/O

Clear

PSRSYNC

T0

Synchronization

T1

Synchronization

clk_T1

clk_T0

Note:

1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1.

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16.1 Register Description

16.1.1

GTCCR – General Timer/Counter Control Register

Bit

7

6

–

5

–

4

–

3

–

2

–

1

PSRASY

R/W

0

PSRSYNC

R/W

0x23 (0x43)

Read/Write

Initial Value

TSM

R/W

0

GTCCR

R

0

R

0

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

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17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

17.1 Features

• Single Channel Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)

• Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

17.2 Overview

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified

block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of

I/O pins, refer to “Pinout ATmega48/88/1682545M” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “Register Description” on page 154.

The PRTIM2 bit in “Minimizing Power Consumption” on page 42 must be written to zero to

enable Timer/Counter2 module.

Figure 17-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

Generation

=

OCRnB

TCCRnA

TCCRnB

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17.2.1

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-

isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag

Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register

(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk_T2).

The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and

OC2B). See “Output Compare Unit” on page 143. for details. The compare match event will also

set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare

interrupt request.

17.2.2

Definitions

Many register and bit references in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2

counter value and so on.

The definitions in Table 17-1 are also used extensively throughout the section.

Table 17-1. Definitions

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes zero (0x00).

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR2A Register. The assignment is depen-

dent on the mode of operation.

17.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk_T2is by default equal to the MCU clock, clk_I/O. When the AS2

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR

– Asynchronous Status Register” on page 160. For details on clock sources and prescaler, see

“Timer/Counter Prescaler” on page 153.

17.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

17-2 shows a block diagram of the counter and its surrounding environment.

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Figure 17-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

TOSC1

count

clear

T/C

Oscillator

clk _Tn

TCNTn

Control Logic

Prescaler

direction

TOSC2

clk

bottom

top

I/O

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT2 by 1.

Selects between increment and decrement.

Clear TCNT2 (set all bits to zero).

clk_Tn

Timer/Counter clock, referred to as clk_T2in the following.

Signalizes that TCNT2 has reached maximum value.

Signalizes that TCNT2 has reached minimum value (zero).

top

bottom

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T2). clk_T2can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk_T2is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 146.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

17.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a

match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the Output Compare Flag can be cleared by software by writing a logical

one to its I/O bit location. The Waveform Generator uses the match signal to generate an output

according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)

bits. The max and bottom signals are used by the Waveform Generator for handling the special

cases of the extreme values in some modes of operation (“Modes of Operation” on page 146).

Figure 17-3 shows a block diagram of the Output Compare unit.

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Figure 17-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

=

(8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare

Register to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR2x directly.

17.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the

OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare

match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or

toggled).

17.5.2

17.5.3

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

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The setup of the OC2x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com-

pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM2x1:0 bits are not double buffered together with the compare value.

Changing the COM2x1:0 bits will take effect immediately.

17.6 Compare Match Output Unit

The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses

the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.

Also, the COM2x1:0 bits control the OC2x pin output source. Figure 17-4 shows a simplified

schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the

OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.

Figure 17-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCnx

D

Q

1

0

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform

Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC2x state before the out-

put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 154.

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17.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the

OC2x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 17-5 on page 155. For fast PWM mode, refer to Table 17-6 on

page 156, and for phase correct PWM refer to Table 17-7 on page 156.

A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2x strobe bits.

17.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output

mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See “Compare Match Output Unit” on page 145.).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 150.

17.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV2 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

17.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the compare match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

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Figure 17-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCnx

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR2A is lower than the current

value of TCNT2, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC2A

_{clk_I/O}/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= -------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

17.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2x and TCNT2.

Figure 17-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCnx

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.

Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,

and OCR2A when MGM2:0 = 7. (See Table 17-3 on page 155). The actual OC2x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by setting (or clearing) the OC2x Register at the compare match between

OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the

counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= -----------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform

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generated will have a maximum frequency of f_oc2= f_{clk_I/O}/2 when OCR2A is set to zero. This fea-

ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

17.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 17-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x

and TCNT2.

Figure 17-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCnx

(COMnx1:0 = 3)

OCnx

1

2

3

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM

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output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when

WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 17-4 on page 155). The actual OC2x

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match

between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x

Register at compare match between OCR2x and TCNT2 when the counter decrements. The

PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

f

clk_I/O

f

= -----------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 17-7 OCnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR2A changes its value from MAX, like in Figure 17-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting compare match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR2A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the way

up.

17.8 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk_T2)

is therefore shown as a clock enable signal. In asynchronous mode, clk_I/Oshould be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 17-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 17-9 shows the same timing data, but with the prescaler enabled.

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Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 17-10 shows the setting of OCF2A in all modes except CTC mode.

Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 17-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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17.9 Asynchronous Operation of Timer/Counter2

When Timer/Counter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe

procedure for switching clock source is:

a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.

b. Select clock source by setting AS2 as appropriate.

c. Write new values to TCNT2, OCR2x, and TCCR2x.

d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.

e. Clear the Timer/Counter2 Interrupt Flags.

f. Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a

temporary register, and latched after two positive edges on TOSC1. The user should not write

a new value before the contents of the temporary register have been transferred to its

destination. Each of the five mentioned registers have their individual temporary register, which

means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a

transfer to the destination register has taken place, the Asynchronous Status Register – ASSR

has been implemented.

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2x, or TCCR2x, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if any of the Output Compare2

interrupt is used to wake up the device, since the Output Compare function is disabled during

writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode

before the corresponding OCR2xUB bit returns to zero, the device will never receive a

compare match interrupt, and the MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction

mode, precautions must be taken if the user wants to re-enter one of these modes: If re-

entering sleep mode within the TOSC1 cycle, the interrupt will immidiately occur and the

device wake up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle

from the first interrupt. If the user is in doubt whether the time before re-entering Power-save or

ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that

one TOSC1 cycle has elapsed:

a. Write a value to TCCR2x, TCNT2, or OCR2x.

b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

c. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is

always running, except in Power-down and Standby modes. After a Power-up Reset or wake-

up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator

might take as long as one second to stabilize. The user is advised to wait for at least one

second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby

mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up

from Power-down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

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• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock

(clk_I/O) again becomes active, TCNT2 will read as the previous value (before entering sleep)

until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-

save mode is essentially unpredictable, as it depends on the wake-up time. The recommended

procedure for reading TCNT2 is thus as follows:

a. Write any value to either of the registers OCR2x or TCCR2x.

b. Wait for the corresponding Update Busy Flag to be cleared.

c. Read TCNT2.

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous

timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least

one before the processor can read the timer value causing the setting of the Interrupt Flag. The

Output Compare pin is changed on the timer clock and is not synchronized to the processor

clock.

17.10 Timer/Counter Prescaler

Figure 17-12. Prescaler for Timer/Counter2

clk_I/O

clk_T2S

10-BIT T/C PRESCALER

Clear

TOSC1

AS2

PSRASY

0

CS20

CS21

CS22

TIMER/COUNTER2 CLOCK SOURCE

clk_T2

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The clock source for Timer/Counter2 is named clk_T2S. clk_T2Sis by default connected to the main

system I/O clock clk_IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal.

For Timer/Counter2, the possible prescaled selections are: clk_T2S/8, clk_T2S/32, clk_T2S/64,

clk_T2S/128, clk_T2S/256, and clk_T2S/1024. Additionally, clk_T2Sas well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

17.11 Register Description

17.11.1 TCCR2A – Timer/Counter Control Register A

Bit

7

COM2A1

R/W

6

COM2A0

R/W

5

COM2B1

R/W

4

COM2B0

R/W

3

–

2

–

1

WGM21

R/W

0

WGM20

R/W

0

TCCR2A

(0xB0)

Read/Write

Initial Value

R

0

R

0

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 17-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-2. Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

0

1

0

1

0

1

Normal port operation, OC2A disconnected.

Toggle OC2A on Compare Match

Clear OC2A on Compare Match

Set OC2A on Compare Match

Table 17-3 on page 155 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set

to fast PWM mode.

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Table 17-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC0A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

0

1

0

1

Clear OC2A on Compare Match, set OC2A at BOTTOM,

(non-inverting mode)

Set OC2A on Compare Match, clear OC2A at BOTTOM,

(inverting mode)

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 147

for more details.

Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Table 17-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2A1

COM2A0

Description

0

Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC2A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

0

1

0

1

Clear OC2A on Compare Match when up-counting. Set OC2A on

Compare Match when down-counting.

Set OC2A on Compare Match when up-counting. Clear OC2A on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

• Bits 5:4 – COM2B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0

bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin

must be set in order to enable the output driver.

When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the

WGM22:0 bit setting. Table 17-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-5. Compare Output Mode, non-PWM Mode

COM2B1

COM2B0

Description

0

1

0

1

0

1

Normal port operation, OC2B disconnected.

Toggle OC2B on Compare Match

Clear OC2B on Compare Match

Set OC2B on Compare Match

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Table 17-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Table 17-6. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM2B1

COM2B0

Description

0

1

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match, set OC2B at BOTTOM,

(non-inverting mode)

1

0

1

Set OC2B on Compare Match, clear OC2B at BOTTOM,

(invertiing mode)

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Table 17-7. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM2B1

COM2B0

Description

0

1

Normal port operation, OC2B disconnected.

Reserved

Clear OC2B on Compare Match when up-counting. Set OC2B on

Compare Match when down-counting.

1

0

1

Set OC2B on Compare Match when up-counting. Clear OC2B on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 149 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 1:0 – WGM21:0: Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 17-8. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 146).

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Table 17-8. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Operation

Update of

OCRx at

TOV Flag

Mode

WGM2

WGM1

WGM0

TOP

Set on⁽¹⁾⁽²⁾

0

Normal

0xFF

Immediate

TOP

MAX

PWM, Phase

Correct

1

0

1

0xFF

BOTTOM

2

3

4

0

1

0

1

0

CTC

OCRA

0xFF

–

Immediate

BOTTOM

–

MAX

–

Fast PWM

Reserved

PWM, Phase

Correct

5

1

0

1

OCRA

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCRA

BOTTOM

TOP

Notes: 1. MAX= 0xFF

2. BOTTOM= 0x00

17.11.2 TCCR2B – Timer/Counter Control Register B

Bit

7

FOC2A

W

6

FOC2B

W

5

–

4

–

3

2

CS22

R

1

CS21

R/W

0

CS20

R/W

0

WGM22

TCCR2B

(0xB1)

Read/Write

Initial Value

R

0

R

0

R

0

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is

changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a

strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the

forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6 – FOC2B: Force Output Compare B

The FOC2B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is

changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a

strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the

forced compare.

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A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2B as TOP.

The FOC2B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bit 3 – WGM22: Waveform Generation Mode

See the description in the “TCCR2A – Timer/Counter Control Register A” on page 154.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

17-9.

Table 17-9. Clock Select Bit Description

CS22

CS21

CS20

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped).

clk_T2S/(No prescaling)

clk_T2S/8 (From prescaler)

clk_T2S/32 (From prescaler)

clk_T2S/64 (From prescaler)

clk_T2S/128 (From prescaler)

clk_{T S}/256 (From prescaler)

2

clk_{T S}/1024 (From prescaler)

2

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

17.11.3 TCNT2 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

(0xB2)

TCNT2[7:0]

TCNT2

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.

17.11.4 OCR2A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

(0xB3)

OCR2A[7:0]

OCR2A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

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The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2A pin.

17.11.5 OCR2B – Output Compare Register B

Bit

7

6

5

4

3

2

1

0

(0xB4)

OCR2B[7:0]

OCR2B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC2B pin.

17.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register

Bit

(0x70)

7

6

5

4

–

3

–

2

OCIE2B

R/W

0

1

OCIE2A

R/W

0

TOIE2

R/W

0

–

TIMSK2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt

Flag Register – TIFR2.

17.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register

Bit

0x17 (0x37)

7

6

5

–

4

–

3

–

2

OCF2B

R/W

0

1

OCF2A

R/W

0

TOV2

R/W

0

–

TIFR2

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 2 – OCF2B: Output Compare Flag 2 B

The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt

Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.

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• Bit 1 – OCF2A: Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

17.11.8 ASSR – Asynchronous Status Register

Bit

(0xB6)

7

6

5

4

3

2

1

0

–

EXCLK

AS2

R/W

0

TCN2UB

OCR2AUB

OCR2BUB

TCR2AUB

TCR2BUB

ASSR

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – RES: Reserved bit

This bit is reserved and will always read as zero.

• Bit 6 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input

buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead

of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is

selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 5 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk_I/O. When AS2 is

written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-

lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,

OCR2B, TCCR2A and TCCR2B might be corrupted.

• Bit 4 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.

When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.

When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.

When OCR2B has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.

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• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.

When TCCR2A has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new

value.

• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.

When TCCR2B has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new

value.

If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.

When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A

and TCCR2B the value in the temporary storage register is read.

17.11.9 GTCCR – General Timer/Counter Control Register

Bit

0x23 (0x43)

7

6

5

4

–

3

–

2

–

1

0

TSM

–

PSRASY PSRSYNC

GTCCR

Read/Write

Initial Value

R/W

0

R

0

R

0

R

0

R

0

R

0

R/W

0

R/W

0

• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-

chronization Mode” on page 140 for a description of the Timer/Counter Synchronization mode.

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18. SPI – Serial Peripheral Interface

18.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

18.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega48/88/168 and peripheral devices or between several AVR devices.

The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 200. The

PRSPI bit in “Minimizing Power Consumption” on page 42 must be written to zero to enable SPI

module.

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Figure 18-1. SPI Block Diagram⁽¹⁾

DIVIDER

/2/4/8/16/32/64/128

Note:

1. Refer to Figure 1-1 on page 2, and Table 13-3 on page 79 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The sys-

tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the

communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and

Slave prepare the data to be sent in their respective shift Registers, and the Master generates

the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-

ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In

– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling

high the Slave Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight

bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of

Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an

interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be

kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this state, software may update the contents of the SPI Data

Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin

until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission

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Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt

is requested. The Slave may continue to place new data to be sent into SPDR before reading

the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 18-2. SPI Master-slave Interconnection

SHIFT

ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the minimum low and high periods should be:

Low periods: Longer than 2 CPU clock cycles.

High periods: Longer than 2 CPU clock cycles.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden

according to Table 18-1 on page 164. For more details on automatic port overrides, refer to

“Alternate Port Functions” on page 77.

Table 18-1. SPI Pin Overrides^(Note:)

MOSI

MISO

SCK

SS

Direction, Master SPI

User Defined

Input

Direction, Slave SPI

Input

User Defined

Input

User Defined

Input

Note:

See “Alternate Functions of Port B” on page 79 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction

Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the

actual data direction bits for these pins. E.g. if MOSI is placed on pin PB3, replace DD_MOSI

with DDB3 and DDR_SPI with DDRB.

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Assembly Code Example⁽¹⁾

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

in

r16, SPSR

sbrs r16, SPIF

rjmp Wait_Transmit

ret

C Code Example⁽¹⁾

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

Note:

1. See ”About Code Examples” on page 9.

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The following code examples show how to initialize the SPI as a Slave and how to perform a

simple reception.

Assembly Code Example⁽¹⁾

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in

r16,SPDR

ret

C Code Example⁽¹⁾

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return Data Register */

return SPDR;

}

Note:

1. See ”About Code Examples” on page 9.

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18.3 SS Pin Functionality

18.3.1

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

18.3.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the following

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is

set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

18.4 Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

18-3 and Figure 18-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing

Table 18-3 and Table 18-4, as done below.

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Table 18-2. CPOL Functionality

Leading Edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing eDge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

SPI Mode

CPOL=0, CPHA=0

CPOL=0, CPHA=1

CPOL=1, CPHA=0

CPOL=1, CPHA=1

0

1

2

3

Figure 18-3. SPI Transfer Format with CPHA = 0

SCK (CPOL = 0)

mode 0

SCK (CPOL = 1)

mode 2

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0) MSB

LSB first (DORD = 1) LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

Figure 18-4. SPI Transfer Format with CPHA = 1

SCK (CPOL = 0)

mode 1

SCK (CPOL = 1)

mode 3

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SS

MSB first (DORD = 0)

LSB first (DORD = 1)

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

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18.5 Register Description

18.5.1

SPCR – SPI Control Register

Bit

7

SPIE

R/W

0

6

5

DORD

R/W

0

4

MSTR

R/W

0

3

CPOL

R/W

0

2

CPHA

R/W

0

1

SPR1

R/W

0

SPR0

R/W

0

0x2C (0x4C)

Read/Write

Initial Value

SPE

R/W

0

SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is sum-

marized below:

Table 18-3. CPOL Functionality

CPOL

Leading Edge

Rising

Trailing Edge

Falling

0

1

Falling

Rising

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL

functionality is summarized below:

Table 18-4. CPHA Functionality

CPHA

Leading Edge

Sample

Trailing Edge

Setup

0

1

Setup

Sample

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• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f_oscis

shown in the following table:

Table 18-5. Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

f_osc/4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f_osc/16

f_osc/64

f_osc/128

f_osc/2

f_osc/8

f_osc/32

f_osc/64

18.5.2

SPSR – SPI Status Register

Bit

7

SPIF

R

6

5

–

4

–

3

–

2

–

1

–

0

SPI2X

R/W

0

0x2D (0x4D)

Read/Write

Initial Value

WCOL

SPSR

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f_osc/4

or lower.

The SPI interface on the ATmega48/88/168 is also used for program memory and EEPROM

downloading or uploading. See page 299 for serial programming and verification.

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18.5.3

SPDR – SPI Data Register

Bit

7

6

5

4

3

2

1

0

0x2E (0x4E)

Read/Write

Initial Value

MSB

R/W

X

LSB

R/W

X

SPDR

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

Undefined

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

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19. USART0

19.1 Features

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High Resolution Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 200. The

Power Reduction USART bit, PRUSART0, in “Minimizing Power Consumption” on page 42 must

be disabled by writing a logical zero to it.

19.2 Overview

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a

highly flexible serial communication device.

A simplified block diagram of the USART Transmitter is shown in Table 19-1 on page 173. CPU

accessible I/O Registers and I/O pins are shown in bold.

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

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Figure 19-1. USART Block Diagram⁽¹⁾

Clock Generator

UBRRn[H:L]

OSC

BAUD RATE GENERATOR

SYNC LOGIC

CONTROL

XCKn

Transmitter

TX

CONTROL

UDRn(Transmit)

PARITY

GENERATOR

TxDn

TRANSMIT SHIFT REGISTER

CONTROL

Receiver

CLOCK

RECOVERY

RX

CONTROL

DATA

RECOVERY

CONTROL

RECEIVE SHIFT REGISTER

RxDn

PARITY

CHECKER

UDRn(Receive)

UCSRnA

UCSRnB

UCSRnC

Note:

1. Refer to Figure 1-1 on page 2 and Table 13-9 on page 85 for USART0 pin placement.

19.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

Figure 19-2 shows a block diagram of the clock generation logic.

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Figure 19-2. Clock Generation Logic, Block Diagram

UBRRn

U2Xn

foscn

UBRRn+1

Prescaling

Down-Counter

/2

/4

/2

0

1

0

1

OSC

txclk

UMSELn

rxclk

DDR_XCKn

Sync

Register

Edge

Detector

xcki

0

1

XCKn

xcko

DDR_XCKn

UCPOLn

1

0

Signal description:

txclk

Transmitter clock (Internal Signal).

Receiver base clock (Internal Signal).

rxclk

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

19.3.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 19-2.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

(f_osc), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= f_osc/(UBRRn+1)). The Transmitter divides the

baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-

put is used directly by the Receiver’s clock and data recovery units. However, the recovery units

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCKn bits.

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Table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

Table 19-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud

Rate⁽¹⁾

Equation for Calculating

UBRRn Value

Operating Mode

f

OSC

UBRRn = ----------------------- – 1

16BAUD

f

OSC

Asynchronous Normal mode

(U2Xn = 0)

BAUD = -----------------------------------------

16(UBRRn + 1)

f

OSC

UBRRn = -------------------- – 1

8BAUD

f

OSC

Asynchronous Double Speed

mode (U2Xn = 1)

BAUD = --------------------------------------

8(UBRRn + 1)

f

OSC

UBRRn = -------------------- – 1

2BAUD

f

OSC

Synchronous Master mode

BAUD = --------------------------------------

2(UBRRn + 1)

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

Baud rate (in bits per second, bps)

f_OSC

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 19-9

(see page 196).

19.3.2

Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

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19.3.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 19-2 for details.

External clock input from the XCKn pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency

is limited by the following equation:

f

OSC

-----------

f

<

XCK

4

Note that f_oscdepends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

19.3.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxDn) is sampled at the

opposite XCKn clock edge of the edge the data output (TxDn) is changed.

Figure 19-3. Synchronous Mode XCKn Timing.

UCPOL = 1

XCK

RxD / TxD

Sample

UCPOL = 0

XCK

RxD / TxD

The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is

used for data change. As Figure 19-3 shows, when UCPOLn is zero the data will be changed at

rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed

at falling XCKn edge and sampled at rising XCKn edge.

19.4 Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

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A frame starts with the start bit followed by the least significant data bit. Then the next data bits,

up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 19-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 19-4. Frame Formats

FRAME

(IDLE)

St

0

1

2

3

4

[5]

[6]

[7]

[8]

[P] Sp1 [Sp2] (St / IDLE)

St

Start bit, always low.

Data bits (0 to 8).

(n)

P

Parity bit. Can be odd or even.

Stop bit, always high.

Sp

IDLE

must be

No transfers on the communication line (RxDn or TxDn). An IDLE line

high.

The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores

the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the

first stop bit is zero.

19.4.1

Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

P

= d

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 0

3 2 1 0

even

n – 1

⊕ … ⊕ d ⊕ d ⊕ d ⊕ d ⊕ 1

odd

3 2 1 0

P_even

P^odd

d_n

Parity bit using even parity

Parity bit using odd parity

Data bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

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19.5 USART Initialization

The USART has to be initialized before any communication can take place. The initialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that there are no

ongoing transmissions during the period the registers are changed. The TXCn Flag can be used

to check that the Transmitter has completed all transfers, and the RXC Flag can be used to

check that there are no unread data in the receive buffer. Note that the TXCn Flag must be

cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.

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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

Registers.

Assembly Code Example⁽¹⁾

USART_Init:

; Set baud rate

out UBRRnH, r17

out UBRRnL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBSn)|(3<<UCSZn0)

out UCSRnC,r16

ret

C Code Example⁽¹⁾

#define FOSC 1843200 // Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void main( void )

{

...

USART_Init(MYUBRR)

...

}

void USART_Init( unsigned int ubrr)

{

/*Set baud rate */

UBRR0H = (unsigned char)(ubrr>>8);

UBRR0L = (unsigned char)ubrr;

Enable receiver and transmitter */

UCSR0B = (1<<RXEN0)|(1<<TXEN0);

/* Set frame format: 8data, 2stop bit */

UCSR0C = (1<<USBS0)|(3<<UCSZ00);

}

Note:

1. See ”About Code Examples” on page 9.

More advanced initialization routines can be made that include frame format as parameters, dis-

able interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed directly

in the main routine, or be combined with initialization code for other I/O modules.

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19.6 Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB

Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid-

den by the USART and given the function as the Transmitter’s serial output. The baud rate,

mode of operation and frame format must be set up once before doing any transmissions. If syn-

chronous operation is used, the clock on the XCKn pin will be overridden and used as

transmission clock.

19.6.1

Sending Frames with 5 to 8 Data Bit

A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The

CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or

immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2Xn bit or by XCKn depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-

nificant bits written to the UDRn are ignored. The USART has to be initialized before the function

can be used. For the assembly code, the data to be sent is assumed to be stored in Register

R16

Assembly Code Example⁽¹⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example⁽¹⁾

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) )

;

/* Put data into buffer, sends the data */

UDRn = data;

}

Note:

1. See ”About Code Examples” on page 9.

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The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,

the interrupt routine writes the data into the buffer.

19.6.2

Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCS-

RnB before the low byte of the character is written to UDRn. The following code examples show

a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is

assumed to be stored in registers R17:R16.

Assembly Code Example⁽¹⁾⁽²⁾

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRnB,TXB8

sbrc r17,0

sbi UCSRnB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example⁽¹⁾⁽²⁾

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn))) )

;

/* Copy 9th bit to TXB8 */

UCSRnB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRnB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDRn = data;

}

Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used

after initialization.

2. See ”About Code Examples” on page 9.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for other protocol handling as for example synchronization.

19.6.3

Transmitter Flags and Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty

(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.

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The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Register. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that

global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift

Register has been shifted out and there are no new data currently present in the transmit buffer.

The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-

nication interfaces (like the RS-485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART

Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt

is executed.

19.6.4

19.6.5

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxDn pin.

19.7 Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the

UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn

pin is overridden by the USART and given the function as the Receiver’s serial input. The baud

rate, mode of operation and frame format must be set up once before any serial reception can

be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer

clock.

19.7.1

Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register

until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.

When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift

Register, the contents of the Shift Register will be moved into the receive buffer. The receive

buffer can then be read by reading the UDRn I/O location.

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The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant

bits of the data read from the UDRn will be masked to zero. The USART has to be initialized

before the function can be used.

Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get and return received data from buffer

in

r16, UDRn

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get and return received data from buffer */

return UDRn;

}

Note:

1. See ”About Code Examples” on page 9.

The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,

before reading the buffer and returning the value.

19.7.2

Receiving Frames with 9 Data Bits

If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCS-

RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn

Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O

location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,

DORn and UPEn bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both nine bit

characters and the status bits.

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Assembly Code Example⁽¹⁾

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in

r18, UCSRnA

r17, UCSRnB

r16, UDRn

; If error, return -1

andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example⁽¹⁾

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRnA;

resh = UCSRnB;

resl = UDRn;

/* If error, return -1 */

if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

Note:

1. See ”About Code Examples” on page 9.

The receive function example reads all the I/O Registers into the Register File before any com-

putation is done. This gives an optimal receive buffer utilization since the buffer location read

will be free to accept new data as early as possible.

19.7.3

184

Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

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The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0),

the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive

Complete interrupt will be executed as long as the RXCn Flag is set (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

19.7.4

Receiver Error Flags

The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and

Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the

receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.

Another equality for the Error Flags is that they can not be altered by software doing a write to

the flag location. However, all flags must be set to zero when the UCSRnA is written for upward

compatibility of future USART implementations. None of the Error Flags can generate interrupts.

The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame

stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),

and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn

Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,

except for the first, stop bits. For compatibility with future devices, always set this bit to zero

when writing to UCSRnA.

The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A

Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-

ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there

was one or more serial frame lost between the frame last read from UDRn, and the next frame

read from UDRn. For compatibility with future devices, always write this bit to zero when writing

to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from

the Shift Register to the receive buffer.

The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more

details see “Parity Bit Calculation” on page 177 and “Parity Checker” on page 185.

19.7.5

Parity Checker

The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par-

ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit from the serial frame. The result of the check is stored in the receive buffer together

with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software

to check if the frame had a Parity Error.

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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is

valid until the receive buffer (UDRn) is read.

19.7.6

19.7.7

Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will

no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag

is cleared. The following code example shows how to flush the receive buffer.

Assembly Code Example⁽¹⁾

USART_Flush:

sbis UCSRnA, RXCn

ret

in

rjmp USART_Flush

C Code Example⁽¹⁾

r16, UDRn

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

Note:

1. See ”About Code Examples” on page 9.

19.8 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

19.8.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-

izontal arrows illustrate the synchronization variation due to the sampling process. Note the

larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples

denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).

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Figure 19-5. Start Bit Sampling

RxD

IDLE

START

BIT 0

Sample

(U2X = 0)

0

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

2

3

2

Sample

(U2X = 1)

0

When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

19.8.2

Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Speed mode. Figure 19-6 shows the sampling of the data bits and

the parity bit. Each of the samples is given a number that is equal to the state of the recovery

unit.

Figure 19-6. Sampling of Data and Parity Bit

RxD

BIT n

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

11

6

12

13

7

14

15

8

16

1

Sample

(U2X = 1)

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples are emphasized

on the figure by having the sample number inside boxes. The majority voting process is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

Figure 19-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit

of the next frame.

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Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling

(A)

(B)

(C)

RxD

STOP 1

Sample

(U2X = 0)

1

2

3

2

4

5

3

6

7

4

8

9

5

10

0/1 0/1 0/1

Sample

(U2X = 1)

6

0/1

The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.

A new high to low transition indicating the start bit of a new frame can come right after the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 19-7. For Double Speed mode the first low level must be delayed to

(B). (C) marks a stop bit of full length. The early start bit detection influences the operational

range of the Receiver.

19.8.3

Asynchronous Operational Range

The operational range of the Receiver is dependent on the mismatch between the received bit

rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too

slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 19-2) base frequency, the Receiver will not be able to synchronize the frames to the start

bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

(D + 1)S

S – 1 + D ⋅ S + S

(D + 2)S

(D + 1)S + S

R

= ------------------------------------------

R

= -----------------------------------

slow

fast

F

M

D

S

Sum of character size and parity size (D = 5 to 10 bit)

Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

S_F

First sample number used for majority voting. S_F= 8 for normal speed and S_F= 4

for Double Speed mode.

S_M

Middle sample number used for majority voting. S_M= 9 for normal speed and

S_M= 5 for Double Speed mode.

R_slow

is the ratio of the slowest incoming data rate that can be accepted in relation to the

receiver baud rate. R_fastis the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 19-2 and Table 19-3 list the maximum receiver baud rate error that can be tolerated. Note

that Normal Speed mode has higher toleration of baud rate variations.

188

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Table 19-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2Xn = 0)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R

_slow(%)

93.20

94.12

94.81

95.36

95.81

96.17

R_fast(%)

106.67

105.79

105.11

104.58

104.14

103.78

Max Total Error (%)

+6.67/-6.8

5

6

± 3.0

± 2.5

± 2.0

± 1.5

+5.79/-5.88

+5.11/-5.19

+4.58/-4.54

+4.14/-4.19

+3.78/-3.83

7

8

9

10

Table 19-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2Xn = 1)

D

Recommended Max

Receiver Error (%)

# (Data+Parity Bit)

R_slow(%)

94.12

94.92

95.52

96.00

96.39

96.70

R_fast(%)

105.66

104.92

104,35

103.90

103.53

103.23

Max Total Error (%)

+5.66/-5.88

5

6

± 2.5

± 2.0

± 1.5

± 1.0

+4.92/-5.08

7

+4.35/-4.48

8

+3.90/-4.00

9

+3.53/-3.61

10

+3.23/-3.30

The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the Receiver and Transmitter equally divides the maximum total error.

There are two possible sources for the receivers baud rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator the system clock may differ more than 2% depending of the resonators tolerance. The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value

that gives an acceptable low error can be used if possible.

19.9 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering

function of incoming frames received by the USART Receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the Receiver is set up for frames with

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nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When

the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the

frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

19.9.1

Using MPCMn

For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The

ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame

(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character

frame format.

The following procedure should be used to exchange data in Multi-processor Communication

mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in

UCSRnA is set).

2. The Master MCU sends an address frame, and all slaves receive and read this frame. In

the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.

3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,

it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and

keeps the MPCMn setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCMn bit and waits for a new address frame from master. The process then

repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes full-

duplex operation difficult since the Transmitter and Receiver uses the same character size set-

ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit

(USBSn = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The

MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be

cleared when using SBI or CBI instructions.

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19.10 Register Description

19.10.1 UDRn – USART I/O Data Register n

Bit

7

6

5

4

3

2

1

0

RXB[7:0]

TXB[7:0]

UDRn (Read)

UDRn (Write)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the

same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-

ister (TXB) will be the destination for data written to the UDRn Register location. Reading the

UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.

Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions

(SBIC and SBIS), since these also will change the state of the FIFO.

19.10.2 UCSRnA – USART Control and Status Register n A

Bit

7

6

5

4

FEn

R

3

DORn

R

2

UPEn

R

1

U2Xn

R/W

0

MPCMn

R/W

0

RXCn

TXCn

UDREn

UCSRnA

Read/Write

Initial Value

R

0

R/W

0

R

1

0

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCIEn bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIEn bit).

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UDREn is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error

This bit is set if the next character in the receive buffer had a Parity Error when received and the

Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-

chronous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer rate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to

one, all the incoming frames received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed

information see “Multi-processor Communication Mode” on page 189.

19.10.3 UCSRnB – USART Control and Status Register n B

Bit

7

6

5

4

RXENn

R/W

0

3

TXENn

R/W

0

2

UCSZn2

R/W

1

0

TXB8n

R/W

0

RXCIEn

TXCIEn

UDRIEn

RXB8n

UCSRnB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

0

• Bit 7 – RXCIEn: RX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable n

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

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• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 – RXENn: Receiver Enable n

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

• Bit 3 – TXENn: Transmitter Enable n

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8 n

RXB8n is the ninth data bit of the received character when operating with serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8 n

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

19.10.4 UCSRnC – USART Control and Status Register n C

Bit

7

6

5

4

UPMn0

R/W

0

3

USBSn

R/W

0

2

UCSZn1

R/W

1

UCSZn0

R/W

0

UCPOLn

R/W

UMSELn1

UMSELn0

UPMn1

UCSRnC

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

1

0

• Bits 7:6 – UMSELn1:0 USART Mode Select

These bits select the mode of operation of the USARTn as shown in Table 19-4.

Table 19-4. UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

0

1

0

1

0

1

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)⁽¹⁾

Note:

1. See “USART in SPI Mode” on page 200 for full description of the Master SPI Mode (MSPIM)

operation

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• Bits 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

Table 19-5. UPMn Bits Settings

UPMn1

UPMn0

Parity Mode

0

1

0

1

0

1

Disabled

Reserved

Enabled, Even Parity

Enabled, Odd Parity

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

Table 19-6. USBS Bit Settings

USBSn

Stop Bit(s)

1-bit

0

1

2-bit

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

Table 19-7. UCSZn Bits Settings

UCSZn2

UCSZn1

UCSZn0

Character Size

5-bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6-bit

7-bit

8-bit

Reserved

9-bit

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCKn).

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Table 19-8. UCPOLn Bit Settings

Transmitted Data Changed (Output of

Received Data Sampled (Input on RxDn

Pin)

UCPOLn

TxDn Pin)

0

1

Rising XCKn Edge

Falling XCKn Edge

Rising XCKn Edge

19.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers

Bit

15

14

13

12

11

10

9

8

–

UBRRn[11:8]

UBRRnH

UBRRnL

UBRRn[7:0]

7

R

6

R

5

R

4

R

3

R/W

0

2

R/W

0

1

R/W

0

R/W

0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRnH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four

most significant bits, and the UBRRnL contains the eight least significant bits of the USART

baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud

rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

19.11 Examples of Baud Rate Setting

For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-

chronous operation can be generated by using the UBRRn settings in Table 19-9. UBRRn

values which yield an actual baud rate differing less than 0.5% from the target baud rate, are

bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resis-

tance when the error ratings are high, especially for large serial frames (see “Asynchronous

Operational Range” on page 188). The error values are calculated using the following equation:

BaudRate_{Closest Match}

⎛

⎞

Error[%] = -------------------------------------------------- – 1 • 100%

⎝

⎠

BaudRate

195

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Table 19-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies

f_osc= 1.0000 MHz f_osc= 1.8432 MHz

U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error

f_osc= 2.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

U2Xn = 1

UBRRn Error

2400

25

12

6

0.2%

-7.0%

8.5%

-18.6%

8.5%

–

51

25

12

8

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

47

23

11

7

0.0%

-25.0%

0.0%

–

95

47

23

15

11

7

0.0%

–

51

25

12

8

0.2%

-3.5%

-7.0%

8.5%

-18.6%

8.5%

–

103

51

25

16

12

8

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

–

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

3

2

6

5

6

1

3

1

2

5

2

6

0

1

3

1

3

–

1

2

1

2

–

0

1

0

1

–

0

–

0

0.0%

Max.⁽¹⁾

62.5 kbps

125 kbps

115.2 kbps

230.4 kbps

125 kbps

250 kbps

Note:

1. UBRRn = 0, Error = 0.0%

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Table 19-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 3.6864 MHz

U2Xn = 0

f_osc= 4.0000 MHz

U2Xn = 0

f_osc= 7.3728 MHz

U2Xn = 0

UBRRn Error

Baud

Rate

(bps)

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

95

47

23

15

11

7

0.0%

-7.8%

–

191

95

47

31

23

15

11

7

0.0%

-7.8%

–

103

51

25

16

12

8

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

207

103

51

34

25

16

12

8

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

191

95

47

31

23

15

11

7

0.0%

-7.8%

–

383

191

95

63

47

31

23

15

11

7

0.0%

-7.8%

5

6

3

2

5

2

6

5

1

3

1

3

0

1

0

1

3

0

1

0

1

3

0.5M

–

0

–

0

1

1M

–

0

Max. ⁽¹⁾

230.4 kbps

460.8 kbps

250 kbps

0.5 Mbps

460.8 kbps

921.6 kbps

1.

UBRRn = 0, Error = 0.0%

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Table 19-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 8.0000 MHz f_osc= 11.0592 MHz f_osc= 14.7456 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

207

103

51

34

25

16

12

8

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

0.0%

–

416

207

103

68

51

34

25

16

12

8

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

287

143

71

47

35

23

17

11

8

0.0%

-7.8%

–

575

287

143

95

71

47

35

23

17

11

5

0.0%

-7.8%

–

383

191

95

63

47

31

23

15

11

7

0.0%

-7.8%

767

383

191

127

95

63

47

31

23

15

7

0.0%

5.3%

-7.8%

6

3

5

1

3

2

3

1

3

2

5

3

6

0.5M

0

1

–

2

1

3

1M

–

0

–

0

1

Max. ⁽¹⁾

0.5 Mbps

UBRRn = 0, Error = 0.0%

1 Mbps

691.2 kbps

1.3824 Mbps

921.6 kbps

1.8432 Mbps

1.

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Table 19-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

f_osc= 16.0000 MHz f_osc= 18.4320 MHz f_osc= 20.0000 MHz

Baud

Rate

(bps)

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

U2Xn = 0

UBRRn Error

U2Xn = 1

UBRRn Error

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

416

207

103

68

51

34

25

16

12

8

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

8.5%

0.0%

832

416

207

138

103

68

51

34

25

16

8

0.0%

-0.1%

0.2%

-0.1%

0.2%

0.6%

0.2%

-0.8%

0.2%

2.1%

-3.5%

0.0%

479

239

119

79

59

39

29

19

14

9

0.0%

-7.8%

–

959

479

239

159

119

79

59

39

29

19

9

0.0%

2.4%

-7.8%

–

520

259

129

86

64

42

32

21

15

10

4

0.0%

0.2%

-0.2%

0.2%

0.9%

-1.4%

1.7%

-1.4%

8.5%

0.0%

–

1041

520

259

173

129

86

0.0%

0.2%

-0.2%

0.2%

-0.2%

0.2%

0.9%

-1.4%

0.0%

–

64

42

32

21

3

4

10

3

7

4

8

4

9

0.5M

1

3

–

4

–

4

1M

0

1

–

Max. ⁽¹⁾

1 Mbps

UBRRn = 0, Error = 0.0%

2 Mbps

1.152 Mbps

2.304 Mbps

1.25 Mbps

2.5 Mbps

1.

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20. USART in SPI Mode

20.1 Features

• Full Duplex, Three-wire Synchronous Data Transfer

• Master Operation

• Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)

• LSB First or MSB First Data Transfer (Configurable Data Order)

• Queued Operation (Double Buffered)

• High Resolution Baud Rate Generator

• High Speed Operation (fXCKmax = fCK/2)

• Flexible Interrupt Generation

20.2 Overview

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be

set to a master SPI compliant mode of operation. Setting both UMSELn1:0 bits to one enables

the USART in Master SPI Mode (MSPIM) logic. In this mode of operation the SPI master control

logic takes direct control over the USART resources. These resources include the transmitter

and receiver shift register and buffers, and the baud rate generator. The parity generator and

checker, the data and clock recovery logic, and the RX and TX control logic is disabled. The

USART RX and TX control logic is replaced by a common SPI transfer control logic. However,

the pin control logic and interrupt generation logic is identical in both modes of operation.

The I/O register locations are the same in both modes. However, some of the functionality of the

control registers changes when using MSPIM.

20.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For

USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-

ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one

(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should

be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).

The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-

ter mode. The baud rate or UBRRn setting can therefore be calculated using the same

equations, see Table 20-1:

Table 20-1. Equations for Calculating Baud Rate Register Setting

Equation for Calculating Baud

Rate⁽¹⁾

Equation for Calculating UBRRn

Value

Operating Mode

Synchronous Master

mode

f

OSC

f

OSC

BAUD = --------------------------------------

UBRRn = -------------------- – 1

2(UBRRn + 1)

2BAUD

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Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD

f_OSC

Baud rate (in bits per second, bps)

System Oscillator clock frequency

UBRRn

Contents of the UBRRnH and UBRRnL Registers, (0-4095)

20.4 SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which

are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are

shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn

signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-

ality is summarized in Table 20-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Table 20-2. UCPOLn and UCPHAn Functionality-

UCPOLn

UCPHAn

SPI Mode

Leading Edge

Sample (Rising)

Setup (Rising)

Sample (Falling)

Setup (Falling)

Trailing Edge

Setup (Falling)

Sample (Falling)

Setup (Rising)

Sample (Rising)

0

1

0

1

0

1

0

1

2

3

Figure 20-1. UCPHAn and UCPOLn data transfer timing diagrams.

UCPOL=0

UCPOL=1

XCK

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

Data setup (TXD)

Data sample (RXD)

20.5 Frame Formats

A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM

mode has two valid frame formats:

• 8-bit data with MSB first

• 8-bit data with LSB first

A frame starts with the least or most significant data bit. Then the next data bits, up to a total of

eight, are succeeding, ending with the most or least significant bit accordingly. When a complete

frame is transmitted, a new frame can directly follow it, or the communication line can be set to

an idle (high) state.

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2545M–AVR–09/07

The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The

Receiver and Transmitter use the same setting. Note that changing the setting of any of these

bits will corrupt all ongoing communication for both the Receiver and Transmitter.

16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-

plete interrupt will then signal that the 16-bit value has been shifted out.

20.5.1

USART MSPIM Initialization

The USART in MSPIM mode has to be initialized before any communication can take place. The

initialization process normally consists of setting the baud rate, setting master mode of operation

(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the

Receiver. Only the transmitter can operate independently. For interrupt driven USART opera-

tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when

doing the initialization.

Note:

To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be

zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the

UBRRn must then be written to the desired value after the transmitter is enabled, but before the

first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces-

sary if the initialization is done immediately after a reset since UBRRn is reset to zero.

Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that

there is no ongoing transmissions during the period the registers are changed. The TXCn Flag

can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can

be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag

must be cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initialization code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume polling (no interrupts enabled). The

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baud rate is given as a function parameter. For the assembly code, the baud rate parameter is

assumed to be stored in the r17:r16 registers.

Assembly Code Example⁽¹⁾

USART_Init:

clr r18

out UBRRnH,r18

out UBRRnL,r18

; Setting the XCKn port pin as output, enables master mode.

sbi XCKn_DDR, XCKn

; Set MSPI mode of operation and SPI data mode 0.

ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)

out UCSRnC,r18

; Enable receiver and transmitter.

ldi r18, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r18

; Set baud rate.

; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!

out UBRRnH, r17

out UBRRnL, r18

ret

C Code Example⁽¹⁾

void USART_Init( unsigned int baud )

{

UBRRn = 0;

/* Setting the XCKn port pin as output, enables master mode. */

XCKn_DDR |= (1<<XCKn);

/* Set MSPI mode of operation and SPI data mode 0. */

UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);

/* Enable receiver and transmitter. */

UCSRnB = (1<<RXENn)|(1<<TXENn);

/* Set baud rate. */

/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled

*/

UBRRn = baud;

}

Note:

1. See ”About Code Examples” on page 9.

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2545M–AVR–09/07

20.6 Data Transfer

Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in

the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation

of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling

the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.

When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given

the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer

clock.

After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-

ing to the UDRn I/O location. This is the case for both sending and receiving data since the

transmitter controls the transfer clock. The data written to UDRn is moved from the transmit

buffer to the shift register when the shift register is ready to send a new frame.

Note:

To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must

be read once for each byte transmitted. The input buffer operation is identical to normal USART

mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the

buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the

UDRn is not read before all transfers are completed, then byte 3 to be received will be lost, and not

byte 1.

The following code examples show a simple USART in MSPIM mode transfer function based on

polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The

USART has to be initialized before the function can be used. For the assembly code, the data to

be sent is assumed to be stored in Register R16 and the data received will be available in the

same register (R16) after the function returns.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. The function then waits for data to be present

in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the

value.

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Assembly Code Example⁽¹⁾

USART_MSPIM_Transfer:

; Wait for empty transmit buffer

sbis UCSRnA, UDREn

rjmp USART_MSPIM_Transfer

; Put data (r16) into buffer, sends the data

out UDRn,r16

; Wait for data to be received

USART_MSPIM_Wait_RXCn:

sbis UCSRnA, RXCn

rjmp USART_MSPIM_Wait_RXCn

; Get and return received data from buffer

in r16, UDRn

ret

C Code Example⁽¹⁾

unsigned char USART_Receive( void )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) );

/* Put data into buffer, sends the data */

UDRn = data;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) );

/* Get and return received data from buffer */

return UDRn;

}

Note:

1. See ”About Code Examples” on page 9.

20.6.1

20.6.2

Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode

are identical in function to the normal USART operation. However, the receiver error status flags

(FE, DOR, and PE) are not in use and is always read as zero.

Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to

the normal USART operation.

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20.7 AVR USART MSPIM vs. AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:

• Master mode timing diagram.

• The UCPOLn bit functionality is identical to the SPI CPOL bit.

• The UCPHAn bit functionality is identical to the SPI CPHA bit.

• The UDORDn bit functionality is identical to the SPI DORD bit.

However, since the USART in MSPIM mode reuses the USART resources, the use of the

USART in MSPIM mode is somewhat different compared to the SPI. In addition to differences of

the control register bits, and that only master operation is supported by the USART in MSPIM

mode, the following features differ between the two modules:

• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no

buffer.

• The USART in MSPIM mode receiver includes an additional buffer level.

• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.

• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved

by setting UBRRn accordingly.

• Interrupt timing is not compatible.

• Pin control differs due to the master only operation of the USART in MSPIM mode.

A comparison of the USART in MSPIM mode and the SPI pins is shown in Table 20-3 on page

206.

Table 20-3. Comparison of USART in MSPIM mode and SPI pins.

USART_MSPIM

TxDn

SPI

Comment

MOSI

MISO

SCK

Master Out only

Master In only

RxDn

XCKn

(Functionally identical)

Not supported by USART in

MSPIM

(N/A)

SS

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20.8 Register Description

The following section describes the registers used for SPI operation using the USART.

20.8.1

20.8.2

UDRn – USART MSPIM I/O Data Register

The function and bit description of the USART data register (UDRn) in MSPI mode is identical to

normal USART operation. See “UDRn – USART I/O Data Register n” on page 191.

UCSRnA – USART MSPIM Control and Status Register n A

Bit

7

6

5

4

3

-

2

-

1

-

0

-

RXCn

TXCn

UDREn

-

UCSRnA

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

R

0

R

1

R

1

R

0

• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIEn bit).

• Bit 6 - TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCIEn bit).

• Bit 5 - UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to

indicate that the Transmitter is ready.

• Bit 4:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnA is written.

20.8.3

UCSRnB – USART MSPIM Control and Status Register n B

Bit

7

6

5

4

3

TXENn

R/W

0

2

-

1

-

0

-

RXCIEn

TXCIEn

UDRIE

RXENn

R/W

0

UCSRnB

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R

1

R

1

R

0

• Bit 7 - RXCIEn: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

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2545M–AVR–09/07

• Bit 6 - TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set.

• Bit 4 - RXENn: Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override

normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the

receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)

has no meaning since it is the transmitter that controls the transfer clock and since only master

mode is supported.

• Bit 3 - TXENn: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnB is written.

20.8.4

UCSRnC – USART MSPIM Control and Status Register n C

Bit

7

6

5

4

3

-

2

UDORDn

R/W

1

UCPHAn

R/W

0

UCPOLn

R/W

UMSELn1

UMSELn0

-

UCSRnC

Read/Write

Initial Value

R/W

0

R/W

0

R

0

R

0

R

0

1

0

• Bit 7:6 - UMSELn1:0: USART Mode Select

These bits select the mode of operation of the USART as shown in Table 20-4. See “UCSRnC –

USART Control and Status Register n C” on page 193 for full description of the normal USART

operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,

UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.

Table 20-4. UMSELn Bits Settings

UMSELn1

UMSELn0

Mode

0

1

0

1

0

1

Asynchronous USART

Synchronous USART

(Reserved)

Master SPI (MSPIM)

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• Bit 5:3 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnC is written.

• Bit 2 - UDORDn: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the

data word is transmitted first. Refer to the Frame Formats section page 4 for details.

• Bit 1 - UCPHAn: Clock Phase

The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)

edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.

• Bit 0 - UCPOLn: Clock Polarity

The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and

UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and

Timing section page 4 for details.

20.8.5

USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH

The function and bit description of the baud rate registers in MSPI mode is identical to normal

USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 195.

209

2545M–AVR–09/07

21. 2-wire Serial Interface

21.1 Features

• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space Allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up When AVR is in Sleep Mode

• Compatible with Philips I²C protocol

21.2 2-wire Serial Interface Bus Definition

The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The

TWI protocol allows the systems designer to interconnect up to 128 different devices using only

two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-

ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All

devices connected to the bus have individual addresses, and mechanisms for resolving bus

contention are inherent in the TWI protocol.

Figure 21-1. TWI Bus Interconnection

V_CC

Device 1

Device 3

R1

R2

Device 2

Device n

........

SDA

SCL

21.2.1

TWI Terminology

The following definitions are frequently encountered in this section.

Table 21-1. TWI Terminology

Term

Description

The device that initiates and terminates a transmission. The Master also generates the

SCL clock.

Master

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Table 21-1. TWI Terminology

Term

Description

Slave

The device addressed by a Master.

The device placing data on the bus.

The device reading data from the bus.

Transmitter

Receiver

The PRTWI bit in “Minimizing Power Consumption” on page 42 must be written to zero to enable

the 2-wire Serial Interface.

21.2.2

Electrical Interconnection

As depicted in Figure 21-1, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line

high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any

bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in “2-wire Serial Interface Characteristics” on page 309. Two

different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,

and one valid for bus speeds up to 400 kHz.

21.3 Data Transfer and Frame Format

21.3.1

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating start and stop conditions.

Figure 21-2. Data Validity

SDA

SCL

Data Stable

Data Change

21.3.2

START and STOP Conditions

The Master initiates and terminates a data transmission. The transmission is initiated when the

Master issues a START condition on the bus, and it is terminated when the Master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

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other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the Master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behavior, and therefore START is used to describe both

START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As

depicted below, START and STOP conditions are signalled by changing the level of the SDA

line when the SCL line is high.

Figure 21-3. START, REPEATED START and STOP conditions

SDA

SCL

START

STOP START

REPEATED START

STOP

21.3.3

Address Packet Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one

READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera-

tion is to be performed, otherwise a write operation should be performed. When a Slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a Master wishes to transmit the same message to several

slaves in the system. When the general call address followed by a Write bit is transmitted on the

bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by all the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

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Figure 21-4. Address Packet Format

Addr MSB

Addr LSB

R/W

ACK

SDA

SCL

1

2

7

8

9

START

21.3.4

Data Packet Format

All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and

an acknowledge bit. During a data transfer, the Master generates the clock and the START and

STOP conditions, while the Receiver is responsible for acknowledging the reception. An

Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL

cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has

received the last byte, or for some reason cannot receive any more bytes, it should inform the

Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

Figure 21-5. Data Packet Format

Data MSB

Data LSB

ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

1

2

7

8

9

STOP, REPEATED

START or Next

Data Byte

SLA+R/W

Data Byte

21.3.5

Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets

and a STOP condition. An empty message, consisting of a START followed by a STOP condi-

tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement

handshaking between the Master and the Slave. The Slave can extend the SCL low period by

pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the

Slave, or the Slave needs extra time for processing between the data transmissions. The Slave

extending the SCL low period will not affect the SCL high period, which is determined by the

Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the

SCL duty cycle.

Figure 21-6 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP condition, depending on the software protocol imple-

mented by the application software.

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Figure 21-6. Typical Data Transmission

Addr MSB

Addr LSB R/W

ACK

Data MSB

Data LSB ACK

SDA

SCL

1

2

7

8

9

1

2

7

8

9

START

SLA+R/W

Data Byte

STOP

21.4 Multi-master Bus Systems, Arbitration and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken

in order to ensure that transmissions will proceed as normal, even if two or more masters initiate

a transmission at the same time. Two problems arise in multi-master systems:

• An algorithm must be implemented allowing only one of the masters to complete the

transmission. All other masters should cease transmission when they discover that they have

lost the selection process. This selection process is called arbitration. When a contending

master discovers that it has lost the arbitration process, it should immediately switch to Slave

mode to check whether it is being addressed by the winning master. The fact that multiple

masters have started transmission at the same time should not be detectable to the slaves, i.e.

the data being transferred on the bus must not be corrupted.

• Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a

lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from

all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one

from the Master with the shortest high period. The low period of the combined clock is equal to

the low period of the Master with the longest low period. Note that all masters listen to the SCL

line, effectively starting to count their SCL high and low time-out periods when the combined

SCL line goes high or low, respectively.

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Figure 21-7. SCL Synchronization Between Multiple Masters

TA _low

TA _high

SCL from

Master A

SCL from

Master B

SCL Bus

Line

TB_low

TB_high

Masters Start

Counting Low Period

Counting High Period

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting

data. If the value read from the SDA line does not match the value the Master had output, it has

lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value

while another Master outputs a low value. The losing Master should immediately go to Slave

mode, checking if it is being addressed by the winning Master. The SDA line should be left high,

but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one Master remains, and this may take many

bits. If several masters are trying to address the same Slave, arbitration will continue into the

data packet.

Figure 21-8. Arbitration Between Two Masters

START

Master A Loses

Arbitration, SDA_ASDA

SDA from

Master A

SDA from

Master B

SDA Line

Synchronized

SCL Line

Note that arbitration is not allowed between:

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• A REPEATED START condition and a data bit.

• A STOP condition and a data bit.

• A REPEATED START and a STOP condition.

It is the user software’s responsibility to ensure that these illegal arbitration conditions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

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21.5 Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 21-9. All registers

drawn in a thick line are accessible through the AVR data bus.

Figure 21-9. Overview of the TWI Module

SCL

SDA

Spike

Filter

Spike

Filter

Slew-rate

Control

Slew-rate

Control

Bus Interface Unit

Bit Rate Generator

START / STOP

Spike Suppression

Prescaler

Control

Address/Data Shift

Register (TWDR)

Bit Rate Register

(TWBR)

Arbitration detection

Ack

Address Match Unit

Control Unit

Address Register

(TWAR)

Status Register

(TWSR)

Control Register

(TWCR)

State Machine and

Status control

Address Comparator

21.5.1

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

21.5.2

Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the

CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note

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that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

CPU Clock frequency

SCL frequency = ----------------------------------------------------------------------------------------

16 + 2(TWBR) ⋅ (PrescalerValue)

• TWBR = Value of the TWI Bit Rate Register.

• PrescalerValue = Value of the prescaler, see Table 21-7 on page 239.

Note:

Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus

line load. See Table 28-5 on page 309 for value of pull-up resistor.

21.5.3

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up

if addressed by a Master.

If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-

ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

21.5.4

Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the

TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0)

occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-

tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the

only enabled interrupt when entering Power-down.

21.5.5

Control Unit

The Control unit monitors the TWI bus and generates responses corresponding to settings in the

TWI Control Register (TWCR). When an event requiring the attention of the application occurs

on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta-

tus Register (TWSR) is updated with a status code identifying the event. The TWSR only

contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,

the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application

software to complete its tasks before allowing the TWI transmission to continue.

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The TWINT Flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START condition.

• After the TWI has transmitted SLA+R/W.

• After the TWI has transmitted an address byte.

• After the TWI has lost arbitration.

• After the TWI has been addressed by own slave address or general call.

• After the TWI has received a data byte.

• After a STOP or REPEATED START has been received while still addressed as a Slave.

• When a bus error has occurred due to an illegal START or STOP condition.

21.6 Using the TWI

The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,

the application software is free to carry on other operations during a TWI byte transfer. Note that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in

order to detect actions on the TWI bus.

When the TWINT Flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 21-10 is a simple example of how the application can interface to the TWI hardware. In

this example, a Master wishes to transmit a single data byte to a Slave. This description is quite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired behavior is also presented.

Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission

3. Check TWSR to see if START was

sent. Application loads SLA+W into

TWDR, and loads appropriate control

signals into TWCR, makin sure that

TWINT is written to one,

5. Check TWSR to see if SLA+W was

sent and ACK received.

Application loads data into TWDR, and

loads appropriate control signals into

TWCR, making sure that TWINT is

written to one

1. Application

writes to TWCR to

initiate

transmission of

START

7. Check TWSR to see if data was sent

and ACK received.

Application loads appropriate control

signals to send STOP into TWCR,

making sure that TWINT is written to one

and TWSTA is written to zero.

TWI bus START

SLA+W

A

Data

A

STOP

Indicates

TWINT set

4. TWINT set.

Status code indicates

SLA+W sent, ACK

received

2. TWINT set.

Status code indicates

START condition sent

6. TWINT set.

Status code indicates

data sent, ACK received

1. The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instructing the TWI hardware to transmit a START

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condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the START condition.

2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the START condition has success-

fully been sent.

3. The application software should now examine the value of TWSR, to make sure that the

START condition was successfully transmitted. If TWSR indicates otherwise, the applica-

tion software might take some special action, like calling an error routine. Assuming that

the status code is as expected, the application must load SLA+W into TWDR. Remember

that TWDR is used both for address and data. After TWDR has been loaded with the

desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware

to transmit the SLA+W present in TWDR. Which value to write is described later on.

However, it is important that the TWINT bit is set in the value written. Writing a one to

TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in

TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate

transmission of the address packet.

4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the address packet has successfully

been sent. The status code will also reflect whether a Slave acknowledged the packet or

not.

5. The application software should now examine the value of TWSR, to make sure that the

address packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some special

action, like calling an error routine. Assuming that the status code is as expected, the

application must load a data packet into TWDR. Subsequently, a specific value must be

written to TWCR, instructing the TWI hardware to transmit the data packet present in

TWDR. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the data packet.

6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR

is updated with a status code indicating that the data packet has successfully been sent.

The status code will also reflect whether a Slave acknowledged the packet or not.

7. The application software should now examine the value of TWSR, to make sure that the

data packet was successfully transmitted, and that the value of the ACK bit was as

expected. If TWSR indicates otherwise, the application software might take some special

action, like calling an error routine. Assuming that the status code is as expected, the

application must write a specific value to TWCR, instructing the TWI hardware to transmit

a STOP condition. Which value to write is described later on. However, it is important that

the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI

will not start any operation as long as the TWINT bit in TWCR is set. Immediately after

the application has cleared TWINT, the TWI will initiate transmission of the STOP condi-

tion. Note that TWINT is NOT set after a STOP condition has been sent.

Even though this example is simple, it shows the principles involved in all TWI transmissions.

These can be summarized as follows:

• When the TWI has finished an operation and expects application response, the TWINT Flag is

set. The SCL line is pulled low until TWINT is cleared.

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• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant for

the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted

in the next bus cycle.

• After all TWI Register updates and other pending application software tasks have been

completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one

to TWINT clears the flag. The TWI will then commence executing whatever operation was

specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note that the code

below assumes that several definitions have been made, for example by using include-files.

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Assembly Code Example

C Example

TWCR = (1<<TWINT)|(1<<TWSTA)|

Comments

ldi r16,

(1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)

1

2

Send START condition

(1<<TWEN)

out TWCR, r16

wait1:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the START

condition has been transmitted

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait1

in

r16,TWSR

if ((TWSR & 0xF8) != START)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from START go to

ERROR

andi r16, 0xF8

cpi r16, START

brne ERROR

ERROR();

3

4

5

ldi r16, SLA_W

out TWDR, r16

TWDR = SLA_W;

Load SLA_W into TWDR

Register. Clear TWINT bit in

TWCR to start transmission of

address

TWCR = (1<<TWINT) |

(1<<TWEN);

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait2:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the SLA+W has

been transmitted, and

in

r16,TWCR

;

sbrs r16,TWINT

rjmp wait2

ACK/NACK has been received.

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_SLA_ACK)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from

andi r16, 0xF8

cpi r16, MT_SLA_ACK

brne ERROR

ERROR();

MT_SLA_ACK go to ERROR

ldi r16, DATA

out TWDR, r16

TWDR = DATA;

TWCR = (1<<TWINT) |

(1<<TWEN);

Load DATA into TWDR Register.

Clear TWINT bit in TWCR to

start transmission of data

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

wait3:

while (!(TWCR & (1<<TWINT)))

Wait for TWINT Flag set. This

indicates that the DATA has been

transmitted, and ACK/NACK has

been received.

in

r16,TWCR

;

6

7

sbrs r16,TWINT

rjmp wait3

in

r16,TWSR

if ((TWSR & 0xF8) !=

MT_DATA_ACK)

Check value of TWI Status

Register. Mask prescaler bits. If

status different from

andi r16, 0xF8

cpi r16, MT_DATA_ACK

brne ERROR

ERROR();

MT_DATA_ACK go to ERROR

ldi r16,

(1<<TWINT)|(1<<TWEN)|

TWCR = (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO);

Transmit STOP condition

(1<<TWSTO)

out TWCR, r16

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21.7 Transmission Modes

The TWI can operate in one of four major modes. These are named Master Transmitter (MT),

Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these

modes can be used in the same application. As an example, the TWI can use MT mode to write

data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters

are present in the system, some of these might transmit data to the TWI, and then SR mode

would be used. It is the application software that decides which modes are legal.

The following sections describe each of these modes. Possible status codes are described

along with figures detailing data transmission in each of the modes. These figures contain the

following abbreviations:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In Figure 21-12 to Figure 21-18, circles are used to indicate that the TWINT Flag is set. The

numbers in the circles show the status code held in TWSR, with the prescaler bits masked to

zero. At these points, actions must be taken by the application to continue or complete the TWI

transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.

When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate soft-

ware action. For each status code, the required software action and details of the following serial

transfer are given in Table 21-2 to Table 21-5. Note that the prescaler bits are masked to zero in

these tables.

21.7.1

Master Transmitter Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver

(see Figure 21-11). In order to enter a Master mode, a START condition must be transmitted.

The format of the following address packet determines whether Master Transmitter or Master

Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is trans-

mitted, MR mode is entered. All the status codes mentioned in this section assume that the

prescaler bits are zero or are masked to zero.

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Figure 21-11. Data Transfer in Master Transmitter Mode

V_CC

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans-

mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will

then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes

free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the

status code in TWSR will be 0x08 (see Table 21-2). In order to enter MT mode, SLA+W must be

transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be

cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow-

ing value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes

is detailed in Table 21-2.

When SLA+W has been successfully transmitted, a data packet should be transmitted. This is

done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,

the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-

ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the

transfer. This is accomplished by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-

ing a STOP condition or a repeated START condition. A STOP condition is generated by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

224

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables

the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-

out losing control of the bus.

Table 21-2. Status codes for Master Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To/from TWDR To TWCR

STO TWIN

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

STA

0

TWE

A

Next Action Taken by TWI Hardware

T

0x08

0x10

A START condition has been

transmitted

Load SLA+W

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

A repeated START condition

has been transmitted

Load SLA+W or

Load SLA+R

0

1

X

SLA+W will be transmitted;

ACK or NOT ACK will be received

SLA+R will be transmitted;

Logic will switch to Master Receiver mode

0x18

0x20

0x28

0x30

0x38

SLA+W has been transmitted;

ACK has been received

Load data byte or

0

1

X

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

SLA+W has been transmitted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Data byte has been transmit-

ted;

ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

Load data byte or

1

0

1

0

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Data byte has been transmit-

ted;

NOT ACK has been received

Data byte will be transmitted and ACK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

No TWDR action or

1

0

1

X

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

Arbitration lost in SLA+W or

data bytes

No TWDR action or

No TWDR action

0

1

0

1

X

2-wire Serial Bus will be released and not addressed

Slave mode entered

A START condition will be transmitted when the bus

becomes free

225

2545M–AVR–09/07

Figure 21-12. Formats and States in the Master Transmitter Mode

MT

Successfull

S

SLA

W

A

DATA

A

P

transmission

to a slave

receiver

$08

$18

$28

Next transfer

started with a

repeated start

condition

R_S

SLA

W

R

$10

Not acknowledge

received after the

slave address

A

P

$20

MR

Not acknowledge

received after a data

byte

A

P

$30

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

21.7.2

Master Receiver Mode

In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter

(Slave see Figure 21-13). In order to enter a Master mode, a START condition must be transmit-

ted. The format of the following address packet determines whether Master Transmitter or

Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R

is transmitted, MR mode is entered. All the status codes mentioned in this section assume that

the prescaler bits are zero or are masked to zero.

226

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 21-13. Data Transfer in Master Receiver Mode

V_CC

Device 1

MASTER

RECEIVER

Device 2

SLAVE

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

A START condition is sent by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to

one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI

will then test the 2-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-

ware, and the status code in TWSR will be 0x08 (See Table 21-2). In order to enter MR mode,

SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

X

1

0

X

When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes

is detailed in Table 21-3. Received data can be read from the TWDR Register when the TWINT

Flag is set high by hardware. This scheme is repeated until the last byte has been received.

After the last byte has been received, the MR should inform the ST by sending a NACK after the

last received data byte. The transfer is ended by generating a STOP condition or a repeated

START condition. A STOP condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

0

1

X

1

0

X

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

1

X

1

0

X

1

0

X

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables

227

2545M–AVR–09/07

the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with-

out losing control over the bus.

Table 21-3. Status codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

To/from TWDR

STA

STO

TWIN

T

TWE

A

Next Action Taken by TWI Hardware

0x08

0x10

A START condition has been

transmitted

Load SLA+R

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

A repeated START condition

has been transmitted

Load SLA+R or

Load SLA+W

0

1

X

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

Logic will switch to Master Transmitter mode

0x38

0x40

0x48

Arbitration lost in SLA+R or

NOT ACK bit

No TWDR action or

No TWDR action

0

1

0

1

X

2-wire Serial Bus will be released and not addressed

Slave mode will be entered

A START condition will be transmitted when the bus

becomes free

SLA+R has been transmitted;

ACK has been received

No TWDR action or

No TWDR action

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

SLA+R has been transmitted;

NOT ACK has been received

No TWDR action or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

No TWDR action

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

0x50

0x58

Data byte has been received;

ACK has been returned

Read data byte or

Read data byte

0

1

0

1

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

Data byte has been received;

NOT ACK has been returned

Read data byte or

1

0

1

X

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

Read data byte

1

X

STOP condition followed by a START condition will be

transmitted and TWSTO Flag will be reset

228

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 21-14. Formats and States in the Master Receiver Mode

MR

Successfull

reception

S

SLA

R

A

DATA

A

DATA

A

P

from a slave

receiver

$08

$40

$50

$58

Next transfer

started with a

repeated start

condition

R_S

SLA

R

$10

Not acknowledge

received after the

slave address

W

A

P

$48

MT

Arbitration lost in slave

address or data byte

Other master

continues

Other master

continues

A or A

A

$38

A

$38

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

$68 $78 $B0

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

21.7.3

Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter

(see Figure 21-15). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 21-15. Data transfer in Slave Receiver mode

V_CC

Device 1

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device 3

Device n

R1

R2

........

SDA

SCL

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

229

2545M–AVR–09/07

The upper 7 bits are the address to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgement of the device’s own slave address or the general call address. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 21-4.

The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master

mode (see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the Slave is not able to

receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave

address. However, the 2-wire Serial Bus is still monitored and address recognition may resume

at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate

the TWI from the 2-wire Serial Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and

the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by

writing it to one). Further data reception will be carried out as normal, with the AVR clocks run-

ning as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be

held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these Sleep modes.

230

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Table 21-4. Status Codes for Slave Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

STO TWIN

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

To/from TWDR

STA

X

TWE

A

Next Action Taken by TWI Hardware

T

0x60

0x68

0x70

0x78

Own SLA+W has been received;

ACK has been returned

No TWDR action or

0

1

0

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

Arbitration lost in SLA+R/W as

Master; own SLA+W has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

General call address has been

received; ACK has been returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

X

0

1

0

Data byte will be received and ACK will be returned

Arbitration lost in SLA+R/W as

Master; General call address has

been received; ACK has been

returned

No TWDR action or

Data byte will be received and NOT ACK will be

returned

No TWDR action

Read data byte or

X

0

1

0

Data byte will be received and ACK will be returned

0x80

0x88

Previously addressed with own

SLA+W; data has been received;

ACK has been returned

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with own

SLA+W; data has been received;

NOT ACK has been returned

Read data byte or

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Read data byte or

0

1

0

1

0

Read data byte

1

0

1

0

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0x90

0x98

Previously addressed with

general call; data has been re-

ceived; ACK has been returned

Read data byte or

X

Data byte will be received and NOT ACK will be

returned

Read data byte

X

0

1

0

Data byte will be received and ACK will be returned

Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Read data byte or

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

Read data byte or

0

1

0

1

0

Read data byte

No action

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xA0

A STOP condition or repeated

START condition has been

received while still addressed as

Slave

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

231

2545M–AVR–09/07

Figure 21-16. Formats and States in the Slave Receiver Mode

Reception of the own

S

SLA

W

A

DATA

A

DATA

A

P or S

slave address and one or

more data bytes. All are

acknowledged

$60

$80

A

$A0

Last data byte received

is not acknowledged

P or S

$88

Arbitration lost as master

and addressed as slave

A

$68

A

Reception of the general call

address and one or more data

bytes

General Call

DATA

A

DATA

A

P or S

$70

$90

A

$A0

Last data byte received is

not acknowledged

P or S

$98

Arbitration lost as master and

addressed as slave by general call

A

$78

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

21.7.4

Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver

(see Figure 21-17). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 21-17. Data Transfer in Slave Transmitter Mode

V_CC

Device 1

SLAVE

TRANSMITTER

Device 2

MASTER

RECEIVER

Device 3

Device n

R1

R2

........

SDA

SCL

232

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:

TWAR

TWA6

TWA5

TWA4

TWA3

TWA2

TWA1

TWA0

TWGCE

value

Device’s Own Slave Address

The upper seven bits are the address to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),

otherwise it will ignore the general call address.

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

value

0

1

0

1

0

X

TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable

the acknowledgement of the device’s own slave address or the general call address. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own

slave address (or the general call address if enabled) followed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 21-5.

The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the

Master mode (see state 0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver

transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave

mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives

all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by

transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-

ing NACK from the Master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial

Bus.

In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and

the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared

(by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these sleep modes.

233

2545M–AVR–09/07

Table 21-5. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler

Bits

Application Software Response

To TWCR

STO TWIN

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

To/from TWDR

STA

TWE

A

Next Action Taken by TWI Hardware

T

are 0

0xA8

0xB0

0xB8

0xC0

Own SLA+R has been received;

ACK has been returned

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

1

Arbitration lost in SLA+R/W as

Master; own SLA+R has been

received; ACK has been returned

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Load data byte

X

0

1

0

1

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

No TWDR action

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

0xC8

Last data byte in TWDR has been

transmitted (TWEA = “0”); ACK

has been received

No TWDR action or

0

1

0

1

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitted when the bus

becomes free

No TWDR action or

No TWDR action

1

0

1

0

1

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitted when the bus

becomes free

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Figure 21-18. Formats and States in the Slave Transmitter Mode

Reception of the own

slave address and one or

more data bytes

S

SLA

R

A

DATA

A

DATA

A

P or S

$A8

A

$B8

$C0

Arbitration lost as master

and addressed as slave

$B0

Last data byte transmitted.

Switched to not addressed

slave (TWEA = '0')

A

All 1's

P or S

$C8

Any number of data bytes

and their associated acknowledge bits

From master to slave

From slave to master

DATA

A

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

n

21.7.5

Miscellaneous States

There are two status codes that do not correspond to a defined TWI state, see Table 21-6.

Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not

set. This occurs between other states, and when the TWI is not involved in a serial transfer.

Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in

TWCR are affected). The SDA and SCL lines are released, and no STOP condition is

transmitted.

Table 21-6. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Application Software Response

To TWCR

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

To/from TWDR

STA

STO

TWIN

T

TWE

A

Next Action Taken by TWI Hardware

Wait or proceed current transfer

0xF8

0x00

No relevant state information

available; TWINT = “0”

No TWDR action

No TWCR action

Bus error due to an illegal

START or STOP condition

0

1

X

Only the internal hardware is affected, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

21.7.6

Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated.

2. The EEPROM must be instructed what location should be read.

3. The reading must be performed.

4. The transfer must be finished.

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Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct

the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must

be changed. The Master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multi master sys-

tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the

Master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the Master keeps ownership of the bus. The following

figure shows the flow in this transfer.

Figure 21-19. Combining Several TWI Modes to Access a Serial EEPROM

Master Transmitter

Master Receiver

S

SLA+W

A

ADDRESS

A

Rs

SLA+R

A

DATA

A

P

S = START

Transmitted from master to slave

Rs = REPEATED START

Transmitted from slave to master

P = STOP

21.8 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a Slave Receiver.

Figure 21-20. An Arbitration Example

V_CC

Device 1

MASTER

TRANSMITTER

Device 3

SLAVE

RECEIVER

Device 2

MASTER

TRANSMITTER

Device n

R1

R2

........

SDA

SCL

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same Slave. In this

case, neither the Slave nor any of the masters will know about the bus contention.

• Two or more masters are accessing the same Slave with different data or direction bit. In this

case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying

to output a one on SDA while another Master outputs a zero will lose the arbitration. Losing

masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new

START condition, depending on application software action.

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• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are

being addressed by the winning Master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed Slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

This is summarized in Figure 21-21. Possible status values are given in circles.

Figure 21-21. Possible Status Codes Caused by Arbitration

START

SLA

Data

STOP

Arbitration lost in SLA

Arbitration lost in Data

Own

No

38

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Address / General Call

received

Yes

Write

68/78

B0

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Direction

Read

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

21.9 Register Description

21.9.1

TWBR – TWI Bit Rate Register

Bit

7

6

TWBR6

R/W

0

5

4

3

TWBR3

R/W

0

2

TWBR2

R/W

0

1

TWBR1

R/W

0

TWBR0

R/W

0

(0xB8)

TWBR7

R/W

0

TWBR5

R/W

0

TWBR4

R/W

0

TWBR

Read/Write

Initial Value

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator

Unit” on page 217 for calculating bit rates.

21.9.2

TWCR – TWI Control Register

Bit

7

TWINT

R/W

0

6

TWEA

R/W

0

5

TWSTA

R/W

0

4

TWSTO

R/W

0

3

2

TWEN

R/W

0

1

–

0

TWIE

R/W

0

(0xBC)

TWWC

TWCR

Read/Write

Initial Value

R

0

R

0

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a

Master access by applying a START condition to the bus, to generate a Receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

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• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application

software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the

TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT

Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-

cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag

starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-

tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this

flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to

one, the ACK pulse is generated on the TWI bus if the following conditions are met:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial

Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one

again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire

Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition

on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is

detected, and then generates a new START condition to claim the bus Master status. TWSTA

must be cleared by software when the START condition has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire

Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-

matically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.

This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed

Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is

low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to

one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the

slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero

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• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT Flag is high.

21.9.3

TWSR – TWI Status Register

Bit

7

TWS7

R

6

TWS6

R

5

TWS5

R

4

TWS4

R

3

TWS3

R

2

–

1

TWPS1

R/W

0

TWPS0

R/W

0

(0xB9)

TWSR

Read/Write

Initial Value

R

0

1

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status

codes are described later in this section. Note that the value read from TWSR contains both the

5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-

caler bits to zero when checking the Status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 21-7. TWI Bit Rate Prescaler

TWPS1

TWPS0

Prescaler Value

0

1

0

1

0

1

4

16

64

To calculate bit rates, see “Bit Rate Generator Unit” on page 217. The value of TWPS1..0 is

used in the equation.

21.9.4

TWDR – TWI Data Register

Bit

7

TWD7

R/W

1

6

TWD6

R/W

1

5

TWD5

R/W

1

4

TWD4

R/W

1

3

TWD3

R/W

1

2

TWD2

R/W

1

TWD1

R/W

1

0

TWD0

R/W

1

(0xBB)

TWDR

Read/Write

Initial Value

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.

This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-

ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains

stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously

shifted in. TWDR always contains the last byte present on the bus, except after a wake up from

a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case

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of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the

ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the 2-wire Serial Bus.

21.9.5

TWAR – TWI (Slave) Address Register

Bit

7

6

TWA5

R/W

1

5

TWA4

R/W

1

4

TWA3

R/W

1

3

TWA2

R/W

1

2

TWA1

R/W

1

TWA0

R/W

1

0

TWGCE

R/W

0

TWA6

R/W

1

TWAR

(0xBA)

Read/Write

Initial Value

The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of

TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,

and not needed in the Master modes. In multi master systems, TWAR must be set in masters

which can be addressed as Slaves by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TWI unit.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

21.9.6

TWAMR – TWI (Slave) Address Mask Register

Bit

7

6

5

4

TWAM[6:0]

R/W

3

2

1

0

–

TWAMR

(0xBD)

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R

0

• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can

mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 21-22 shown the address match logic in

detail.

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ATmega48/88/168

Figure 21-22. TWI Address Match Logic, Block Diagram

TWAR0

Address

Match

Address

Bit 0

TWAMR0

Address Bit Comparator 0

Address Bit Comparator 6..1

• Bit 0 – Res: Reserved Bit

This bit is an unused bit in the ATmega48/88/168, and will always read as zero.

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22. Analog Comparator

22.1 Overview

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger

the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate

interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on com-

parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is

shown in Figure 22-1.

The Power Reduction ADC bit, PRADC, in “Minimizing Power Consumption” on page 42 must

be disabled by writing a logical zero to be able to use the ADC input MUX.

Figure 22-1. Analog Comparator Block Diagram⁽²⁾

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

Notes: 1. See Table 22-1 on page 242.

2. Refer to Figure 1-1 on page 2 and Table 13-9 on page 85 for Analog Comparator pin

placement.

22.2 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

22-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 22-1. Analog Comparator Multiplexed Input

ACME

ADEN

MUX2..0

xxx

Analog Comparator Negative Input

0

1

x

1

0

AIN1

ADC0

xxx

000

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Table 22-1. Analog Comparator Multiplexed Input (Continued)

ACME

ADEN

MUX2..0

001

Analog Comparator Negative Input

1

0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

010

011

100

101

110

111

22.3 Register Description

22.3.1

ADCSRB – ADC Control and Status Register B

Bit

7

–

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

(0x7B)

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 242.

22.3.2

ACSR – Analog Comparator Control and Status Register

Bit

0x30 (0x50)

7

6

5

4

3

ACIE

R/W

0

2

ACIC

R/W

0

1

ACIS1

R/W

0

ACIS0

R/W

0

ACD

ACBG

ACO

ACI

R/W

0

ACSR

Read/Write

Initial Value

R/W

0

R/W

0

R

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. When the bandgap reference voltage is used as input to the Analog Comparator, it will take

a certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong

value. See “Internal Voltage Reference” on page 49

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

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• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-

gered by the Analog Comparator. The comparator output is in this case directly connected to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask

Register (TIMSK1) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 22-2.

Table 22-2. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

22.3.3

DIDR1 – Digital Input Disable Register 1

Bit

(0x7F)

7

6

5

–

4

–

3

–

2

–

1

AIN1D

R/W

0

AIN0D

R/W

0

–

R

0

DIDR1

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48/88/168, and will always read as zero.

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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ATmega48/88/168

23. Analog-to-Digital Converter

23.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 13 - 260 µs Conversion Time

• Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)

• 6 Multiplexed Single Ended Input Channels

• 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only)

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

23.2 Overview

The ATmega48/88/168 features a 10-bit successive approximation ADC. The ADC is connected

to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed

from the pins of PortC. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 23-1

on page 246.

The ADC has a separate analog supply voltage pin, AV_CC. AV_CCmust not differ more than ±

0.3V from V_CC. See the paragraph “ADC Noise Canceler” on page 251 on how to connect this

pin.

Internal reference voltages of nominally 1.1V or AV_CCare provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

The Power Reduction ADC bit, PRADC, in “Minimizing Power Consumption” on page 42 must

be disabled by writing a logical zero to enable the ADC.

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

the AREF pin minus 1 LSB. Optionally, AV_CCor an internal 1.1V reference voltage may be con-

nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve

noise immunity.

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2545M–AVR–09/07

Figure 23-1. Analog to Digital Converter Block Schematic Operation

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC DATA REGISTER

(ADCH/ADCL)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

MUX DECODER

PRESCALER

CONVERSION LOGIC

AVCC

INTERNAL 1.1V

REFERENCE

SAMPLE & HOLD

COMPARATOR

AREF

GND

10-BIT DAC

-

+

BANDGAP

REFERENCE

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

ADC MULTIPLEXER

OUTPUT

INPUT

MUX

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input

pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended

inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-

age reference and input channel selections will not go into effect until ADEN is set. The ADC

does not consume power when ADEN is cleared, so it is recommended to switch off the ADC

before entering power saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

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read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

23.3 Starting a Conversion

A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in “Minimizing

Power Consumption” on page 42 by writing a logical zero to it and writing a logical one to the

ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress

and will be cleared by hardware when the conversion is completed. If a different data channel is

selected while a conversion is in progress, the ADC will finish the current conversion before per-

forming the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to

trigger a new conversion at the next interrupt event.

Figure 23-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADIF

ADATE

SOURCE 1

.

CONVERSION

LOGIC

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

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If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

23.4 Prescaling and Conversion Timing

Figure 23-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

When the bandgap reference voltage is used as input to the ADC, it will take a certain time for

the voltage to stabilize. If not stabilized, the first value read after the first conversion may be

wrong.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic.

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In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 23-1 on page

250.

Figure 23-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

LSB of Result

ADCH

ADCL

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

Sample & Hold

Figure 23-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

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Figure 23-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

Table 23-1. ADC Conversion Time

Sample & Hold

(Cycles from Start of Conversion)

Conversion Time

(Cycles)

Condition

First conversion

13.5

1.5

2

25

13

Normal conversions, single ended

Auto Triggered conversions

13.5

23.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, minimum one ADC clock cycle after the trigger event.

c. After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

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23.5.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

23.5.2

ADC Voltage Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either AV_CC, internal 1.1V reference, or external AREF pin.

AV_CCis connected to the ADC through a passive switch. The internal 1.1V reference is gener-

ated from the internal bandgap reference (V_BG) through an internal amplifier. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and ground. V_REFcan

also be measured at the AREF pin with a high impedance voltmeter. Note that V_REFis a high

impedance source, and only a capacitive load should be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use the other

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AV_CCand 1.1V as ref-

erence selection. The first ADC conversion result after switching reference voltage source may

be inaccurate, and the user is advised to discard this result.

23.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

a. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be selected and the ADC conversion complete interrupt must be enabled.

b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If

another interrupt wakes up the CPU before the ADC conversion is complete, that

interrupt will be executed, and an ADC Conversion Complete interrupt request will be

generated when the ADC conversion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

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23.6.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 23-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedance

sources with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 23-8. Analog Input Circuitry

I_IH

ADCn

1..100 kOhm

C_S/H= 14 pF

I_IL

V_CC/2

23.6.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

a. Keep analog signal paths as short as possible. Make sure analog tracks run over the

analog ground plane, and keep them well away from high-speed switching digital

tracks.

b. The AV_CCpin on the device should be connected to the digital V_CCsupply voltage via

an LC network as shown in Figure 23-9.

c. Use the ADC noise canceler function to reduce induced noise from the CPU.

d. If any ADC [3..0] port pins are used as digital outputs, it is essential that these do not

switch while a conversion is in progress. However, using the 2-wire Interface (ADC4

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and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC

channels.

Figure 23-9. ADC Power Connections

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

ADC6

AVCC

PB5

23.6.3

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at

0.5 LSB). Ideal value: 0 LSB.

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Figure 23-10. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

• Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition

(0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0

LSB

Figure 23-11. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

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Figure 23-12. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 23-13. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a

range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.

• Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.

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23.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 23-2 on page 256 and Table 23-3 on page 257). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

23.8 Register Description

23.8.1

ADMUX – ADC Multiplexer Selection Register

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

–

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

(0x7C)

ADMUX

Read/Write

Initial Value

R

0

• Bit 7:6 – REFS1:0: Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 23-2. If these bits are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

Table 23-2. Voltage Reference Selections for ADC

REFS1

REFS0

Voltage Reference Selection

0

1

0

1

0

1

AREF, Internal V_refturned off

AV_CCwith external capacitor at AREF pin

Reserved

Internal 1.1V Voltage Reference with external capacitor at AREF pin

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on

page 259.

• Bit 4 – Res: Reserved Bit

This bit is an unused bit in the ATmega48/88/168, and will always read as zero.

• Bits 3:0 – MUX3:0: Analog Channel Selection Bits

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The value of these bits selects which analog inputs are connected to the ADC. See Table 23-3

for details. If these bits are changed during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set).

Table 23-3. Input Channel Selections

MUX3..0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Single Ended Input

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

(reserved)

1.1V (V_BG

)

0V (GND)

23.8.2

ADCSRA – ADC Control and Status Register A

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADATE

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

(0x7A)

ADCSRA

Read/Write

Initial Value

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

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• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Registers are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI

instructions are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

Table 23-4. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

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23.8.3

ADCL and ADCH – The ADC Data Register

23.8.3.1

ADLAR = 0

Bit

15

14

13

12

11

10

9

8

(0x79)

(0x78)

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

23.8.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

(0x79)

(0x78)

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 256.

23.8.4

ADCSRB – ADC Control and Status Register B

Bit

7

–

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

(0x7B)

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7, 5:3 – Res: Reserved Bits

These bits are reserved for future use. To ensure compatibility with future devices, these bist

must be written to zero when ADCSRB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

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trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 23-5. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match A

Timer/Counter0 Overflow

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

23.8.5

DIDR0 – Digital Input Disable Register 0

Bit

7

–

6

–

5

ADC5D

R/W

0

4

ADC4D

R/W

0

3

ADC3D

R/W

0

2

ADC2D

R/W

0

1

ADC1D

R/W

0

ADC0D

R/W

0

(0x7E)

DIDR0

Read/Write

Initial Value

R

0

R

0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved for future use. To ensure compatibility with future devices, these bits

must be written to zero when DIDR0 is written.

• Bit 5:0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC5..0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not

require Digital Input Disable bits.

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24. debugWIRE On-chip Debug System

24.1 Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

24.2 Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

24.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 24-1. The debugWIRE Setup

1.8 - 5.5V

VCC

dW

dW(RESET)

GND

Figure 24-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL Fuses.

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When designing a system where debugWIRE will be used, the following observations must be

made for correct operation:

• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor

is not required for debugWIRE functionality.

• Connecting the RESET pin directly to V_CCwill not work.

• Capacitors connected to the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

24.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio^®will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to

end customers.

24.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

The debugWIRE system shares system clock with the SPI module. Thus the PRSPI bit in the

PRR register must not be set when debugging. Setting the PRSPI bit will disable the clock to the

debugWIRE module and may lead to lockup of the device.

A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWire is not used.

24.6 Register Description

The following section describes the registers used with the debugWire.

24.6.1

DWDR – debugWire Data Register

Bit

7

6

5

4

3

2

1

0

DWDR[7:0]

DWDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The DWDR Register provides a communication channel from the running program in the MCU

to the debugger. This register is only accessible by the debugWIRE and can therefore not be

used as a general purpose register in the normal operations.

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25. Self-Programming the Flash, ATmega48

25.1 Overview

In ATmega48, there is no Read-While-Write support, and no separate Boot Loader Section. The

SPM instruction can be executed from the entire Flash.

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory.

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the same

page.

25.1.1

25.1.2

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• The CPU is halted during the Page Erase operation.

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

25.1.3

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• The CPU is halted during the Page Write operation.

25.2 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 27-9 on page 290), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 26-3. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the software addresses the

same page in both the Page Erase and Page Write operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 25-1. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 26-3 are listed in Table 27-9 on page 290.

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25.2.1

25.2.2

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM

instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles

after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte

(FLB) will be loaded in the destination register as shown below.See Table 27-5 on page 288 for

a detailed description and mapping of the Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the

SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown

below. See Table 27-4 on page 287 for detailed description and mapping of the Extended Fuse

byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an

LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set

in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as

shown below. See Table 27-5 on page 288 for detailed description and mapping of the Extended

Fuse byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

25.2.3

Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

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A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V_CCreset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

25.2.4

Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 25-1. SPM Programming Time⁽¹⁾

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

Note:

1. Minimum and maximum programming time is per individual operation.

25.2.5

Simple Assembly Code Example for a Boot Loader

Note that the RWWSB bit will always be read as zero in ATmega48. Nevertheless, it is recom-

mended to check this bit as shown in the code example, to ensure compatibility with devices

supporting Read-While-Write.

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

Write_page:

;PAGESIZEB is page size in BYTES, not words

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)

rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

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rcallDo_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcrval, (1<<SELFPRGEN)

rcallDo_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

; execute Page Write

subi ZL, low(PAGESIZEB)

sbci ZH, high(PAGESIZEB)

;restore pointer

;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)

rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

rcallDo_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

Rdloop:

;restore pointer

lpm r0, Z+

ld

r1, Y+

cpse r0, r1

rjmp Error

sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

in

temp1, SPMCSR

sbrs temp1, RWWSB

ret

; If RWWSB is set, the RWW section is not ready yet

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

rcallDo_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in

temp1, SPMCSR

sbrc temp1, SELFPRGEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

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Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

25.3 Register Description

25.3.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

Bit

7

SPMIE

R/W

0

6

5

–

4

RWWSRE

R/W

3

BLBSET

R/W

0

2

PGWRT

R/W

0

1

PGERS

R/W

0

SELFPRGEN

RWWSB

SPMCSR

0x37 (0x57)

Read/Write

Initial Value

R

0

R

0

R/W

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-

PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during

EEPROM write or SPM.

• Bit 6 – RWWSB: Read-While-Write Section Busy

This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero

in ATmega48.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48/88/168 and will always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. If the

RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. An

LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR

Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “Reading the Fuse and Lock Bits from Software” on page 265 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

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PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write operation.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SELFPRGEN is written, the following SPM

instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an

SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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26. Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and

ATmega168

26.1 Features

• Read-While-Write Self-Programming

• Flexible Boot Memory Size

• High Security (Separate Boot Lock Bits for a Flexible Protection)

• Separate Fuse to Select Reset Vector

• Optimized Page⁽¹⁾Size

• Code Efficient Algorithm

• Efficient Read-Modify-Write Support

Note:

1. A page is a section in the Flash consisting of several bytes (see Table 27-9 on page 290) used

during programming. The page organization does not affect normal operation.

26.2 Overview

In ATmega88 and ATmega168, the Boot Loader Support provides a real Read-While-Write Self-

Programming mechanism for downloading and uploading program code by the MCU itself. This

feature allows flexible application software updates controlled by the MCU using a Flash-resi-

dent Boot Loader program. The Boot Loader program can use any available data interface and

associated protocol to read code and write (program) that code into the Flash memory, or read

the code from the program memory. The program code within the Boot Loader section has the

capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can

thus even modify itself, and it can also erase itself from the code if the feature is not needed any-

more. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has

two separate sets of Boot Lock bits which can be set independently. This gives the user a

unique flexibility to select different levels of protection.

26.3 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 26-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 26-6 on page 282 and Figure 26-2. These two sections can

have different level of protection since they have different sets of Lock bits.

26.3.1

26.3.2

Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the application Boot Lock bits

(Boot Lock bits 0), see Table 26-2 on page 274. The Application section can never store any

Boot Loader code since the SPM instruction is disabled when executed from the Application

section.

BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 26-3 on page 274.

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26.4 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is dependent on which address that is being programmed. In addition to the two

sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 26-

7 on page 282 and Figure 26-2 on page 273. The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

• When erasing or writing a page located inside the NRWW section, the CPU is halted during the

entire operation.

Note that the user software can never read any code that is located inside the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

26.4.1

RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by a

call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown

state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-

tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy

bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read

as logical one as long as the RWW section is blocked for reading. After a programming is com-

pleted, the RWWSB must be cleared by software before reading code located in the RWW

section. See “SPMCSR – Store Program Memory Control and Status Register” on page 284. for

details on how to clear RWWSB.

26.4.2

NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire Page Erase or Page Write operation.

Table 26-1. Read-While-Write Features

Which Section does the Z-

pointer Address during

the Programming?

Which Section can be

read during

Read-While-Write

Supported?

Programming?

CPU Halted?

RWW Section

NRWW Section

None

No

Yes

No

NRWW Section

Yes

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Figure 26-1. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

Z-pointer

Addresses NRWW

Section

Z-pointer

No Read-While-Write

(NRWW) Section

Addresses RWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 26-2. Memory Sections

Program Memory

BOOTSZ = '10'

Program Memory

BOOTSZ = '11'

0x0000

Application Flash Section

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

Application Flash Section

Boot Loader Flash Section

End Application

Start Boot Loader

Flashend

Start Boot Loader

Flashend

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

0x0000

Application Flash Section

End RWW, End Application

End RWW

Start NRWW, Start Boot Loader

Start NRWW

Application Flash Section

Boot Loader Flash Section

End Application

Boot Loader Flash Section

Start Boot Loader

Flashend

Note:

1. The parameters in the figure above are given in Table 26-6 on page 282.

26.5 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives

the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a software update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

• Allow software update in the entire Flash.

See Table 26-2 and Table 26-3 for further details. The Boot Lock bits can be set in software and

in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command

only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash

memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not

control reading nor writing by LPM/SPM, if it is attempted.

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Table 26-2. Boot Lock Bit0 Protection Modes (Application Section)⁽¹⁾

BLB0 Mode

BLB02

BLB01

Protection

No restrictions for SPM or LPM accessing the Application

section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 26-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)⁽¹⁾

BLB1 Mode

BLB12

BLB11

Protection

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

3

4

0

1

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

Note:

1. “1” means unprogrammed, “0” means programmed

26.6 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,

the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash

start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-

tion code is loaded, the program can start executing the application code. Note that the fuses

cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial or parallel programming interface.

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Table 26-4. Boot Reset Fuse⁽¹⁾

BOOTRST

Reset Address

1

0

Reset Vector = Application Reset (address 0x0000)

Reset Vector = Boot Loader Reset (see Table 26-6 on page 282)

Note:

1. “1” means unprogrammed, “0” means programmed

26.7 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 27-9 on page 290), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is1 shown in Figure 26-3. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the Boot Loader software

addresses the same page in both the Page Erase and Page Write operation. Once a program-

ming operation is initiated, the address is latched and the Z-pointer can be used for other

operations.

The only SPM operation that does not use the Z-pointer is Setting the Boot Loader Lock bits.

The content of the Z-pointer is ignored and will have no effect on the operation. The LPM

instruction does also use the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

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Figure 26-3. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 26-3 are listed in Table 26-8 on page 282.

26.8 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the same

page. See “Simple Assembly Code Example for a Boot Loader” on page 280 for an assembly

code example.

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26.8.1

Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

26.8.2

Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

26.8.3

Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

26.8.4

Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of

polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors

should be moved to the BLS section to avoid that an interrupt is accessing the RWW section

when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page

57.

26.8.5

26.8.6

Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS

as described in “Interrupts” on page 57, or the interrupts must be disabled. Before addressing

the RWW section after the programming is completed, the user software must clear the

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RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on

page 280 for an example.

26.8.7

Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general lock bits, write the desired data to R0, write

“X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.

Bit

7

6

5

4

3

2

1

0

R0

1

BLB12

BLB11

BLB02

BLB01

LB2

LB1

See Table 26-2 and Table 26-3 for how the different settings of the Boot Loader bits affect the

Flash access.

If bits 5..0 in R0 are cleared (zero), the corresponding Boot Lock bit and general lock bit will be

programmed if an SPM instruction is executed within four cycles after BLBSET and SELF-

PRGEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for future

compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the

lO_ckbits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when

writing the Lock bits. When programming the Lock bits the entire Flash can be read during the

operation.

26.8.8

26.8.9

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM

instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

Bit

Rd

7

6

5

4

3

2

1

0

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET

and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles

after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte

(FLB) will be loaded in the destination register as shown below. Refer to Table 27-5 on page 288

for a detailed description and mapping of the Fuse Low byte.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the

SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as

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shown below. Refer to Table 27-6 on page 288 for detailed description and mapping of the Fuse

High byte.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction

is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR,

the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown

below. Refer to Table 27-4 on page 287 for detailed description and mapping of the Extended

Fuse byte.

Bit

Rd

7

6

5

4

3

2

1

0

–

EFB3

EFB2

EFB1

EFB0

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

26.8.10 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock

bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-

age matches the detection level. If not, an external low V_CCreset protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

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26.8.11 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-5 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 26-5. SPM Programming Time⁽¹⁾

Symbol

Min Programming Time

3.7 ms

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

4.5 ms

Note:

1. Minimum and maximum programming time is per individual operation.

26.8.12 Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2

.org SMALLBOOTSTART

Write_page:

;PAGESIZEB is page size in BYTES, not words

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld

r0, Y+

r1, Y+

ldi spmcrval, (1<<SELFPRGEN)

call Do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2

brne Wrloop

;use subi for PAGESIZEB<=256

; execute Page Write

subi ZL, low(PAGESIZEB)

sbci ZH, high(PAGESIZEB)

;restore pointer

;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)

call Do_spm

; re-enable the RWW section

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ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB)

;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)

sbci YH, high(PAGESIZEB)

Rdloop:

;restore pointer

lpm r0, Z+

ld

r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1

brne Rdloop

;use subi for PAGESIZEB<=256

; return to RWW section

; verify that RWW section is safe to read

Return:

in

temp1, SPMCSR

sbrs temp1, RWWSB

ret

; If RWWSB is set, the RWW section is not ready yet

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in

temp1, SPMCSR

sbrc temp1, SELFPRGEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in

temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

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26.8.13 ATmega88 Boot Loader Parameters

In Table 26-6 through Table 26-8, the parameters used in the description of the self program-

ming are given.

Table 26-6. Boot Size Configuration, ATmega88

Boot Reset

Address

(Start Boot

Loader

Boot

Loader

Flash

Application

Flash

Section

End

Application

Section

Boot

Size

BOOTSZ1

BOOTSZ0

Pages

Section

Section)

128

words

0x000 -

0xF7F

0xF80 -

0xFFF

1

4

0xF7F

0xEFF

0xDFF

0xBFF

0xF80

0xF00

0xE00

0xC00

256

words

0x000 -

0xEFF

0xF00 -

0xFFF

1

0

1

0

8

512

words

0x000 -

0xDFF

0xE00 -

0xFFF

16

32

1024

words

0x000 -

0xBFF

0xC00 -

0xFFF

Note:

The different BOOTSZ Fuse configurations are shown in Figure 26-2.

Table 26-7. Read-While-Write Limit, ATmega88

Section

Pages

96

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

0x000 - 0xBFF

0xC00 - 0xFFF

32

For details about these two section, see “NRWW – No Read-While-Write Section” on page 271

and “RWW – Read-While-Write Section” on page 271

Table 26-8. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-

pointer, ATmega88

Corresponding

Variable

Z-value⁽¹⁾

Description

Most significant bit in the Program Counter. (The

Program Counter is 12 bits PC[11:0])

PCMSB

11

4

Most significant bit which is used to address the

words within one page (32 words in a page requires

5 bits PC [4:0]).

PAGEMSB

ZPCMSB

Bit in Z-register that is mapped to PCMSB. Because

Z0 is not used, the ZPCMSB equals PCMSB + 1.

Z12

Z5

Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB equals

PAGEMSB + 1.

ZPAGEMSB

PCPAGE

Program counter page address: Page select, for

page erase and page write

PC[11:5]

PC[4:0]

Z12:Z6

Z5:Z1

Program counter word address: Word select, for

filling temporary buffer (must be zero during page

write operation)

PCWORD

Note:

1. Z15:Z13: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

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See “Addressing the Flash During Self-Programming” on page 275 for details about the use of

Z-pointer during Self-Programming.

26.8.14 ATmega168 Boot Loader Parameters

In Table 26-9 through Table 26-11, the parameters used in the description of the self program-

ming are given.

Table 26-9. Boot Size Configuration, ATmega168

Boot Reset

Boot

Loader

Flash

Address

(Start Boot

Loader

Application

Flash

Section

End

Application

Section

Boot

Size

BOOTSZ1

BOOTSZ0

Pages

Section

Section)

128

words

0x0000 -

0x1F7F

0x1F80 -

0x1FFF

1

2

0x1F7F

0x1EFF

0x1DFF

0x1BFF

0x1F80

0x1F00

0x1E00

0x1C00

256

words

0x0000 -

0x1EFF

0x1F00 -

0x1FFF

1

0

1

0

4

8

512

words

0x0000 -

0x1DFF

0x1E00 -

0x1FFF

1024

words

0x0000 -

0x1BFF

0x1C00 -

0x1FFF

16

Note:

The different BOOTSZ Fuse configurations are shown in Figure 26-2.

Table 26-10. Read-While-Write Limit, ATmega168

Section

Pages

112

Address

Read-While-Write section (RWW)

No Read-While-Write section (NRWW)

0x0000 - 0x1BFF

0x1C00 - 0x1FFF

16

For details about these two section, see “NRWW – No Read-While-Write Section” on page 271

and “RWW – Read-While-Write Section” on page 271

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Table 26-11. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-

pointer, ATmega168

Corresponding

Variable

Z-value⁽¹⁾

Description

Most significant bit in the Program Counter. (The

Program Counter is 12 bits PC[11:0])

PCMSB

12

5

Most significant bit which is used to address

the words within one page (64 words in a page

requires 6 bits PC [5:0])

PAGEMSB

ZPCMSB

Bit in Z-register that is mapped to PCMSB. Because

Z0 is not used, the ZPCMSB equals PCMSB + 1.

Z13

Z6

Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB equals

PAGEMSB + 1.

ZPAGEMSB

PCPAGE

Program counter page address: Page select, for

page erase and page write

PC[12:6]

PC[5:0]

Z13:Z7

Z6:Z1

Program counter word address: Word select, for

filling temporary buffer (must be zero during page

write operation)

PCWORD

Note:

1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See “Addressing the Flash During Self-Programming” on page 275 for details about the use of

Z-pointer during Self-Programming.

26.9 Register Description

26.9.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

Bit

7

SPMIE

R/W

0

6

5

–

4

RWWSRE

R/W

3

BLBSET

R/W

0

2

PGWRT

R/W

0

1

PGERS

R/W

0

RWWSB

SELFPRGEN

SPMCSR

0x37 (0x57)

Read/Write

Initial Value

R

0

R

0

R/W

0

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-

PRGEN bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

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• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48/88/168 and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SELFPRGEN will be cleared).

Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM

instruction within four clock cycles re-enables the RWW section. The RWW section cannot be

re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If

the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort

and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in

R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared

upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.

An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR

Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “Reading the Fuse and Lock Bits from Software” on page 278 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW

section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write operation if the NRWW section is addressed.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SELFPRGEN is written, the following SPM

instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an

SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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27. Memory Programming

27.1 Program And Data Memory Lock Bits

The ATmega88/168 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be

erased to “1” with the Chip Erase command.The ATmega48 has no separate Boot Loader sec-

tion. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed

(“0”), otherwise it is disabled.

Table 27-1. Lock Bit Byte⁽¹⁾

Lock Bit Byte

Bit No

Description

–

Default Value

7

6

5

4

3

2

1

0

1 (unprogrammed)

–

BLB12⁽²⁾

Boot Lock bit

Lock bit

BLB11⁽²⁾

BLB02⁽²⁾

BLB01⁽²⁾

LB2

LB1

Lock bit

Notes: 1. “1” means unprogrammed, “0” means programmed

2. Only on ATmega88/168.

Table 27-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits

Protection Type

LB Mode

LB2

LB1

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

Parallel and Serial Programming mode. The Fuse bits are

locked in both Serial and Parallel Programming mode.⁽¹⁾

2

1

0

Further programming and verification of the Flash and EEPROM

is disabled in Parallel and Serial Programming mode. The Boot

Lock bits and Fuse bits are locked in both Serial and Parallel

Programming mode.⁽¹⁾

3

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

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Table 27-3. Lock Bit Protection Modes⁽¹⁾⁽²⁾. Only ATmega88/168.

BLB0 Mode

BLB02

BLB01

No restrictions for SPM or LPM accessing the Application

section.

1

2

1

0

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

3

4

0

1

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

BLB1 Mode

BLB12

BLB11

No restrictions for SPM or LPM accessing the Boot Loader

section.

1

2

1

0

SPM is not allowed to write to the Boot Loader section.

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

3

4

0

1

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

27.2 Fuse Bits

The ATmega48/88/168 has three Fuse bytes. Table 27-4 - Table 27-7 describe briefly the func-

tionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are

read as logical zero, “0”, if they are programmed.

Table 27-4. Extended Fuse Byte for mega48

Extended Fuse Byte

Bit No

Description

Default Value

–

7

6

5

4

3

2

1

0

–

1

–

1

–

1

–

1

–

1

–

1

–

1

SELFPRGEN

Self Programming Enable

1 (unprogrammed)

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Table 27-5. Extended Fuse Byte for mega88/168

Extended Fuse Byte

Bit No

Description

Default Value

–

7

6

5

4

3

–

1

Select Boot Size

(see Table 26-6 on page 282

and Table 26-9 on page 283

for details)

BOOTSZ1

2

0 (programmed)⁽¹⁾

Select Boot Size

(see Table 26-6 on page 282

and Table 26-9 on page 283

for details)

BOOTSZ0

BOOTRST

1

0

0 (programmed)⁽¹⁾

1 (unprogrammed)

Select Reset Vector

Note:

1. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 27-11 on page

291 for details.

Table 27-6. Fuse High Byte

High Fuse Byte

RSTDISBL⁽¹⁾

DWEN

Bit No

Description

Default Value

7

6

External Reset Disable

debugWIRE Enable

1 (unprogrammed)

Enable Serial Program and

Data Downloading

0 (programmed, SPI

programming enabled)

SPIEN⁽²⁾

5

4

WDTON⁽³⁾

Watchdog Timer Always On

1 (unprogrammed)

EEPROM memory is

preserved through the Chip

Erase

1 (unprogrammed), EEPROM

not reserved

EESAVE

3

Brown-out Detector trigger

level

BODLEVEL2⁽⁴⁾

BODLEVEL1⁽⁴⁾

BODLEVEL0⁽⁴⁾

2

1

0

1 (unprogrammed)

Brown-out Detector trigger

level

Brown-out Detector trigger

level

Notes: 1. See “Alternate Functions of Port C” on page 82 for description of RSTDISBL Fuse.

2. The SPIEN Fuse is not accessible in serial programming mode.

3. See “WDTCSR – Watchdog Timer Control Register” on page 54 for details.

4. See Table 28-4 on page 308 for BODLEVEL Fuse decoding.

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Table 27-7. Fuse Low Byte

Low Fuse Byte

CKDIV8⁽⁴⁾

CKOUT⁽³⁾

SUT1

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

Divide clock by 8

Clock output

0 (programmed)

1 (unprogrammed)

1 (unprogrammed)⁽¹⁾

0 (programmed)⁽¹⁾

0 (programmed)⁽²⁾

1 (unprogrammed)⁽²⁾

0 (programmed)⁽²⁾

Select start-up time

Select Clock source

SUT0

CKSEL3

CKSEL2

CKSEL1

CKSEL0

Note:

1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 8-9 on page 35 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 8-8 on

page 35 for details.

3. The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock Output Buffer”

on page 36 for details.

4. See “System Clock Prescaler” on page 37 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

27.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

27.3 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space. For the ATmega48/88/168 the signature bytes are

given in Table 27-8.

Table 27-8. Device ID

Signature Bytes Address

Part

0x000

0x1E

0x001

0x92

0x93

0x94

0x002

0x05

0x0A

0x06

ATmega48

ATmega88

ATmega168

27.4 Calibration Byte

The ATmega48/88/168 has a byte calibration value for the internal RC Oscillator. This byte

resides in the high byte of address 0x000 in the signature address space. During reset, this byte

is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated

RC Oscillator.

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27.5 Page Size

Table 27-9. No. of Words in a Page and No. of Pages in the Flash

No. of

Device

Flash Size

Page Size

PCWORD

Pages

PCPAGE

PCMSB

2K words

(4K bytes)

ATmega48

32 words

PC[4:0]

64

PC[10:5]

10

4K words

(8K bytes)

ATmega88

32 words

64 words

PC[4:0]

PC[5:0]

128

PC[11:5]

PC[12:6]

11

12

8K words

(16K bytes)

ATmega168

Table 27-10. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM

Size

Page

Size

No. of

Pages

Device

PCWORD

EEA[1:0]

PCPAGE

EEA[7:2]

EEA[8:2]

EEAMSB

ATmega48

ATmega88

ATmega168

256 bytes

512 bytes

4 bytes

64

7

8

128

27.6 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATmega48/88/168. Pulses are assumed

to be at least 250 ns unless otherwise noted.

27.6.1

Signal Names

In this section, some pins of the ATmega48/88/168 are referenced by signal names describing

their functionality during parallel programming, see Figure 27-1 and Table 27-11. Pins not

described in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 27-13.

When pulsing WR or OE, the command loaded determines the action executed. The different

Commands are shown in Table 27-14.

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Figure 27-1. Parallel Programming

+4.5 - 5.5V

RDY/BSY

OE

PD1

PD2

PD3

PD4

PD5

PD6

PD7

VCC

+4.5 - 5.5V

AVCC

WR

BS1

PC[1:0]:PB[5:0]

DATA

XA0

XA1

PAGEL

+12 V

BS2

RESET

PC2

XTAL1

GND

Note:

V_CC- 0.3V < AV_CC< V_CC+ 0.3V, however, AV_CCshould always be within 4.5 - 5.5V

Table 27-11. Pin Name Mapping

Signal Name in

Programming Mode

Pin Name

I/O Function

0: Device is busy programming, 1: Device is

ready for new command

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (Active low)

Write Pulse (Active low)

WR

Byte Select 1 (“0” selects Low byte, “1” selects

High byte)

BS1

PD4

I

XA0

XA1

PD5

PD6

I

XTAL Action Bit 0

XTAL Action Bit 1

Program memory and EEPROM Data Page

Load

PAGEL

PD7

PC2

I

Byte Select 2 (“0” selects Low byte, “1” selects

2’nd High byte)

BS2

DATA

{PC[1:0]: PB[5:0]}

I/O Bi-directional Data bus (Output when OE is low)

Table 27-12. Pin Values Used to Enter Programming Mode

PAGEL

XA1

Symbol

Value

Prog_enable[3]

Prog_enable[2]

Prog_enable[1]

Prog_enable[0]

0

XA0

BS1

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Table 27-13. XA1 and XA0 Coding

XA1

XA0

Action when XTAL1 is Pulsed

0

1

0

1

0

1

Load Flash or EEPROM Address (High or low address byte determined by BS1).

Load Data (High or Low data byte for Flash determined by BS1).

Load Command

No Action, Idle

Table 27-14. Command Byte Bit Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0001 0001

0000 1000

0000 0100

0000 0010

0000 0011

Command Executed

Chip Erase

Write Fuse bits

Write Lock bits

Write Flash

Write EEPROM

Read Signature Bytes and Calibration byte

Read Fuse and Lock bits

Read Flash

Read EEPROM

27.7 Parallel Programming

27.7.1

Enter Programming Mode

The following algorithm puts the device in Parallel (High-voltage) Programming mode:

1. Set Prog_enable pins listed in Table 27-12 on page 291 to “0000”, RESET pin to 0V and

V

_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND.

Ensure that V_CCreaches at least 1.8V within the next 20 µs.

3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been

applied to ensure the Prog_enable Signature has been latched.

5. Wait at least 300 µs before giving any parallel programming commands.

6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of the V_CCis unable to fulfill the requirements listed above, the following alterna-

tive algorithm can be used.

1. Set Prog_enable pins listed in Table 27-12 on page 291 to “0000”, RESET pin to 0V and

V

_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND.

3. Monitor V_CC, and as soon as V_CCreaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

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4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been

applied to ensure the Prog_enable Signature has been latched.

5. Wait until V_CCactually reaches 4.5 -5.5V before giving any parallel programming

commands.

6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

27.7.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

27.7.3

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Note:

1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

27.7.4

Programming the Flash

The Flash is organized in pages, see Table 27-9 on page 290. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

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4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 27-3 for signal

waveforms)

F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.

While the lower bits in the address are mapped to words within the page, the higher bits address

the pages within the FLASH. This is illustrated in Figure 27-2 on page 295. Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)

in the address low byte are used to address the page when performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY

goes low.

2. Wait until RDY/BSY goes high (See Figure 27-3 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

reset.

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Figure 27-2. Addressing the Flash Which is Organized in Pages⁽¹⁾

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. PCPAGE and PCWORD are listed in Table 27-9 on page 290.

Figure 27-3. Programming the Flash Waveforms⁽¹⁾

F

A

B

C

D

E

B

C

D

E

G

H

0x10

ADDR. LOW

DATA LOW

DATA HIGH

ADDR. LOW DATA LOW

DATA HIGH

ADDR. HIGH

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

Note:

1. “XX” is don’t care. The letters refer to the programming description above.

27.7.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 27-10 on page 290. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to “Programming the Flash” on page 293 for details on Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

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5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS1 to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. Wait until to RDY/BSY goes high before programming the next page (See Figure 27-4 for

signal waveforms).

Figure 27-4. Programming the EEPROM Waveforms

K

A

G

B

C

E

B

C

E

L

0x11

ADDR. HIGH

ADDR. LOW

DATA

ADDR. LOW

DATA

XX

DATA

XA1

XA0

BS1

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

BS2

27.7.6

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on

page 293 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

27.7.7

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”

on page 293 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

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27.7.8

Programming the Fuse Low Bits

The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”

on page 293 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

27.7.9

Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the

Flash” on page 293 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

27.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the

Flash” on page 293 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 27-5. Programming the FUSES Waveforms

Write Fuse Low byte

Write Fuse high byte

Write Extended Fuse byte

A

C

A

C

A

C

0x40

DATA

XX

0x40

DATA

XX

0x40

DATA

XX

DATA

XA1

XA0

BS1

BS2

XTAL1

WR

RDY/BSY

RESET +12V

OE

PAGEL

27.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on

page 293 for details on Command and Data loading):

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1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

27.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”

on page 293 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

0

Fuse Low Byte

Extended Fuse Byte

Lock Bits

0

1

0

DATA

BS2

BS1

Fuse High Byte

1

BS2

27.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on

page 293 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

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27.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on

page 293 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

27.7.15 Parallel Programming Characteristics

For characteristics of the parallel programming, see “Parallel Programming Characteristics” on

page 313.

27.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 27-15 on page 300, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

Figure 27-7. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

+1.8 - 5.5V⁽²⁾

MOSI

AVCC

MISO

SCK

XTAL1

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V_CC- 0.3V < AV_CC< V_CC+ 0.3V, however, AV_CCshould always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

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27.8.1

Serial Programming Pin Mapping

Table 27-15. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB3

PB4

PB5

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

27.8.2

Serial Programming Algorithm

When writing serial data to the ATmega48/88/168, data is clocked on the rising edge of SCK.

When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See

Figure 27-9 for timing details.

To program and verify the ATmega48/88/168 in the serial programming mode, the following

sequence is recommended (See Serial Programming Instruction set in Table 27-17 on page

301):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at a

time by supplying the 6 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of

the address. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH}before

issuing the next page (See Table 27-16). Accessing the serial programming interface

before the Flash write operation completes can result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling (RDY/BSY) is not used, the

user must wait at least t_{WD_EEPROM}before issuing the next byte (See Table 27-16). In a

chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 6 LSB of the address and data together with the Load

EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading

the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using

EEPROM page access only byte locations loaded with the Load EEPROM Memory Page

instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is

not used, the used must wait at least t_{WD_EEPROM}before issuing the next byte (See Table

27-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

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ATmega48/88/168

6. Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

Table 27-16. Typical Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

3.6 ms

9.0 ms

27.8.3

Serial Programming Instruction set

Table 27-17 on page 301 and Figure 27-8 on page 302 describes the Instruction set.

Table 27-17. Serial Programming Instruction Set (Hexadecimal values)

Instruction Format

Instruction/Operation

Byte 1

$AC

Byte 2

Byte 3

$00

Byte4

$00

Programming Enable

$53

$80

$00

Chip Erase (Program Memory/EEPROM)

Poll RDY/BSY

$AC

$00

$F0

$00

data byte out

Load Instructions

Load Extended Address byte⁽¹⁾

Load Program Memory Page, High byte

Load Program Memory Page, Low byte

Load EEPROM Memory Page (page access)

Read Instructions

$4D

$48

$40

$C1

$00

Extended adr

adr LSB

$00

high data byte in

low data byte in

data byte in

adr LSB

0000 000aa

Read Program Memory, High byte

Read Program Memory, Low byte

Read EEPROM Memory

Read Lock bits

$28

$20

$A0

$58

$30

$50

$58

$50

$38

adr MSB

0000 00aa

$00

adr LSB

aaaa aaaa

$00

high data byte out

low data byte out

data byte out

Read Signature Byte

$00

0000 000aa

$00

Read Fuse bits

$00

Read Fuse High bits

$08

$00

Read Extended Fuse Bits

$08

$00

Read Calibration Byte

$00

Write Instructions⁽⁶⁾

Write Program Memory Page

Write EEPROM Memory

$4C

$C0

adr MSB

adr LSB

$00

0000 00aa

aaaa aaaa

data byte in

301

2545M–AVR–09/07

Table 27-17. Serial Programming Instruction Set (Hexadecimal values) (Continued)

Instruction Format

Instruction/Operation

Write EEPROM Memory Page (page access)

Write Lock bits

Byte 1

$C2

Byte 2

Byte 3

aaaa aa00

$00

Byte4

0000 00aa

$E0

$00

$AC

data byte in

Write Fuse bits

$A0

$00

Write Fuse High bits

$A8

$00

Write Extended Fuse Bits

$A4

$00

Notes: 1. Not all instructions are applicable for all parts.

2. a = address.

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6. Instructions accessing program memory use a word address. This word may be random within the page range.

7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 27-8 on page

302.

Figure 27-8. Serial Programming Instruction example

Serial Programming Instruction

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Write Program Memory Page/

Write EEPROM Memory Page

Byte 1

Byte 2

Byte 3

Byte 4

Byte 1

Byte 2

Byte 3

Byte 4

Adr MSB

Adr LSB

Adr MSB

Adr LSB

Bit 15

B

0

Bit 15

B

0

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

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ATmega48/88/168

27.8.4

SPI Serial Programming Characteristics

Figure 27-9. Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

(MISO)

MSB

SERIAL CLOCK INPUT

(SCK)

SAMPLE

For characteristics of the SPI module see “SPI Timing Characteristics” on page 310.

303

2545M–AVR–09/07

28. Electrical Characteristics

28.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

28.2 DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

(1)

Input Low Voltage, except

XTAL1 and RESET pin

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

-0.5

0.2V_CC

0.3V_CC

V_IL

V

(2)

Input High Voltage, except

XTAL1 and RESET pins

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

V_CC+ 0.5

V_IH

V

(2)

Input Low Voltage,

XTAL1 pin

(1)

V_IL1

V_IH1

V_IL2

V_IH2

V_IL3

V_IH3

V_OL

V_OH

I_IL

V_CC= 1.8V - 5.5V

-0.5

0.1V_CC

(2)

Input High Voltage,

XTAL1 pin

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

0.8V_CC

0.7V_CC

V_CC+ 0.5

V

Input Low Voltage,

RESET pin

(1)

V_CC= 1.8V - 5.5V

-0.5

0.2V_CC

V

Input High Voltage,

RESET pin

(2)

0.9V_CC

V_CC+ 0.5

V

(1)

Input Low Voltage,

RESET pin as I/O

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

-0.5

0.2V_CC

0.3V_CC

V

(1)

(2)

Input High Voltage,

RESET pin as I/O

V_CC= 1.8V - 2.4V

0.7V_CC

0.6V_CC

V_CC+ 0.5

_CC+ 0.5

V

V_CC= 2.4V - 5.5V

V

Output Low Voltage⁽³⁾,

RESET pin as I/O

I

_OL= 20mA, V_CC= 5V

0.7

0.5

V

I_OL= 6mA, V_CC= 3V

Output High Voltage⁽⁴⁾,

RESET pin as I/O

I

_OH= -20mA, V_CC= 5V

4.2

2.3

V

I_OH= -10mA, V_CC= 3V

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin low

(absolute value)

1

µA

Input Leakage

Current I/O Pin

V_CC= 5.5V, pin high

(absolute value)

I_IH

R_RST

R_PU

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

30

20

60

50

kΩ

304

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted) (Continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Active 1MHz, V_CC= 2V

(ATmega48/88/168V)

0.55

mA

Active 4MHz, V_CC= 3V

(ATmega48/88/168L)

3.5

12

mA

Active 8MHz, V_CC= 5V

(ATmega48/88/168)

Power Supply Current⁽⁵⁾

Idle 1MHz, V_CC= 2V

(ATmega48/88/168V)

0.25

0.5

1.5

5.5

I_CC

Idle 4MHz, V_CC= 3V

(ATmega48/88/168L)

Idle 8MHz, V_CC= 5V

(ATmega48/88/168)

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

8

1

15

2

µA

Power-down mode

V_CC= 5V

Analog Comparator

Input Offset Voltage

V_ACIO

I_ACLK

t_ACID

10

40

50

mV

nA

ns

V_in= V_CC/2

Analog Comparator

Input Leakage Current

V_CC= 5V

V_in= V_CC/2

-50

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750

500

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

ATmega48/88/168:

1] The sum of all I_OL, for ports C0 - C5, ADC7, ADC6 should not exceed 100 mA.

2] The sum of all I_OL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100 mA.

3] The sum of all I_OL, for ports D0 - D4, RESET should not exceed 100 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

ATmega48/88/168:

1] The sum of all I_OH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150 mA.

2] The sum of all I_OH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150 mA.

If II_OHexceeds the test condition, V_OHmay exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

5. Values with “Minimizing Power Consumption” enabled (0xFF).

305

2545M–AVR–09/07

28.3 Speed Grades

Maximum frequency is dependent on V_CC.As shown in Figure 28-1 and Figure 28-2, the Maxi-

mum Frequency vs. V_CCcurve is linear between 1.8V < V_CC< 2.7V and between 2.7V < V_CC

4.5V.

<

Figure 28-1. Maximum Frequency vs. V_CC, ATmega48V/88V/168V

10 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 28-2. Maximum Frequency vs. V_CC, ATmega48/88/168

20 MHz

10 MHz

Safe Operating Area

2.7V

4.5V

5.5V

306

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ATmega48/88/168

28.4 Clock Characteristics

28.4.1

Calibrated Internal RC Oscillator Accuracy

Table 28-1. Calibration Accuracy of Internal RC Oscillator

Frequency

V_CC

Temperature

Calibration Accuracy

Factory

Calibration

8.0 MHz

3V

25°C

±10%

User

Calibration

1.8V - 5.5V⁽¹⁾

2.7V - 5.5V⁽²⁾

7.3 - 8.1 MHz

-40°C - 85°C

±1%

Notes: 1. Voltage range for ATmega48V/88V/168V.

2. Voltage range for ATmega48/88/168.

28.4.2

External Clock Drive Waveforms

Figure 28-3. External Clock Drive Waveforms

V

IH1

V

IL1

28.4.3

External Clock Drive

Table 28-2. External Clock Drive

V_CC=1.8-5.5V

V_CC=2.7-5.5V

V_CC=4.5-5.5V

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Units

Oscillator

Frequency

1/t_CLCL

0

4

0

10

0

20

MHz

t_CLCL

t_CHCX

t_CLCX

t_CLCH

t_CHCL

Clock Period

High Time

Low Time

Rise Time

Fall Time

250

100

40

50

20

ns

μs

40

2.0

1.6

0.5

Change in period

from one clock

cycle to the next

Δt_CLCL

2

%

307

2545M–AVR–09/07

28.5 System and Reset Characteristics

Table 28-3. Reset, Brown-out and Internal voltage Characteristics

Symbol

Parameter

Condition

Min

0.7

Typ

1.0

0.9

Max

1.4

Units

V

Power-on Reset Threshold Voltage (rising)

Power-on Reset Threshold Voltage (falling)⁽¹⁾

Power-on Slope Rate

V_POT

0.05

1.3

V

V_PSR

V_RST

t_RST

0.01

4.5

V/ms

V

RESET Pin Threshold Voltage

Minimum pulse width on RESET Pin

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

0.2 V_CC

0.9 V_CC

2.5

µs

V_HYST

t_BOD

50

2

mV

µs

V_CC=2.7

T_A=25°C

V_BG

t_BG

I_BG

Bandgap reference voltage

1.0

1.1

40

10

1.2

70

V

V_CC=2.7

Bandgap reference start-up time

Bandgap reference current consumption

µs

µA

T_A=25°C

V_CC=2.7

T_A=25°C

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

Table 28-4. BODLEVEL Fuse Coding⁽¹⁾

BODLEVEL 2:0 Fuses

Min V_BOT

Typ V_BOT

BOD Disabled

Max V_BOT

Units

111

110

101

100

011

010

001

000

1.7

2.5

4.1

1.8

2.7

4.3

2.0

2.9

4.5

V

Reserved

Notes: 1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is

tested down to V_CC= V_BOTduring the production test. This guarantees that a Brown-Out Reset will occur before V_CCdrops to

a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 110 and BODLEVEL = 101 for ATmega48V/88V/168V, and BODLEVEL = 101 and BODLEVEL = 100 for

ATmega48/88/168.

308

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ATmega48/88/168

28.6 2-wire Serial Interface Characteristics

Table 28-5 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48/88/168 2-wire Serial

Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 28-4.

Table 28-5. 2-wire Serial Bus Requirements

Symbol Parameter

Condition

Min

-0.5

Max

0.3 V_CC

V_CC+ 0.5

–

Units

V

Input Low-voltage

VIL

Input High-voltage

0.7 V_CC

V

VIH

Vhys

(1)

(2)

Hysteresis of Schmitt Trigger Inputs

Output Low-voltage

0.05 V_CC

V

(1)

VOL

3 mA sink current

10 pF < C_b< 400 pF⁽³⁾

0.1V_CC< V_i< 0.9V_CC

0

0.4

V

(1)

tr

(3)(2)

Rise Time for both SDA and SCL

Output Fall Time from V_IHminto V_ILmax

Spikes Suppressed by Input Filter

Input Current each I/O Pin

Capacitance for each I/O Pin

SCL Clock Frequency

20 + 0.1C_b

300

ns

µA

pF

kHz

(1)

tof

20 + 0.1C_b

250

0

-10

–

50⁽²⁾

(1)

tSP

I_i

10

C_i⁽¹⁾

10

f_SCL

f_CK⁽⁴⁾> max(16f_SCL, 250kHz)⁽⁵⁾

0

400

V_CC– 0,4V

---------------------------

3mA

f_SCL≤ 100 kHz

1000ns

C_b

----------------

Ω

Rp

Value of Pull-up resistor

V

_CC– 0,4V

f_SCL> 100 kHz

300ns

---------------------------

-------------

3mA

C_b

f_SCL≤ 100 kHz

_SCL> 100 kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0

–

µs

ns

µs

t_HD;STA

Hold Time (repeated) START Condition

Low Period of the SCL Clock

High period of the SCL clock

Set-up time for a repeated START condition

Data hold time

f

–

f_SCL≤ 100 kHz⁽⁶⁾

f_SCL> 100 kHz⁽⁷⁾

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

–

t_LOW

–

t_HIGH

–

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

f_SCL> 100 kHz

–

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

f_SCL> 100 kHz

f_SCL≤ 100 kHz

3.45

0.9

–

0

250

100

4.0

0.6

4.7

1.3

Data setup time

–

Setup time for STOP condition

f

_SCL> 100 kHz

f_SCL≤ 100 kHz

_SCL> 100 kHz

–

Bus free time between a STOP and START

condition

f

–

Notes: 1. In ATmega48/88/168, this parameter is characterized and not 100% tested.

2. Required only for f_SCL> 100 kHz.

309

2545M–AVR–09/07

3. C_b= capacitance of one bus line in pF.

4. f_CK= CPU clock frequency

5. This requirement applies to all ATmega48/88/168 2-wire Serial Interface operation. Other devices connected to the 2-wire

Serial Bus need only obey the general f_SCLrequirement.

6. The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/f_SCL- 2/f_CK), thus f_CKmust be greater

than 6 MHz for the low time requirement to be strictly met at f_SCL= 100 kHz.

7. The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/f_SCL- 2/f_CK), thus the low time require-

ment will not be strictly met for f_SCL> 308 kHz when f_CK= 8 MHz. Still, ATmega48/88/168 devices connected to the bus may

communicate at full speed (400 kHz) with other ATmega48/88/168 devices, as well as any other device with a proper t_LOW

acceptance margin.

Figure 28-4. 2-wire Serial Bus Timing

t

HIGH

t

r

of

t

LOW

SCL

SDA

t

HD;DAT

SU;STA

HD;STA

t

SU;DAT

t

SU;STO

t

BUF

28.7 SPI Timing Characteristics

See Figure 28-5 and Figure 28-6 for details.

Table 28-6. SPI Timing Parameters

Description

SCK period

SCK high/low

Rise/Fall time

Setup

Mode

Master

Slave

Min

Typ

Max

1

See Table 18-5

2

50% duty cycle

3

3.6

10

4

5

Hold

10

6

Out to SCK

SCK to out

SCK to out high

SS low to out

SCK period

SCK high/low⁽¹⁾

Rise/Fall time

Setup

0.5 • t_sck

10

7

8

10

9

15

ns

10

11

12

13

14

15

16

17

18

Slave

4 • t_ck

2 • t_ck

Slave

1600

Slave

10

t_ck

Hold

Slave

SCK to out

SCK to SS high

SS high to tri-state

SS low to SCK

Slave

15

10

Slave

20

Slave

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

- 2 t_CLCLfor f_CK< 12 MHz

- 3 t_CLCLfor f_CK> 12 MHz

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Figure 28-5. SPI Interface Timing Requirements (Master Mode)

SS

6

1

SCK

(CPOL = 0)

2

SCK

(CPOL = 1)

4

5

3

MISO

(Data Input)

MSB

...

LSB

7

8

MOSI

(Data Output)

MSB

...

LSB

Figure 28-6. SPI Interface Timing Requirements (Slave Mode)

SS

10

16

9

SCK

(CPOL = 0)

11

SCK

(CPOL = 1)

13

14

12

MOSI

(Data Input)

MSB

...

LSB

15

17

MISO

(Data Output)

MSB

...

LSB

X

311

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28.8 ADC Characteristics

Table 28-7. ADC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Resolution

10

Bits

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

2

LSB

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

4.5

Absolute accuracy (Including

INL, DNL, quantization error,

gain and offset error)

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

2

LSB

Noise Reduction Mode

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Noise Reduction Mode

4.5

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Integral Non-Linearity (INL)

0.5

0.25

2

LSB

Differential Non-Linearity

(DNL)

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

V_REF= 4V, V_CC= 4V,

Gain Error

ADC clock = 200 kHz

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Offset Error

2

Conversion Time

Free Running Conversion

13

50

260

1000

µs

kHz

V

Clock Frequency

(1)

AV_CC

Analog Supply Voltage

Reference Voltage

V_CC- 0.3

1.0

V_CC+ 0.3

AV_CC

V_REF

V_IN

V

Input Voltage

GND

V_REF

V

Input Bandwidth

38.5

1.1

kHz

V

V_INT

R_REF

R_AIN

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

1.0

1.2

32

kΩ

MΩ

100

Note:

1. AV_CCabsolute min/max: 1.8V/5.5V

312

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28.9 Parallel Programming Characteristics

Figure 28-7. Parallel Programming Timing, Including some General Timing Requirements

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDX

Data & Contol

(DATA, XA0/1, BS1, BS2)

t_BVPH

t_PLBXt_BVWL

t_WLBX

PAGEL

t_PHPL

t_WLWH

WR

t_PLWL

WLRL

RDY/BSY

t_WLRH

Figure 28-8. Parallel Programming Timing, Loading Sequence with Timing Requirements⁽¹⁾

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

LOAD DATA

(LOW BYTE)

LOAD DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLPH

t_XLXH

t_PLXH

XTAL1

BS1

PAGEL

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 28-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to load-

ing operation.

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Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements⁽¹⁾

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

t_XLOL

XTAL1

BS1

t_BVDV

t_OLDV

OE

t_OHDZ

ADDR1 (Low Byte)

DATA (High Byte)

DATA

ADDR0 (Low Byte)

DATA (Low Byte)

XA0

XA1

Note:

1. The timing requirements shown in Figure 28-7 (i.e., t_DVXH, t_XHXL, and t_XLDX) also apply to read-

ing operation.

Table 28-8. Parallel Programming Characteristics, V_CC= 5V ± 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

250

Units

V

Programming Enable Voltage

Programming Enable Current

Data and Control Valid before XTAL1 High

XTAL1 Low to XTAL1 High

XTAL1 Pulse Width High

11.5

I_PP

μA

ns

μs

ms

t_DVXH

t_XLXH

t_XHXL

t_XLDX

t_XLWL

t_XLPH

t_PLXH

t_BVPH

t_PHPL

t_PLBX

t_WLBX

t_PLWL

t_BVWL

t_WLWH

t_WLRL

t_WLRH

t_{WLRH_CE}

67

200

150

67

Data and Control Hold after XTAL1 Low

XTAL1 Low to WR Low

0

XTAL1 Low to PAGEL high

PAGEL low to XTAL1 high

BS1 Valid before PAGEL High

PAGEL Pulse Width High

BS1 Hold after PAGEL Low

BS2/1 Hold after WR Low

PAGEL Low to WR Low

0

150

67

150

67

BS1 Valid to WR Low

67

WR Pulse Width Low

150

0

WR Low to RDY/BSY Low

WR Low to RDY/BSY High⁽¹⁾

WR Low to RDY/BSY High for Chip Erase⁽²⁾

1

4.5

9

3.7

7.5

314

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Table 28-8. Parallel Programming Characteristics, V_CC= 5V ± 10% (Continued)

Symbol

t_XLOL

Parameter

Min

0

Typ

Max

Units

ns

XTAL1 Low to OE Low

BS1 Valid to DATA valid

OE Low to DATA Valid

OE High to DATA Tri-stated

t_BVDV

0

250

ns

t_OLDV

ns

t_OHDZ

ns

Notes: 1. t_WLRHis valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. t_{WLRH_CE}is valid for the Chip Erase command.

315

2545M–AVR–09/07

29. Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock

source.

All Active- and Idle current consumption measurements are done with all bits in the PRR register

set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is dis-

abled during these measurements. Table 29-1 on page 322 and Table 29-2 on page 323 show

the additional current consumption compared to I_CCActive and I_CCIdle for every I/O module con-

trolled by the Power Reduction Register. See “Power Reduction Register” on page 42 for details.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f where

C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

29.1 Active Supply Current

Figure 29-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

1.2

1

5.5 V

5.0 V

4.5 V

4.0 V

0.8

0.6

0.4

0.2

0

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

316

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Figure 29-2. Active Supply Current vs. Frequency (1 - 24 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 24 MHz

18

16

14

12

10

8

5.5V

5.0V

4.5V

4.0V

6

3.3V

4

2.7V

2

1.8V

0

4

8

12

16

20

24

Frequency (MHz)

Figure 29-3. Active Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 128 KHz

0.14

-40 °C

25 °C

85 °C

0.12

0.1

0.08

0.06

0.04

0.02

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

317

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Figure 29-4. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

1.4

25 °C

-40 °C

85 °C

1.2

1

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-5. Active Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

7

25 °C

-40 °C

6

5

4

3

2

1

0

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

318

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Figure 29-6. Active Supply Current vs. V_CC(32 kHz External Oscillator)

ACTIVE SUPPLY CURRENT vs. V_CC

32 kHz EXTERNAL OSCILLATOR

60

50

40

30

20

10

0

25 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

29.2 Idle Supply Current

Figure 29-7. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

0.18

0.16

0.14

0.12

0.1

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

0.08

0.06

0.04

0.02

0

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

319

2545M–AVR–09/07

Figure 29-8. Idle Supply Current vs. Frequency (1 - 24 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 24 MHz

4.5

4

5.5V

3.5

3

5.0V

4.5V

2.5

2

4.0V

1.5

3.3V

1

2.7V

0.5

1.8V

0

4

8

12

16

20

24

Frequency (MHz)

Figure 29-9. Idle Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 128 KHz

0.03

-40 °C

85 °C

25 °C

0.025

0.02

0.015

0.01

0.005

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

320

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Figure 29-10. Idle Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

0.35

0.3

85 °C

25 °C

-40 °C

0.25

0.2

0.15

0.1

0.05

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-11. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

1.6

85 °C

25 °C

-40 °C

1.4

1.2

1

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

321

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Figure 29-12. Idle Supply Current vs. V_CC(32 kHz External Oscillator)

IDLE SUPPLY CURRENT vs. V_CC

32 kHz EXTERNAL OSCILLATOR

30

25

20

15

10

5

25 °C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

29.3 Supply Current of I/O modules

The tables and formulas below can be used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Power Reduction Register. See “Power Reduction Register” on page 42 for

details.

Table 29-1. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit

Typical numbers

V_CC= 2V, F = 1MHz

V_CC= 3V, F = 4MHz

51 uA

V_CC= 5V, F = 8MHz

220 uA

PRUSART0

PRTWI

8.0 uA

12 uA

11 uA

5.0 uA

4.0 uA

15 uA

12 uA

75 uA

72 uA

32 uA

24 uA

95 uA

75 uA

315 uA

300 uA

130 uA

100 uA

400 uA

315 uA

PRTIM2

PRTIM1

PRTIM0

PRSPI

PRADC

322

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Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode

Additional Current consumption

compared to Active with external

clock

Additional Current consumption

compared to Idle with external clock

(see Figure 29-7 and Figure 29-8)

PRR bit

PRUSART0

PRTWI

(see Figure 29-1 and Figure 29-2)

3.3%

4.8%

4.7%

2.0%

1.6%

6.1%

4.9%

18%

26%

25%

11%

8.5%

33%

26%

PRTIM2

PRTIM1

PRTIM0

PRSPI

PRADC

It is possible to calculate the typical current consumption based on the numbers from Table 2 for

other V_CCand frequency settings than listed in Table 1.

29.3.0.1

29.3.0.2

29.3.0.3

Example 1

Example 2

Example 3

Calculate the expected current consumption in idle mode with USART0, TIMER1, and TWI

enabled at V_CC= 3.0V and F = 1MHz. From Table 2, third column, we see that we need to add

18% for the USART0, 26% for the TWI, and 11% for the TIMER1 module. Reading from Figure

3, we find that the idle current consumption is ~0,075mA at V_CC= 3.0V and F = 1MHz. The total

current consumption in idle mode with USART0, TIMER1, and TWI enabled, gives:

ICCtotal ≈ 0,075mA • (1 + 0,18 + 0,26 + 0,11) ≈ 0,116mA

Same conditions as in example 1, but in active mode instead. From Table 2, second column we

see that we need to add 3.3% for the USART0, 4.8% for the TWI, and 2.0% for the TIMER1

module. Reading from Figure 1, we find that the active current consumption is ~0,42mA at V_CC

=

3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and

TWI enabled, gives:

ICCtotal ≈ 0,42mA • (1 + 0,033 + 0,048 + 0,02) ≈ 0,46mA

All I/O modules should be enabled. Calculate the expected current consumption in active mode

at V_CC= 3.6V and F = 10MHz. We find the active current consumption without the I/O modules

to be ~ 4.0mA (from Figure 2). Then, by using the numbers from Table 2 - second column, we

find the total current consumption:

ICCtotal ≈ 4,0mA • (1 + 0,033 + 0,048 + 0,047 + 0,02 + 0,016 + 0,061 + 0,049) ≈ 5,1mA

323

2545M–AVR–09/07

29.4 Power-Down Supply Current

Figure 29-13. Power-Down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

2.5

2

85 °C

1.5

1

25 °C

-40 °C

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-14. Power-Down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

12

10

85 °C

-40 °C

25 °C

8

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

324

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29.5 Power-Save Supply Current

Figure 29-15. Power-Save Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-SAVE SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

12

10

8

25 °C

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

29.6 Standby Supply Current

Figure 29-16. Standby Supply Current vs. V_CC(Low Power Crystal Oscillator)

STANDBY SUPPLY CURRENT vs. V_CC

Low Power Crystal Oscillator

180

6 MHz Xtal

6 MHz Res.

160

140

120

100

80

4 MHz Res.

4 MHz Xtal

2 MHz Xtal

2 MHz Res.

455kHz Res.

1 MHz Res.

60

40

20

32 kHz Xtal

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

325

2545M–AVR–09/07

Figure 29-17. Standby Supply Current vs. V_CC(Full Swing Crystal Oscillator)

STANDBY SUPPLY CURRENT vs. V_CC

Full Swing Crystal Oscillator

500

16 MHz Xtal

12 MHz Xtal

450

400

350

300

250

200

150

100

50

6 MHz Xtal

(ckopt)

4 MHz Xtal

(ckopt)

2 MHz Xtal

(ckopt)

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

29.7 Pin Pull-up

Figure 29-18. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 5V

160

140

25 °C

85 °C

120

-40 °C

100

80

60

40

20

0

1

2

3

4

5

6

V_OP(V)

326

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ATmega48/88/168

Figure 29-19. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 2.7V

90

80

25 °C

-40 °C

85 °C

70

60

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_OP(V)

Figure 29-20. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 5V

120

-40ºC

25ºC

100

85ºC

80

60

40

20

0

1

2

3

4

5

6

V_RESET(V)

327

2545M–AVR–09/07

Figure 29-21. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 2.7V

70

60

-40 °C

25 °C

50

85 °C

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_RESET(V)

29.8 Pin Driver Strength

Figure 29-22. I/O Pin Source Current vs. Output Voltage (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

90

80

-40 °C

70

25 °C

60

85 °C

50

40

30

20

10

0

1

2

3

4

5

6

V_OH(V)

328

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Figure 29-23. I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

35

30

25

20

15

10

5

-40 °C

25 °C

85 °C

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 29-24. I/O Pin Source Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

9

25 °C

-40 °C

8

85 °C

7

6

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

329

2545M–AVR–09/07

Figure 29-25. I/O Pin Sink Current vs. Output Voltage (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

80

25 °C

85 °C

70

60

50

40

30

20

10

0

0.5

1

1.5

2

2.5

V_OL(V)

Figure 29-26. I/O Pin Sink Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

40

35

-40 °C

30

25

20

15

10

5

25 °C

85 °C

0

0.5

1

1.5

2

2.5

V_OL(V)

330

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 29-27. I/O Pin Sink Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

14

12

10

8

-40 °C

25 °C

85 °C

6

4

2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

29.9 Pin Thresholds and Hysteresis

Figure 29-28. I/O Pin Input Threshold Voltage vs. V_CC(VIH, I/O Pin Read As '1')

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3

2.5

2

25 °C

85 °C

-40 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

331

2545M–AVR–09/07

Figure 29-29. I/O Pin Input Threshold Voltage vs. V_CC(VIL, I/O Pin Read As '0')

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

3

85 °C

-40 °C

25 °C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-30. Reset Input Threshold Voltage vs. V_CC(VIH, Reset Pin Read As '1')

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3

25 °C

85 °C

-40 °C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

332

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 29-31. Reset Input Threshold Voltage vs. V_CC(VIL, Reset Pin Read As '0')

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

3

2.5

2

-40 °C

85 °C

25 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-32. Reset Input Pin Hysteresis vs. V_CC

RESET PIN INPUT HYSTERESIS vs. V_CC

600

500

400

300

200

100

0

VIL

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

333

2545M–AVR–09/07

29.10 BOD Thresholds and Analog Comparator Offset

Figure 29-33. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3V

4.5

4.45

4.4

Rising Vcc

4.35

4.3

Falling Vcc

4.25

4.2

-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

Figure 29-34. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

2.9

2.85

Rising Vcc

2.8

2.75

2.7

Falling Vcc

2.65

2.6

-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

334

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 29-35. BOD Thresholds vs. Temperature (BODLEVEL Is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8V

1.86

1.84

1.82

1.8

Rising Vcc

Falling Vcc

1.78

1.76

-50

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

Figure 29-36. Bandgap Voltage vs. V_CC

BANDGAP VOLTAGE vs. V_CC

1.1

1.095

1.09

-40 C

85 C

1.085

1.08

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

335

2545M–AVR–09/07

Figure 29-37. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC=5V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

V_CC=5V

0.009

0.008

85 C

0.007

-40 C

0.006

0.005

0.004

0.003

0.002

0.001

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Common Mode Voltage (V)

Figure 29-38. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC=2.7V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

V

CC=2.7V

4

3.5

3

85 C

-40 C

2.5

2

1.5

1

0.5

0

0.5

1

1.5

Common Mode Voltage (V)

2

2.5

336

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

29.11 Internal Oscillator Speed

Figure 29-39. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

120

115

110

105

100

95

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-40. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

8.4

8.3

8.2

8.1

8

5.0 V

2.7 V

1.8 V

7.9

7.8

7.7

7.6

7.5

7.4

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature (C)

337

2545M–AVR–09/07

Figure 29-41. Calibrated 8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V_CC

8.6

8.4

8.2

8

85 ˚C

25 ˚C

-40 ˚C

7.8

7.6

7.4

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-42. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

85 °C

25 °C

-40 °C

13.5

11.5

9.5

7.5

5.5

3.5

0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

338

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

29.12 Current Consumption of Peripheral Units

Figure 29-43. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. V_CC

32

30

28

26

24

22

20

18

-40 ˚C

25 ˚C

85 ˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-44. ADC Current vs. V_CC(AREF = AV_CC

)

ADC Current vs. V_CC

AREF = AV_CC

500

450

400

350

300

250

200

150

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

339

2545M–AVR–09/07

Figure 29-45. AREF External Reference Current vs. V_CC

AREF EXTERNAL REFERENCE CURRENT vs. V_CC

180

160

140

120

100

80

85 ˚C

25 ˚C

-40 ˚C

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 29-46. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V_CC

140

120

100

80

-40 ˚C

25 ˚C

85 ˚C

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

340

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Figure 29-47. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. V

cc

14

-40 ˚C

12

10

25 ˚C

8

85 ˚C

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V

(V)

V_C_C_C_C(V)

29.13 Current Consumption in Reset and Reset Pulse width

Figure 29-48. Reset Supply Current vs. V_CC(0.1 - 1.0 MHz, Excluding Current through the

Reset Pull-up)

RESET SUPPLY CURRENT vs. V_CC

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

0.18

5.5 V

0.16

5.0 V

0.14

4.5 V

0.12

4.0 V

0.1

3.3 V

0.08

2.7 V

0.06

1.8 V

0.04

0.02

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

341

2545M–AVR–09/07

Figure 29-49. Reset Supply Current vs. V_CC(1 - 24 MHz, Excluding Current through the Reset

Pull-up)

RESET SUPPLY CURRENT vs. V_CC

1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

4.5

4

3.5

3

5.5V

5.0V

4.5V

2.5

2

4.0V

1.5

1

3.3V

2.7V

0.5

0

1.8V

0

4

8

12

Frequency (MHz)

16

20

24

Figure 29-50. Reset Pulse Width vs. V_CC

RESET PULSE WIDTH vs. V_CC

2500

2000

1500

1000

500

85 ˚C

-40 ˚C

25 ˚C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

342

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

30. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

Reserved

UDR0

–

USART I/O Data Register

191

195

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

UCSR0A

USART Baud Rate Register High

USART Baud Rate Register Low

–

UCSZ01 /UDORD0

UCSZ02

UPE0

UCSZ00 / UCPHA0

UMSEL01

RXCIE0

RXC0

UMSEL00

TXCIE0

TXC0

UPM01

UDRIE0

UDRE0

UPM00

RXEN0

FE0

USBS0

TXEN0

DOR0

UCPOL0

TXB80

MPCM0

193/208

192

RXB80

U2X0

191

343

2545M–AVR–09/07

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

Reserved

TWAMR

TWCR

–

TWAM0

–

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

–

240

237

239

240

239

237

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

–

AS2

–

TCN2UB

–

OCR2AUB

–

OCR2BUB

–

TCR2AUB

–

TCR2BUB

–

EXCLK

–

160

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8-bit)

159

158

157

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

–

WGM22

CS22

–

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

154

–

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

135

136

135

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

WGM12

–

CS12

–

134

133

131

244

260

–

WGM13

COM1B0

–

CS11

WGM11

AIN1D

ADC1D

CS10

WGM10

AIN0D

ADC0D

COM1B1

–

DIDR0

–

ADC5D

ADC4D

ADC3D

ADC2D

3 4 4

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7D)

(0x7C)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

–

MUX3

–

REFS1

–

REFS0

ACME

ADSC

ADLAR

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

256

259

257

259

(0x7B)

–

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

–

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

–

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

–

159

136

107

71

(0x6F)

–

ICIE1

–

(0x6E)

–

PCINT19

PCINT11

PCINT3

–

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

(0x6C)

–

PCINT14

PCINT13

PCINT12

71

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

71

(0x6A)

–

(0x69)

ISC11

–

ISC10

PCIE2

–

ISC01

PCIE1

–

ISC00

PCIE0

–

68

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

–

(0x66)

Oscillator Calibration Register

38

42

(0x65)

–

(0x64)

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

38

54

12

14

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

I

T

H

–

S

V

N

Z

C

SPH

–

(SP10) ^5.

SP9

SP8

SPL

SP7

SP6

SP5

–

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

PGERS

–

SPMIE

(RWWSB)^5.

–

(RWWSRE)^5.

BLBSET

PGWRT

SELFPRGEN

284

–

PUD

–

IVCE

PORF

SE

–

IVSEL

EXTRF

SM0

–

WDRF

SM2

–

BORF

SM1

–

40

Reserved

ACSR

–

ACBG

–

ACD

–

ACO

–

ACI

–

ACIE

–

ACIC

–

ACIS1

–

ACIS0

–

243

Reserved

SPDR

SPI Data Register

171

170

169

27

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

27

–

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8-bit)

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

COM0A0

–

COM0B1

–

COM0B0

–

WGM02

CS02

CS01

CS00

–

WGM01

PSRASY

WGM00

–

PSRSYNC

140/161

23

(EEPROM Address Register High Byte) ^5.

EEPROM Address Register Low Byte

EEPROM Data Register

23

EEDR

23

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

23

GPIOR0

EIMSK

General Purpose I/O Register 0

27

–

INT1

INT0

69

EIFR

INTF1

INTF0

69

345

2545M–AVR–09/07

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x0 (0x20)

PCIFR

Reserved

TIFR2

–

PCIF2

PCIF1

PCIF0

–

OCF2B

OCF2A

TOV2

159

137

TIFR1

–

ICF1

–

OCF1B

OCF1A

TOV1

TIFR0

–

OCF0B

OCF0A

TOV0

Reserved

PORTD

DDRD

–

PORTD7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

89

88

DDD7

PIND

PIND7

PORTC

DDRC

–

PINC

–

PORTB

DDRB

PORTB7

DDB7

PINB

PINB7

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48/88/168 is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

5. Only valid for ATmega88/168

346

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

31. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

IJMP

Indirect Jump to (Z)

PC ← Z

JMP⁽¹⁾

RCALL

ICALL

CALL⁽¹⁾

RET

k

Direct Jump

PC ← k

3

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

347

2545M–AVR–09/07

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

Out Port

P ← Rr

Push Register on Stack

STACK ← Rr

348

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

Mnemonics

Operands

Description

Operation

Flags

#Clocks

POP

Rd

Pop Register from Stack

Rd ← STACK

None

2

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

Note:

1. These instructions are only available in ATmega168.

349

2545M–AVR–09/07

32. Ordering Information

32.1 ATmega48

Speed (MHz)

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega48V-10AI

32A

ATmega48V-10MI

32M1-A

28P3

32A

ATmega48V-10PI

Industrial

10⁽³⁾

1.8 - 5.5

ATmega48V-10AU⁽²⁾

ATmega48V-10MMU⁽²⁾

ATmega48V-10MU⁽²⁾

ATmega48V-10PU⁽²⁾

(-40°C to 85°C)

28M1

32M1-A

28P3

ATmega48-20AI

32A

ATmega48-20MI

32M1-A

28P3

32A

ATmega48-20PI

Industrial

20⁽³⁾

2.7 - 5.5

ATmega48-20AU⁽²⁾

ATmega48-20MMU⁽²⁾

ATmega48-20MU⁽²⁾

ATmega48-20PU⁽²⁾

(-40°C to 85°C)

28M1

32M1-A

28P3

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

3. See Figure 28-1 on page 306 and Figure 28-2 on page 306.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

350

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

32.2 ATmega88

Speed (MHz)

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega88V-10AI

ATmega88V-10MI

ATmega88V-10PI

ATmega88V-10AU⁽²⁾

ATmega88V-10MU⁽²⁾

ATmega88V-10PU⁽²⁾

32A

32M1-A

28P3

32A

Industrial

10⁽³⁾

1.8 - 5.5

(-40°C to 85°C)

32M1-A

28P3

ATmega88-20AI

ATmega88-20MI

ATmega88-20PI

ATmega88-20AU⁽²⁾

ATmega88-20MU⁽²⁾

ATmega88-20PU⁽²⁾

32A

32M1-A

28P3

32A

Industrial

20⁽³⁾

2.7 - 5.5

(-40°C to 85°C)

32M1-A

28P3

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

3. See Figure 28-1 on page 306 and Figure 28-2 on page 306.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

28P3

351

2545M–AVR–09/07

32.3 ATmega168

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega168V-10AI

ATmega168V-10MI

ATmega168V-10PI

ATmega168V-10AU⁽²⁾

ATmega168V-10MU⁽²⁾

ATmega168V-10PU⁽²⁾

32A

32M1-A

28P3

32A

Industrial

10

20

1.8 - 5.5

(-40°C to 85°C)

32M1-A

28P3

ATmega168-20AI

ATmega168-20MI

ATmega168-20PI

ATmega168-20AU⁽²⁾

ATmega168-20MU⁽²⁾

ATmega168-20PU⁽²⁾

32A

32M1-A

28P3

32A

Industrial

2.7 - 5.5

(-40°C to 85°C)

32M1-A

28P3

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

3. See Figure 28-1 on page 306 and Figure 28-2 on page 306.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32M1-A

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

28P3

352

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

33. Packaging Information

33.1 32A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

C

–

3. Lead coplanarity is 0.10 mm maximum.

L

–

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

B

R

353

2545M–AVR–09/07

33.2 28M1

D

C

1

2

3

Pin 1 ID

E

SIDE VIEW

A1

TOP VIEW

A

y

K

D2

0.45

E2

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

3

R 0.20

MIN

MAX

NOM

NOTE

SYMBOL

A

0.80

0.90

1.00

A1

b

0.00

0.17

0.02

0.22

0.20 REF

4.00

2.40

4.00

2.40

0.45

0.40

–

0.05

0.27

b

C

D

D2

E

3.95

2.35

3.95

2.35

4.05

2.45

4.05

2.45

L

e

E2

e

BOTTOM VIEW

L

0.35

0.00

0.20

0.45

0.08

–

y

K

–

The terminal #1 ID is a Laser-marked Feature.

Note:

9/7/06

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 mm Exposed Pad, Micro Lead Frame Package (MLF)

28M1

A

R

354

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

33.3 32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

(Unit of Measure = mm)

0.08

C

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

355

2545M–AVR–09/07

33.4 28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

28P3

B

R

356

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

34. Errata

34.1 Errata ATmega48

The revision letter in this section refers to the revision of the ATmega48 device.

34.1.1

Rev. D

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-

pare interrupt routine where the compare register is not 0xFF, or if the compare register is

0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.

34.1.2

Rev. C

• Reading EEPROM when system clock frequency is below 900 kHz may not work

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Reading EEPROM when system clock frequency is below 900 kHz may not work

Reading Data from the EEPROM at system clock frequency below 900 kHz may result in

wrong data read.

Problem Fix/Workaround

Avoid using the EEPROM at clock frequency below 900 kHz.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-

pare interrupt routine where the compare register is not 0xFF, or if the compare register is

0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.

34.1.3

Rev. B

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.

357

2545M–AVR–09/07

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-

pare interrupt routine where the compare register is not 0xFF, or if the compare register is

0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.

34.1.4

Rev A

• Part may hang in reset

• Wrong values read after Erase Only operation

• Watchdog Timer Interrupt disabled

• Start-up time with Crystal Oscillator is higher than expected

• High Power Consumption in Power-down with External Clock

• Asynchronous Oscillator does not stop in Power-down

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Part may hang in reset

Some parts may get stuck in a reset state when a reset signal is applied when the internal

reset state-machine is in a specific state. The internal reset state-machine is in this state for

approximately 10 ns immediately before the part wakes up after a reset, and in a 10 ns win-

dow when altering the system clock prescaler. The problem is most often seen during In-

System Programming of the device. There are theoretical possibilities of this happening also

in run-mode. The following three cases can trigger the device to get stuck in a reset-state:

- Two succeeding resets are applied where the second reset occurs in the 10ns window

before the device is out of the reset-state caused by the first reset.

- A reset is applied in a 10 ns window while the system clock prescaler value is updated by

software.

- Leaving SPI-programming mode generates an internal reset signal that can trigger this

case.

The two first cases can occur during normal operating mode, while the last case occurs only

during programming of the device.

Problem Fix/Workaround

The first case can be avoided during run-mode by ensuring that only one reset source is

active. If an external reset push button is used, the reset start-up time should be selected

such that the reset line is fully debounced during the start-up time.

The second case can be avoided by not using the system clock prescaler.

The third case occurs during In-System programming only. It is most frequently seen when

using the internal RC at maximum frequency.

If the device gets stuck in the reset-state, turn power off, then on again to get the device out

of this state.

2. Wrong values read after Erase Only operation

At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only oper-

ation may read as programmed (0x00).

Problem Fix/Workaround

358

ATmega48/88/168

2545M–AVR–09/07

ATmega48/88/168

If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write opera-

tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can

be used as intended. Thus no special considerations are needed as long as the erased loca-

tion is not read before it is programmed.

3. Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog

will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in

interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-

out following an interrupt, the device works correctly.

Problem fix / Workaround

Make sure there is enough time to always service the first timeout event before a new

watchdog timeout occurs. This is done by selecting a long enough time-out period.

4. Start-up time with Crystal Oscillator is higher than expected

The clock counting part of the start-up time is about 2 times higher than expected for all

start-up periods when running on an external Crystal. This applies only when waking up by

reset. Wake-up from power down is not affected. For most settings, the clock counting parts

is a small fraction of the overall start-up time, and thus, the problem can be ignored. The

exception is when using a very low frequency crystal like for instance a 32 kHz clock crystal.

Problem fix / Workaround

No known workaround.

5. High Power Consumption in Power-down with External Clock

The power consumption in power down with an active external clock is about 10 times

higher than when using internal RC or external oscillators.

Problem fix / Workaround

Stop the external clock when the device is in power down.

6. Asynchronous Oscillator does not stop in Power-down

The Asynchronous oscillator does not stop when entering power down mode. This leads to

higher power consumption than expected.

Problem fix / Workaround

Manually disable the asynchronous timer before entering power down.

7. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-

pare interrupt routine where the compare register is not 0xFF, or if the compare register is

0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.

359

2545M–AVR–09/07

34.2 Errata ATmega88

The revision letter in this section refers to the revision of the ATmega88 device.

34.2.1

Rev. D

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is writ-

ten in the cycle before an overflow interrupt occurs, the interrupt may be lost.

The only safe time to write to any of the Timer2 registers in asynchronous mode is in a com-

pare interrupt routine where the compare register is not 0xFF, or if the compare register is

0xFF, after a delay of at least one asynchronous clock cycle from the start of the interrupt.

Problem Fix/Workaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF

before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

34.2.2

34.2.3

Rev. B/C

Rev. A

Not sampled.

• Writing to EEPROM does not work at low Operating Voltages

• Part may hang in reset

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Writing to EEPROM does not work at low operating voltages

Writing to the EEPROM does not work at low voltages.

Problem Fix/Workaround

Do not write the EEPROM at voltages below 4.5 Volts.

This will be corrected in rev. B.

2. Part may hang in reset