ATMEGA644PA_14 [ATMEL]
8-bit Atmel Microcontroller with 16/32/64/128K Bytes;
| 型号： | ATMEGA644PA_14 |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Atmel Microcontroller with 16/32/64/128K Bytes 微控制器 |
| 文件： | 总34页 (文件大小：820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
8-bit Atmel Microcontroller with 16/32/64/128K Bytes
In-System Programmable Flash
DATASHEET SUMMARY
Features
z High-performance, low-power 8-bit Atmel® AVR® Microcontroller
z Advanced RISC architecture
̶
̶
̶
̶
̶
131 powerful Instructions – most single-clock cycle execution
32 × 8 general purpose working registers
Fully static operation
Up to 20MIPS throughput at 20MHz
On-chip 2-cycle multiplier
z High endurance non-volatile memory segments
̶
̶
̶
̶
̶
̶
16/32/64/128KBytes of In-System Self-programmable Flash program memory
512/1K/2K/4KBytes EEPROM
1/2/4/16KBytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
Data retention: 20 years at 85°C/ 100 years at 25°C(1)
Optional Boot Code Section with Independent Lock Bits
z In-System Programming by On-chip Boot Program
z True Read-While-Write Operation
̶
Programming Lock for Software Security
z Atmel QTouch® library support
̶
̶
̶
Capacitive touch buttons, sliders and wheels
QTouch and QMatrix acquisition
Up to 64 sense channels
z JTAG (IEEE std. 1149.1 Compliant) Interface
̶
̶
̶
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG
Interface
z Peripheral Features
̶
̶
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
̶
̶
̶
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel, 10-bit ADC
z Differential mode with selectable gain at 1×, 10× or 200×
Byte-oriented Two-wire Serial Interface
Two Programmable Serial USART
̶
̶
̶
Master/Slave SPI Serial Interface
Atmel-8272FS-AVR--07/2014
̶
̶
̶
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
z Special Microcontroller Features
̶
̶
̶
̶
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
z I/O and Packages
̶
̶
̶
32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF
44-pad DRQFN
– 49-ball VFBGA
z Operating Voltages
1.8 - 5.5V
z Speed Grades
̶
̶
̶
̶
0 - 4MHz @ 1.8 - 5.5V
0 - 10MHz @ 2.7 - 5.5V
0 - 20MHz @ 4.5 - 5.5V
z Power Consumption at 1MHz, 1.8V, 25°C
̶
̶
̶
Active: 0.4mA
Power-down Mode: 0.1µA
Power-save Mode: 0.6µA (Including 32kHz RTC)
Note:
1. See ”Data retention” on page 9 for details.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
1.
Pin configurations
1.1
Pinout - PDIP/TQFP/VQFN/QFN/MLF for
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
Figure 1-1.
Pinout.
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/ICP3/MOSI) PB5
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
VCC
GND
XTAL2
XTAL1
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
(PCINT24/RXD0/T3*) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
TQFP/QFN/MLF
(PCINT13/ICP3/MOSI) PB5
PA4 (ADC4/PCINT4)
(PCINT14/OC3A/MISO) PB6
(PCINT15/OC3B/SCK) PB7
RESET
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVCC
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0/T3*) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
*T3 is only available for ATmega1284/1284P
Note:
The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to
ensure good mechanical stability.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
1.2
Pinout - DRQFN for Atmel ATmega164A/164PA/324A/324PA
Figure 1-2.
DRQFN - pinout.
Top view
Bottom view
A1
A2
A3
A4
A5
A6
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A18
B15
A17
B14
A16
B13
A15
B12
A14
B11
A13
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B1
B2
B3
B4
B5
A13
Table 1-1.
A1
DRQFN - pinout.
PB5
PB6
A7
PD3
PD4
PD5
PD6
PD7
VCC
GND
PC0
PC1
PC2
PC3
A13
B11
A14
B12
A15
B13
A16
B14
A17
B15
A18
PC4
PC5
PC6
PC7
AVCC
GND
AREF
PA7
A19
B16
A20
B17
A21
B18
A22
B19
A23
B20
A24
PA3
B1
B6
PA2
PA1
PA0
VCC
GND
PB0
PB1
PB2
PB3
PB4
A2
PB7
A8
B2
RESET
VCC
B7
A3
A9
B3
GND
XTAL2
XTAL1
PD0
B8
A4
A10
B9
B4
A5
A11
B10
A12
PA6
B5
PD1
PA5
A6
PD2
PA4
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
1.3
Pinout - VFBGA for Atmel ATmega164A/164PA/324A/324PA
Figure 1-3.
VFBGA - pinout.
Top view
Bottom view
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
G
Table 1-2.
BGA - pinout.
1
2
3
4
5
6
7
A
B
C
D
E
F
GND
PB6
PB4
PB5
PB2
PB3
PB7
PD0
PD5
PD6
VCC
GND
PB0
PB1
GND
PD7
PC0
GND
VCC
PA0
PA1
PA4
PC5
PC2
PC1
PA2
PA3
PA6
PA7
PC7
PC4
PC3
GND
PA5
VCC
GND
XTAL1
PD2
RESET
XTAL2
PD1
AREF
GND
AVCC
PC6
PD3
G
GND
PD4
GND
2.
Overview
The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit
microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single
clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing
speed.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
2.1
Block diagram
Figure 2-1.
Block diagram.
PA7..0
PB7..0
VCC
Power
Supervision
POR / BOD &
RESET
RESET
PORT A (8)
PORT B (8)
Watchdog
Timer
GND
Analog
Comparator
A/D
Converter
Watchdog
Oscillator
USART 0
XTAL1
XTAL2
Oscillator
Circuits /
Clock
Internal
Bandgap reference
EEPROM
SPI
Generation
8bit T/C 0
CPU
16bit T/C 1
16bit T/C 1
USART 1
JTAG/OCD
TWI
8bit T/C 2
FLASH
SRAM
16bit T/C 3*
PORT C (8)
PORT D (8)
PD7..0
TOSC2/PC7 TOSC1/PC6
PC5..0
* Only available in ATmega1284/1284P
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features:
16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes
EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real
Time Counter (RTC), three (four for ATmega1284/1284P) flexible Timer/Counters with compare modes and
PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential
input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and
programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves
the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator
and the Asynchronous Timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into
AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™) technology for
unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop
and debug your own touch applications.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash
allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-
While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is supported with a full suite of program and
system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators, and evaluation kits.
2.2
Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA,
ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P
Table 2-1.
Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A,
ATmega644PA, ATmega1284 and ATmega1284P.
Device
Flash
16K
EEPROM
512
512
1K
RAM
1K
Units
ATmega164A
ATmega164PA
ATmega324A
ATmega324PA
ATmega644A
ATmega644PA
ATmega1284
ATmega1284P
16K
1K
32K
2K
32K
1K
2K
bytes
64K
2K
4K
64K
2K
4K
128K
128K
4K
16K
16K
4K
2.3
Pin Descriptions11
2.3.1 VC
Digital supply voltage.
2.3.2 GND
Ground.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
2.3.3 Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins
are tri-stated when a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the Atmel
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 79.
2.3.4 Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 80.
2.3.5 Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the Atmel
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 83.
2.3.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 86.
2.3.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running. The minimum pulse length is given in ”” on page 325. Shorter pulses are not guaranteed to
generate a reset.
2.3.8 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.9 XTAL2
Output from the inverting Oscillator amplifier.
2.3.10 AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.3.11 AREF
This is the analog reference pin for the Analog-to-digital Converter.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
3.
4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
About code examples
This documentation contains simple code examples that briefly show how to use various parts of the device. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Please confirm with the C compiler documentation for more details.
The code examples assume that the part specific header file is included before compilation. For I/O registers
located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with
instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC",
"SBR", and "CBR".
Note:
1.
5.
Data retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85°C or 100 years at 25°C.
6. Capacitive touch sensing
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then
calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch
Library User Guide - also available for download from the Atmel website.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
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Atmel-8272FS-AVR--07/2014
7.
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UDR1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-
-
USART1 I/O Data Register
185
UBRR1H
UBRR1L
Reserved
UCSR1C
UCSR1B
UCSR1A
Reserved
UDR0
-
-
-
-
USART1 Baud Rate Register High Byte
189/202
189/202
USART1 Baud Rate Register Low Byte
-
-
UMSEL10
TXCIE1
TXC1
-
-
-
-
-
-
-
UMSEL11
RXCIE1
RXC1
-
UPM11
UDRIE1
UDRE1
-
UPM10
RXEN1
FE1
USBS1
TXEN1
DOR1
-
UCSZ11/UDORD0(5)
UCSZ10/UCPHA0(5)
UCPOL1
TXB81
MPCM1
-
187/201
186/200
185/200
UCSZ12
UPE1
-
RXB81
U2X1
-
-
USART0 I/O Data Register
185
UBRR0H
UBRR0L
Reserved
UCSR0C
UCSR0B
-
-
-
-
USART0 Baud Rate Register High Byte
189/202
189/202
USART0 Baud Rate Register Low Byte
-
-
-
-
-
-
-
-
UMSEL01
RXCIE0
UMSEL00
TXCIE0
UPM01
UDRIE0
UPM00
RXEN0
USBS0
TXEN0
UCSZ01/UDORD0(5)
UCSZ00/UCPHA0(5)
UCPOL0
TXB80
187/201
186/200
UCSZ02
RXB80
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
10
Atmel-8272FS-AVR--07/2014
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xC0)
(0xBF)
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
UCSR0A
Reserved
Reserved
TWAMR
TWCR
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
185/200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TWAM6
TWINT
TWAM5
TWEA
TWAM4
TWSTA
TWAM3
TWSTO
TWAM2
TWWC
TWAM1
TWEN
TWAM0
-
231
228
230
231
229
228
TWIE
TWDR
two-wire Serial Interface Data Register
TWAR
TWA6
TWS7
TWA5
TWS6
TWA4
TWS5
TWA3
TWS4
TWA2
TWS3
TWA1
TWA0
TWGCE
TWPS0
TWSR
-
TWPS1
TWBR
two-wire Serial Interface Bit Rate Register
Reserved
ASSR
-
-
-
-
-
AS2
-
-
-
-
-
-
EXCLK
-
TCN2UB
-
OCR2AUB
-
OCR2BUB
-
TCR2AUB
-
TCR2BUB
-
155
Reserved
OCR2B
Timer/Counter2 Output Compare Register B
Timer/Counter2 Output Compare Register A
Timer/Counter2 (8 Bit)
155
155
154
153
151
OCR2A
TCNT2
TCCR2B
TCCR2A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR3BH
OCR3BL
OCR3AH
OCR3AL
ICR3H
FOC2A
FOC2B
-
-
WGM22
CS22
CS21
CS20
COM2A1
COM2A0
COM2B1
COM2B0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WGM21
WGM20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter3 - Output Compare Register B High Byte(7)
Timer/Counter3 - Output Compare Register B Low Byte(7)
Timer/Counter3 - Output Compare Register A High Byte(7)
Timer/Counter3 - Output Compare Register A Low Byte(7)
Timer/Counter3 - Input Capture Register High Byte(7)
Timer/Counter3 - Input Capture Register Low Byte(7)
Timer/Counter3 - Counter Register High Byte(7)
132
132
132
132
133
133
132
132
ICR3L
TCNT3H
TCNT3L
Reserved
TCCR3C
TCCR3B
TCCR3A
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
Timer/Counter3 - Counter Register Low Byte(7)
-
-
-
-
-
-
-
-
FOC3A
FOC3B
-
-
-
-
-
-
131
130
128
ICNC3
ICES3
-
WGM33
WGM32
CS32
CS31
CS30
COM3A1
COM3A0
COM3B1
COM3B0
-
-
-
-
-
-
-
-
-
-
WGM31
WGM30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
Timer/Counter1 - Counter Register High Byte
132
132
132
132
133
133
132
132
ICR1L
TCNT1H
TCNT1L
Reserved
TCCR1C
TCCR1B
TCCR1A
DIDR1
Timer/Counter1 - Counter Register Low Byte
-
FOC1A
ICNC1
COM1A1
-
-
FOC1B
ICES1
COM1A0
-
-
-
-
-
-
-
-
-
-
-
-
-
131
130
128
234
253
-
WGM13
WGM12
CS12
CS11
WGM11
AIN1D
ADC1D
-
CS10
WGM10
AIN0D
ADC0D
-
COM1B1
COM1B0
-
-
-
-
-
-
DIDR0
ADC7D
-
ADC6D
-
ADC5D
-
ADC4D
-
ADC3D
-
ADC2D
-
Reserved
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
11
Atmel-8272FS-AVR--07/2014
Address
Name
ADMUX
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7C)
(0x7B)
REFS1
-
REFS0
ACME
ADSC
ADLAR
-
MUX4
-
MUX3
MUX2
ADTS2
ADPS2
MUX1
ADTS1
ADPS1
MUX0
ADTS0
ADPS0
249
233
250
251
251
ADCSRB
ADCSRA
ADCH
-
(0x7A)
ADEN
ADATE
ADIF
ADIE
(0x79)
ADC Data Register High byte
(0x78)
ADCL
ADC Data Register Low byte
(0x77)
Reserved
Reserved
Reserved
Reserved
PCMSK3
Reserved
TIMSK3
TIMSK2
TIMSK1
TIMSK0
PCMSK2
PCMSK1
PCMSK0
Reserved
EICRA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(0x76)
-
-
-
-
-
-
-
-
(0x75)
-
-
-
-
(0x74)
-
-
-
-
-
-
(0x73)
PCINT31
PCINT30
PCINT29
PCINT28
PCINT27
PCINT26
-
PCINT25
-
PCINT24
-
70
(0x72)
-
-
-
-
-
(0x71)
-
-
ICIE3
-
-
OCIE3B
OCIE2B
OCIE1B
OCIE0B
PCINT18
PCINT10
PCINT2
-
OCIE3A
OCIE2A
OCIE1A
OCIE0A
PCINT17
PCINT9
PCINT1
-
TOIE3
TOIE2
TOIE1
TOIE0
PCINT16
PCINT8
PCINT0
-
134
156
134
105
70
(0x70)
-
-
-
-
-
(0x6F)
-
-
ICIE1
-
-
(0x6E)
-
-
-
-
-
(0x6D)
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT11
PCINT3
-
(0x6C)
PCINT15
PCINT14
PCINT13
PCINT12
70
(0x6B)
PCINT7
PCINT6
PCINT5
PCINT4
71
(0x6A)
-
-
-
-
-
-
-
-
-
-
(0x69)
ISC21
ISC20
ISC11
PCIE3
-
ISC10
PCIE2
-
ISC01
PCIE1
-
ISC00
PCIE0
-
67
69
(0x68)
PCICR
-
-
-
-
(0x67)
Reserved
OSCCAL
PRR1
(0x66)
Oscillator Calibration Register
-
40
49
48
(0x65)
-
-
-
-
-
-
--PRTIM3
(0x64)
PRR0
PRTWI
PRTIM2
PRTIM0
PRUSART1
PRTIM1
PRSPI
PRUSART0
PRADC
(0x63)
Reserved
Reserved
CLKPR
WDTCSR
SREG
-
-
-
-
-
-
-
-
(0x62)
-
-
-
-
-
-
-
-
(0x61)
CLKPCE
-
-
-
CLKPS3
CLKPS2
CLKPS1
CLKPS0
40
59
11
12
12
(0x60)
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
I
T
H
S
V
N
Z
C
SPH
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PGERS
-
-
SPMEN
-
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
285
-
-
-
-
-
-
JTD
BODS(6)
BODSE(6)
PUD
-
-
BORF
SM1
-
IVSEL
EXTRF
SM0
-
IVCE
PORF
SE
89/268
58/268
47
-
-
-
-
-
-
-
-
-
JTRF
WDRF
-
-
SM2
Reserved
OCDR
-
-
On-Chip Debug Register
259
250
ACSR
ACD
-
ACBG
-
ACO
-
ACI
-
ACIE
ACIC
-
ACIS1
-
ACIS0
-
Reserved
SPDR
-
SPI 0 Data Register
166
165
164
29
SPSR
SPIF0
SPIE0
WCOL0
SPE0
-
-
-
-
-
SPI2X0
SPR00
SPCR
DORD0
MSTR0
CPOL0
CPHA0
SPR01
GPIOR2
GPIOR1
Reserved
OCR0B
OCR0A
TCNT0
General Purpose I/O Register 2
General Purpose I/O Register 1
-
29
-
-
-
-
-
-
-
Timer/Counter0 Output Compare Register B
Timer/Counter0 Output Compare Register A
Timer/Counter0 (8 Bit)
105
105
105
104
105
157
24
TCCR0B
TCCR0A
GTCCR
EEARH
EEARL
FOC0A
COM0A1
TSM
FOC0B
-
-
WGM02
CS02
CS01
CS00
COM0A0
COM0B1
COM0B0
-
-
-
-
WGM01
PSRASY
WGM00
-
-
-
-
-
-
PSRSYNC
-
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
EEPROM Data Register
24
EEDR
24
EECR
-
-
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
24
GPIOR0
EIMSK
General Purpose I/O Register 0
29
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT2
INT1
INT0
68
EIFR
-
INTF2
INTF1
INTF0
68
PCIFR
PCIF3
PCIF2
PCIF1
PCIF0
69
Reserved
Reserved
-
-
-
-
-
-
-
-
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
12
Atmel-8272FS-AVR--07/2014
Address
Name
TIFR3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
-
-
ICF3
-
-
OCF3B
OCF3A
TOV3
136
156
135
106
TIFR2
-
-
-
-
-
OCF2B
OCF2A
TOV2
TIFR1
-
-
ICF1
-
-
OCF1B
OCF1A
TOV1
TIFR0
-
-
-
-
-
OCF0B
OCF0A
TOV0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTD
DDRD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD7
DDD7
PIND7
PORTC7
DDC7
PINC7
PORTB7
DDB7
PINB7
PORTA7
DDA7
PINA7
PORTD6
DDD6
PIND6
PORTC6
DDC6
PINC6
PORTB6
DDB6
PINB6
PORTA6
DDA6
PINA6
PORTD5
DDD5
PIND5
PORTC5
DDC5
PINC5
PORTB5
DDB5
PINB5
PORTA5
DDA5
PINA5
PORTD4
DDD4
PIND4
PORTC4
DDC4
PINC4
PORTB4
DDB4
PINB4
PORTA4
DDA4
PINA4
PORTD3
DDD3
PIND3
PORTC3
DDC3
PINC3
PORTB3
DDB3
PINB3
PORTA3
DDA3
PINA3
PORTD2
DDD2
PIND2
PORTC2
DDC2
PINC2
PORTB2
DDB2
PINB2
PORTA2
DDA2
PINA2
PORTD1
DDD1
PIND1
PORTC1
DDC1
PINC1
PORTB1
DDB1
PINB1
PORTA1
DDA1
PINA1
PORTD0
DDD0
PIND0
PORTC0
DDC0
PINC0
PORTB0
DDB0
PINB0
PORTA0
DDA0
PINA0
90
90
90
90
90
90
89
89
90
89
89
89
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
PORTA
DDRA
PINA
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate
on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI
instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O
registers as data space using LD and ST instructions, $20 must be added to these addresses.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O
space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. USART in SPI Master Mode.
6. Only available in the ATmega164PA/324PA/644PA/1284P.
7. Only available in the ATmega1284/1284P
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
13
Atmel-8272FS-AVR--07/2014
8.
Instruction set summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
JMP
k
k
Direct Jump
PC ← k
3
RCALL
ICALL
CALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
k
Direct Subroutine Call
Subroutine Return
PC ← k
4
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
k
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
14
Atmel-8272FS-AVR--07/2014
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRVC
BRIE
BRID
k
k
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
1/2
1/2
1/2
Branch if Interrupt Enabled
Branch if Interrupt Disabled
None
None
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
15
Atmel-8272FS-AVR--07/2014
Mnemonics
Operands
Description
Operation
Flags
#Clocks
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
None
Watchdog Reset
Break
1
BREAK
N/A
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
16
Atmel-8272FS-AVR--07/2014
9.
Ordering information
9.1
Atmel ATmega164A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega164A-AU
44A
44A
ATmega164A-AUR(5)
ATmega164A-PU
40P6
44M1
44M1
44MC
44MC
49C2
49C2
ATmega164A-MU
Industrial
20
1.8 - 5.5V
ATmega164A-MUR(5)
ATmega164A-MCH(4)
ATmega164A-MCHR(4)(5)
ATmega164A-CU
(-40oC to 85oC)
ATmega164A-CUR(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
44MC
49C2
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44-lead (2-row Staggered), 5 × 5 × 1.0mm body, 2.60 × 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49-ball, (7 × 7 Array) 0.65mm Pitch, 5 × 5 × 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
17
Atmel-8272FS-AVR--07/2014
9.2
Atmel ATmega164PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega164PA-AU
44A
44A
ATmega164PA-AUR(5)
ATmega164PA-PU
40P6
44M1
44M1
44MC
44MC
49C2
49C2
ATmega164PA-MU
Industrial
20
1.8 - 5.5V
ATmega164PA-MUR(5)
ATmega164PA-MCH(4)
ATmega164PA-MCHR(4)(5)
ATmega164PA-CU
(-40oC to 85oC)
ATmega164PA-CUR(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
44MC
49C2
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44-lead (2-row Staggered), 5 × 5 × 1.0mm body, 2.60 × 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49-ball, (7 × 7 Array) 0.65mm Pitch, 5 × 5 × 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
18
Atmel-8272FS-AVR--07/2014
9.3
Atmel ATmega324A
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega324A-AU
44A
44A
ATmega324A-AUR(5)
ATmega324A-PU
40P6
44M1
44M1
44MC
44MC
49C2
49C2
ATmega324A-MU
Industrial
20
1.8 - 5.5V
ATmega324A-MUR(5)
ATmega324A-MCH(4)
ATmega324A-MCHR(4)(5)
ATmega324A-CU
(-40oC to 85oC)
ATmega324A-CUR(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
44MC
49C2
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44-lead (2-row Staggered), 5 × 5 × 1.0mm body, 2.60 × 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49-ball, (7 × 7 Array) 0.65mm Pitch, 5 × 5 × 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
19
Atmel-8272FS-AVR--07/2014
9.4
Atmel ATmega324PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega324PA-AU
44A
44A
ATmega324PA-AUR(5)
ATmega324PA-PU
40P6
44M1
44M1
44MC
44MC
49C2
49C2
ATmega324PA-MU
Industrial
20
1.8 - 5.5V
ATmega324PA-MUR(5)
ATmega324PA-MCH(4)
ATmega324PA-MCHR(4)(5)
ATmega324PA-CU
(-40oC to 85oC)
ATmega324PA-CUR(5)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. NiPdAu Lead Finish.
5. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
44MC
49C2
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
44-lead (2-row Staggered), 5 × 5 × 1.0mm body, 2.60 × 2.60mm Exposed Pad, Quad Flat No-Lead Package (QFN)
49-ball, (7 × 7 Array) 0.65mm Pitch, 5 × 5 × 1mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
20
Atmel-8272FS-AVR--07/2014
9.5
Atmel ATmega644A
Speed [MHz](3)
Power supply
Ordering code(2)
Package(1)
Operational range
ATmega644A-AU
ATmega644A-AUR(4)
ATmega644A-PU
ATmega644A-MU
ATmega644A-MUR(4)
44A
44A
40P6
44M1
44M1
Industrial
20
1.8 - 5.5V
(-40oC to 85oC)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. Taper & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.5 mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
21
Atmel-8272FS-AVR--07/2014
9.6
Atmel ATmega644PA
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega644PA-AU
ATmega644PA-AUR(4)
ATmega644PA-PU
ATmega644PA-MU
ATmega644PA-MUR(4)
44A
44A
40P6
44M1
44M1
Industrial
20
1.8 - 5.5V
(-40oC to 85oC)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. Taper & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-Lead (VQFN)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
22
Atmel-8272FS-AVR--07/2014
9.7
Atmel ATmega1284
Speed [MHz](3)
Power supply
Ordering code(2)
Package(1)
Operational range
ATmega1284-AU
ATmega1284-AUR(4)
ATmega1284-PU
ATmega1284-MU
ATmega1284-MUR(4)
44A
44A
40P6
44M1
44M1
Industrial
20
1.8 - 5.5V
(-40oC to 85oC)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
23
Atmel-8272FS-AVR--07/2014
9.8
Atmel ATmega1284P
Speed [MHz] (3)
Power supply
Ordering code (2)
Package (1)
Operational range
ATmega1284P-AU
ATmega1284P-AUR(4)
ATmega1284P-PU
ATmega1284P-MU
ATmega1284P-MUR(4)
44A
44A
40P6
44M1
44M1
Industrial
20
1.8 - 5.5V
(-40oC to 85oC)
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering
information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC see ”Speed grades” on page 324.
4. Tape & Reel.
Package Type
44A
44-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6
44M1
40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
24
Atmel-8272FS-AVR--07/2014
10. Packaging information
10.1 44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
–
0.15
1.00
1.05
12.00
10.00
12.00
10.00
0.37
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
(0.17)
0.60
0.20
3. Lead coplanarity is 0.10mm maximum.
L
0.75
e
0.80 TYP
06/02/2014
44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,
0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)
44A
C
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
25
Atmel-8272FS-AVR--07/2014
10.2 40P6
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
eB
A
–
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
–
3.556
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
C
–
–
0.381
2. Dimensions D and E1 do not include mold Flash or Protrusion.
eB
e
17.526
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
2.540 TYP
13/02/2014
40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual
Inline Package (PDIP)
C
40P6
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
26
Atmel-8272FS-AVR--07/2014
10.3 44M1
C
Pin 1 ID
D
SIDE VIEW
y
A1
E
A
TOP VIEW
eT/2
A19
A24
B20
B16
eR
A1
A18
COMMON DIMENSIONS
B1
B15
(Unit of Measure = mm)
b
MIN
0.80
0.00
0.18
MAX
1.00
0.05
0.30
NOM
0.90
0.02
0.23
0.20 REF
5.00
2.60
5.00
2.60
0.70
0.40
–
NOTE
SYMBOL
0.40
R0.20
A
D2
A1
b
eT
C
B5
B11
D
4.90
2.55
4.90
2.55
–
5.10
2.65
5.10
2.65
–
A6
A13
D2
E
B10
A12
B6
A7
E2
eT
eR
K
L
L
L
E2
–
–
BOTTOM VIEW
0.45
0.30
0.00
–
L
0.35
–
0.40
0.075
1. The terminal #1 ID is a Laser-marked Feature.
Note:
y
9/13/07
DRA WING NO .
TITLE
REV .
44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body,
Package Drawing Contact:
packagedrawings@atmel.com
44MC
A
2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
27
Atmel-8272FS-AVR--07/2014
10.4 44MC
C
Pin 1 ID
D
SIDE VIEW
y
A1
E
A
TOP VIEW
eT/2
A19
A24
B20
B16
eR
A1
A18
COMMON DIMENSIONS
B1
B15
(Unit of Measure = mm)
b
MIN
0.80
0.00
0.18
MAX
1.00
0.05
0.30
NOM
0.90
0.02
0.23
0.20 REF
5.00
2.60
5.00
2.60
0.70
0.40
–
NOTE
SYMBOL
0.40
R0.20
A
D2
A1
b
eT
C
B5
B11
D
4.90
2.55
4.90
2.55
–
5.10
2.65
5.10
2.65
–
A6
A13
D2
E
B10
A12
B6
A7
E2
eT
eR
K
L
L
L
E2
–
–
BOTTOM VIEW
0.45
0.30
0.00
–
L
0.35
–
0.40
0.075
1. The terminal #1 ID is a Laser-marked Feature.
Note:
y
9/13/07
DRA WING NO .
TITLE
REV .
44MC, 44QFN (2-Row Staggered), 5 x 5 x 1.00 mm Body,
Package Drawing Contact:
packagedrawings@atmel.com
44MC
A
2.60 x 2.60 mm Exposed Pad, Quad Flat No Lead Package
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
28
Atmel-8272FS-AVR--07/2014
10.5 49C2
E
A1 BALL ID
0.10
D
A1
A2
TOP VIEW
A
SIDE VIEW
E1
G
F
e
E
D
C
B
A
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.00
–
NOM
–
NOTE
SYMBOL
A
1
2
3
4
5
6
7
A1
A2
D
0.20
0.65
4.90
–
A1 BALL CORNER
49 - Ø0.35 0.05
b
e
–
–
5.00
5.10
BOTTOM VIEW
D1
E4.90
E1
b
3.90 BSC
5.10
5.00
0.30
3.90 BSC
0.35
0.40
e
0.65 BSC
3/14/08
GPC
CBD
DRAWING NO.
TITLE
REV.
49C2, 49-ball (7 x 7 array), 0.65mm pitch,
5.0 x 5.0 x 1.0mm, very thin, fine-pitch
ball grid array package (VFBGA)
Package Drawing Contact:
packagedrawings@atmel.com
49C2
A
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
29
Atmel-8272FS-AVR--07/2014
11. Errata
11.1 Errata for ATmega164A
11.1.1 Rev. E
No known Errata.
11.2 Errata for ATmega164PA
11.2.1 Rev. E
No known Errata.
11.3 Errata for ATmega324A
11.3.1 Rev. F
No known Errata.
11.4 Errata for ATmega324PA
11.4.1 Rev. F
No known Errata.
11.5 Errata for ATmega644A
11.5.1 Rev. F
No known Errata.
11.6 Errata for ATmega644PA
11.6.1 Rev. F
No known Errata.
11.7 Errata for ATmega1284
11.7.1 Rev. B
No known Errata.
11.8 Errata for ATmega1284P
11.8.1 Rev. B
No known Errata.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
30
Atmel-8272FS-AVR--07/2014
12. Datasheet revision history
Please note that the referring page numbers in this section are referred to this document. The referring revision
in this section are referring to the document revision.
12.1 Rev. 8272F - 08/2014
Updated text in Section 13.2.8 ”PCMSK1 – Pin Change Mask Register 1” on page 70 to: “If
PCINT15:8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the
1.
corresponding I/O pin.”
Corrected description of PAGEMSB in Table 26-9 on page 281. The device has 64 words in a
page and not 128.
2.
3.
4.
Corrected description of PAGEMSB in Table 26-12 on page 282. PAGESMB is 5 and the device
has 64 words in a page and not 128. The page require six bits and not seven.
Corrected values in Table 26-16 on page 284. PAGEMSB is 6. ZPAGEMSB is Z7 and PCPAGE
is Z15:Z8
5.
6.
Corrected value for PCPAGE in Table 27-7 on page 290. The correct value is PC[14:7]
Updated description in Table 17-2 on page 151 to “Normal port operation, OC2A disconnected.”
Updated Assembly code examples on for ”Watchdog Timer” on page 55. and onwards
“out WDTCSR, r16” changed to “sts WDTCSR, r16”
“in r16, WDTCSR” changed to “lds r16, WDTCSR”
7.
“idi r16, WDTCSR” changed to “lds r16, WDTCSR”
8.
9.
Updated addresses 0x65 and 0x64 in Section 7. ”Register summary” on page 10.
Removed notes 5 and 6 from Table 28-16 on page 328.
Corrected values in Section 8. ”Instruction set summary” on page 14.Changed clock values for
RCALL and ICALL to 2, for Call, Ret and RETI to 4. Also changed values in Section 7.7.1
”Interrupt response time” on page 18.
10.
11.
Updated layout, footer and back page according to template 0205/2014
12.2 Rev. 8272E - 04/2013
Updated Figure 1-1 on page 3 and Figure 2-1 on page 6: T3 and T/C3 only available in
ATmega1284/1284P.
1.
2.
3.
4.
5.
6.
Updated descriptive text on page 6 to indicate that ATmega1284/1284P has four T/Cs.
Updated the Assembly code example for WDT_off (p.56) following the ej# 705736.
Added note in ”16-bit Timer/Counter1 and Timer/Counter3(1) with PWM” on page 107.
Added ”Prescaler Reset” on page 112.
Corrected three typo for Waveform generation mode (WGM) instead of MGM.
Updated Table 23-6 on page 253. ADC Auto Trigger Source Selections, ADTS=0b011, the
statement is Timer/Counter0 Compare Match A.
7.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
31
Atmel-8272FS-AVR--07/2014
Updated Table 27-18 on page 310. Command for 6d Poll for Fuse Write Complete:
0111011_00000000
8.
9.
Updated the table notes of the Table 28-1 on page 318.
Updated ”Register summary” on page 10. Added table note 7: Only available in
ATmega1284/1284P.
10.
12.3 Rev. 8272D - 05/12
1.
2.
Updated ”Power-down mode” on page 44.
Updated ”Overview” on page 67.
Corrected references for Bit 2, Bit 1, and Bit 0 in Section ”UCSRnC – USART MSPIM Control
and Status Register n C” on page 201.
3.
4.
5.
6.
Several small corrections throughout the whole document made according to the template
Notes in Table 27-17 on page 304 have been corrected
Note (1) in Table 28-3 on page 320 is added
12.4 Rev. 8272C - 06/11
1.
Updated ”Atmel ATmega1284P DC characteristics” on page 323.
12.5 Rev. 8272B - 05/11
1.
2.
Added Atmel QTouch Library Support and QTouch Sensing Capability Features.
Replaced the Figure 1-1 on page 3 by an updated “Pinout.” that includes Timer/Counter3.
Replaced the Figure 7-1 on page 10 by an updated “Block diagram of the AVR architecture.” that
includes Timer/Counter3.
3.
4.
5.
6.
Added ”RAMPZ – Extended Z-pointer Register for ELPM/SPM(1)” on page 15.
Added ”PRR1 – Power Reduction Register 1” on page 49.
Renamed PRR to ”PRR0 – Power Reduction Register 0” on page 48.
7.
Updated ”PCIFR – Pin Change Interrupt Flag Register” on page 69. PCICR replaces EIMSR in
the PCIF3, PCIF2, PCIF1 and PCIF0 bit description.
8.
Updated ”PCMSK3 – Pin Change Mask Register 3” on page 70. PCIE3 replaces PCIE2 in the bit
description.
9.
Updated ”Alternate Functions of Port B” on page 80 to include Timer/Counter3
Updated ”Alternate Functions of Port D” on page 86 to include Timer/Counter3
Added ”TCNT3H and TCNT3L –Timer/Counter3” on page 132
10.
11.
12.
13.
14.
15.
Added ”OCR3AH and OCR3AL – Output Compare Register3 A” on page 133
Added ”OCR3BH and OCR3BL – Output Compare Register3 B” on page 133
Added ”TIMSK3 – Timer/Counter3 Interrupt Mask Register” on page 134
Updated All “SPI – Serial Peripheral Interface” “Register description” to reflect ATmega1284 and
ATmega1284P.
16.
Updated ”Addressing the Flash During Self-Programming” on page 274 to include RAMPZ
register.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
32
Atmel-8272FS-AVR--07/2014
17.
18.
19.
20.
21.
Updated Table 27-16 on page 303. tWD_EEPROM is 3.6ms instead of 9ms.
BODS and BODSE bits denoted as R/W
Description of external pin modes below table 16-9 removed.
Updated ”Register summary” on page 10 to include Timer/Counter3.
Updated the datasheet with Atmel new style guide.
12.6 Rev. 8272A - 01/10
1.
2.
Initial revision (Based on the ATmega164PA/324PA/644PA/1284P datasheet 8252G-AVR-11/09
and on the ATmega644 datasheet 2593N-AVR-09/09).
Changes done:
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
̶
Non-picoPower devices added: ATmega164A/324A/644A/1284
Updated Table 2-1 on page 7
Updated Table 10-1 on page 42
Updated ”Sleep Modes” on page 42 and ”BOD disable(1)” on page 43
Updated ”Register description” on page 67
Updated ”USART” on page 167 and ”USART in SPI mode” on page 194
Updated ”Signature Bytes” on page 290 and ”Page Size” on page 290
Added ”DC Characteristics” on page 318 for non-picoPower devices.
Added ”Atmel ATmega164A typical characteristics” on page 333
Added ”Atmel ATmega324A typical characteristics” on page 386
Added ”Atmel ATmega644A typical characteristics” on page 438
Added ”ATmega1284 typical characteristics” on page 490
Added ”Ordering information” on page 17 for non-picoPower devices
Added ”Errata for ATmega164A” on page 30
Added ”Errata for ATmega324A” on page 30
Added ”Errata for ATmega644PA” on page 30
Added ”Errata for ATmega1284” on page 30
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET SUMMARY]
33
Atmel-8272FS-AVR--07/2014
X
X X X X
X
Atmel Corporation
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T: (+1)(408) 441.0311
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|
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© 2014 Atmel Corporation. / Rev.: Atmel-8272FS-AVR-ATmega164A/PA/324A/PA/644A/PA/1284/P-Datasheet Summary_07/2014.
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