ATMEGA644P_技术文档

Features

• High-performance, Low-power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 16/32/64K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

8-bit

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 16/32/64K

Bytes In-System

Programmable

Flash

– 512B/1K/2K Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 1/2/4K Bytes Internal SRAM

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

ATmega164P/V

ATmega324P/V

ATmega644P/V

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Advance

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

Information

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

Summary

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 1.8 - 5.5V for ATmega164P/324P/644PV

– 2.7 - 5.5V for ATmega164P/324P/644P

• Speed Grades

– ATmega164P/324P/644PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V

– ATmega164P/324P/644P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644P

– Active: 338/398/TBD µA

– Power-down Mode:0.035 /0.027/TBD µA

– Power-save Mode:0.5 /0.5/TBD µA (Including 32 kHz RTC)

8011DS–AVR–02/07

1. Pin Configurations

Figure 1-1. Pinout ATmega164P/324P/644P

PDIP

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5

(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

VCC

GND

XTAL2

XTAL1

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

PC3 (TMS/PCINT19)

PC2 (TCK/PCINT18)

PC1 (SDA/PCINT17)

PC0 (SCL/PCINT16)

PD7 (OC2A/PCINT31)

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

TQFP/QFN/MLF

(PCINT13/MOSI) PB5

PA4 (ADC4/PCINT4)

(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

Note:

The large center pad underneath the QFN/MLF package should be soldered to ground on the

board to ensure good mechanical stability.

2

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

1.1

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

3

8011DS–AVR–02/07

2. Overview

The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys-

tem designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

PA7..0

PB7..0

VCC

Power

Supervision

POR / BOD &

RESET

PORT A (8)

PORT B (8)

RESET

Watchdog

Timer

GND

Analog

Comparator

A/D

Converter

Watchdog

Oscillator

USART 0

XTAL1

Oscillator

Circuits /

Clock

Internal

Bandgap reference

EEPROM

SPI

Generation

XTAL2

8bit T/C 0

CPU

JTAG/OCD

TWI

16bit T/C 1

8bit T/C 2

USART 1

FLASH

SRAM

PORT C (8)

PORT D (8)

PD7..0

TOSC2/PC7 TOSC1/PC6

PC5..0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

4

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K

bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time

Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte

oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage

with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial

port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip

Debug system and programming and six software selectable power saving modes. The Idle

mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system

to continue functioning. The Power-down mode saves the register contents but freezes the

Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-

save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base

while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all

I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC

conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the

device is sleeping. This allows very fast start-up combined with low power consumption. In

Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible

and cost effective solution to many embedded control applications.

The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel-

opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit

emulators, and evaluation kits.

2.2

Comparison Between ATmega164P, ATmega324P and ATmega644P

Table 2-1.

Device

Differences between ATmega164P and ATmega644P

Flash

EEPROM

512 Bytes

1 Kbyte

RAM

ATmega164P

ATmega324P

ATmega644P

16 Kbyte

32 Kbyte

64 Kbyte

1 Kbyte

2 Kbyte

4 Kbyte

2 Kbyte

2.3

Pin Descriptions

2.3.1

VCC

Digital supply voltage.

Ground.

2.3.2

GND

5

8011DS–AVR–02/07

2.3.3

Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source current if

the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega164P/324P/644P as

listed on page 79.

2.3.4

2.3.5

2.3.6

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega164P/324P/644P as

listed on page 81.

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega164P/324P/644P as listed on page 84.

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega164P/324P/644P as

listed on page 86.

2.3.7

2.3.8

RESET

XTAL1

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page

50. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

6

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

2.3.9

XTAL2

AVCC

Output from the inverting Oscillator amplifier.

2.3.10

AVCC is the supply voltage pin for Port F and the Analog-to-digital Converter. It should be exter-

nally connected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected

to V_CCthrough a low-pass filter.

2.3.11

AREF

This is the analog reference pin for the Analog-to-digital Converter.

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for

download on http://www.atmel.com/avr.

7

8011DS–AVR–02/07

4. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

Reserved

UDR1

-

USART1 I/O Data Register

-

184

UBRR1H

UBRR1L

Reserved

UCSR1C

UCSR1B

UCSR1A

Reserved

UDR0

-

USART1 Baud Rate Register High Byte

189/201

USART1 Baud Rate Register Low Byte

-

UMSEL10

TXCIE1

TXC1

-

UMSEL11

RXCIE1

RXC1

-

UPM11

UDRIE1

UDRE1

-

UPM10

RXEN1

FE1

USBS1

TXEN1

DOR1

-

UCSZ11

UCSZ12

UPE1

-

UCSZ10

RXB81

U2X1

-

UCPOL1

TXB81

MPCM1

-

187/200

186/200

185/199

-

USART0 I/O Data Register

-

184

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

UCSR0A

-

USART0 Baud Rate Register High Byte

189/201

USART0 Baud Rate Register Low Byte

-

UMSEL01

RXCIE0

RXC0

UMSEL00

TXCIE0

TXC0

UPM01

UDRIE0

UDRE0

UPM00

RXEN0

FE0

USBS0

TXEN0

DOR0

UCSZ01

UCSZ02

UPE0

UCSZ00

RXB80

U2X0

UCPOL0

TXB80

MPCM0

187/200

186/200

185/199

8

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

Reserved

TWAMR

TWCR

-

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWAM0

-

232

228

230

232

230

228

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

-

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

-

AS2

-

EXCLK

-

TCN2UB

-

OCR2AUB

-

OCR2BUB

-

TCR2AUB

-

TCR2BUB

-

153

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8 Bit)

152

151

148

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

-

WGM22

CS22

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

-

WGM21

WGM20

-

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

134

135

134

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

-

FOC1A

ICNC1

COM1A1

-

FOC1B

ICES1

COM1A0

-

133

132

130

235

255

-

WGM13

COM1B0

-

WGM12

CS12

CS11

WGM11

AIN1D

ADC1D

CS10

WGM10

AIN0D

ADC0D

COM1B1

-

DIDR0

ADC7D

ADC6D

ADC5D

ADC4D

ADC3D

ADC2D

9

8011DS–AVR–02/07

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7D)

(0x7C)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

-

REFS1

-

REFS0

ACME

ADSC

ADLAR

-

MUX4

-

MUX3

-

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

251

233

252

254

(0x7B)

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

PCMSK3

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

-

(0x76)

-

(0x75)

-

(0x74)

-

(0x73)

PCINT31

PCINT30

PCINT29

PCINT28

PCINT27

PCINT26

-

PCINT25

-

PCINT24

-

69

(0x72)

-

(0x71)

-

(0x70)

-

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

-

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

-

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

-

155

135

107

69

(0x6F)

-

ICIE1

-

(0x6E)

-

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT11

PCINT3

-

(0x6C)

PCINT15

PCINT14

PCINT13

PCINT12

69

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

70

(0x6A)

-

(0x69)

ISC21

ISC20

ISC11

PCIE3

-

ISC10

PCIE2

-

ISC01

PCIE1

-

ISC00

PCIE0

-

66

68

(0x68)

PCICR

-

(0x67)

Reserved

OSCCAL

Reserved

PRR

(0x66)

Oscillator Calibration Register

39

47

(0x65)

-

(0x64)

PRTWI

PRTIM2

PRTIM0

PRUSART1

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

WDTCSR

SREG

-

(0x62)

-

(0x61)

CLKPCE

-

CLKPS3

CLKPS2

CLKPS1

CLKPS0

39

58

12

(0x60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

I

T

H

S

V

N

Z

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

RAMPZ

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

-

RAMPZ0

15

-

PGERS

-

SPMEN

-

SPMIE

RWWSB

SIGRD

RWWSRE

BLBSET

PGWRT

277

-

JTD

BODS

BODSE

PUD

-

WDRF

SM2

-

BORF

SM1

-

IVSEL

EXTRF

SM0

-

IVCE

PORF

SE

78/265

53/266

46

-

JTRF

-

Reserved

OCDR

-

On-Chip Debug Register

261

252

ACSR

ACD

-

ACBG

-

ACO

-

ACI

-

ACIE

-

ACIC

-

ACIS1

-

ACIS0

-

Reserved

SPDR

SPI 0 Data Register

165

163

27

SPSR

SPIF0

SPIE0

WCOL0

SPE0

-

SPI2X0

SPR00

SPCR

DORD0

MSTR0

CPOL0

CPHA0

SPR01

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

27

-

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8 Bit)

107

106

107

157

22

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

-

WGM02

CS02

CS01

WGM01

PSR2

CS00

COM0A0

COM0B1

COM0B0

-

WGM00

-

PSR54310

-

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

EEPROM Data Register

22

EEDR

22

EECR

-

EEPM1

EEPM0

EERIE

EEMWE

EEWE

EERE

23

GPIOR0

EIMSK

General Purpose I/O Register 0

28

-

INT2

INT1

INT0

67

EIFR

INTF2

INTF1

INTF0

67

10

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

Address

Name

PCIFR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

-

PCIF3

PCIF2

PCIF1

PCIF0

68

Reserved

TIFR2

-

OCF2b

OCF2A

TOV2

156

136

108

TIFR1

-

ICF1

-

OCF1B

OCF1A

TOV1

TIFR0

-

OCF0B

OCF0A

TOV0

Reserved

PORTD

DDRD

-

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

91

90

91

90

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-

ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega164P/324P/644P is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions

can be used.

11

8011DS–AVR–02/07

5. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

4

PC ← Z

4

k

Direct Subroutine Call

Subroutine Return

PC ← k

5

PC ← STACK

5

RETI

Interrupt Return

PC ← STACK

5

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

k

12

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Enabled

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

LD

LDD

LD

Rd ← (Z)

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

LD

LDD

LDS

ST

Rd ← (k)

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

ELPM

(k) ← Rr

Load Program Memory

Load Program Memory and Post-Inc

Extended Load Program Memory

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

R0 ← (RAMPZ:Z)

Rd ← (Z)

Rd, Z

Rd, Z+

Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1

13

8011DS–AVR–02/07

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SPM

Store Program Memory

In Port

(Z) ← R1:R0

Rd ← P

None

-

IN

Rd, P

None

1

2

OUT

PUSH

POP

P, Rr

Rr

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

14

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

6. Ordering Information

6.1

ATmega164P

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega164PV-10AU⁽²⁾

ATmega164PV-10PU⁽²⁾

ATmega164PV-10MU⁽²⁾

ATmega164P-20AU⁽²⁾

ATmega164P-20PU⁽²⁾

ATmega164P-20MU⁽²⁾

44A

Industrial

10

20

1.8 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

44A

Industrial

2.7 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CCsee ”Maximum speed vs. V_CC” on page 323.

Package Type

44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

44M1

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

15

8011DS–AVR–02/07

6.2

ATmega324P

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega324PV-10AU⁽²⁾

ATmega324PV-10PU⁽²⁾

ATmega324PV-10MU⁽²⁾

ATmega324P-20AU⁽²⁾

ATmega324P-20PU⁽²⁾

ATmega324P-20MU⁽²⁾

44A

Industrial

10

20

1.8 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

44A

Industrial

2.7 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CCsee ”Maximum speed vs. V_CC” on page 323.

Package Type

44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

44M1

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

16

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

6.3

ATmega644P

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package⁽¹⁾

Operational Range

ATmega644PV-10AU⁽²⁾

ATmega644PV-10PU⁽²⁾

ATmega644PV-10MU⁽²⁾

ATmega644P-20AU⁽²⁾

ATmega644P-20PU⁽²⁾

ATmega644P-20MU⁽²⁾

44A

Industrial

10

20

1.8 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

44A

Industrial

2.7 - 5.5V

40P6

44M1

(-40^oC to 85^oC)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CCsee ”Maximum speed vs. V_CC” on page 323.

Package Type

44A

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6

44M1

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

17

8011DS–AVR–02/07

7. Packaging Information

7.1

44A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

B

R

18

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

7.2

40P6

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.826

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.381

52.070

15.240

13.462

0.356

1.041

3.048

0.203

15.494

–

52.578 Note 2

15.875

E

–

E1

B

–

13.970 Note 2

0.559

–

B1

L

–

1.651

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

–

3.556

C

–

0.381

eB

e

17.526

2.540 TYP

09/28/01

DRAWING NO. REV.

40P6

TITLE

2325 Orchard Parkway

San Jose, CA 95131

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

19

8011DS–AVR–02/07

7.3

44M1

D

Marked Pin# 1 ID

E

SEATING PLANE

A1

A3

TOP VIEW

A

K

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

NOM

0.90

NOTE

SYMBOL

E2

Option B

Option C

Pin #1

A

Chamfer

(C 0.30)

A1

A3

b

0.02

0.25 REF

0.23

0.18

6.90

5.00

6.90

0.30

7.10

5.40

7.10

D

7.00

K

Pin #1

Notch

(0.20 R)

D2

E

5.20

e

b

7.00

BOTTOM VIEW

E2

e

5.00

5.20

0.50 BSC

0.64

5.40

L

0.59

0.20

0.69

0.41

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

K

0.26

5/27/06

DRAWING NO. REV.

44M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.20 mm Exposed Pad, Micro Lead Frame Package (MLF)

G

R

20

ATmega164P/324P/644P

8011DS–AVR–02/07

ATmega164P/324P/644P

8. Errata

8.1

8.2

8.3

ATmega164P Rev. A

No known Errata.

ATmega324P Rev. A

No known Errata.

ATmega644P Rev. A

No known Errata.

21

8011DS–AVR–02/07

9. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

9.1

Rev. 8011D - 02/07

1.

Updated ”Pinout ATmega164P/324P/644P” on page 2.

Updated ”Power-down Mode” on page 44.

Updated note in Table 11-1 on page 67.

2.

3.

4.

5.

6.

7.

8.

9.

Updated Table 23-1 on page 270.

Updated ”Boot Size Configuration(1)” on page 287.

Updated V_OLlimits in ”DC Characteristics” on page 323.

Updated note 3 and 4 in ”DC Characteristics” on page 323.

Added note to ”ATmega164P DC Characteristics” on page 325.

Added note to ”ATmega324P DC Characteristics” on page 325.

10. Updated Figure 27-13 on page 343 and Figure 27-60 on page 368.

9.2

9.3

Rev. 8011C - 10/06

1.

Updated ”DC Characteristics” on page 323.

Rev. 8011B - 09/06

1.

9.4

Rev. 8011A - 08/06

1.

Initial revision.

22

ATmega164P/324P/644P

8011DS–AVR–02/07

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

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Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

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Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

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38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

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Japan

Tel: (81) 3-3523-3551

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Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

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ers.

8011DS–AVR–02/07


型号：	ATMEGA644P
厂家：	ATMEL
描述：	8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash 8位微控制器与16/32 / 64K字节的系统内可编程闪存闪存微控制器
文件：	总23页 (文件大小：332K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA644P [ATMEL]

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