ATMEGA649_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles

32K bytes (ATmega329/ATmega3290)

8-bit

64K bytes (ATmega649/ATmega6490)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– EEPROM, Endurance: 100,000 Write/Erase Cycles

1K bytes (ATmega329/ATmega3290)

Microcontroller

with In-System

Programmable

Flash

2K bytes (ATmega649/ATmega6490)

– Internal SRAM

2K bytes (ATmega329/ATmega3290)

4K bytes (ATmega649/ATmega6490)

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

ATmega329/V

ATmega3290/V

ATmega649/V

ATmega6490/V

– 4 x 25 Segment LCD Driver (ATmega329/ATmega649)

– 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490)

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Universal Serial Interface with Start Condition Detector

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Preliminary

Summary

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 53/68 Programmable I/O Lines

– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V

– ATmega329/3290/649/6490:

0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

2552HS–AVR–11/06

Features (Continued)

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 350 µA

32 kHz, 1.8V: 20 µA (including Oscillator)

32 kHz, 1.8V: 40 µA (including Oscillator and LCD)

– Power-down Mode:

100 nA at 1.8V

Pin Configurations

Figure 1. Pinout ATmega3290/6490

TQFP

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

2

INDEX CORNER

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

GND

DNC

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

DNC

ATmega3290/6490

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

2

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Figure 2. Pinout ATmega329/649

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

1

2

3

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

48

47

46

INDEX CORNER

(XCK/AIN0/PCINT2) PE2

4

45

(AIN1/PCINT3) PE3

5

6

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

PC5 (SEG7)

44

43

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

7

8

9

42

41

40

ATmega329/649

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0 10

(SCK/PCINT9) PB1 11

(MOSI/PCINT10) PB2 12

(MISO/PCINT11) PB3 13

39 PC4 (SEG8)

PC3 (SEG9)

PC2 (SEG10)

PC1 (SEG11)

PC0 (SEG12)

38

37

36

(OC0A/PCINT12) PB4 14

(OC1A/PCINT13) PB5 15

(OC1B/PCINT14) PB6 16

35

34

33

PG1 (SEG13)

PG0 (SEG14)

Note:

The large center pad underneath the QFN/MLF packages is made of metal and internally

connected to GND. It should be soldered or glued to the board to ensure good mechani-

cal stability. If the center pad is left unconnected, the package might loosen from the

board.

Disclaimer

Typical values contained in this datasheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

3

2552HS–AVR–11/06

Overview

The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architec-

ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs

approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure 3. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

GND

VCC

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC

AGND

AREF

ADC

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

JTAG TAP

TIMING AND

CONTROL

LCD

CONTROLLER/

DRIVER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

AVR CPU

UNIVERSAL

SERIAL INTERFACE

SPI

USART

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

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ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-

System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM,

2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working regis-

ters, a JTAG interface for Boundary-scan, On-chip Debugging support and

programming, a complete On-chip LCD controller with internal contrast control, three

flexible Timer/Counters with compare modes, internal and external interrupts, a serial

programmable USART, Universal Serial Interface with Start Condition Detector, an 8-

channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI

serial port, and five software selectable power saving modes. The Idle mode stops the

CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to con-

tinue functioning. The Power-down mode saves the register contents but freezes the

Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In

Power-save mode, the asynchronous timer and the LCD controller continues to run,

allowing the user to maintain a timer base and operate the LCD display while the rest of

the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O mod-

ules except asynchronous timer, LCD controller and ADC, to minimize switching noise

during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running

while the rest of the device is sleeping. This allows very fast start-up combined with low-

power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be

reprogrammed In-System through an SPI serial interface, by a conventional non-volatile

memory programmer, or by an On-chip Boot program running on the AVR core. The

Boot program can use any interface to download the application program in the Applica-

tion Flash memory. Software in the Boot Flash section will continue to run while the

Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic

chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications.

The ATmega329/3290/649/6490 AVR is supported with a full suite of program and sys-

tem development tools including: C Compilers, Macro Assemblers, Program

Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

5

2552HS–AVR–11/06

Comparison between

ATmega329,

ATmega3290,

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory

sizes, pin count and pinout. Table 1 on page 6 summarizes the different configurations

for the four devices.

ATmega649 and

ATmega6490

Table 1. Configuration Summary

LCD

Segments

General Purpose

I/O Pins

Device

Flash

EEPROM

1K bytes

2K bytes

RAM

ATmega329

32K bytes

2K bytes

4K bytes

4 x 25

4 x 40

4 x 25

4 x 40

54

69

54

69

ATmega3290 32K bytes

ATmega649 64K bytes

ATmega6490 64K bytes

Pin Descriptions

V_CC

The following section describes the I/O-pin special functions.

Digital supply voltage.

Ground.

GND

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the

ATmega329/3290/649/6490 as listed on page 67.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the

ATmega329/3290/649/6490 as listed on page 68.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega329/3290/649/6490

as listed on page 71.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

6

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Port D also serves the functions of various special features of the

ATmega329/3290/649/6490 as listed on page 73.

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port E pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the

ATmega329/3290/649/6490 as listed on page 75.

Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port F output

buffers have symmetrical drive characteristics with both high sink and source capability.

As inputs, Port F pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port F pins are tri-stated when a reset condition becomes

active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis-

tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset

occurs.

Port F also serves the functions of the JTAG interface.

Port G (PG5..PG0)

Port H (PH7..PH0)

Port J (PJ6..PJ0)

RESET

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port G output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port G pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the

ATmega329/3290/649/6490 as listed on page 75.

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port H output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port H pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290/6490 as

listed on page 75.

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port J output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port J pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3290/6490 as

listed on page 75.

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

16 on page 41. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

7

2552HS–AVR–11/06

XTAL2

AVCC

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally

connected to V_CC, even if the ADC is not used. If the ADC is used, it should be con-

nected to V_CCthrough a low-pass filter.

AREF

This is the analog reference pin for the A/D Converter.

LCDCAP

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as

shown in Figure 99. This capacitor acts as a reservoir for LCD power (V_LCD). A large

capacitance reduces ripple on V_LCDbut increases the time until V_LCDreaches its target

value.

Resources

A comprehensive set of development tools, application notes and datasheets are avail-

able for download on http://www.atmel.com/avr.

8

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Register Summary

Note:

Registers with bold type only available in ATmega3290/6490.

Address

Name

LCDDR19

LCDDR18

LCDDR17

LCDDR16

LCDDR15

LCDDR14

LCDDR13

LCDDR12

LCDDR11

LCDDR10

LCDDR09

LCDDR08

LCDDR07

LCDDR06

LCDDR05

LCDDR04

LCDDR03

LCDDR02

LCDDR01

LCDDR00

Reserved

LCDCCR

LCDFRR

LCDCRB

LCDCRA

Reserved

PORTJ

Bit 7

SEG339

Bit 6

SEG338

Bit 5

SEG337

Bit 4

SEG336

Bit 3

SEG335

Bit 2

SEG334

Bit 1

SEG333

Bit 0

SEG332

Page

234

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

SEG331

SEG330

SEG329

SEG328

SEG327

SEG326

SEG325

SEG324

SEG323

SEG322

SEG321

SEG320

SEG319

SEG318

SEG317

SEG316

SEG315

SEG314

SEG313

SEG312

SEG311

SEG310

SEG309

SEG308

SEG307

SEG306

SEG305

SEG304

SEG303

SEG302

SEG301

SEG300

SEG239

SEG238

SEG237

SEG236

SEG235

SEG234

SEG233

SEG232

SEG231

SEG230

SEG229

SEG228

SEG227

SEG226

SEG225

SEG224

SEG223

SEG222

SEG221

SEG220

SEG219

SEG218

SEG217

SEG216

SEG215

SEG214

SEG213

SEG212

SEG211

SEG210

SEG209

SEG208

SEG207

SEG206

SEG205

SEG204

SEG203

SEG202

SEG201

SEG200

SEG139

SEG138

SEG137

SEG136

SEG135

SEG134

SEG133

SEG132

SEG131

SEG130

SEG129

SEG128

SEG127

SEG126

SEG125

SEG124

SEG123

SEG122

SEG121

SEG120

SEG119

SEG118

SEG117

SEG116

SEG115

SEG114

SEG113

SEG112

SEG111

SEG110

SEG109

SEG108

SEG107

SEG106

SEG105

SEG104

SEG103

SEG102

SEG101

SEG100

SEG039

SEG038

SEG037

SEG036

SEG035

SEG034

SEG033

SEG032

SEG031

SEG030

SEG029

SEG028

SEG027

SEG026

SEG025

SEG024

SEG023

SEG022

SEG021

SEG020

SEG019

SEG018

SEG017

SEG016

SEG015

SEG014

SEG013

SEG012

SEG011

SEG010

SEG009

SEG008

SEG007

SEG006

SEG005

SEG004

SEG003

SEG002

SEG001

SEG000

-

LCDDC2

LCDDC1

LCDDC0

-

LCDCC3

LCDCC2

LCDCC1

LCDCC0

233

231

229

-

LCDPS2

LCDPS1

LCDPS0

-

LCDCD2

LCDCD1

LCDCD0

LCDCS

LCD2B

LCDMUX1

LCDMUX0

LCDPM3

LCDPM2

LCDPM1

LCDPM0

LCDEN

LCDAB

-

LCDIF

LCDIE

-

LCDBL

-

PORTJ6

PORTJ5

PORTJ4

PORTJ3

PORTJ2

PORTJ1

PORTJ0

88

DDRJ

-

DDJ6

DDJ5

DDJ4

DDJ3

DDJ2

DDJ1

DDJ0

PINJ

-

PINJ6

PINJ5

PINJ4

PINJ3

PINJ2

PINJ1

PINJ0

PORTH

PORTH7

PORTH6

PORTH5

PORTH4

PORTH3

PORTH2

PORTH1

PORTH0

DDRH

DDH7

DDH6

DDH5

DDH4

DDH3

DDH2

DDH1

DDH0

PINH

PINH7

PINH6

PINH5

PINH4

PINH3

PINH2

PINH1

PINH0

Reserved

UDR0

-

USART0 Data Register

179

182

UBRR0H

UBRR0L

Reserved

USART0 Baud Rate Register High

USART0 Baud Rate Register Low

-

9

2552HS–AVR–11/06

Address

Name

UCSR0C

UCSR0B

UCSR0A

Reserved

USIDR

Bit 7

-

Bit 6

UMSEL0

Bit 5

UPM01

Bit 4

UPM00

Bit 3

USBS0

Bit 2

UCSZ01

Bit 1

UCSZ00

Bit 0

UCPOL0

Page

181

(0xC2)

(0xC1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

180

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

179

-

USI Data Register

194

195

196

USISR

USISIF

USIOIF

USIPF

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USICR

USISIE

USIOIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

Reserved

ASSR

-

EXCLK

AS2

TCN2UB

OCR2UB

TCR2UB

147

Reserved

OCR2A

-

Timer/Counter 2 Output Compare Register A

Timer/Counter2

146

TCNT2

Reserved

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

-

FOC2A

WGM20

COM2A1

COM2A0

WGM21

CS22

CS21

CS20

144

-

Timer/Counter1 Output Compare Register B High

Timer/Counter1 Output Compare Register B Low

Timer/Counter1 Output Compare Register A High

Timer/Counter1 Output Compare Register A Low

Timer/Counter1 Input Capture Register High

Timer/Counter1 Input Capture Register Low

Timer/Counter1 High

130

ICR1L

TCNT1H

TCNT1L

Timer/Counter1 Low

10

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Address

Name

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Bit 7

Bit 6

-

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

-

Bit 1

-

Bit 0

-

Page

-

FOC1A

ICNC1

COM1A1

-

(0x83)

(0x82)

FOC1B

ICES1

COM1A0

-

CS12

-

129

128

126

201

218

-

WGM13

WGM12

CS11

WGM11

AIN1D

ADC1D

-

CS10

WGM10

AIN0D

ADC0D

-

(0x81)

COM1B1

COM1B0

-

(0x80)

-

ADC4D

-

ADC3D

-

(0x7F)

DIDR0

ADC7D

-

ADC6D

-

ADC5D

-

ADC2D

-

(0x7E)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

(0x7D)

REFS1

-

REFS0

ACME

ADSC

ADLAR

-

MUX4

-

MUX3

-

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

214

199/217

216

(0x7C)

(0x7B)

ADEN

ADATE

ADIF

ADIE

(0x7A)

ADC Data Register High

ADC Data Register Low

217

(0x79)

ADCL

217

(0x78)

Reserved

PCMSK3

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

-

(0x77)

-

(0x76)

-

(0x75)

-

(0x74)

-

PCINT30

PCINT29

PCINT28

PCINT27

PCINT26

PCINT25

PCINT24

57

(0x73)

-

(0x72)

-

(0x71)

-

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

-

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

-

149

131

102

58

(0x70)

-

ICIE1

-

OCIE1B

(0x6F)

-

(0x6E)

PCINT23

PCINT22

PCINT21

PCINT20

PCINT19

PCINT18

(0x6D)

PCINT15

PCINT14

PCINT13

PCINT12

PCINT11

PCINT10

58

(0x6C)

PCINT7

PCINT6

PCINT5

PCINT4

PCINT3

PCINT2

58

(0x6B)

-

(0x6A)

ISC01

-

ISC00

-

55

(0x69)

Reserved

OSCCAL

Reserved

PRR

(0x68)

-

(0x67)

Oscillator Calibration Register [CAL7..0]

29

38

(0x66)

-

(0x65)

-

PRLCD

PRTIM1

PRSPI

PSUSART0

PRADC

(0x64)

Reserved

CLKPR

-

(0x63)

-

CLKPS3

WDE

V

-

(0x62)

CLKPCE

-

WDCE

S

CLKPS2

WDP2

N

CLKPS1

WDP1

Z

CLKPS0

WDP0

C

31

46

11

13

(0x61)

WDTCR

SREG

-

I

-

(0x60)

T

H

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

SPH

Stack Pointer High

Stack Pointer Low

SPL

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

-

SPMIE

RWWSB

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

271

JTD

-

PUD

-

WDRF

SM2

-

BORF

SM1

-

IVSEL

EXTRF

SM0

-

IVCE

PORF

SE

52/67/244

-

JTRF

44

38

-

Reserved

OCDR

-

OCDR5

ACO

-

OCDR4

ACI

-

IDRD/OCDR7

OCDR6

ACBG

-

OCDR3

ACIE

-

OCDR2

ACIC

-

OCDR1

ACIS1

-

OCDR0

ACIS0

-

240

199

ACSR

ACD

-

Reserved

SPDR

-

SPI Data Register

159

157

24

SPSR

SPIF

SPIE

WCOL

SPE

-

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0A

TCNT0

General Purpose I/O Register

24

-

Timer/Counter0 Output Compare A

Timer/Counter0

102

101

Reserved

-

11

2552HS–AVR–11/06

Address

Name

TCCR0A

GTCCR

EEARH

EEARL

EEDR

Bit 7

FOC0A

TSM

-

Bit 6

WGM00

Bit 5

COM0A1

Bit 4

COM0A0

Bit 3

WGM01

Bit 2

CS02

-

Bit 1

CS01

PSR2

Bit 0

CS00

Page

99

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

-

PSR10

104/151

20

EEPROM Address Register High

EEPROM Address Register Low

EEPROM Data Register

20

EECR

-

EERIE

EEMWE

EEWE

EERE

20

GPIOR0

EIMSK

EIFR

General Purpose I/O Register

24

PCIE3

PCIF3

-

PCIE2

PCIF2

-

PCIE1

PCIF1

-

PCIE0

PCIF0

-

INT0

INTF0

-

56

-

57

Reserved

TIFR2

-

OCF2A

OCF1A

OCF0A

PORTG1

DDG1

PING1

PORTF1

DDF1

PINF1

PORTE1

DDE1

PINE1

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

PORTA1

DDA1

PINA1

TOV2

TOV1

TOV0

PORTG0

DDG0

PING0

PORTF0

DDF0

PINF0

PORTE0

DDE0

PINE0

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

PORTA0

DDA0

PINA0

149

131

102

88

87

86

TIFR1

-

ICF1

-

OCF1B

-

TIFR0

-

PORTG

DDRG

PING

-

PORTG4

DDG4

PING4

PORTF4

DDF4

PINF4

PORTE4

DDE4

PINE4

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

PORTA4

DDA4

PINA4

PORTG3

DDG3

PING3

PORTF3

DDF3

PINF3

PORTE3

DDE3

PINE3

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

PORTA3

DDA3

PINA3

PORTG2

DDG2

PING2

PORTF2

DDF2

PINF2

PORTE2

DDE2

PINE2

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

PORTA2

DDA2

PINA2

-

PING5

PORTF5

DDF5

PINF5

PORTE5

DDE5

PINE5

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

PORTA5

DDA5

PINA5

PORTF

DDRF

PORTF7

DDF7

PINF7

PORTE7

DDE7

PINE7

PORTD7

DDD7

PIND7

PORTC7

DDC7

PINC7

PORTB7

DDB7

PINB7

PORTA7

DDA7

PINA7

PORTF6

DDF6

PINF6

PORTE6

DDE6

PINE6

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

PORTA6

DDA6

PINA6

PINF

PORTE

DDRE

PINE

PORTD

DDRD

PIND

PORTC

DDRC

PINC

PORTB

DDRB

PINB

PORTA

DDRA

PINA

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64

location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only

the ST/STS/STD and LD/LDS/LDD instructions can be used.

12

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

k

13

2552HS–AVR–11/06

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRIE

BRID

k

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

Out Port

P ← Rr

Push Register on Stack

STACK ← Rr

14

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Mnemonics

Operands

Description

Operation

Flags

#Clocks

POP

Rd

Pop Register from Stack

Rd ← STACK

None

2

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

15

2552HS–AVR–11/06

Ordering Information

ATmega329

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega329V-8AI

ATmega329V-8AU⁽²⁾

ATmega329V-8MI

ATmega329V-8MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

2.7 - 5.5V

ATmega329-16AI

ATmega329-16AU⁽²⁾

ATmega329-16MI

ATmega329-16MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

16

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. V_CCsee Figure 138 on page 314 and Figure 139 on page 315.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

16

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

ATmega3290

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega3290V-8AI

100A

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

ATmega3290V-8AU⁽²⁾

ATmega3290-16AI

100A

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

ATmega3290-16AU⁽²⁾

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. V_CCsee Figure 138 on page 314 and Figure 139 on page 315.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

17

2552HS–AVR–11/06

ATmega649

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega649V-8AI

ATmega649V-8AU⁽²⁾

ATmega649V-8MI

ATmega649V-8MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

ATmega649-16AI

ATmega649-16AU⁽²⁾

ATmega649-16MI

ATmega649-16MU⁽²⁾

64A

64M1

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. V_CCsee Figure 138 on page 314 and Figure 139 on page 315.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

18

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

ATmega6490

Speed (MHz)⁽³⁾

Power Supply

Ordering Code

Package Type⁽¹⁾

Operational Range

ATmega6490V-8AI

100A

Industrial

(-40°C to 85°C)

8

1.8 - 5.5V

ATmega6490V-8AU⁽²⁾

ATmega6490-16AI

100A

Industrial

(-40°C to 85°C)

16

2.7 - 5.5V

ATmega6490-16AU⁽²⁾

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive). Also Halide free and fully Green.

3. For Speed vs. V_CCsee Figure 138 on page 314 and Figure 139 on page 315.

Package Type

64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

100A

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

19

2552HS–AVR–11/06

Packaging Information

64A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

14.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64A

B

R

20

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

9.10

NOM

0.90

0.02

0.25

9.00

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.18

8.90

D

D2

E

5.20

5.40

9.00

5.60

9.10

K

Pin #1

Notch

(0.20 R)

8.90

e

b

E2

e

5.20

5.40

0.50 BSC

0.40

5.60

BOTTOM VIEW

L

0.35

1.25

0.45

1.55

K

1.40

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Note:

5/25/06

DRAWING NO. REV.

64M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

G

R

21

2552HS–AVR–11/06

100A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.17

0.09

0.45

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

14.10 Note 2

0.27

C

–

0.20

3. Lead coplanarity is 0.08 mm maximum.

L

–

0.75

e

0.50 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

100A

C

R

22

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Errata

ATmega329 rev. C

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

ATmega329 rev. B

ATmega329 rev. A

Not sampled.

• LCD contrast voltage too high

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. LCD contrast voltage too high

When the LCD is active and using low power waveform, the LCD contrast voltage

can be too high. This occurs when V_CCis higher than V_LCD, and when using low

LCD drivetime.

Problem Fix/Workaround

There are several possible workarounds:

- Use normal waveform instead of low power waveform

- Use drivetime of 375 µs or longer

2. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

23

2552HS–AVR–11/06

ATmega3290 rev. C

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

ATmega3290 rev. B

ATmega3290 rev. A

Not sampled.

• LCD contrast voltage too high

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. LCD contrast voltage too high

When the LCD is active and using low power waveform, the LCD contrast voltage

can be too high. This occurs when V_CCis higher than V_LCD, and when using low

LCD drivetime.

Problem Fix/Workaround

There are several possible workarounds:

- Use normal waveform instead of low power waveform

- Use drivetime of 375 µs or longer

2. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

24

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

ATmega649 rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

ATmega6490 rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous

timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock

is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the

value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare

Register, OCR2.

25

2552HS–AVR–11/06

Datasheet Revision

History

Please note that the referring page numbers in this section are referring to this docu-

ment.The referring revision in this section are referring to the document revision.

Rev. 2552H – 11/06

1.

2.

Updated Table 141 on page 318.

Updated note in Table 141 on page 318 and Table 143 on page 319.

Rev. 2552G – 07/06

1.

Updated Table 55 on page 100, Table 57 on page 100, Table 62 on page

127, Table 64 on page 128, Table 64 on page 128, Table 67 on page 144

and Table 69 on page 145.

2.

3.

4.

5.

Updated “Fast PWM Mode” on page 118.

Updated Features in “USI – Universal Serial Interface” on page 187.

Added “Clock speed considerations.” on page 194.

“Errata” on page 364.

Rev. 2552F – 06/06

1.

2.

3.

Updated “Calibrated Internal RC Oscillator” on page 28.

Updated “OSCCAL – Oscillator Calibration Register” on page 29

Added Table 143 on page 319.

Rev. 2552E – 04/06

Rev. 2552D – 03/06

Rev. 2552C – 03/06

1.

Updated “Calibrated Internal RC Oscillator” on page 28.

Updated “Errata” on page 364.

1.

2.

3.

4.

Added “Resources” on page 8.

Added Addresses in Registers.

Updated number of General Purpose I/O pins.

Updated code example in “Bit 0 – IVCE: Interrupt Vector Change Enable”

on page 52.

5.

6.

7.

Updated Introduction in “I/O-Ports” on page 59.

Updated “SPI – Serial Peripheral Interface” on page 152.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page

201.

8.

9.

Updated Features in “Analog to Digital Converter” on page 203.

Updated “Prescaling and Conversion Timing” on page 206.

10. Updated features in “LCD Controller” on page 220.

11. Updated “ATmega329/3290/649/6490 Boot Loader Parameters” on page

280.

12. Updated “DC Characteristics” on page 310.

13. Updated “LCD Controller Characteristics – Preliminary Data – TBD” on

page 319.

26

ATmega329/3290/649/6490

2552HS–AVR–11/06

ATmega329/3290/649/6490

Rev. 2552B – 05/05

1.

MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead

Frame Package QFN/MLF”.

2.

3.

Added “Pin Change Interrupt Timing” on page 54.

Updated Table 104 on page 233, Table 105 on page 234 and Table 137 on

page 299.

4.

5.

6.

7.

8.

Added Figure 131 on page 300.

Updated Figure 92 on page 211 and Figure 124 on page 292.

Updated algorithm “Enter Programming Mode” on page 287.

Added “Supply Current of I/O modules” on page 325.

Updated “Ordering Information” on page 357.

Rev. 2552A –11/04

1.

Initial version.

27

2552HS–AVR–11/06

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

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Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

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Tel: (41) 26-426-5555

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Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

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intended, authorized, or warranted for use as components in applications intended to support or sustain life.

registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

2552HS–AVR–11/06


型号：	ATMEGA649
厂家：	ATMEL
描述：	8-bit Microcontroller with In-System Programmable Flash 8 -bit微控制器在系统内可编程Flash 微控制器
文件：	总28页 (文件大小：330K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA649 [ATMEL]

相关型号：

ATMEGA649-16AI

ATMEGA649-16AU

ATMEGA649-16AU-SL383

ATMEGA649-16AUR

ATMEGA649-16AUR

ATMEGA649-16MI

ATMEGA649-16MU

ATMEGA649-16MU-SL383

ATMEGA6490

ATMEGA6490-16AI

ATMEGA6490-16AU

ATMEGA6490-16AU-SL383