ATMEGA64A-ANR_技术文档

8-bit Atmel Microcontroller with 64KB In-System Programmable Flash

ATmega64A

SUMMARY

Features

• High-performance, Low-power Atmel^®AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 64 Kbytes of In-System Reprogrammable Flash program memory

– 2 Kbytes EEPROM

– 4 Kbytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Up to 64 Kbytes Optional External Memory Space

– Programming Lock for Software Security

– SPI Interface for In-System Programming

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits

– 8-channel, 10-bit ADC

• 8 Single-ended Channels

• 7 Differential Channels

• 2 Differential Channels with Programmable Gain (1x, 10x, 200x)

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended

Standby

– Software Selectable Clock Frequency

– ATmega103 Compatibility Mode Selected by a Fuse

– Global Pull-up Disable

• I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega64A

• Speed Grades

– 0 - 16 MHz for ATmega64A

8160DS–AVR–02/2013

1. Pin Configuration

Figure 1-1. Pinout ATmega64A

TQFP/MLF

PEN

RXD0/(PDI) PE0

(TXD0/PDO) PE1

(XCK0/AIN0) PE2

(OC3A/AIN1) PE3

(OC3B/INT4) PE4

(OC3C/INT5) PE5

(T3/INT6) PE6

1

2

3

4

5

6

7

8

9

48 PA3 (AD3)

47 PA4 (AD4)

46 PA5 (AD5)

45 PA6 (AD6)

44 PA7 (AD7)

43 PG2(ALE)

42 PC7 (A15)

41 PC6 (A14)

40 PC5 (A13)

39 PC4 (A12)

38 PC3 (A11)

37 PC2 (A10

36 PC1 (A9)

35 PC0 (A8)

34 PG1(RD)

33 PG0(WR)

(ICP3/INT7) PE7

(SS) PB0 10

(SCK) PB1 11

(MOSI) PB2 12

(MISO) PB3 13

(OC0) PB4 14

(OC1A) PB5 15

(OC1B) PB6

16

Note:

The bottom pad under the QFN/MLF package should be soldered to ground.

ATmega64A [DATASHEET]

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2. Overview

The ATmega64A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the ATmega64A achieves throughputs approaching 1 MIPS

per MHz, allowing the system designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC

GND

PORTA DRIVERS

PORTF DRIVERS

PORTC DRIVERS

AVCC

DATA REGISTER

PORTF

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

DATA DIR.

REG. PORTA

DATA REGISTER

PORTC

DATA DIR.

REG. PORTC

8-BIT DATA BUS

XTAL1

XTAL2

AREF

CALIB. OSC

INTERNAL

OSCILLATOR

ADC

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

JTAG TAP

TIMING AND

CONTROL

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

ON-CHIP DEBUG

RESET

BOUNDARY-

SCAN

INSTRUCTION

REGISTER

TIMER/

COUNTERS

GENERAL

PURPOSE

REGISTERS

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

INTERRUPT

UNIT

PEN

CONTROL

LINES

ALU

EEPROM

STATUS

REGISTER

2-WIRE SERIAL

INTERFACE

SPI

USART0

USART1

DATA REGISTER

PORTE

DATA DIR.

REG. PORTE

DATA REGISTER

PORTB

DATA DIR.

REG. PORTB

DATA REGISTER

PORTD

DATA DIR.

REG. PORTD

DATA REG. DATA DIR.

PORTG

REG. PORTG

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PORTE DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are

directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega64A provides the following features: 64 Kbytes In-System Programmable Flash with Read-While-

Write capabilities, 2 Kbytes EEPROM, 4 Kbytes SRAM, 53 general purpose I/O lines, 32 general purpose working

registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, two USARTs, a

byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with pro-

grammable gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1

ATmega64A [DATASHEET]

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compliant JTAG test interface, also used for accessing the On-chip Debug system and programming, and six soft-

ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,

SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but

freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save

mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer

and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator

is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the asynchronous timer continue to run.

The device is manufactured using Atmel’s high-density non-volatile memory technology. The On-chip ISP Flash

allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-

volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use

any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash

section will continue to run while the Application Flash section is updated, providing true Read-While-Write opera-

tion. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel

ATmega64A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embed-

ded control applications.

The ATmega64A AVR is supported with a full suite of program and system development tools including: C compil-

ers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits.

2.2

ATmega103 and ATmega64A Compatibility

The ATmega64A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O

location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O loca-

tions present in ATmega103 have the same location in ATmega64A. Most additional I/O locations are added in an

Extended I/O space starting from 0x60 to 0xFF (that is, in the ATmega103 internal RAM space). These location

can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions.

The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number

of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an

ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the func-

tions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended

Interrupt Vectors are removed.

The ATmega64A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current printed cir-

cuit boards. The application notes “Replacing ATmega103 by ATmega128” and “Migration between ATmega64

and ATmega128” describes what the user should be aware of replacing the ATmega103 by an ATmega128 or

ATmega64.

2.2.1

ATmega103 Compatibility Mode

By programming the M103C Fuse, the ATmega64A will be compatible with the ATmega103 regards to RAM, I/O

pins and Interrupt Vectors as described above. However, some new features in ATmega64A are not available in

this compatibility mode, these features are listed below:

• One USART instead of two, asynchronous mode only. Only the eight least significant bits of the Baud Rate

Register is available.

• One 16-bits Timer/Counter with two compare registers instead of two 16-bits Timer/Counters with three

compare registers.

• Two-wire serial interface is not supported.

• Port G serves alternate functions only (not a general I/O port).

• Port F serves as digital input only in addition to analog input to the ADC.

ATmega64A [DATASHEET]

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• Boot Loader capabilities is not supported.

• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.

• The External Memory Interface can not release any Address pins for general I/O, neither configure different wait

states to different External Memory Address sections.

• Only EXTRF and PORF exist in the MCUCSR Register.

• No timed sequence is required for Watchdog Timeout change.

• Only low-level external interrupts can be used on four of the eight External Interrupt sources.

• Port C is output only.

• USART has no FIFO buffer, so Data OverRun comes earlier.

• The user must have set unused I/O bits to 0 in ATmega103 programs.

2.3

Pin Descriptions

2.3.1

VCC

Digital supply voltage.

2.3.2

2.3.3

GND

Ground.

Port A (PA7:PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega64A as listed on page 72.

2.3.4

2.3.5

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega64A as listed on page 73.

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega64A as listed on page 76. In ATmega103 com-

patibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active.

2.3.6

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega64A as listed on page 77.

ATmega64A [DATASHEET]

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2.3.7

2.3.8

Port E (PE7:PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega64A as listed on page 80.

Port F (PF7:PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal

pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both

high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not

running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be

activated even if a reset occurs.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

Port F also serves the functions of the JTAG interface.

In ATmega103 compatibility mode, Port F is an input port only.

2.3.9

Port G (PG4:PG0)

Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features.

In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as

input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when

a reset condition becomes active, even if the clock is not running. PG3 and PG4 are Oscillator pins.

2.3.10

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock

is not running. The minimum pulse length is given in Table 29-3 on page 307. Shorter pulses are not guaranteed to

generate a reset.

2.3.11

2.3.12

2.3.13

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V_CC, even if

the ADC is not used. If the ADC is used, it should be connected to V_CCthrough a low-pass filter.

2.3.14

AREF

AREF is the analog reference pin for the A/D Converter.

ATmega64A [DATASHEET]

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2.3.15

PEN

This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low during a Power-on

Reset, the device will enter the SPI Serial Programming mode. PEN is internally pulled high. The pullup is shown in

Figure 11-1 on page 49 and its value is given in Section 29.2 “DC Characteristics” on page 304. PEN has no func-

tion during normal operation.

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for download on

http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20

years at 85°C or 100 years at 25°C.

5. About Code Examples

This datasheet contains simple code examples that briefly show how to use various parts of the device. These

code examples assume that the part specific header file is included before compilation. Be aware that not all C

compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.

Please confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be

replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,

“SBRC”, “SBR”, and “CBR”.

6. Capacitive touch sensing

The Atmel^®QTouch^®Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel

AVR^®microcontrollers. The QTouch Library includes support for the QTouch and QMatrix^®acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Micro-

controller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the

touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library

User Guide - also available for download from the Atmel website.

ATmega64A [DATASHEET]

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7. Ordering Information

Speed (MHz)

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

64A

64M1

Operation Range

ATmega64A-AU

ATmega64A-AUR⁽³⁾

ATmega64A-MU

ATmega64A-MUR⁽³⁾

Industrial

(-40C to 85C)

16

2.7 - 5.5

ATmega64A-AN

64A

64M1

ATmega64A-ANR⁽³⁾

ATmega64A-MN

ATmega64A-MNR⁽³⁾

Extended

(-40C to 105C)⁽⁴⁾

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. Tape and Reel

4. See characterization specifications at 105C

Package Type

64A

64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1

64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega64A [DATASHEET]

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8. Packaging Information

8.1

64A

PIN 1

B

e

PIN 1 IDENTIFIER

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

15.75

13.90

15.75

13.90

0.30

0.09

0.45

–

0.15

1.00

16.00

14.00

16.00

14.00

–

1.05

16.25

D1

E

14.10 Note 2

16.25

Notes:

E1

B

14.10 Note 2

0.45

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

C

–

0.20

3. Lead coplanarity is 0.10mm maximum.

L

–

0.75

e

0.80 TYP

2010-10-20

DRAWING NO. REV.

64A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness,

0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

C

ATmega64A [DATASHEET]

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8.2

64M1

D

Marked Pin# 1 ID

E

SEATING PLANE

C

A1

TOP VIEW

A

K

0.08

C

L

Pin #1 Corner

SIDE VIEW

D2

Pin #1

Triangle

Option A

1

2

3

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

0.30

9.10

NOM

0.90

0.02

0.25

9.00

NOTE

SYMBOL

E2

Option B

Option C

A

Pin #1

Chamfer

(C 0.30)

A1

b

0.18

8.90

D

D2

E

5.20

5.40

9.00

5.60

9.10

K

Pin #1

Notch

(0.20 R)

8.90

e

b

E2

e

5.20

5.40

0.50 BSC

0.40

5.60

BOTTOM VIEW

L

0.35

0.45

1.55

K

1.25

1.40

Notes:

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

2. Dimension and tolerance conform to ASMEY14.5M-1994.

2010-10-19

TITLE

DRAWING NO. REV.

64M1

2325 Orchard Parkway

San Jose, CA 95131

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

H

R

9. Errata

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The revision letter in this section refers to the revision of the ATmega64A device.

9.1

ATmega64A, rev. D

• First Analog Comparator conversion may be delayed

• Interrupts may be lost when writing the timer registers in the asynchronous timer

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

• IDCODE masks data from TDI input

• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed

If the device is powered by a slow rising V_CC, the first Analog Comparator conversion will take longer than

expected on some devices.

Problem Fix/Workaround

When the device has been powered or reset, disable then enable theAnalog Comparator before the first

conversion.

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous

Timer/Counter register (TCNTx) is 0x00.

Problem Fix / Workaround

Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writ-

ing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or

asynchronous Output Compare Register (OCRx).

3. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV register, the device may

execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency change. Thus, the next 8

instructions after the change should be NOP instructions. To ensure this, follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

; set new prescale value

; no operation

OUT XDIV, temp

NOP

SEI

; no operation

; clear global interrupt enable

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4. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device

may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata.

5. IDCODE masks data from TDI input

The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones

during Update-DR.

Problem Fix / Workaround

–

If ATmega64A is the only device in the scan chain, the problem is not visible.

Select the Device ID Register of the ATmega64A by issuing the IDCODE instruction or by entering the

Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and

possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the

ATmega64A while reading the Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the

ATmega64A must be the first device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request.

Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an

unexpected EEPROM interrupt request.

Problem Fix / Workaround

Always use OUT or SBI to set EERE in EECR.

ATmega64A [DATASHEET]

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型号：	ATMEGA64A-ANR
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026AEB, TQFP-64 时钟微控制器外围集成电路
文件：	总13页 (文件大小：256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATMEGA64A-ANR [ATMEL]

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