ATMEGA8-16MU [ATMEL]
8-bit with 8K Bytes In-System Programmable Flash; 8位具有8K字节的系统内可编程闪存
| 型号： | ATMEGA8-16MU |
| 厂家： | 
ATMEL |
| 描述： | 8-bit with 8K Bytes In-System Programmable Flash |
| 文件： | 总25页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 8K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
8-bit
– 1K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
with 8K Bytes
In-System
Programmable
Flash
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
Eight Channels 10-bit Accuracy
ATmega8
ATmega8L
– 6-channel ADC in PDIP package
Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Summary
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V (ATmega8L)
– 4.5 - 5.5V (ATmega8)
• Speed Grades
– 0 - 8 MHz (ATmega8L)
– 0 - 16 MHz (ATmega8)
• Power Consumption at 4 Mhz, 3V, 25°C
– Active: 3.6 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 0.5 µA
Rev. 2486XS–AVR–06/10
Pin
PDIP
Configurations
(RESET) PC6
(RXD) PD0
1
2
3
4
5
6
7
8
9
28 PC5 (ADC5/SCL)
27 PC4 (ADC4/SDA)
26 PC3 (ADC3)
25 PC2 (ADC2)
24 PC1 (ADC1)
23 PC0 (ADC0)
22 GND
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
21 AREF
(XTAL1/TOSC1) PB6
20 AVCC
(XTAL2/TOSC2) PB7 10
(T1) PD5 11
19 PB5 (SCK)
18 PB4 (MISO)
17 PB3 (MOSI/OC2)
16 PB2 (SS/OC1B)
15 PB1 (OC1A)
(AIN0) PD6 12
(AIN1) PD7 13
(ICP1) PB0 14
TQFP Top View
(INT1) PD3
(XCK/T0) PD4
GND
1
2
3
4
5
6
7
8
24 PC1 (ADC1)
23 PC0 (ADC0)
22 ADC7
VCC
21 GND
GND
20 AREF
VCC
19 ADC6
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
18 AVCC
17 PB5 (SCK)
MLF Top View
(INT1) PD3
(XCK/T0) PD4
GND
PC1 (ADC1)
PC0 (ADC0)
ADC7
1
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
VCC
GND
GND
AREF
VCC
ADC6
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
AVCC
PB5 (SCK)
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.
2
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Overview
The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture.
By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs
approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption ver-
sus processing speed.
Block Diagram
Figure 1. Block Diagram
XTAL1
RESET
PC0 - PC6
PB0 - PB7
VCC
XTAL2
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
GND
ADC
INTERFACE
MUX &
ADC
TWI
AGND
AREF
TIMERS/
COUNTERS
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
INTERNAL
OSCILLATOR
SRAM
INSTRUCTION
REGISTER
WATCHDOG
TIMER
GENERAL
PURPOSE
REGISTERS
OSCILLATOR
X
Y
Z
INSTRUCTION
DECODER
MCU CTRL.
& TIMING
CONTROL
LINES
INTERRUPT
UNIT
ALU
STATUS
REGISTER
AVR CPU
EEPROM
USART
PROGRAMMING
LOGIC
SPI
+
-
COMP.
INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
2486XS–AVR–06/10
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose
I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-
wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with
10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-
down mode saves the register contents but freezes the Oscillator, disabling all other chip func-
tions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleep-
ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution
to many embedded control applications.
The ATmega8 AVR is supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
4
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
XTAL1/XTAL2/TOSC1/ Port B output buffers have symmetrical drive characteristics with both high sink and source
TOSC2
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
58 and “System Clock and Clock Options” on page 25.
Port C (PC5..PC0)
PC6/RESET
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-
acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to
generate a Reset.
The various special features of Port C are elaborated on page 61.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8 as listed on page
63.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
38. Shorter pulses are not guaranteed to generate a reset.
5
2486XS–AVR–06/10
AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC
.
AREF
AREF is the analog reference pin for the A/D Converter.
ADC7..6 (TQFP and
QFN/MLF Package
Only)
In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.
6
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:
1.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
7
2486XS–AVR–06/10
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
SREG
SPH
I
–
T
–
H
–
S
–
V
–
N
Z
C
11
13
13
SP10
SP2
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
Reserved
GICR
INT1
INTF1
OCIE2
OCF2
SPMIE
TWINT
SE
INT0
INTF0
TOIE2
TOV2
RWWSB
TWEA
SM2
–
–
–
–
–
IVSEL
IVCE
–
49, 67
GIFR
–
TICIE1
ICF1
–
–
–
–
–
68
TIMSK
TIFR
OCIE1A
OCF1A
RWWSRE
TWSTO
SM0
OCIE1B
OCF1B
BLBSET
TWWC
ISC11
WDRF
–
TOIE1
TOV1
PGWRT
TWEN
ISC10
BORF
CS02
TOIE0
TOV0
SPMEN
TWIE
ISC00
PORF
CS00
72, 102, 122
–
73, 102, 122
SPMCR
TWCR
MCUCR
MCUCSR
TCCR0
TCNT0
OSCCAL
SFIOR
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
ICR1H
ICR1L
PGERS
–
213
TWSTA
SM1
–
171
ISC01
EXTRF
CS01
33, 66
–
–
–
41
–
–
–
–
72
Timer/Counter0 (8 Bits)
72
Oscillator Calibration Register
31
–
–
–
COM1B1
–
–
ACME
FOC1A
WGM12
PUD
FOC1B
CS12
PSR2
WGM11
CS11
PSR10
WGM10
CS10
58, 75, 123, 193
COM1A1
ICNC1
COM1A0
ICES1
COM1B0
WGM13
96
100
101
101
101
101
101
101
102
102
117
119
119
119
43
Timer/Counter1 – Counter Register High byte
Timer/Counter1 – Counter Register Low byte
Timer/Counter1 – Output Compare Register A High byte
Timer/Counter1 – Output Compare Register A Low byte
Timer/Counter1 – Output Compare Register B High byte
Timer/Counter1 – Output Compare Register B Low byte
Timer/Counter1 – Input Capture Register High byte
Timer/Counter1 – Input Capture Register Low byte
TCCR2
TCNT2
OCR2
FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
Timer/Counter2 (8 Bits)
Timer/Counter2 Output Compare Register
ASSR
–
–
–
–
WDCE
–
AS2
TCN2UB
WDP2
OCR2UB
WDP1
TCR2UB
WDP0
WDTCR
UBRRH
UCSRC
EEARH
EEARL
EEDR
–
–
–
–
–
WDE
URSEL
URSEL
–
UBRR[11:8]
158
156
20
0x20(1) (0x40)(1)
UMSEL
–
UPM1
–
UPM0
–
USBS
–
UCSZ1
–
UCSZ0
–
UCPOL
EEAR8
EEAR0
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
20
EEPROM Data Register
20
EECR
–
–
–
–
EERIE
EEMWE
EEWE
EERE
20
Reserved
Reserved
Reserved
PORTB
DDRB
PORTB7
DDB7
PINB7
–
PORTB6
DDB6
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
65
65
PINB
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
65
PORTC
DDRC
PORTC6
DDC6
PORTC5
DDC5
PORTC4
DDC4
PORTC3
DDC3
PORTC2
DDC2
PORTC1
DDC1
PORTC0
DDC0
65
–
65
PINC
–
PINC6
PORTD6
DDD6
PINC5
PORTD5
DDD5
PINC4
PORTD4
DDD4
PINC3
PORTD3
DDD3
PINC2
PORTD2
DDD2
PINC1
PORTD1
DDD1
PINC0
PORTD0
DDD0
65
PORTD
DDRD
PORTD7
DDD7
PIND7
65
65
PIND
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
65
SPDR
SPI Data Register
131
131
129
153
154
155
158
194
205
207
208
208
173
174
SPSR
SPIF
SPIE
WCOL
SPE
–
–
–
–
–
SPI2X
SPR0
SPCR
DORD
MSTR
CPOL
CPHA
SPR1
UDR
USART I/O Data Register
UCSRA
UCSRB
UBRRL
ACSR
RXC
TXC
UDRE
UDRIE
FE
DOR
PE
U2X
MPCM
TXB8
RXCIE
TXCIE
RXEN
TXEN
UCSZ2
RXB8
USART Baud Rate Register Low byte
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ADLAR
ADFR
ACI
–
ACIE
MUX3
ADIE
ACIC
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
ADMUX
ADCSRA
ADCH
ADIF
ADC Data Register High byte
ADC Data Register Low byte
ADCL
TWDR
TWAR
Two-wire Serial Interface Data Register
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
8
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
TWS6
TWS5
TWS4
TWS3
TWPS1
TWPS0
0x01 (0x21)
0x00 (0x20)
TWSR
TWBR
TWS7
–
173
171
Two-wire Serial Interface Bit Rate Register
Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
9
2486XS–AVR–06/10
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
ADIW
SUB
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
SUBI
SBC
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
Rd ← Rd ⊕ Rr
Z,N,V
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
CBR
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
INC
Z,N,V
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
SER
Rd
Set Register
None
MUL
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Multiply Unsigned
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
BRANCH INSTRUCTIONS
RJMP
IJMP
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
k
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1 / 2 / 3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2 / 3
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
1 / 2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
k
k
Mnemonics
Operands
Description
Operation
Flags
#Clocks
10
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Instruction Set Summary (Continued)
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
None
None
1 / 2
1 / 2
BRID
k
Branch if Interrupt Disabled
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(Z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CBI
I/O(P,b) ← 0
None
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Mnemonics
Operands
Description
Operation
Flags
#Clocks
11
2486XS–AVR–06/10
Instruction Set Summary (Continued)
CLT
SEH
CLH
Clear T in SREG
T ← 0
H ← 1
H ← 0
T
1
1
1
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
None
None
None
1
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Watchdog Reset
12
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Ordering Information
Speed (MHz)
Power Supply
Ordering Code(2)
Package(1)
Operation Range
ATmega8L-8AU
ATmega8L-8PU
ATmega8L-8MU
32A
28P3
32M1-A
8
2.7 - 5.5
4.5 - 5.5
Industrial
(-40°C to 85°C)
ATmega8-16AU
ATmega8-16PU
ATmega8-16MU
32A
28P3
32M1-A
16
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
Package Type
32A
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
13
2486XS–AVR–06/10
Packaging Information
32A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
0.15
1.05
9.25
7.10
9.25
7.10
0.45
0.20
0.75
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
8.75
6.90
8.75
6.90
0.30
0.09
0.45
1.00
9.00
7.00
9.00
7.00
–
D1
E
Note 2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
C
–
3. Lead coplanarity is 0.10 mm maximum.
L
–
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
32A
B
R
14
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
28P3
D
PIN
1
E1
A
SEATING PLANE
A1
L
B2
(4 PLACES)
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.5724
–
NOM
NOTE
SYMBOL
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.508
34.544
7.620
7.112
0.381
1.143
0.762
3.175
0.203
–
34.798 Note 1
8.255
E
E1
B
7.493 Note 1
0.533
B1
B2
L
1.397
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
1.143
3.429
C
0.356
eB
e
10.160
2.540 TYP
09/28/01
DRAWING NO. REV.
28P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
B
R
15
2486XS–AVR–06/10
32M1-A
D
D1
1
2
3
0
Pin 1 ID
SIDE VIEW
E1
E
TOP VIEW
A3
A1
A2
A
K
COMMON DIMENSIONS
0.08
C
(Unit of Measure = mm)
P
D2
MIN
0.80
–
MAX
1.00
0.05
1.00
NOM
0.90
0.02
0.65
0.20 REF
0.23
5.00
4.75
3.10
5.00
4.75
3.10
0.50 BSC
0.40
–
NOTE
SYMBOL
A
A1
A2
A3
b
1
2
3
P
–
Pin #1 Notch
(0.20 R)
E2
0.18
4.90
4.70
2.95
4.90
4.70
2.95
0.30
5.10
4.80
3.25
5.10
4.80
3.25
D
K
D1
D2
E
e
b
L
E1
E2
e
BOTTOM VIEW
L
0.30
–
0.50
0.60
P
o
–
–
12
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
K
0.20
–
–
5/25/06
DRAWING NO. REV.
32M1-A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
E
R
16
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Errata
The revision letter in this section refers to the revision of the ATmega8 device.
ATmega8
Rev. D to I, M
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Signature may be Erased in Serial Programming Mode
• CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is
Used to Clock the Asynchronous Timer/Counter2
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix / Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronized to the asynchronous timer
clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
Problem Fix / Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous
Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx).
3. Signature may be Erased in Serial Programming Mode
If the signature bytes are read before a chiperase command is completed, the signature may
be erased causing the device ID and calibration bytes to disappear. This is critical, espe-
cially, if the part is running on internal RC oscillator.
Problem Fix / Workaround:
Ensure that the chiperase command has exceeded before applying the next command.
4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz
Oscillator is Used to Clock the Asynchronous Timer/Counter2
When the internal RC Oscillator is used as the main clock source, it is possible to run the
Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1
and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock
source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and
XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and
XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed.
Problem Fix / Workaround
Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2.
This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors
also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G,
CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Cus-
tomers who want compatibility between Rev. G and older revisions, must ensure that
CKOPT is unprogrammed (CKOPT = 1).
17
2486XS–AVR–06/10
5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg-
ister triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
18
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Datasheet
Revision
History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
Changes from Rev. 1. Updated “DC Characteristics” on page 242 with new VOL maximum value (0.9V and
0.6V).
2486W- 02/10 to
Rev. 2486X- 06/10
Changes from Rev. 1. Updated “ADC Characteristics” on page 248 with VINT maximum value (2.9V).
2486V- 05/09 to
Rev. 2486W- 02/10
Changes from Rev. 1. Added “Not recommended for new designs” on page 1.
2486U- 08/08 to
Rev. 2486V- 05/09
2. Updated “Errata” on page 17.
3. Updated the last page with Atmel’s new adresses.
Changes from Rev. 1.
2486T- 05/08 to
Updated “DC Characteristics” on page 242 with ICC typical values.
Rev. 2486U- 08/08
Changes from Rev. 1. Updated Table 98 on page 240.
2486S- 08/07 to
2. Updated “Ordering Information” on page 292.
Rev. 2486T- 05/08
- Commercial Ordering Code removed.
- No Pb-free packaging option removed.
Changes from Rev. 1. Updated “Features” on page 1.
2486R- 07/07 to
2. Added “Data Retention” on page 7.
Rev. 2486S- 08/07
3. Updated “Errata” on page 17.
4. Updated “Slave Mode” on page 129.
Changes from Rev. 1. Added text to Table 81 on page 218.
2486Q- 10/06 to
2. Fixed typo in “Peripheral Features” on page 1.
Rev. 2486R- 07/07
3. Updated Table 16 on page 42.
4. Updated Table 75 on page 206.
5. Removed redundancy and updated typo in Notes section of “DC Characteristics” on
page 242.
19
2486XS–AVR–06/10
Changes from Rev. 1. Updated “Timer/Counter Oscillator” on page 32.
2486P- 02/06 to
Rev. 2486Q- 10/06
2. Updated “Fast PWM Mode” on page 89.
3. Updated code example in “USART Initialization” on page 138.
4. Updated Table 37 on page 97, Table 39 on page 98, Table 42 on page 117, Table 44 on
page 118, and Table 98 on page 240.
5. Updated “Errata” on page 17.
Changes from Rev. 1. Added “Resources” on page 7.
2486O-10/04 to
2. Updated “External Clock” on page 32.
Rev. 2486P- 02/06
3. Updated “Serial Peripheral Interface – SPI” on page 124.
4. Updated Code Example in “USART Initialization” on page 138.
5. Updated Note in “Bit Rate Generator Unit” on page 170.
6. Updated Table 98 on page 240.
7. Updated Note in Table 103 on page 248.
8. Updated “Errata” on page 17.
Changes from Rev. 1. Removed to instances of “analog ground”. Replaced by “ground”.
2486N-09/04 to
Rev. 2486O-10/04
2. Updated Table 7 on page 29, Table 15 on page 38, and Table 100 on page 244.
3. Updated “Calibrated Internal RC Oscillator” on page 30 with the 1 MHz default value.
4. Table 89 on page 225 and Table 90 on page 225 moved to new section “Page Size” on
page 225.
5. Updated descripton for bit 4 in “Store Program Memory Control Register – SPMCR”
on page 213.
6. Updated “Ordering Information” on page 13.
Changes from Rev. 1. Added note to MLF package in “Pin Configurations” on page 2.
2486M-12/03 to
Rev. 2486N-09/04
2. Updated “Internal Voltage Reference Characteristics” on page 42.
3. Updated “DC Characteristics” on page 242.
4. ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this.
Updated features in “Analog-to-Digital Converter” on page 196.
Updated “ADC Characteristics” on page 248.
5. Removed reference to “External RC Oscillator application note” from “External RC
Oscillator” on page 28.
20
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
Changes from Rev. 1. Updated “Calibrated Internal RC Oscillator” on page 30.
2486L-10/03 to
Rev. 2486M-12/03
Changes from Rev. 1. Removed “Preliminary” and TBDs from the datasheet.
2486K-08/03 to
Rev. 2486L-10/03
2. Renamed ICP to ICP1 in the datasheet.
3. Removed instructions CALL and JMP from the datasheet.
4. Updated tRST in Table 15 on page 38, VBG in Table 16 on page 42, Table 100 on page
244 and Table 102 on page 246.
5. Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in
“Calibrated Internal RC Oscillator” on page 30. Added text regarding XTAL1/XTAL2
and CKOPT Fuse in “Timer/Counter Oscillator” on page 32.
6. Updated Watchdog Timer code examples in “Timed Sequences for Changing the
Configuration of the Watchdog Timer” on page 45.
7. Removed bit 4, ADHSM, from “Special Function IO Register – SFIOR” on page 58.
8. Added note 2 to Figure 103 on page 215.
9. Updated item 4 in the “Serial Programming Algorithm” on page 238.
10. Added tWD_FUSE to Table 97 on page 239 and updated Read Calibration Byte, Byte 3, in
Table 98 on page 240.
11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Character-
istics” on page 242.
Changes from Rev. 1. Updated VBOT values in Table 15 on page 38.
2486J-02/03 to
Rev. 2486K-08/03
2. Updated “ADC Characteristics” on page 248.
3. Updated “ATmega8 Typical Characteristics” on page 249.
4. Updated “Errata” on page 17.
Changes from Rev. 1. Improved the description of “Asynchronous Timer Clock – clkASY” on page 26.
2486I-12/02 to Rev.
2486J-02/03
2. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz
Crystal Oscillator” application note, which do not exist.
3. Corrected OCn waveforms in Figure 38 on page 90.
4. Various minor Timer 1 corrections.
5. Various minor TWI corrections.
21
2486XS–AVR–06/10
6. Added note under “Filling the Temporary Buffer (Page Loading)” on page 216 about
writing to the EEPROM during an SPM Page load.
7. Removed ADHSM completely.
8. Added section “EEPROM Write during Power-down Sleep Mode” on page 23.
9. Removed XTAL1 and XTAL2 description on page 5 because they were already
described as part of “Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2” on page 5.
10. Improved the table under “SPI Timing Characteristics” on page 246 and removed the
table under “SPI Serial Programming Characteristics” on page 241.
11. Corrected PC6 in “Alternate Functions of Port C” on page 61.
12. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 58.
13. Corrected 230.4 Mbps to 230.4 kbps under “Examples of Baud Rate Setting” on page
159.
14. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode”
on page 113.
15. Added thick lines around accessible registers in Figure 76 on page 169.
16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits
under “Performing a Page Write” on page 216.
17. Added note for RSTDISBL Fuse in Table 87 on page 223.
18. Updated drawings in “Packaging Information” on page 14.
Changes from Rev. 1. Added errata for Rev D, E, and F on page 17.
2486H-09/02 to
Rev. 2486I-12/02
Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
2486G-09/02 to
Rev. 2486H-09/02
Changes from Rev. 1. Updated Table 103, “ADC Characteristics,” on page 248.
2486F-07/02 to
Rev. 2486G-09/02
Changes from Rev. 1. Changes in “Digital Input Enable and Sleep Modes” on page 55.
2486E-06/02 to
Rev. 2486F-07/02
2. Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 59.
3. The following tables have been updated:
Table 51, “CPOL and CPHA Functionality,” on page 132, Table 59, “UCPOL Bit Settings,”
on page 158, Table 72, “Analog Comparator Multiplexed Input(1),” on page 195, Table 73,
22
ATmega8(L)
2486XS–AVR–06/10
ATmega8(L)
“ADC Conversion Time,” on page 200, Table 75, “Input Channel Selections,” on page 206,
and Table 84, “Explanation of Different Variables used in Figure 103 and the Mapping to the
Z-pointer,” on page 221.
4. Changes in “Reading the Calibration Byte” on page 234.
5. Corrected Errors in Cross References.
Changes from Rev. 1. Updated Some Preliminary Test Limits and Characterization Data
2486D-03/02 to
The following tables have been updated:
Rev. 2486E-06/02
Table 15, “Reset Characteristics,” on page 38, Table 16, “Internal Voltage Reference Char-
acteristics,” on page 42, DC Characteristics on page 242, Table , “ADC Characteristics,” on
page 248.
2. Changes in External Clock Frequency
Added the description at the end of “External Clock” on page 32.
Added period changing data in Table 99, “External Clock Drive,” on page 244.
3. Updated TWI Chapter
More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Pres-
caler,” on page 173.
Changes from Rev. 1. Updated Typical Start-up Times.
2486C-03/02 to
The following tables has been updated:
Rev. 2486D-03/02
Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6,
“Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28,
Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and
Table 12, “Start-up Times for the External Clock Selection,” on page 32.
2. Added “ATmega8 Typical Characteristics” on page 249.
Changes from Rev. 1. Updated TWI Chapter.
2486B-12/01 to
Rev. 2486C-03/02
More details regarding use of the TWI Power-down operation and using the TWI as Master
with low TWBRR values are added into the datasheet.
Added the note at the end of the “Bit Rate Generator Unit” on page 170.
Added the description at the end of “Address Match Unit” on page 170.
2. Updated Description of OSCCAL Calibration Byte.
In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4,
and 8 MHz Oscillator selections. This is now added in the following sections:
Improved description of “Oscillator Calibration Register – OSCCAL” on page 31 and “Cali-
bration Byte” on page 225.
3. Added Some Preliminary Test Limits and Characterization Data.
Removed some of the TBD’s in the following tables and pages:
Table 3 on page 26, Table 15 on page 38, Table 16 on page 42, Table 17 on page 44, “TA =
-40×C to 85×C, VCC = 2.7V to 5.5V (unless otherwise noted)” on page 242, Table 99 on
page 244, and Table 102 on page 246.
23
2486XS–AVR–06/10
4. Updated Programming Figures.
Figure 104 on page 226 and Figure 112 on page 237 are updated to also reflect that AVCC
must be connected during Programming mode.
5. Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Dis-
abled or if External Oscillators are Selected.
Added a note in section “Enter Programming Mode” on page 228.
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2486XS–AVR–06/10
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