ATMEGA8535L_技术文档

Features

• High-performance, Low-power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 8K Bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

ATmega8535

ATmega8535L

7 Differential Channels for TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x for TQFP

Package Only

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Preliminary

Summary

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega8535L

– 4.5 - 5.5V for ATmega8535

• Speed Grades

– 0 - 8 MHz for ATmega8535L

– 0 - 16 MHz for ATmega8535

Rev. 2502FS–AVR–06/04

Note: This is a summary document. A complete document

is available on our Web site at www.atmel.com.

Pin Configurations

Figure 1. Pinout ATmega8535

(XCK/T0) PB0

(T1) PB1

(INT2/AIN0) PB2

(OC0/AIN1) PB3

(SS) PB4

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (ADC3)

PA4 (ADC4)

PA5 (ADC5)

PA6 (ADC6)

PA7 (ADC7)

AREF

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

VCC

GND

AVCC

XTAL2

XTAL1

PC7 (TOSC2)

PC6 (TOSC1)

PC5

PC4

PC3

(RXD) PD0

(TXD) PD1

(INT0) PD2

(INT1) PD3

(OC1B) PD4

(OC1A) PD5

(ICP1) PD6

PC2

PC1 (SDA)

PC0 (SCL)

PD7 (OC2)

PLCC

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

1

2

3

4

5

6

7

8

9

33 PA4 (ADC4)

32 PA5 (ADC5)

31 PA6 (ADC6)

30 PA7 (ADC7)

29 AREF

(MOSI) PB5

7

8

9

39 PA4 (ADC4)

38 PA5 (ADC5)

37 PA6 (ADC6)

36 PA7 (ADC7)

35 AREF

(MISO) PB6

(SCK) PB7

RESET 10

VCC 11

VCC

GND

28 GND

GND 12

34 GND

XTAL2

27 AVCC

XTAL2 13

33 AVCC

XTAL1

26 PC7 (TOSC2)

25 PC6 (TOSC1)

24 PC5

XTAL1 14

32 PC7 (TOSC2)

31 PC6 (TOSC1)

30 PC5

(RXD) PD0

(RXD) PD0 15

(TXD) PD1 16

(INT0) PD2 17

(TXD) PD1 10

(INT0) PD2 11

23 PC4

29 PC4

NOTE: MLF Bottom pad should be soldered to ground.

Disclaimer

Typical values contained in this data sheet are based on simulations and characteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

2

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Overview

The ATmega8535 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing instructions in a single clock cycle, the

ATmega8535 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

Block Diagram

Figure 2. Block Diagram

PA0 - PA7

PC0 - PC7

V_CC

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

GND

AVCC

AREF

ADC

INTERFACE

MUX &

ADC

TWI

TIMERS/

COUNTERS

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH

INTERNAL

OSCILLATOR

SRAM

XTAL1

INSTRUCTION

REGISTER

WATCHDOG

TIMER

GENERAL

PURPOSE

REGISTERS

OSCILLATOR

XTAL2

X

Y

Z

INSTRUCTION

DECODER

MCU CTRL.

& TIMING

RESET

INTERNAL

CALIBRATED

OSCILLATOR

CONTROL

LINES

INTERRUPT

UNIT

ALU

STATUS

REGISTER

AVR CPU

EEPROM

USART

PROGRAMMING

LOGIC

SPI

+

-

COMP.

INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

3

2502FS–AVR–06/04

The AVR core combines a rich instruction set with 32 general purpose working registers.

All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega8535 provides the following features: 8K bytes of In-System Programmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 32

general purpose I/O lines, 32 general purpose working registers, three flexible

Timer/Counters with compare modes, internal and external interrupts, a serial program-

mable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with

optional differential input stage with programmable gain in TQFP package, a program-

mable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software

selectable power saving modes. The Idle mode stops the CPU while allowing the

SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The

Power-down mode saves the register contents but freezes the Oscillator, disabling all

other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the

asynchronous timer continues to run, allowing the user to maintain a timer base while

the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and

all I/O modules except asynchronous timer and ADC, to minimize switching noise during

ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low-power

consumption. In Extended Standby mode, both the main Oscillator and the asynchro-

nous timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology.

The On-chip ISP Flash allows the program memory to be reprogrammed In-System

through an SPI serial interface, by a conventional nonvolatile memory programmer, or

by an On-chip Boot program running on the AVR core. The boot program can use any

interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU

with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8535

is a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega8535 AVR is supported with a full suite of program and system develop-

ment tools including: C compilers, macro assemblers, program debugger/simulators, In-

Circuit Emulators, and evaluation kits.

AT90S8535 Compatibility The ATmega8535 provides all the features of the AT90S8535. In addition, several new

features are added. The ATmega8535 is backward compatible with AT90S8535 in most

cases. However, some incompatibilities between the two microcontrollers exist. To

solve this problem, an AT90S8535 compatibility mode can be selected by programming

the S8535C fuse. ATmega8535 is pin compatible with AT90S8535, and can replace the

AT90S8535 on current Printed Circuit Boards. However, the location of fuse bits and the

electrical characteristics differs between the two devices.

AT90S8535 Compatibility

Mode

Programming the S8535C fuse will change the following functionality:

•

The timed sequence for changing the Watchdog Time-out period is disabled. See

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page

43 for details.

The double buffering of the USART Receive Register is disabled. See “AVR USART

vs. AVR UART – Compatibility” on page 143 for details.

4

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Pin Descriptions

V_CC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

Port pins can provide internal pull-up resistors (selected for each bit). The Port A output

buffers have symmetrical drive characteristics with both high sink and source capability.

When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source

current if the internal pull-up resistors are activated. The Port A pins are tri-stated when

a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega8535 as listed

on page 58.

Port C (PC7..PC0)

Port D (PD7..PD0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port C pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8535 as listed

on page 62.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

15 on page 35. Shorter pulses are not guaranteed to generate a reset.

XTAL1

XTAL2

AVCC

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally

connected to V_CC, even if the ADC is not used. If the ADC is used, it should be con-

nected to V_CCthrough a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

5

2502FS–AVR–06/04

.

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

SREG

SPH

I

–

T

–

H

–

S

–

V

–

N

–

Z

C

8

SP9

SP1

SP8

SP0

10

SPL

SP7

SP6

SP5

SP4

SP3

SP2

10

Timer/Counter0 Output Compare Register

OCR0

83

GICR

INT1

INTF1

OCIE2

OCF2

SPMIE

TWINT

SM2

INT0

INTF0

TOIE2

TOV2

RWWSB

TWEA

SE

INT2

INTF2

TICIE1

ICF1

–

IVSEL

–

IVCE

–

47, 67

GIFR

–

68

TIMSK

TIFR

OCIE1A

OCF1A

RWWSRE

TWSTO

SM0

OCIE1B

OCF1B

BLBSET

TWWC

ISC11

WDRF

WGM01

TOIE1

TOV1

PGWRT

TWEN

ISC10

BORF

CS02

OCIE0

OCF0

PGERS

–

TOIE0

TOV0

SPMEN

TWIE

ISC00

PORF

CS00

83, 113, 131

84, 114, 132

SPMCR

TWCR

MCUCR

MCUCSR

TCCR0

TCNT0

OSCCAL

SFIOR

TCCR1A

TCCR1B

TCNT1H

TCNT1L

OCR1AH

OCR1AL

OCR1BH

OCR1BL

ICR1H

ICR1L

225

178

30, 66

38, 67

81

TWSTA

SM1

ISC01

EXTRF

CS01

–

ISC2

–

FOC0

WGM00

COM01

COM00

Timer/Counter0 (8 Bits)

83

Oscillator Calibration Register

28

ADTS2

COM1A1

ICNC1

ADTS1

COM1A0

ICES1

ADTS0

COM1B1

–

ACME

FOC1A

WGM12

PUD

FOC1B

CS12

PSR2

WGM11

CS11

PSR10

WGM10

CS10

57,86,133,200,220

108

111

112

126

128

129

40

COM1B0

WGM13

Timer/Counter1 – Counter Register High Byte

Timer/Counter1 – Counter Register Low Byte

Timer/Counter1 – Output Compare Register A High Byte

Timer/Counter1 – Output Compare Register A Low Byte

Timer/Counter1 – Output Compare Register B High Byte

Timer/Counter1 – Output Compare Register B Low Byte

Timer/Counter1 – Input Capture Register High Byte

Timer/Counter1 – Input Capture Register Low Byte

TCCR2

TCNT2

OCR2

FOC2

WGM20

COM21

COM20

WGM21

CS22

CS21

CS20

Timer/Counter2 (8 Bits)

Timer/Counter2 Output Compare Register

ASSR

–

WDCE

–

AS2

TCN2UB

WDP2

OCR2UB

WDP1

TCR2UB

WDP0

WDTCR

UBRRH

UCSRC

EEARH

EEARL

EEDR

–

WDE

URSEL

–

UMSEL

–

UPM1

–

UBRR[11:8]

166

164

17

0x20⁽¹⁾(0x40)⁽¹⁾

UPM0

–

USBS

–

UCSZ1

–

UCSZ0

–

UCPOL

EEAR8

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

EEPROM Address Register Low Byte

EEPROM Data Register

17

EECR

–

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

17

PORTA

DDRA

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

64

PINA

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PORTB5

DDB5

PINA4

PORTB4

DDB4

PINA3

PINA2

PINA1

PINA0

64

PORTB

DDRB

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

64

PINB

PINB7

PORTC7

DDC7

PINB6

PORTC6

DDC6

PINB5

PORTC5

DDC5

PINB4

PORTC4

DDC4

PINB3

PINB2

PINB1

PINB0

65

PORTC

DDRC

PINC

PORTC3

DDC3

PORTC2

DDC2

PORTC1

DDC1

PORTC0

DDC0

65

PINC7

PORTD7

DDD7

PINC6

PORTD6

DDD6

PINC5

PORTD5

DDD5

PINC4

PORTD4

DDD4

PINC3

PINC2

PINC1

PORTD1

DDD1

PINC0

PORTD0

DDD0

65

PORTD

DDRD

PIND

PORTD3

DDD3

PORTD2

DDD2

65

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

65

SPDR

SPI Data Register

140

138

161

162

163

166

200

216

218

219

180

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

UDR

USART I/O Data Register

UCSRA

UCSRB

UBRRL

ACSR

RXC

TXC

UDRE

UDRIE

FE

DOR

PE

U2X

MPCM

TXB8

RXCIE

TXCIE

RXEN

TXEN

UCSZ2

RXB8

USART Baud Rate Register Low Byte

ACD

REFS1

ADEN

ACBG

REFS0

ADSC

ACO

ACI

MUX4

ADIF

ACIE

MUX3

ADIE

ACIC

MUX2

ADPS2

ACIS1

MUX1

ADPS1

ACIS0

MUX0

ADPS0

ADMUX

ADCSRA

ADCH

ADLAR

ADATE

ADC Data Register High Byte

ADC Data Register Low Byte

ADCL

TWDR

TWAR

TWSR

Two-wire Serial Interface Data Register

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWPS1

6

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Register Summary (Continued)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x00 (0x20)

TWBR

Two-wire Serial Interface Bit Rate Register

178

Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.

2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

7

2502FS–AVR–06/04

Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

^{R1:R0 ← (Rd x Rr)}<< 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1 / 2 / 3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1 / 2 / 3

1 / 2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

DATA TRANSFER INSTRUCTIONS

8

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Mnemonics

Operands

Description

Operation

Flags

#Clocks

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

MCU CONTROL INSTRUCTIONS

NOP

No Operation

None

1

9

2502FS–AVR–06/04

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SLEEP

WDR

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/Timer)

For On-chip Debug Only

None

1

Watchdog Reset

Break

BREAK

N/A

10

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Ordering Information

Speed (MHz)

Power Supply

Ordering Code

Package⁽¹⁾

Operation Range

ATmega8535L-8AC

ATmega8535L-8PC

ATmega8535L-8JC

ATmega8535L-8MC

44A

40P6

44J

Commercial

(0°C to 70°C)

44M1

8

2.7 - 5.5V

ATmega8535L-8AI

ATmega8535L-8PI

ATmega8535L-8JI

ATmega8535L-8MI

44A

40P6

44J

Industrial

(-40°C to 85°C)

44M1

ATmega8535-16AC

ATmega8535-16PC

ATmega8535-16JC

ATmega8535-16MC

44A

40P6

44J

Commercial

(0°C to 70°C)

44M1

16

4.5 - 5.5V

ATmega8535-16AI

ATmega8535-16PI

ATmega8535-16JI

ATmega8535-16MI

44A

40P6

44J

Industrial

(-40°C to 85°C)

44M1

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

Package Type

44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44-lead, Plastic J-leaded Chip Carrier (PLCC)

44A

40P6

44J

44M1-A

44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Frame Package (MLF)

11

2502FS–AVR–06/04

Packaging Information

44A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

0.15

1.00

12.00

10.00

12.00

10.00

–

1.05

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

–

0.20

3. Lead coplanarity is 0.10 mm maximum.

L

–

0.75

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

44A

B

R

12

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

40P6

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.826

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.381

52.070

15.240

13.462

0.356

1.041

3.048

0.203

15.494

–

52.578 Note 2

15.875

E

–

E1

B

–

13.970 Note 2

0.559

–

B1

L

–

1.651

Notes:

1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

–

3.556

C

–

0.381

eB

e

17.526

2.540 TYP

09/28/01

DRAWING NO. REV.

40P6

TITLE

2325 Orchard Parkway

San Jose, CA 95131

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

13

2502FS–AVR–06/04

44J

1.14(0.045) X 45˚

PIN NO. 1

1.14(0.045) X 45˚

0.318(0.0125)

0.191(0.0075)

IDENTIFIER

D2/E2

E1

E

B1

B

e

A2

A1

D1

D

A

0.51(0.020)MAX

45˚ MAX (3X)

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

4.191

MAX

4.572

3.048

–

NOM

NOTE

SYMBOL

A

–

A1

A2

D

2.286

–

0.508

–

17.399

16.510

17.399

16.510

–

17.653

D1

E

–

16.662 Note 2

17.653

–

Notes:

1. This package conforms to JEDEC reference MS-018, Variation AC.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

E1

–

16.662 Note 2

16.002

D2/E2 14.986

–

B

0.660

0.330

–

0.813

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

B1

e

0.533

1.270 TYP

10/04/01

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

44J

B

R

14

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

44M1-A

D

Marked Pin# 1 ID

E

SEATING PLANE

A1

A3

TOP VIEW

A

L

Pin #1 Corner

SIDE VIEW

D2

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

0.80

–

MAX

1.00

0.05

NOM

0.90

NOTE

SYMBOL

E2

A

A1

A3

b

0.02

0.25 REF

0.23

0.18

5.00

0.35

0.30

5.40

0.75

D

7.00 BSC

5.20

D2

E

e

b

7.00 BSC

5.20

BOTTOM VIEW

E2

e

0.50 BSC

0.55

L

Notes: 1. JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1.

01/15/03

DRAWING NO. REV.

44M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm

Micro Lead Frame Package (MLF)

C

R

15

2502FS–AVR–06/04

Errata

ATmega8535 all rev.

No known errata.

16

ATmega8535(L)

2502FS–AVR–06/04

ATmega8535(L)

Datasheet Change

Log for ATmega8535

Please note that the referring page numbers in this section are referring to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

2502E-12/03 to Rev.

2502F-06/04

1. Updated “Reset Characteristics” on page 35.

2. Updated SPH in “Stack Pointer” on page 10.

3. Updated C code in “USART Initialization” on page 147.

4. Updated “Errata” on page 16.

Changes from Rev.

2502D-09/03 to Rev.

2502E-12/03

1. Updated “Calibrated Internal RC Oscillator” on page 27.

2. Added section “Errata” on page 16.

Changes from Rev.

2502C-04/03 to Rev.

2502D-09/03

1. Removed “Advance Information” and some TBD’s from the datasheet.

2. Added note to “Pinout ATmega8535” on page 2.

3. Updated “Reset Characteristics” on page 35.

4. Updated “Absolute Maximum Ratings” and “DC Characteristics” in “Electrical

Characteristics” on page 252.

5. Updated Table 111 on page 255.

6. Updated “ADC Characteristics – Preliminary Data” on page 260.

7. Updated “ATmega8535 Typical Characteristics – Preliminary Data” on page

263.

8. Removed CALL and JMP instructions from code examples and “Instruction

Set Summary” on page 8.

Changes from Rev.

2502B-09/02 to Rev.

2502C-04/03

1. Updated “Packaging Information” on page 12.

2. Updated Figure 1 on page 2, Figure 84 on page 176, Figure 85 on page 182,

Figure 87 on page 188, Figure 98 on page 204.

3. Added the section “EEPROM Write During Power-down Sleep Mode” on page

20.

4. Removed the references to the application notes “Multi-purpose Oscillator”

and “32 kHz Crystal Oscillator”, which do not exist.

5. Updated code examples on page 42.

6. Removed ADHSM bit.

7. Renamed Port D pin ICP to ICP1. See “Alternate Functions of Port D” on page

62.

17

2502FS–AVR–06/04

8. Added information about PWM symmetry for Timer 0 on page 77 and Timer 2

on page 124.

9. Updated Table 68 on page 166, Table 75 on page 187, Table 76 on page 190,

Table 77 on page 193, Table 108 on page 250, Table 113 on page 258.

10. Updated description on “Bit 5 – TWSTA: TWI START Condition Bit” on page

179.

11. Updated the description in “Filling the Temporary Buffer (Page Loading)” and

“Performing a Page Write” on page 228.

12. Removed the section description in “SPI Serial Programming Characteristics”

on page 251.

13. Updated “Electrical Characteristics” on page 252.

14. Updated “ADC Characteristics – Preliminary Data” on page 260.

14. Updated “Register Summary” on page 6.

15. Various Timer 1 corrections.

16. Added WD_FUSE period in Table 108 on page 250.

Changes from Rev.

2502A-06/02 to Rev.

2502B-09/02

1. Canged the Endurance on the Flash to 10,000 Write/Erase Cycles.

18

ATmega8535(L)

2502FS–AVR–06/04

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

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Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

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Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

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Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

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Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

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Tel: 1(719) 576-3300

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Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Atmel Corporation or its subsidiaries. Microsoft^®, Windows^®, Windows NT^®, and Windows XP^®are the registered trademarks of Microsoft Corpo-

ration. Other terms and product names may be the trademarks of others

Printed on recycled paper.

2502FS–AVR–06/04


型号：	ATMEGA8535L
厂家：	ATMEL
描述：	8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash 8位AVR微控制器具有8K字节的系统内可编程闪存闪存微控制器
文件：	总19页 (文件大小：215K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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