ATMEGA8HVD_技术文档

Features

• High Performance, Low Power AVR^®8-bit Microcontroller

• Advanced RISC Architecture

– 124 Powerful Instructions - Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 4 MIPS Throughput at 4 MHz

• Nonvolatile Program and Data Memories

– 4K/8K Bytes of In-System Self-Programmable Flash (ATmega4HVD/8HVD)

– 256 Bytes EEPROM

8-bit

– 512 Bytes Internal SRAM

Microcontroller

with 4K/8K

Bytes In-System

Programmable

Flash

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data Retention: 20 years at 85°C /100 years at 25°C⁽¹⁾

– Programming Lock for Software Security

• Battery Management Features

– One Cell Batteries

– Short-circuit Protection (Discharge)

– Over-current Protection (Charge and Discharge)

– External Protection Input

– High Voltage Outputs to Drive N-Channel Charge/Discharge FETs

– Operation with 1 FET or 2 FETs supported

Charge FET is optional

ATmega4HVD

ATmega8HVD

– Battery authentication features (Available only under NDA)

• Peripheral Features

– Two 8/16-bit Timer/Counters with Separate Prescaler and two output compare

units

– 10-bit ADC with One External Input

– Two High-voltage open-drain I/O pins

– Programmable Watchdog Timer

Preliminary

Summary

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable

– Power-on Reset

– On-chip Voltage Reference with built-in Temperature Sensor

– On-chip Voltage Regulator

– External and Internal Interrupt Sources

– Sleep Modes:

Idle, ADC Noise Reduction, Power-save, and Power-off

• Package

– 18-pad DRDFN/ MLF

• Operating Voltage (VFET): 2.1 - 6.0V

• Operating Voltage (V_CC):2.0 - 2.4V

• Maximum Withstand Voltage (VFET): 12V

• Maximum Withstand Voltage (High-voltage pins): 5V

• Temperature Range: -20°C to 85°C

• Speed Grade: 1 - 4 MHz

8052BS–AVR–09/08

ATmega4HVD/8HVD

1. Pin Configurations

Figure 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD.

Top view

Bottom view

B1

B10

B9

A1

A8

B2

A7

A6

A2

B3

B8

A3

B4

B7

B6

A4

A5

B5

Table 1-1.

1

Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD.

2

3

4

5

6

7

8

9

10

PB1

(SCK/

SGND/T0)

PC1

(MOSI/INT1/

EXT_PROT)

DNC

BATT

GND

PV1

DNC

VCC

-

A

PB0

(ADC0)

PB2

PC0

OD

OC

VFET

VREG

NI

GND

RESET

B

(MISO/CKOUT/T1)

(INT0/ICP0/XTAL)

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8052BS–AVR–09/08

ATmega4HVD/8HVD

1.1

Pin Descriptions

1.1.1

VFET

Input to the internal voltage regulator.

1.1.2

VCC

Pin for connection of external decoupling capacitor. VCC is internally connected to the voltage

regulator output VREG.

1.1.3

1.1.4

1.1.5

VREG

Output from the internal voltage regulator. Internally connected to VCC.

Ground

GND

Port B (PB2:PB0)

Port B is a low-voltage 3-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATmega4HVD/8HVD.

1.1.6

Port C (PC1:PC0)

Port C is a High-voltage open-drain 2 bit bi-directional I/O port. Port C also serves the func-

tions of various special features of the ATmega4HVD/8HVD.

1.1.7

OC

High voltage output to drive Charge FET (optional).

High voltage output to drive Discharge FET.

Negative input from the battery protection resistor.

Input from battery cell to ADC.

1.1.8

OD

1.1.9

NI

1.1.10

1.1.11

1.1.12

PV1

BATT

RESET/dw

Input for detecting when a charger is connected.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

This pin is also used as debugWIRE communication pin.

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8052BS–AVR–09/08

ATmega4HVD/8HVD

2. Overview

The ATmega4HVD/8HVD is a monitoring and protection circuit for 1-cell Li-ion applications

with focus on high security/authentication, low cost and high utilization of the cell energy. The

device contains secure authentication features as well as autonomous battery protection dur-

ing charging and discharging. The External Protection Input can be used to implement other

battery protection mechanisms using external components, e.g. protection against chargers

with too high charge voltage can be easily implemented with a few low cost passive compo-

nents. The feature set makes the ATmega4HVD/8HVD a key component in any system

focusing on high security, battery protection, high system utilization and low cost.

Figure 2-1. Block Diagram

PB2:0

PB2 (CKOUT)

PB0 (ADC0)

Oscillator

Circuits /

Clock

PORTB (3)

Generation

FET

Control

OC

OD

Oscillator

Sampling

Interface

Watchdog

Oscillator

8/16-bit T/C0

SPI

NI

VCC

Program

Logic

Watchdog

Timer

Battery

Protection

8/16-bit T/C1

EEPROM

Flash

SRAM

Power

Supervision

POR &

debugWIRE

PV1

Voltage

ADC

RESET/dW

GND

RESET

CPU

Security

Module

Voltage

Reference

GND

BATT

Charger

Detect

DATA BUS

VFET

VREG

Voltage

Regulator

Voltage Regulator

Monitor Interface

PORTC (2)

PC1 (External Protection Input)

PC1:0

An integrated, low-dropout linear regulator that can handle input voltages as low as 2.1V,

ensures that the stored energy can be fully exploited. The regulator capabilities, combined

with a extremely low power consumption in the power saving modes, greatly enhances the cell

energy utilization compared to existing solutions.

The chip utilizes Atmel's Deep Under-voltage Recovery (DUVR) mode that supports pre-

charging of deeply discharged battery cells without using a separate Pre-charge FET. An

enhanced start-up scheme allows the chip to operate correctly even with only Discharge FET

connected. This makes it possible to further reduce system cost for applications that do not

require Charge Over-current protection.

The ATmega4HVD/8HVD contains a 10-bit ADC for cell voltage measurements. The ADC is

also used to monitor the on-chip temperature. Temperature is measured by the integrated

Voltage Reference, which contains a built-in temperature sensor. ATmega4HVD/8HVD con-

4

8052BS–AVR–09/08

ATmega4HVD/8HVD

tains a high-voltage tolerant, open-drain IO pin that supports serial communication.

Programming can be done in-system using the 4 General Purpose IO ports that support SPI

programming

The MCU includes 4K/8K bytes of In-System Programmable Flash with Self-programming

capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 4

general purpose I/O lines, debugWIRE for On-chip debugging and SPI for In-system Program-

ming, two flexible Timer/Counters with Input Capture, internal and external interrupts, a 10-bit

ADC for measuring the cell voltage and on-chip temperature, a programmable Watchdog

Timer with wake-up capabilities, and software selectable power saving modes.

The AVR core combines a rich instruction set with 32 general purpose working registers. All

the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two inde-

pendent registers to be accessed in one single instruction executed in one clock cycle. The

resulting architecture is more code efficient while achieving throughputs up to ten times faster

than conventional CISC microcontrollers.

The device is manufactured using Atmel’s high voltage high density non-volatile memory tech-

nology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System,

by a conventional non-volatile memory programmer or by an On-chip Boot program running

on the AVR core.

The ATmega4HVD/8HVD AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and

On-chip Debugger.

The ATmega4HVD/8HVD is a low-power CMOS 8-bit microcontroller based on the AVR archi-

tecture. It is part of the AVR Smart Battery family that provides secure authentication, highly

accurate monitoring and autonomous protection for Lithium-ion battery cells.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5

8052BS–AVR–09/08

ATmega4HVD/8HVD

5. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

Reserved

BPPLR

–

BPPL

–

DOCD

–

COCD

–

BPPLE

BPCR

EPID

–

SCD

–

Reserved

BPOCTR

BPSCTR

Reserved

BPCOCD

BPDOCD

BPSCD

–

OCTR[5:0]

SCTR[6:0]

–

COCDL[7:0]

DOCDL[7:0]

SCDL[7:0]

Reserved

BPIFR

–

SCIF

SCIE

–

DOCIF

COCIF

–

BPIMSK

Reserved

FCSR

–

DOCIE

COCIE

–

DUVRD

CPS

DFE

CFE

Reserved

ROCR

–

ROCS

–

RSCDEN

RSCWIF

RSCWIE

Reserved

–

Reserved

–

Reserved

–

6

8052BS–AVR–09/08

ATmega4HVD/8HVD

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

Reserved

OCR1B

–

Timer/Counter1 - Output Compare Register B

Timer/Counter1 - Output Compare Register A

OCR1A

Reserved

TCNT1H

TCNT1L

–

Timer/Counter1 - Counter Register High Byte

Timer/Counter1 - Counter Register Low Byte

Reserved

TCCR1B

TCCR1A

Reserved

DIDR0

–

CS12

CS11

CS10

WGM10

–

TCW1

ICEN1

ICNC1

ICES1

ICS1

–

PB0DID

7

8052BS–AVR–09/08

ATmega4HVD/8HVD

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7D)

(0x7C)

Reserved

ADCSRA

ADCH

–

(0x7B)

–

ADEN

–

ADSC

–

(0x7A)

ADIF

–

ADIE

–

ADMUX1

ADC9

ADMUX0

ADC8

(0x79)

(0x78)

ADCL

ADC[7:0]

(0x77)

Reserved

TIMSK1

TIMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

(0x6F)

ICIE1

OCIE1B

OCIE1A

TOIE1

(0x6E)

ICIE0

OCIE0B

OCIE0A

TOIE0

(0x6D)

–

(0x6C)

–

(0x6B)

–

(0x6A)

–

(0x69)

ISC11

ISC10

ISC01

ISC00

(0x68)

Reserved

FOSCCAL

Reserved

PRR0

–

(0x67)

(0x66)

Fast Oscillator Calibration Register

(0x65)

–

(0x64)

–

PRVRM

–

PRSPI

PRTIM1

PRTIM0

PRADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS1

CLKPS0

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

I

T

H

S

V

N

Z

C

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPL

SP7

–

SP6

–

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

CTPB

–

RFLB

–

SIGRD

PGWRT

PGERS

SPMEN

–

CKOE

PUD

OCDRF

–

WDRF

SM2

–

EXTRF

SM0

–

PORF

SE

–

SM1

–

Reserved

DWDR

–

debugWIRE Data Register

Reserved

GPIOR2

GPIOR1

OCR0B

–

General Purpose I/O Register 2

General Purpose I/O Register 1

Timer/Counter0 - Output Compare Register A

Timer/Counter0 - Output Compare Register B

Timer/Counter0 - Counter Register High Byte

Timer/Counter0 - Counter Register Low Byte

OCR0A

TCNT0H

TCNT0L

TCCR0B

TCCR0A

GTCCR

Reserved

EEARL

–

TCW0

TSM

–

ICS0

–

CS02

CS01

CS00

WGM00

PSR

ICEN0

ICNC0

ICES0

–

EEPROM Address Register

EEPROM Data Register

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

EIMSK

General Purpose I/O Register 0

–

INT1

INT0

EIFR

INTF1

INTF0

8

8052BS–AVR–09/08

ATmega4HVD/8HVD

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved

OSICSR

TIFR1

–

OSISEL0

–

OSIST

OSIEN

–

ICF1

ICF0

–

OCF1B

OCF1A

TOV1

TIFR0

OCF0B

OCF0A

TOV0

Reserved

PORTC

–

PORTC1

–

PORTC0

–

Reserved

PINC

–

PINC1

PORTB1

DDB1

PINB1

–

PINC0

PORTB0

DDB0

PINB0

–

PORTB

–

PORTB2

DDRB

–

DDB2

PINB

–

PINB2

Reserved

–

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-

isters, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-

ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega4HVD/8HVD is a

complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the

IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

9

8052BS–AVR–09/08

ATmega4HVD/8HVD

6. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

2

ADC

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

ADIW

SUB

SUBI

SBC

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

Rd ← Rd ⊕ Rr

Z,N,V

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

CBR

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

INC

Z,N,V

DEC

Rd

Decrement

Rd ← Rd − 1

Z,N,V

TST

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Z,N,V

CLR

Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

SER

Rd

Set Register

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

Z,C

MULS

MULSU

FMUL

FMULS

FMULSU

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

JMP

k

Direct Jump

PC ← k

3

RCALL

ICALL

CALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

k

Direct Subroutine Call

Subroutine Return

PC ← k

4

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

k

10

8052BS–AVR–09/08

ATmega4HVD/8HVD

Mnemonics

Operands

Description

Operation

Flags

#Clocks

BRVC

BRIE

BRID

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

None

1/2

Branch if Interrupt Enabled

Branch if Interrupt Disabled

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

-

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rd ← P

1

OUT

Out Port

P ← Rr

11

8052BS–AVR–09/08

ATmega4HVD/8HVD

Mnemonics

Operands

Description

Operation

Flags

#Clocks

PUSH

POP

Rr

Rd

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

None

2

None

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

12

8052BS–AVR–09/08

ATmega4HVD/8HVD

7. Ordering Information

7.1

ATmega4HVD

Speed (MHz)

1 - 4 MHz

Power Supply

Ordering Code

Package

18M1

Operation Range

2.0 - 2.4V

ATmega4HVD-4MX

-20 - 85°C

Note:

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and

minimum quantities.

Package Type

18M1

18-pad (Staggered Dual-row) 6.5 x 3.5 x 0.80 mm Body. 3.20 x 2.00 mm Exposed Pad, (MLF)

13

8052BS–AVR–09/08

ATmega4HVD/8HVD

7.2

ATmega8HVD

Speed (MHz)

1 - 4 MHz

Power Supply

Ordering Code

Package

18M1

Operation Range

2.0 - 2.4V

ATmega8HVD-4MX

-20 - 85°C

Note:

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and

minimum quantities.

Package Type

18M1

18-pad (Staggered Dual-row) 6.5 x 3.5 x 0.80 mm Body. 3.20 x 2.00 mm Exposed Pad, (MLF)

14

8052BS–AVR–09/08

ATmega4HVD/8HVD

8. Packaging Information

8.1

18M1

D

C

Pin 1 ID

E

SIDE VIEW

y

TOP VIEW

A1

A

eR

D2

B10

B1

A8

A1

A2

COMMON DIMENSIONS

(Unit of Measure = mm)

eT

B9

B2

A7

R0.20

0.40

MIN

0.70

0.00

0.23

MAX

0.80

0.05

0.33

NOM

0.75

0.02

0.28

0.20 REF

6.50

3.20

3.50

2.00

0.70

0.40

–

NOTE

SYMBOL

eT/2

B3

B8

E2

A

A6

A5

A3

A1

b

B4

B5

B7

B6

A4

b

C

D

6.40

3.15

3.40

1.95

–

6.60

3.25

3.60

2.05

–

L

D2

E

BOTTOM VIEW

E2

eT

eR

L

–

1. The terminal #1 ID is a Laser-marked Feature.

Note:

0.35

0.00

0.45

0.075

y

3/21/07

DRAWING NO. REV.

18M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

18M1, 18-pad (Staggered Dual-row), 6.5 x 3.5 x 0.80 mm Body,

B

3.20 x 2.00 mm Exposed Pad, MicroLeadFrame^®Package (MLF)

R

15

8052BS–AVR–09/08

ATmega4HVD/8HVD

9. Errata

9.1

ATmega4HVD

9.1.1

All revisions

No known errata.

9.2

ATmega8HVD

9.2.1

All revisions

16

8052BS–AVR–09/08

ATmega4HVD/8HVD

10. Datasheet Revision History

10.1 Rev. B - 09/08

1.

Updated Table 20-2 on page 110 and Table 20-3 on page 111 in the Register sum-

mary of section of ”Battery Protection” on page 104.

10.2 Rev.A - 09/08

Initial revision.

17

8052BS–AVR–09/08

Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Atmel Europe

Le Krebs

Atmel Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

Yvelines Cedex

France

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

avr@atmel.com

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF

THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8052BS–AVR–09/08


型号：	ATMEGA8HVD
厂家：	ATMEL
描述：	8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash 8 -bit微控制器4K / 8K字节的系统内可编程闪存闪存微控制器
文件：	总18页 (文件大小：277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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