ATR0797-6CPH [ATMEL]
65-300 MHZ SIGE IF RECEIVER DEMODULATOR; 65-300 MHZ SIGE中频接收机解调器
| 型号： | ATR0797-6CPH |
| 厂家： | 
ATMEL |
| 描述： | 65-300 MHZ SIGE IF RECEIVER DEMODULATOR |
| 文件： | 总11页 (文件大小：473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Gain Control in 20-dB Steps
• Very Low I/Q Amplitude and Phase Errors
• High Input P1dB
• Small and Optimized Package for High Reliability and Performance
Applications
65 - 300 MHz
SiGe IF
• Infrastructure Digital Communication Systems
• GSM/Cellular Transceivers
• ISM Band Transceivers
Receiver/
Demodulator
Benefits
• Fully Integrated Device with Reduced External Component Count
ATR0797
Electrostatic sensitive device.
Observe precautions for handling.
Description
The ATR0797 is a multi-purpose demodulator RFIC. The silicon monolithic integrated
circuit is designed with Atmel’s advanced SiGe technology. This demodulator is capa-
ble of both quadrature demodulation or direct IF output. Features include switchable
gain control on a frequency range from 65 MHz to 300 MHz. The device performs a
very low amplitude as well as phase error and allows high input P1dB. The ATR0797
targets a variety of system applications for communications including 3G wireless.
Figure 1. Block Diagram
GC1
GC2
5
4
2
1
BBIP
BBIN
8
9
IFP
IFN
ϕ
16
15
BBQP
BBQN
13 12
Rev. 4665D–SIGE–08/04
Pin Configuration
Figure 2. Pinning
BBIN
BBIP
VCC
GC2
GC1
GND
VCC
IFP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BBQP
BBQN
VCC
LOP
LON
GND
VCC
IFN
Pin Description
Pin
Symbol
BBIN
BBIP
VCC
GC2
GC1
GND
VCC
IFP
Function
1
Baseband I-axis negative output, self biasing
Baseband I-axis positive output, self biasing
5 V power supply
2
3
4
Gain control input, stage 2, 5 V CMOS levels
Gain control input, stage 1, 5 V CMOS levels
Ground
5
6
7
5 V power supply
8
IF positive input, self biasing, AC-coupled
IF negative input, self biasing, AC-coupled
5 V power supply
9
IFN
10
11
12
13
14
15
16
VCC
GND
LON
LOP
Ground
Local oscillator, negative input, self biasing, AC-coupled
Local oscillator, positive input, self biasing, AC-coupled
5 V power supply
VCC
BBQN
BBQP
Baseband Q-axis negative output, self biasing
Baseband Q-axis positive output, self biasing
2
ATR0797
4665D–SIGE–08/04
ATR0797
Product Description
Atmel’s ATR0797 is a variable gain I-Q demodulator designed for use in receiver IF sec-
tions, that are typically existing in superheterodyne RF architectures.
The ATR0797 has two gain stages that are independent of each other. These gain
stages are broadband differential amplifiers each with a digital control pin to set the
gain. Since the amplifiers have approximately the same gain, setting GC1 high and GC2
low results in approximately the same gain as setting GC1 low and GC2 high. Former
setting offers better noise figures.
The IF input is a differential input that has internal bias circuitry to set the common mode
voltage. The use of blocking capacitors to facilitate AC coupling is highly recommended
to avoid changing the common mode voltage. Either input may be driven single ended if
the other input is connected to ground through an AC short such as a 1000 pF capacitor.
This typically results in slightly lower input P1dB.
The two matched mixers are configured with the quadrature LO generator to provide in-
phase and quadrature baseband outputs.
The LO and IF ports offer a differential 50 Ω impedance. The passives at these ports
(parallel L-R network) and the package itself adds inductance that tends to degrade
return loss.
The ATR0797 features immunity from changes in LO power. The gain features change
by less than 0.6 dB over a 6 dB range of LO power. Also note the excellent I/Q balance,
which typically falls within 0.1 dB and 1 degree from 65 MHz to 300 MHz, and varies
less than 0.05 dB and 0.5 degree over temperature (-40°C to +85°C).
The frequency response of the IF and LO ports is dominated by the L-R network on the
input. When de-embedded, the gain and P1dB response is within 0.5 dB from 65 MHz to
300 MHz.
The figures in the datasheet illustrate a typical ATR0797’s performance with respect to
temperature. Note that these numbers include the effect of the R-L network in the IF
port.
Evaluation board design and equipment constraints:
Please take into account that the evaluation board uses baluns on the I/Q outputs, and
these baluns limit the low frequency response of the device. For true baseband opera-
tion, the baluns should be removed, and the differential signals used directly.
The 27 pF capacitor on the evaluation board is appropriate for lower frequencies.
3
4665D–SIGE–08/04
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referred to GND.
Parameters
Symbol
VCC
Value
5.5
Unit
V
Supply voltage
LO input
LOP, LON
IFN, IFP
TOP
10
dBm
V
IF input
10
Operating temperature
Storage temperature
-40 to +85
-65 to +150
°C
Tstg
°C
Note:
The device may not survive all maximums applied simultaneously.
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
35
K/W
Electrical Characteristics
Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz
IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type(1)
IF Input (I/Q Mixing to Baseband)
120 -
220
1.1
1.2
Frequency range
8-9
8-9
8, 9
f
65
300
MHz
dB
B
D
50 Ω nominal
IF input return loss
RL
20
differential input(2)
IF input common
mode voltage
1.3
1.4
Internally generated
VCH
G
2
V
Gain
2-1,
16-15
32
35
38
17
dB
A
C
D
A
C
D
1.5
1.6
1.7
1.8
1.9
Input P1dB
DSB Noise figure
Gain
Gain set = high;
GC1 = GC2 = 1
1, 2,
15, 16
P1dB
NF
-29
-27
11
dBm
dB
2-1,
16-15
2-1,
16-15
G
12
-8
15
dB
Gain set = medium;
GC1 = 1; GC2 = 0 or
GC1 = 0; GC2 = 1
Input P1dB
DSB Noise figure
1, 2,
15, 16
P1dB
NF
-6
dBm
dB
2-1,
14.5
16-15
Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series
capacitor to achieve 20 dB of port match.
3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
4
ATR0797
4665D–SIGE–08/04
ATR0797
Electrical Characteristics (Continued)
Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz
IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm
IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type(1)
1.10
Gain
2-1,
G
-7
-4
-2
dB
A
16-15
1.11
1.12
Input P1dB
Gain set = low;
GC1 = GC2 = 0
1, 2,
15, 16
P1dB
NF
12
14
31
dBm
dB
C
D
DSB Noise figure
2-1,
16-15
2
I/Q Output
I/Q output frequency
range
1, 2,
15, 16
2.1
fI/Q
DC
-0.2
-2
500
+0.2
+2
MHz
dB
D
A
A
A
A
D
I/Q output amplitude
error
2-1,
16-15
2.2
2.3
2.4
2.5
2.6
2-1,
16-15
I/Q phase error
deg
V
I/Q output common
mode voltage
1, 2,
15, 16
2.5
20
I/Q output differential
offset voltage
2-1,
16-15
Voffset
RLI/Q
-100
+100
mV
dB
50 Ω nominal
1, 2,
15, 16
I/Q output return loss
differential output(3)
3
LO input
3.1
3.2
3.3
4
LO input level
Return loss
13-12
13-12
13-12
PLO
-3
0
+3
dBm
dB
D
D
D
RLLO
RLLO
20
LO frequency range
Miscellaneous
65
300
MHz
3, 7,
10, 14
4.1
4.2
4.3
4.4
4.5
Supply voltage
Supply current
VCC
ICC
VIL
VIH
Z
4.75
5
5.25
V
mA
V
A
A
D
D
D
3, 7,
10, 14
195
GC1, GC2 logic level
low
0.3 ×
VCC
4, 5
4, 5
4, 5
0
GC1, GC2 logic level
high
0.7 ×
VCC
VCC
V
GC1, GC2 input
impedance
40
kΩ
Notes: 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series
capacitor to achieve 20 dB of port match.
3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz.
5
4665D–SIGE–08/04
Figure 3. Gain versus Temperature
35
30
25
High Gain
20
15
10
5
Med Gain
0
-5
Low Gain
-10
-40
-20
0
20
40
60
80
100
100
800
Temperature (°C)
Figure 4. Noise Figure versus Temperature
35
Low Gain
30
25
20
15
10
5
Med Gain
High Gain
0
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 5. Amplitude Difference versus LO Frequency
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
0
100
200
300
400
500
600
700
LO Frequency (MHz)
6
ATR0797
4665D–SIGE–08/04
ATR0797
Figure 6. Output P1dB versus Temperature
10
9
8
7
6
5
Low Gain
High Gain
Med Gain
60
-40
-20
0
20
40
80
100
Temperature (°C)
Figure 7. Output P1dB versus LO Power
10
9
8
7
6
5
Low Gain
High Gain
Med Gain
-4
-3
-2
-1
0
1
2
3
4
Temperature (°C)
Figure 8. Phase Difference versus LO Frequency
92.0
91.5
91.0
90.5
90.0
89.5
89.0
0
100
200
300
400
500
600
700
800
LO Frequency (MHz)
7
4665D–SIGE–08/04
Figure 9. Demo Test Board Schematic
J3
J4
J2
L2
C4
C3
R5
C9
L3
C5
C6
L4
R4
C8
BBIN
BBIP
BBQP
BBQN
J1
C10
R6
C7
R3
L1
VCC
D1
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
C13
VCC
J5
R7
R8
C12
C11
LOin
GC2
C14
GC1
T3
VCC
VCC
C15
VCC
C16
R10
L5
L6
C18
R9
5 V
C17
L7
C19
T4
H2
J6
Table 1. Bill of Materials
Component
Reference
Vendor
Atmel
Part Number
Value
Size/Package
IF Demodulator
D1
ATR0797
PSSO16
SMA end launch
connector
Johnson
J1, J2, J3, J4, J5, J6
742-0711-841
TC1-1
Components™
Mini-Circuits®
Transformer
T3, T4
C19
Supply bypass
capacitor
1 µF
1206
Resistor
Capacitor
Inductor
Capacitor
Resistor
R7, R8
1 kΩ
22 pF
1 µH
68 pF
0 Ω
0402
0402
1210
0402
0402
C11, C12, C16
L1, L2, L3, L4, L7
C13, C14, C17, C18
R3, R4, R5, R6
Würth Elektronik®
74476401
C3, C4, C5, C6, C7, C8,
C9, C10
Capacitor
820 pF
0402
Resistor
Inductor
Capacitor
R9, R10
L5, L6
C15
51 Ω
10 nH
100 pF
0402
0402
0402
8
ATR0797
4665D–SIGE–08/04
ATR0797
Figure 10. Demo Test Board (Fully Assembled PCB)
Figure 11. Recommended Package Footprint
1.25
3.0
0.25
0.74
0.4
0.74
3.0
φ0.33 via
0.7
0.9
6.9
all units are in mm
- Indicates metalization
- vias connect pad to underlying ground plane
Remark: Heatslug must be soldered to GND.
In order to avoid soldering problems, plugging of the vias under the heatslug is recom-
mended. Only ground signal traces are allowed directly under the package.
9
4665D–SIGE–08/04
Ordering Information
Extended Type Number
Package
Remarks
ATR0797-6CPH
PSSO16
Lead free
Package Information
10
ATR0797
4665D–SIGE–08/04
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Fax: (44) 1355-242-743
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© Atmel Corporation 2004. All rights reserved.
Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Johnson Components™ is a trademark
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4665D–SIGE–08/04
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