ATSAM3X4CA-CU [ATMEL]
AT91SAM ARM-based Flash MCU; AT91SAM基于ARM的闪存微控制器
| 型号： | ATSAM3X4CA-CU |
| 厂家： | 
ATMEL |
| 描述： | AT91SAM ARM-based Flash MCU |
| 文件： | 总71页 (文件大小：851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Core
– ARM® Cortex®-M3 revision 2.0 running at up to 84 MHz
– Memory Protection Unit (MPU)
– Thumb®-2 instruction set
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
• Memories
–
From 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
– From 32 to 100 Kbytes embedded SRAM with dual banks
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash
controller with 4-kbyte RAM buffer and ECC
AT91SAM
ARM-based
Flash MCU
• System
– Embedded voltage regulator for single supply operation
– POR, BOD and Watchdog for safe reset
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power
32.768 kHz for RTC or device clock.
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default
Frequency for fast device startup
– Slow Clock Internal RC oscillator as permanent clock for device clock in low power
mode
– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini
Host/Device
– Temperature Sensor
SAM3X
SAM3A
Series
– Up to 17 peripheral DMA (PDC) channels and 6-channel central DMA plus
dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC
• Low Power Modes
– Sleep and Backup modes, down to 2.5 µA in Backup mode.
– Backup domain: VDDBU pin, RTC, eight 32-bit backup registers
– Ultra Low-power RTC
Summary
• Peripherals
– USB 2.0 Device/Mini Host: 480 Mbps, 4-kbyte FIFO, up to 10 bidirectional
Endpoints, dedicated DMA
– Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester and LIN support)
and one UART
– 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up
to 2 slots
– 9-Channel 32-bit Timer/Counter (TC) for capture, compare and PWM mode,
Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
– Up to 8-channel 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-
bit Dead Time Generator Counter for Motor Control
– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features
– 16-channel 12-bit 1Msps ADC with differential input mode and programmable gain
stage
– One 2-channel 12-bit 1 Msps DAC
– One Ethernet MAC 10/100 (EMAC) with dedicated DMA
– Two CAN Controller with eight Mailboxes
– One True Random Number Generator (TRNG)
– Write Protected Registers
• I/O
– Up to 103 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Up to Six 32-bit Parallel Input/Outputs (PIO)
• Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
– 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
– 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
11057BS–ATARM–13-Jul-12
1. SAM3X/A Description
Atmel’s SAM3X/A series is a member of a family of Flash microcontrollers based on the high
performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of
84 MHz and features up to 512 Kbytes of Flash and up to 100 Kbytes of SRAM. The peripheral
set includes a High Speed USB Host and Device port with embedded transceiver, an Ethernet
MAC, 2x CANs, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface with NAND
Flash controller, 5x UARTs, 2x TWIs, 4x SPIs, as well as 1 PWM timer, 9x general-purpose 32-
bit timers, an RTC, a 12-bit ADC and a 12-bit DAC.
The SAM3X/A series is ready for capacitive touch thanks to the QTouch library, offering an easy
way to implement buttons, wheels and sliders.
The SAM3X/A architecture is specifically designed to sustain high speed data transfers. It
includes a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that
enable it to run tasks in parallel and maximize data throughput.
It operates from 1.62V to 3.6V and is available in 100- and 144-pin QFP and LFBGA packages.
The SAM3X/A devices are particularly well suited for networking applications: industrial and
home/building automation, gateways.
4
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
1.1
Configuration Summary
The SAM3X/A series devices differ in memory sizes, package and features list. Table 1-1 below
summarizes the configurations.
Table 1-1.
Feature
Configuration Summary
SAM3X8E
SAM3X8C
SAM3X4E
SAM3X4C
SAM3A8C
SAM3A4C
Flash
2 x 256 Kbytes 2 x 256 Kbytes 2 x 128 Kbytes 2 x 128 Kbytes 2 x 256 Kbytes 2 x 128 Kbytes
32 + 32
64 + 32 Kbytes 64 + 32 Kbytes 32 + 32 Kbytes 32 + 32 Kbytes 64 + 32 Kbytes
Kbytes
SRAM
Nand Flash
Controller
(NFC)
Yes
-
-
Yes
-
-
-
-
-
-
NFC SRAM(1)
4K bytes
4K bytes
LQFP144
LFBGA144
LQFP100
LFBGA100
LQFP144
LFBGA144
LQFP100
LFBGA100
LQFP100
LFBGA100
LQFP100
LFBGA100
Package
Number of
PIOs
103
63
103
63
63
63
SHDN
Pin
Yes
No
Yes
No
No
-
No
-
EMAC
MII/RMII
RMII
MII/RMII
RMII
External
Bus
Interface
16-bit data,
8 chip selects,
23-bit address
16-bit data,
8 chip selects,
23-bit address
-
-
-
-
Central DMA
12-bit ADC
12-bit DAC
32-bit Timer
6
4
6
4
4
4
16 ch.(2)
2 ch.
9(5)
16 ch.(2)
2 ch.
9(6)
16 ch.(2)
2 ch.
9(5)
16 ch.(2)
2 ch.
9(6)
16 ch.(2)
2 ch.
9(5)
16 ch.(2)
2 ch.
9(5)
PDC
Channels
17
15
17
15
15
15
USART/
UART
3/2(7)
3/1
3/2(7)
3/1
3/1
3/1
SPI (3)
1/4 + 3
1/4 + 3
1/4 + 3
1/4 + 3
1/4 + 3
1/4 + 3
1 slot
8 bits
1 slot
4 bits
1 slot
8 bits
1 slot
4 bits
1 slot
4 bits
1 slot
4 bits
HSMCI
Notes: 1. 4 Kbytes RAM buffer of the NAND Flash Controller (NFC) which can be used by the core if not
used by the NFC
2. One channel is reserved for internal temperature sensor
3. 2 / 8 + 4 = Number of SPI Controllers / Number of Chip Selects + Number of USART with SPI
Mode
4. 9 TC channels are accessible through PIO
5. 6 TC channels are accessible through PIO
6. 3 TC channels are accessible through PIO
7. USART3 in UART mode (RXD3 and TXD3 available)
5
11057BS–ATARM–13-Jul-12
2. SAM3X/A Block Diagram
Figure 2-1. SAM3A4/8C (100 pins) Block Diagram
Voltage
Regulator
System Controller
TST
PCK0-PCK2
JTAG & Serial Wire
PLLA
PMC
UPLL
XIN
XOUT
In-Circuit Emulator
OSC
24-Bit
SysTic Counter
N
V
I
WDT
Cortex-M3 Processor
Fmax 84 MHz
SM
Flash
SRAM0
SRAM1
RC
12/8/4 M
ROM
16 KBytes
2x256 KBytes 64 KBytes 32 KBytes
2x128 KBytes 32 KBytes 32 KBytes
2x64 KBytes 16 KBytes 16 KBytes
C
MPU
I/D
SUPC
FWUP
XIN32
XOUT32
S
OSC 32K
RC 32K
ERASE
6-layer AHB Bus Matrix Fmax 84MHz
8
GPBREG
VBUS
DFSDM
DFSDP
DHSDM
DHSDP
UOTGVBOF
UOTGID
RTT
RTC
POR
USBOTG
DMA FIFO Device
Low Power
Peripheral
Bridge
Peripheral
DMA
Controller
HS
VDDBU
VDDCORE
VDDUTMI
NRST
RSTC
PIOA
PIOC
PIOB
4-Channel
TRNG
DMA
DMA
PDC
TWCK0
TWD0
TWI0
TWI1
TWCK1
TWD1
PDC
URXD
UTXD
UART
PDC
DMA
TXD0
SCK0
RTS0
CTS0
USART0
PDC
DMA
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
USART1
USART2
PDC
PDC
CANRX0
CANTX0
CAN0
CAN1
CANRX1
CANTX1
TCLK[0:2]
Timer Counter A
High Performance
Peripheral
TIOA[0:2]
TIOB[0:2]
TC[0..2]
Bridge
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
MISO0
DMA DMA
Timer Counter B
TC[3..5]
TCLK[3:5]
SPI0
TIOA[3:5]
TIOB[3:5]
MOSI0
SPCK0
Timer Counter C
TC[6..8]
DMA DMA
TF
TK
TD
RD
RK
RF
PWMH[0:3]
PWML[0:7]
PWMFI[0:1]
DMA
PWM
SSC
DMA DMA
HSMCI
PDC
Temp.
Sensor
ADTRG
AD[0..14]
ADC
PDC
PDC
ADVREF
DAC0
DAC1
MCCK
MCCDA
MCDA[0..3]
DAC
DATRG
6
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 2-2. SAM3X4/8C (100 pins) Block Diagram
Voltage
Regulator
System Controller
TST
PCK0-PCK2
JTAG & Serial Wire
PLLA
UPLL
PMC
XIN
OSC
12M
In-circuit Emulator
XOUT
24-Bit
SysTick Counter
N
V
I
WDT
Cortex-M3 Processor
Fmax 84MHz
FLASH
2x256 KBytes
2x128 KBytes 32 KBytes 32 KBytes
2x64 KBytes 16 KBytes
SRAM1
32 KBytes
SRAM0
64 KBytes
SM
RC
12/8/4 M
ROM
16 KBytes
C
16 KBytes
MPU
I/D
SUPC
FWUP
XIN32
XOUT32
S
OSC 32K
RC 32k
ERASE
6-layer AHB Bus Matrix Fmax 84MHz
8
VBUS
GPBREG
DFSDM
DFSDP
USBOTG
FIFO Device
RTT
Peripheral
DMA
Controller
DHSDM
DHSDP
UOTGVBOF
UOTGID
Low Power
Peripheral
Bridge
DMA
RTC
HS
VDDBU
POR
VDDCORE
VDDUTMI
NRST
EREFCK
ETXEN
ECRSDV
ERXER
ERX0-ERX1
ETX0-ETX1
EMDC
EMDIO
RSTC
FIFO
Ethernet
MAC
RMII
DMA
128-Byte TX
PIOA
PIOC
128-Byte RX
PIOB
4-Channel
TRNG
DMA
DMA
PDC
TWCK0
TWD0
TWI0
TWI1
UART
TWCK1
TWD1
PDC
URXD
UTXD
PDC
DMA
RXD0
TXD0
SCK0
RTS0
CTS0
USART0
USART1
PDC
DMA
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
PDC
PDC
USART2
CANRX0
CANTX0
CAN0
CAN1
CANRX1
CANTX1
TCLK[0:2]
TimerCounter A
High Performance
Peripherals
Bridge
TIOA[0:2]
TIOB[0:2]
TC[0..2]
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
MISO0
DMA
SPI0
TimerCounter B
TC[3..5]
MOSI0
SPCK0
TimerCounter C
TC[6..8]
DMA
DMA
TF
TK
TD
RD
RK
RF
DMA
PWMH[0:3]
PWML[0:3]
PWMFI[0:1]
PWM
SSC
PDC
Te mp .
Sensor
ADTRG
AD[0..14]
ADC
PDC
PDC
ADVREF
DAC0
DAC1
MCCK
MCCDA
MCDA[0..3]
HSMCI
DAC
DATRG
7
11057BS–ATARM–13-Jul-12
Figure 2-3. SAM3X4/8E (144 pins) Block Diagram
Voltage
Regulator
System Controller
TST
PCK0-PCK2
JTAG & Serial Wire
PLLA
UPLL
OSC
PMC
XIN
XOUT
In-circuit Emulator
24-Bit
N
V
I
WDT
SysTick Counter
Cortex-M3 Processor
Fmax 84MHz
SM
FLASH
2x256 KBytes
2x128 KBytes
SRAM1
SRAM0
RC
12/8/4 M
ROM
16 KBytes
32 KBytes
32 KBytes
16 KBytes
64 KBytes
32 KBytes
16 KBytes
C
SHDN
FWUP
XIN32
MPU
I/D
2x64 KBytes
SUPC
S
OSC 32K
XOUT32
RC 32K
ERASE
6-layer AHB Bus Matrix Fmax 84MHz
8
GPBREG
VBUS
DFSDM
DFSDP
RTT
USBOTG
FIFO Device
Low Power
Peripheral
Bridge
Peripheral
DMA
Controller
NRSTB
DHSDM
DHSDP
UOTGVBOF
UOTGID
DMA
DMA
RTC
POR
HS
VDDBU
VDDCORE
VDDUTMI
NRST
ETXCK-ERXCK-EREFCK
ETXER-ETXDV
ECRS-ECOL, ECRSDV
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
RSTC
FIFO
Ethernet
MAC
MII/RMII
128-Byte TX
128-Byte RX
PIOA
PIOB
PIOD
EMDIO
EF100
PIOC
PIOE
6-Channel
TRNG
DMA
DMA
PDC
TWCK0
TWD0
TWI0
TWI1
UART
EBI
TWCK1
TWD1
D[15:0]
A0/NBS0
A[0:23]
PDC
8-bit/16-bit
URXD
UTXD
RXD0
TXD0
SCK0
RTS0
CTS0
A21/NANDALE
A22/NANDCLE
A16
PDC
DMA
NAND Flash
A17
NCS0
NCS1
NCS2
NCS3
NRD
USART0
USART1
PDC
DMA
RXD1
TXD1
SCK1
RTS1
CTS1
RXD2
TXD2
SCK2
RTS2
CTS2
NWR0/NWE
NWR1
Static Memory
PDC
Controller
USART2
USART3
ECC
Controller
PDC
PDC
RXD3
TXD3
NANDRDY
NANDOE
NANDWE
NWAIT
CANRX0
CANTX0
CAN0
CAN1
4Ko FIFO
CANRX1
CANTX1
TCLK[0:2]
Timer Counter A
High Performance
Peripherals
TIOA[0:2]
TIOB[0:2]
TC[0..2]
Bridge
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
MISO0
DMA
Timer Counter B
TC[3..5]
SPI0
MOSI0
SPCK0
TCLK[6:8]
Timer Counter C
TC[6..8]
TIOA[6:8]
TIOB[6:8]
DMA
DMA
TF
TK
TD
RD
RK
RF
PWMH[0:6]
PWML[0:7]
PWMFI[0:2]
DMA
PWM
SSC
PDC
Temp..
Sensor
ADTRG
AD[0..14]
ADC
PDC
PDC
ADVREF
DAC0
DAC1
HSMCI
MCCK
MCCDA
MCDA[0..7]
DAC
DATRG
8
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
3. Signal Description
Table 3-1 gives details on the signal names classified by peripheral.
Signal Description List
Function
Table 3-1.
Active
Level
Voltage
Reference Comments
Signal Name
Type
Power Supplies
VDDIO
Peripherals I/O Lines Power Supply
USB UTMI+ Interface Power Supply
Voltage Regulator Output
Power
Power
Power
1.62V to 3.6V
3.0V to 3.6V
VDDUTMI
VDDOUT
Voltage Regulator, ADC and DAC Power
Supply
VDDIN
Power
GNDUTMI
VDDBU
USB UTMI+ Interface Ground
Backup I/O Lines Power Supply
Backup Ground
Ground
Power
1.62V to 3.6V
1.62 V to 1.95V
2.0V to 3.6V
GNDBU
VDDPLL
GNDPLL
VDDANA
GNDANA
VDDCORE
GND
Ground
Power
PLL A, UPLL and Oscillator Power Supply
PLL A, UPLL and Oscillator Ground
ADC and DAC Analog Power Supply
ADC and DAC Analog Ground
Core Chip Power Supply
Ground
Power
Ground
Power
1.62V to 1.95V
Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
Output
Input
VDDPLL
VDDBU
XOUT
Main Oscillator Output
Slow Clock Oscillator Input
XIN32
XOUT32
VBG
Slow Clock Oscillator Output
Bias Voltage Reference
Output
Analog
PCK0 - PCK2
Programmable Clock Output
Output
Shutdown, Wakeup Logic
0: The device is in
backup mode
SHDN
FWUP
Shut-Down Control
Force Wake-up Input
Output
Input
VDDBU
VDDBU
1: The device is
running (not in
backup mode)
Needs external Pull-
up
9
11057BS–ATARM–13-Jul-12
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
ICE and JTAG
TCK/SWCLK
TDI
Test Clock/Serial Wire Clock
Test Data In
Input
Input
Reset State:
- SWJ-DP Mode
VDDIO
Test Data Out / Trace Asynchronous Data
Out
TDO/TRACESWO
TMS/SWDIO
JTAGSEL
Output
Input / I/O
Input
- Internal pull-up
disabled(1)
Test Mode Select /Serial Wire
Input/Output
Permanent Internal
pull-down
JTAG Selection
High
High
VDDBU
Flash Memory
Flash and NVM Configuration Bits
Erase Command
Input
VDDIO
Pull-down resistor
ERASE
Reset/Test
NRST
NRSTB
TST
Microcontroller Reset
I/O
Low
Low
VDDIO
VDDBU
VDDBU
Pull-up resistor
Pull-up resistor
Pull-down resistor
Asynchronous Microcontroller Reset
Test Mode Select
Input
Input
Universal Asynchronous Receiver Transceiver - UART
URXD
UTXD
UART Receive Data
UART Transmit Data
Input
Output
10
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE
•Schmitt Trigger(3)
Reset State:
•PIO Input
PA0 - PA31
PB0 - PB31
PC0 - PC30
PD0 - PD30
PE0 - PE31
PF0 - PF6
Parallel IO Controller A
I/O
I/O
I/O
I/O
I/O
I/O
•Internal pull-up
enabled
•Schmitt Trigger(4)
Reset State:
•PIO Input
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
Parallel IO Controller E
Parallel IO Controller F
•Internal pull-up
enabled
•Schmitt Trigger(5)
Reset State:
•PIO Input
•Internal pull-up
enabled
VDDIO
•Schmitt Trigger(6)
Reset State:
•PIO Input
•Internal pull-up
enabled
•Schmitt Trigger(7)
Reset State:
•PIO Input
•Internal pull-up
enabled
•Schmitt Trigger(7)
Reset State:
•PIO Input
•Internal pull-up
enabled
External Memory Bus
Pulled-up input at
reset
D0 - D15
A0 - A23
Data Bus
I/O
Address Bus
Output
0 at reset
Static Memory Controller - SMC
NCS0 - NCS7
NWR0 - NWR1
NRD
Chip Select Lines
Write Signal
Output
Output
Output
Output
Output
Input
Low
Low
Low
Low
Low
Low
Read Signal
NWE
Write Enable
NBS0 - NBS1
NWAIT
Byte Mask Signal
External Wait Signal
11
11057BS–ATARM–13-Jul-12
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
NAND Flash Controller-NFC
NANDOE
NANDWE
NANDRDY
NANDCLE
NANDALE
NAND Flash Output Enable
NAND Flash Write Enable
NAND Ready
Output
Output
Input
Low
Low
NAND Flash Command Line Enable
NAND Flash Address Line Enable
Output
Output
Low
Low
High Speed Multimedia Card Interface HSMCI
MCCK
Multimedia Card Clock
I/O
I/O
I/O
I/O
I/O
MCCDA
Multimedia Card Slot A Command
Multimedia Card Slot A Data
Multimedia Card Slot B Command
Multimedia Card Slot A Data
MCDA0 - MCDA7
MCCDB
MCDB0 - MCDB3
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
USARTx Serial Clock
I/O
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
I/O
Input
Output
Input
Ethernet MAC 10/100 - EMAC
EREFCK
ETXCK
ERXCK
ETXEN
Reference Clock
Transmit Clock
Receive Clock
Transmit Enable
Input
Input
RMII only
MII only
MII only
Input
Output
ETX0 -
ETX0 - ETX3
Transmit Data
Output
ETX1 only
in RMII
ETXER
ERXDV
ECRSDV
Transmit Coding Error
Receive Data Valid
Output
Input
MII only
MII only
RMII only
Carrier Sense and Data Valid
Input
ERX0 -
ERX0 - ERX3
Receive Data
Input
ERX1 only
in RMII
ERXER
ECRS
ECOL
Receive Error
Input
Input
Input
Output
I/O
Carrier Sense
MII only
MII only
Collision Detected
EMDC
EMDIO
Management Data Clock
Management Data Input/Output
CAN Controller - CANx
12
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
CANRXx
Function
Type
Input
CAN Input
CAN Output
CANTXx
Output
Synchronous Serial Controller - SSC
TD
RD
TK
RK
TF
RF
SSC Transmit Data
SSC Receive Data
SSC Transmit Clock
SSC Receive Clock
Output
Input
I/O
I/O
SSC Transmit Frame Sync
SSC Receive Frame Sync
I/O
I/O
Timer/Counter - TC
TCLKx
TIOAx
TIOBx
TC Channel x External Clock Input
TC Channel x I/O Line A
Input
I/O
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMHx
PWMLx
PWMFIx
PWM Waveform Output High for channel x
Output
Output
Input
only output in
complementary
mode when dead
time insertion is
enabled
PWM Waveform Output Low for
channel x,
PWM Fault Input for channel x
Serial Peripheral Interface - SPIx
MISOx
Master In Slave Out
Master Out Slave In
SPI Serial Clock
I/O
I/O
I/O
MOSIx
SPCKx
SPIx_NPCS0
SPI Peripheral Chip Select 0
SPI Peripheral Chip Select
I/O
Low
Low
SPIx_NPCS1 -
SPIx_NPCS3
Output
Two-Wire Interface- TWIx
TWDx
TWIx Two-wire Serial Data
TWIx Two-wire Serial Clock
I/O
I/O
TWCKx
Analog-to-Digital Converter - ADC
AD0 - AD14
ADTRG
Analog Inputs
ADC Trigger
Analog
Input
ADVREF
ADC and DAC Reference
Analog
Digital-to-Analog Converter - DACC
DAC0
DAC1
DATRG
DAC channel 0 analog output
Analog
Analog
DAC channel 1 analog output
DAC Trigger
13
11057BS–ATARM–13-Jul-12
Table 3-1.
Signal Description List (Continued)
Active
Level
Voltage
Reference Comments
Signal Name
Function
Type
Fast Flash Programming Interface
PGMEN0-PGMEN2
PGMM0-PGMM3
PGMD0-PGMD15
PGMRDY
Programming Enabling
Programming Mode
Programming Data
Programming Ready
Data Direction
Input
Input
I/O
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
Output
Output
Input
Input
Input
High
Low
Low
PGMNVALID
PGMNOE
Programming Read
Programming Clock
Programming Command
PGMCK
PGMNCMD
Low
USB Mini Host/Device High Speed Device
VBUS
USB Bus Power Measurement Port
Analog
Analog
Analog
Analog
Analog
DFSDM
DFSDP
DHSDM
DHSDP
USB Full Speed Data -
USB Full Speed Data +
USB High Speed Data -
USB High Speed Data +
VDDUTMI
VDDUTMI
VDDUTMI
VDDUTMI
USB VBus On/Off: Bus Power Control
Port
UOTGVBOF
UOTGID
VDDIO
VDDIO
USB Identification: Mini Connector
Identification Port
Notes: 1. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this
PIO line must be enabled to avoid current consumption due to floating input.
2. PIOA: Schmitt Trigger on all, except PA0, PA9, PA26, PA29, PA30, PA31
3. PIOB: Schmitt Trigger on all, except PB14 and PB22
4. PIOC: Schmitt Trigger on all, except PC2 to PC9, PC15 to PC24
5. PIOD: Schmitt Trigger on all, except PD10 to PD30
6. PIOE: Schmitt Trigger on all, except PE0 to PE4, PE15, PE17, PE19, PE21, PE23, PE25, PE29
7. PIOF: Schmitt Trigger on all PIOs
3.1
Design Considerations
In order to facilitate schematic capture when using a SAM3X/A design, Atmel provides a “Sche-
matics Checklist” Application Note. See http://www.atmel.com/products/AT91/
4. Package and Pinout
4.1
SAM3A4/8C and SAM3X4/8C Package and Pinout
The SAM3A4/8C and SAM3X4/8C are available in 100-lead LQFP and 100-ball LFBGA
packages.
14
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
4.1.1
100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
51
75
76
50
26
100
25
1
4.1.2
100-ball LFBGA Package Outline
Figure 4-2. Orientation of the 100-ball LFBGA Package
TOP VIEW
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K
BALL A1
15
11057BS–ATARM–13-Jul-12
4.1.3
100-lead LQFP Pinout
Table 4-1.
100-lead LQFP SAM3A4/8C and SAM3X4/8C Pinout
1
2
P B 2 6
PA9
2 6
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D H S D P
DHSDM
VBUS
5 1
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
V D DA N A
GNDANA
ADVREF
PB15
PB16
PA16
7 6
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PA 2 6
PA27
PA28
PA29
PB0
3
PA10
PA11
PA12
PA13
PA14
PA15
PA17
VDDCORE
VDDIO
GND
4
VBG
5
VDDUTMI
DFSDP
DFSDM
GNDUTMI
VDDCORE
JTAGSEL
XIN32
6
PB1
7
PA24
PB2
8
PA23
PB3
9
PA22
PB4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PA6
PB5
PA4
PB6
XOUT32
TST
PA3
PB7
PA0
PA2
PB8
PA1
VDDBU
FWUP
PB12
PB13
PB17
PB18
PB19
PB20
PB21
VDDCORE
VDDIO
GND
VDDCORE
VDDIO
GND
PB9
PA5
PA7
GND
PA8
VDDOUT
VDDIN
GND
PB28
PB29
PB30
PB31
GNDPLL
VDDPLL
XOUT
XIN
PB10
PB11
PC0
VDDCORE
PB27
PB14
PB22
PB23
PB24
PB25
NRST
PA18
PA19
PA21
PA20
PA25
16
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
4.1.4
100-ball LFBGA Pinout
Table 4-2.
A1
100-ball LFBGA SAM3X4/8E Package and Pinout
PB26
PB24
PB22
PB14
PC0
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
PB11
PB8
F1
F2
VDDPLL
GNDPLL
PB30
H6
H7
H8
H9
H10
J1
NRST
PA19
A2
A3
PB4
F3
PA4
A4
PB0
F4
PB29
PA6
A5
PA25
F5
GND
PA22
A6
PB9
PA5
F6
GND
VBUS
A7
PB6
PA0
F7
VDDIO
PB13
J2
DHSDP
DHSDM
JTAGSEL
XIN32
A8
PB2
PA1
F8
J3
A9
PA28
PA26
PA11
PB25
PB23
PA10
PA9
VDDCORE
VDDIO
VDDCORE
VDDCORE
PB5
F9
PB17
J4
A10
B1
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
PB18
J5
XOUT
VDDUTMI
PB31
J6
VDDIN
PA23
B2
J7
B3
J8
PA24
B4
PB1
GNDBU
PB27
J9
PB16
B5
PA21
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
PA16
B6
PB10
PB7
PB28
PA18
VBG
B7
PA7
PA20
DFSDP
DFSDM
VDDCORE
XOUT32
VDDOUT
VDDANA
GNDANA
ADVREF
PB15
B8
PB3
PA8
PA3
B9
PA29
PA27
PA12
PA14
PA13
PA17
PA15
VDDCORE
GND
PA2
B10
C1
PB12
GND
XIN
C2
VDDIO
PB19
GNDUTMI
TST
C3
C4
PB20
VDDBU
WAKEUP
C5
PB21
17
11057BS–ATARM–13-Jul-12
4.2
SAM3X4/8E Package and Pinout
The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages.
4.2.1
144-lead LQFP Package Outline
Figure 4-3. Orientation of the 144-lead LQFP Package
73
108
109
72
144
1
37
36
4.2.2
144-ball LFBGA Package Outline
The 144-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen-
sions are 10 x 10 x 1.4 mm.
Figure 4-4. Orientation of the 144-ball LFBGA Package
TOP VIEW
12
11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L
M
BALL A1
18
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
4.2.3
144-lead LQFP Pinout
Table 4-3.
1
144-lead LQFP SAM3X4/8E Pinout
PB26
PA9
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DHSDP
DHSDM
VBUS
73
74
VDDANA
GNDANA
ADVREF
PB15
PB16
PA16
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PA26
PA27
PA28
PA29
PB0
2
3
PA10
PA11
PA12
PA13
PA14
PA15
PA17
VDDCORE
VDDIO
GND
PD0
75
4
VBG
76
5
VDDUTMI
DFSDP
DFSDM
GNDUTMI
VDDCORE
JTAGSEL
NRSTB
XIN32
XOUT32
SHDN
TST
77
6
78
PB1
7
79
PA24
PB2
8
80
PA23
PC4
9
81
PA22
PC10
PB3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
82
PA6
83
PA4
PB4
84
PA3
PB5
85
PA2
PB6
PD1
86
PB12
PB13
PB17
PB18
PB19
PB20
PB21
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC29
PC30
VDDCORE
VDDIO
GND
PB7
PD2
87
PB8
PD3
VDDBU
FWUP
GNDBU
PC1
88
VDDCORE
VDDIO
GND
PB9
PD4
89
PD5
90
PD6
91
PD7
VDDOUT
VDDIN
GND
92
PB10
PB11
PC0
PD8
93
PD9
94
PA0
PC2
95
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PB14
PB22
PB23
PB24
PB25
PA1
PC3
96
PA5
VDDCORE
VDDIO
PC5
97
PA7
98
PA8
99
PB28
PB29
PB30
PB31
PD10
GNDPLL
VDDPLL
XOUT
XIN
PC6
100
101
102
103
104
105
106
107
108
PC7
PC8
PC9
PB27
NRST
PA18
PA19
PA21
PA20
PA25
19
11057BS–ATARM–13-Jul-12
4.2.4
144-ball LFBGA Pinout
Table 4-4.
A1
144-ball LFBGA SAM3X4/8E Pinout
PA9
PB23
PB14
PC26
PC24
PC20
PB10
PB6
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
PA17
PD0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
PA5
PA7
K1
K2
VDDCORE
GNDUTMI
VDDPLL
NRSTB
SHDN
PC3
A2
A3
PA11
PA15
PA14
PC27
PC25
VDDIO
PB5
PA8
K3
A4
PA1
K4
A5
GND
K5
A6
GND
K6
A7
GND
K7
PC6
A8
PC16
PC15
PC13
PB13
PB18
XOUT
PB30
PB28
PB29
VDDBU
VDDCORE
VDDIO
PC12
PC11
PA3
K8
PC7
A9
PB4
K9
PA18
A10
A11
A12
B1
PC4
PB0
K10
K11
K12
L1
PA23
PA28
PA27
PA10
PB26
PB24
PC28
PC23
PC0
PC30
PC19
PD1
PA16
PA24
DHSDP
DHSDM
VDDUTMI
JTAGSEL
GNDBU
PC1
B2
E2
PD2
L2
B3
E3
PD3
L3
B4
E4
PD4
L4
B5
E5
PD5
L5
B6
E6
VDDCORE
VDDCORE
VDDCORE
PB1
L6
B7
PB9
E7
L7
PC2
B8
PB8
E8
L8
PC5
B9
PB3
E9
L9
PC9
B10
B11
B12
C1
PB2
E10
E11
E12
F1
PC18
PB19
PB21
PD8
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
PA20
PA26
PA25
PA13
PA12
PB25
PB22
PC22
PC21
PB11
PB7
PB12
PA2
VDDANA
PB16
XIN
DFSDP
DFSDM
VBG
C2
F2
PD6
J2
GNDPLL
PD10
PB31
TST
C3
F3
PD9
J3
C4
F4
PA0
J4
VBUS
C5
F5
PD7
J5
XIN32
XOUT32
VDDOUT
VDDIN
PC8
C6
F6
GND
J6
FWUP
PB27
NRST
PA19
PA22
PA4
C7
F7
GND
J7
C8
F8
VDDIO
PC17
PC14
PB20
PB17
J8
C9
PC10
PA29
PA21
PC29
F9
J9
C10
C11
C12
F10
F11
F12
J10
J11
J12
GNDANA
ADVREF
PB15
PA6
20
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
5. Power Considerations
5.1
Power Supplies
The SAM3X/A series product has several types of power supply pins:
• VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage
ranges from 1.62V to 1.95V.
• VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V.
• VDDIN pin: Powers the Voltage regulator
• VDDOUT pin: It is the output of the voltage regulator.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.62V to 3.6V. VDDBU must be supplied before or at the same time than VDDIO
and VDDCORE.
• VDDPLL pin: Powers the PLL A, UPLL and 3-20 MHz Oscillator; voltage ranges from 1.62V
to 1.95V.
• VDDUTMI pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDANA pin: Powers the ADC and DAC cells; voltage ranges from 2.0V to 3.6V.
Ground pins GND are common to VDDCORE and VDDIO pins power supplies.
Separated ground pins are provided for VDDBU, VDDPLL, VDDUTMI and VDDANA. These
ground pins are respectively GNDBU, GNDPLL, GNDUTMI and GNDANA.
5.2
Voltage Regulator
The SAM3X/A series embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is intended to supply the internal core of SAM3X/A series but can be used
to supply other parts in the application. It features two different operating modes:
• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws
150 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current
depending on the required load current. In Wait Mode or when the output current is low,
quiescent current is only 7µA.
• In Shutdown mode, the voltage regulator consumes less than 1 µA while its output is driven
internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal
mode is inferior to 400 µs.
For adequate input and output power supply decoupling/bypassing, refer to “Voltage Regulator”
in the “Electrical Characteristics” section of the product datasheet.
21
11057BS–ATARM–13-Jul-12
5.3
Typical Powering Schematics
The SAM3X/A series supports a 1.62V-3.6V single supply mode. The internal regulator input
connected to the source and its output feeds VDDCORE. Figure 5-1 shows the power
schematics.
Figure 5-1. Single Supply
VDDBU
VDDUTMI
VDDANA
VDDIO
Main Supply (1.8V-3.6V)
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
Note:
Restrictions
For USB, VDDUTMI needs to be greater than 3.0V.
For ADC, VDDANA needs to be greater than 2.0V.
For DAC, VDDANA needs to be greater than 2.4V.
22
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 5-2. Core Externally Supplied
VDDBU
VDDUTMI
VDDANA
VDDIO
Main Supply (1.62V-3.6V)
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE Supply (1.62V-1.95V)
VDDCORE
VDDPLL
Note:
Restrictions
For USB, VDDUTMI needs to be greater than 3.0V.
For ADC, VDDANA needs to be greater than 2.0V.
For DAC, VDDANA needs to be greater than 2.4V.
23
11057BS–ATARM–13-Jul-12
Note:
Backup Batteries Used
FWUP
SHDN
VDDBU
VDDUTMI
Backup Batteries
VDDANA
VDDIO
VDDIN
Main Supply (1.8V-3.6V)
Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
Note:
1. Restrictions
For USB, VDDUTMI needs to be greater than 3.0V.
For ADC, VDDANA needs to be greater than 2.0V.
For DAC, VDDANA needs to be greater than 2.4V.
2. VDDUTMI and VDDANA cannot be left unpowered.
5.4
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator,
the main crystal oscillator or the PLLA. The power management controller can be used to adapt
the frequency and to disable the peripheral clocks.
5.5
Low Power Modes
The various low power modes of the SAM3X/A series are described below:
5.5.1
Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system
which is performing periodic wake-ups to perform tasks but not requiring fast startup time
(< 0.5ms).
24
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz
Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running.
The regulator and the core supply are off.
Backup Mode is based on the Cortex-M3 deep-sleep mode with the voltage regulator disabled.
The SAM3X/A series can be awakened from this mode through the Force Wake-up pin (FWUP),
and Wake-up input pins WKUP0 to WKUP15, Supply Monitor, RTT or RTC wake-up event. Cur-
rent Consumption is 2.5 µA typical on VDDBU.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con-
trol Register of the Cortex-M3 set to 1. (See the Power management description in the “ARM
Cortex M3 Processor” section of the product datasheet).
Exit from Backup mode happens if one of the following enable wake up events occurs:
• FWUP pin (low level, configurable debouncing)
• WKUPEN0-15 pins (level transition, configurable debouncing)
• SM alarm
• RTC alarm
• RTT alarm
5.5.2
Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the
whole device in a powered state for a startup time of less than 10 µs.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core,
peripherals and memories power supplies are still powered. From this mode, a fast start up is
available.
This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in
PMC_FSMR). The Cortex-M3 is able to handle external events or internal events in order to
wake-up the core (WFE). This is done by configuring the external lines WKUP0-15 as fast
startup wake-up pins (refer to Section 5.7 “Fast Start-Up”). RTC or RTT Alarm and USB wake-up
events can be used to wake up the CPU (exit from WFE).
Current Consumption in Wait mode is typically 23 µA for total current consumption if the internal
voltage regulator is used or 15 µA if an external regulator is used.
Entering Wait Mode:
• Select the 4/8/12 MHz Fast RC Oscillator as Main Clock
• Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR)
• Execute the Wait-For-Event (WFE) instruction of the processor
Note:
Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN
bit and the effective entry in Wait mode. Depending on the user application, Waiting for
MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired
instructions.
5.5.3
Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response
time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. This
mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in
PMC_FSMR.
25
11057BS–ATARM–13-Jul-12
The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or
from an event if the WFE instruction is used to enter this mode.
5.5.4
Low Power Mode Summary Table
The modes detailed above are the main low power modes. Each part can be set to on or off sep-
arately and wake-up sources can be individually configured. Table 5-1 below shows a summary
of the configurations of the low power modes.
Table 5-1.
Low Power Mode Configuration Summary
Core
PIO State
Memory
VDDBU
Potential Wake-up Core at while in Low PIO State
Consumption
Wake-up
Time(4)
Mode Region(1) Regulator Peripherals Mode Entry
Sources
Wake-up Power Mode at Wake-up
(2) (3)
PIOA &
PIOB &
PIOC &
FWUP pin
OFF
WFE
WKUP0-15 pins
BOD alarm
RTC alarm
OFF
PIOD &
PIOE &
Backup
Mode
Previous
state saved
ON
ON
Reset
2.5 µA typ(5)
< 0.5 ms
(Not
powered)
+SLEEPDEEP
bit = 1
SHDN =0
PIOF
RTT alarm
Inputs with
pull-ups
Any Event from: Fast
startup through
+SLEEPDEEP WKUP0-15 pins
WFE
Powered
ON
Wait
Mode
Clocked Previous
back state saved
Unchanged 18.4 µA/26.6 µA (6) < 10 µs
(Not
clocked)
bit = 0
RTC alarm
RTT alarm
USB wake-up
SHDN =1
+LPM bit = 1
Entry mode = WFI
Interrupt Only;
Entry mode = WFE
Any Enabled Interrupt
and/or Any Event from
Fast start-up through
WKUP0-15 pins
RTC alarm
WFE or WFI
Powered(7)
ON
Sleep
Mode
+SLEEPDEEP
bit = 0
Clocked Previous
back state saved
(7)
(7)
ON
Unchanged
(Not
clocked)
SHDN =1
+LPM bit = 0
RTT alarm
USB wake-up
Notes: 1. SUPC, 32 kHz Oscillator, RTC, RTT, Backup Registers, POR
2. The external loads on PIOs are not taken into account in the calculation.
3. BOD current consumption is not included.
4. When considering the wake-up time, the time required to start the PLL is not taken into account. Once started, the device
works with the 4/8/12 MHz Fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The
wake-up time is defined as the time taken for wake-up until the first instruction is fetched
5. Current consumption on VDDBU.
6. 18.4 µA on VDDCORE, 26.6 µA for total current consumption (using internal voltage regulator).
7. Depends on MCK frequency. In this mode, the core is supplied and not clocked but some peripherals can be clocked.
26
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
5.6
Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is
detected, the Supply Controller performs a sequence which automatically reenables the core
power supply.
Figure 5-3. Wake-up Source
SMEN
sm_int
RTCEN
RTTEN
rtc_alarm
rtt_alarm
Core
Supply
Rest ar t
FWUPDBC
Debouncer
SLCK
FWUPEN
FWUP
Falling
Ed g e
Detector
FWUP
WKUPT0
WKUPEN0
WKUPEN1
WKUPIS0
WKUPIS1
Falling/Rising
Ed g e
Detector
WKUP0
WKUP1
WKUPDBC
Debouncer
SLCK
WKUPS
WKUPT1
Falling/Rising
Ed g e
Detector
WKUPT15
WKUPEN15
WKUPIS15
Falling/Rising
Ed g e
WKUP15
Detector
27
11057BS–ATARM–13-Jul-12
5.7
Fast Start-Up
The SAM3X/A series allows the processor to restart in a few microseconds while the processor
is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up
inputs.
The fast restart circuitry, as shown in Figure 5-4, is fully asynchronous and provides a fast start-
up signal to the Power Management Controller. As soon as the fast start-up signal is asserted,
the PMC automatically restarts the embedded 4/8/12 MHz fast RC oscillator, switches the mas-
ter clock on this 4/8/12 MHz clock and reenables the processor clock.
Figure 5-4. Fast Start-Up Sources
USBEN
RTCEN
usb_wakeup
rtc_alarm
RTTEN
rtt_alarm
FSTT0
High/Low
Level
Detector
WKUP0
WKUP1
fast_restart
FSTT1
High/Low
Level
Detector
FSTT15
High/Low
Level
WKUP15
Detector
28
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
6. Input/Output Lines
The SAM3X/A has different kinds of input/output (I/O) lines, such as general purpose I/Os
(GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities
of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed
peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs.
With a few exceptions, the I/Os have input schmitt triggers. Refer to the footnotes associated
with PIOA to PIOF on page 14, at the end of Table 3-1, “Signal Description List”.
6.1
General Purpose I/O Lines (GPIO)
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such
as pull-up, input schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input
change interrupt. Programming of these modes is performed independently for each I/O line
through the PIO controller user interface. For more details, refer to the “PIO Controller” section
of the product datasheet.
The input output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM3X/A embeds high speed pads able to handle up to 65 MHz for HSMCI and SPI clock
lines and 45 MHz on other lines. See product AC Characteristics for more details. Typical pull-up
value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). ODT consists
of an internal series resistor termination scheme for impedance matching between the driver
output (SAM3) and the PCB track impedance preventing signal reflection. The series resistor
helps to reduce IOs switching current (di/dt) thereby reducing in turn, EMI. It also decreases
overshoot and undershoot (ringing) due to inductance of interconnect between devices or
between boards. In conclusion, ODT helps reducing signal integrity issues.
Figure 6-1. On-Die Termination
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
Rodt
Receiver
SAM3 Driver with
PCB Trace
Zout ~ 10 Ohms
Z0 ~ 50 Ohms
6.2
System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset, flash erase and JTAG to name
but a few. Described below are the SAM3X/A system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup, the
default function of these pins is always used.
29
11057BS–ATARM–13-Jul-12
Table 6-1.
System I/O Configuration Pin List
SYSTEM_IO
Bit Number
Default Function
Constraints for
Normal Start
Peripheral
After Reset
Other Function
Configuration
In Matrix User Interface Registers
Low Level at
startup()
(Refer to “System IO Configuration
Register“ in the “Bus Matrix“ section
of the product datasheet.)
12
-
ERASE
PC0
A
A
A
A
TCK/SWCLK
TDI
PB28
PB29
PB30
PB31
-
-
-
-
In PIO Controller
TDO/TRACESWO
TMS/SWDIO
Note:
1. If PC0 is used as PIO input in user applications, a low level must be ensured at startup to pre-
vent Flash erase before the user application sets PC0 into PIO mode.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” section of the product datasheet.
All JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3X/A series. The TST pin integrates a permanent pull-down resistor of about
15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast program-
ming mode, see the “Fast Flash Programming Interface” section. For more information on the
manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
30
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
6.4
6.5
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components, or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse, and the reset con-
troller can guarantee a minimum pulse length.
The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ.
NRSTB Pin
The NRSTB pin is input only and enables asynchronous reset of the SAM3X/A series when
asserted low. The NRSTB pin integrates a permanent pull-up resistor of about 15 kΩ. This allows
connection of a simple push button on the NRSTB pin as a system-user reset. In all modes, this
pin will reset the chip including the Backup region (RTC, RTT and Supply Controller). It reacts as
the Power-on reset. It can be used as an external system reset source. In harsh environments, it
is recommended to add an external capacitor (10 nF) between NRSTB and VDDBU. (For filter-
ing values, refer to “I/O characteristics” in the “Electrical Characteristics” section of the product
datasheet)
It embeds an anti-glitch filter.
6.6
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, the startup level
of this pin must be low to prevent unwanted erasing. Please refer to Section 11.2 “Peripheral
Signal Multiplexing on I/O Lines”. Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
31
11057BS–ATARM–13-Jul-12
7. Processor and Architecture
7.1
ARM Cortex-M3 Processor
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit.
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store.
• Three-stage pipeline.
• Single cycle 32-bit multiply.
• Hardware divide.
• Thumb and Debug states.
• Handler and Thread modes.
• Low latency ISR entry and exit.
7.2
APB/AHB Bridge
The SAM3X/A series product embeds two separate APB/AHB bridges:
• a low speed bridge
• a high speed bridge
This architecture enables a concurrent access on both bridges.
SPI, SSC and HSMCI peripherals are on the high-speed bridge connected to DMAC with the
internal FIFO for Channel buffering.
UART, ADC, TWI0-1, USART0-3, PWM, DAC and CAN peripherals are on the low-speed bridge
and have dedicated channels for the Peripheral DMA Channels (PDC). Please not that
USART0-1 can be used with the DMA as well.
The peripherals on the high speed bridge are clocked by MCK. On the low-speed bridge, CAN
controllers can be clocked at MCK divided by 2 or 4. Refer to the Power Management Controller
(PMC) section of the Full datasheet for further details.
7.3
Matrix Masters
The Bus Matrix of the SAM3X/A series product manages 5 (SAM3A) or 6 (SAM3X) masters,
which means that each master can perform an access, concurrently with others, to an available
slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all masters have the same decodings.
Table 7-1.
List of Bus Matrix Masters
Cortex-M3 Instruction/Data
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Cortex-M3 System
Peripheral DMA Controller (PDC)
USB OTG High Speed DMA
DMA Controller
Ethernet MAC (SAM3X)
32
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
7.4
Matrix Slaves
The Bus Matrix of the SAM3X/A series product manages 9 slaves. Each slave has its own arbi-
ter, allowing a different arbitration per slave.
Table 7-2.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
List of Bus Matrix Slaves
Internal SRAM0
Internal SRAM1
Internal ROM
Internal Flash
USB High Speed Dual Port RAM (DPR)
NAND Flash Controller RAM
External Bus Interface
Low Speed Peripheral Bridge
High Speed Peripheral Bridge
7.5
Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB High Speed DMA to the Internal Peripherals. Thus,
these paths are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.
Slaves
SAM3X/A Series Master to Slave Access
Masters
0
1
2
3
4
5
Cortex-M3
I/D Bus
Cortex-M3 S
Bus
USB High
Speed DMA Controller
DMA
EMAC
DMA
PDC
0
1
2
3
4
5
6
7
8
Internal SRAM0
-
-
X
X
-
X
X
X
-
X
X
X
-
X
X
X
-
X
X
X
-
Internal SRAM1
Internal ROM
X
X
-
Internal Flash
-
USB High Speed Dual Port RAM
Nand Flash Controller RAM
External Bus Interface
Low Speed Peripheral Bridge
High Speed Peripheral Bridge
X
X
X
X
X
-
-
X
X
X
X
X
-
-
X
X
X
-
X
X
-
X
X
-
-
-
-
-
-
33
11057BS–ATARM–13-Jul-12
7.6
DMA Controller
• Acting as one Matrix Master
• Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X) channels
Table 7-4.
DMA Channels
SAM3A
DMA Channel Size
100-pin SAM3X
144-pin SAM3X
3
4
8 bytes FIFO for Channel Buffering
(Channels 0, 1 and 2)
(Channels 0, 1, 2 and 4)
1
2
32 bytes FIFO for Channel Buffering
(Channel 3)
(Channels 3 and 5)
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI0-1, USART0-1, SSC and HSMCI (peripheral to memory,
memory to peripheral)
• Memory to memory transfer
• Can be triggered by PWM and T/C which enables to generates waveform though the
External Bus Interface
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given in Table
7-5.
Table 7-5.
DMA Controller
DMA Channel HW
Interface Number
Instance Name
HSMCI
SPI0
Channel T/R
Transmit/Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
Transmit
Receive
-
0
1
SPI0
2
SSC
3
SSC
4
SPI1
5
SPI1
6
TWI0
7
TWI0
8
-
-
-
-
-
USART0
USART0
USART1
USART1
PWM
Transmit
Receive
Transmit
Receive
Transmit
11
12
13
14
15
34
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
7.7
Peripheral DMA Controller
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-6.
Peripheral DMA Controller
Instance Name
DAC
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Receive
144 Pins
100 Pins
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PWM
TWI1
X
TWI0
X
USART3
USART2
USART1
USART0
UART
X
X
X
X
X
ADC
X
TWI1
X
TWI0
X
USART3
USART2
USART1
USART0
UART
N/A
X
X
X
X
35
11057BS–ATARM–13-Jul-12
7.8
Debug and Test Features
• Debug access to all memory and registers in the system, including Cortex-M3 register bank
when the core is running, halted, or held in reset
• Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
• Flash Patch and Breakpoint (FPB) unit for implementing break points and code patches
• Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and
system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• IEEE® 1149.1 JTAG Boundary-scan on all digital pins
36
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
8. Product Mapping
Figure 8-1. SAM3X/A Product Mapping
Code
Address memory space
Peripherals
HSMCI
0x00000000
0x00000000
0x20000000
0x40000000
0x60000000
0xA0000000
0xE0000000
0xFFFFFFFF
0x40000000
0x40004000
0x40008000
0x4000C000
0x40080000
+0x40
Boot Memory
0x00080000
Internal Flash 0
HALF_FLASHSIZE
Internal Flash 1
0x00100000
Internal ROM
0x00200000
Reserved
9
Code
SSC
SPI0
SPI1
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
TC8
TWI0
TWI1
PWM
14
SRAM
Peripherals
External SRAM
Reserved
TC0
TC0
TC0
TC1
TC1
TC1
TC2
TC2
TC2
17
18
19
0x1FFFFFFF
HALF_FLASHSIZE address:
+0x80
-
-
-
512ko products: 0x000C0000
256k products: 0x000A0000
128k products: 0x00090000
0x40084000
+0x40
SRAM
0x20000000
+0x80
SRAM0
SRAM1
0x20080000
0x20100000
0x20180000
0x20200000
0x40000000
0x60000000
0x61000000
0x62000000
0x63000000
0x64000000
0x65000000
0x66000000
0x67000000
0x68000000
0x69000000
0x70000000
0x80000000
0x9FFFFFFF
0x40088000
+0x40
System
NFC (SRAM)
UOTGHS (DMA)
Undefined (Abort)
+0x80
System controller
SMC
0x400E0000
0x400E0200
0x400E0400
0x400E0600
0x400E0800
0x400E0940
0x400E0A00
0x400E0C00
0x400E0E00
0x400E1000
0x400E1200
0x400E1400
0x400E1600
0x400E1800
0x400E1A00
0x400E1A10
0x400E1A30
0x400E1A50
0x400E1A60
0x400E1A90
0x400E1AB0
0x4007FFFF
0x4008C000
0x40090000
0x40094000
0x40098000
0x4009C000
0x400A0000
0x400A4000
0x400A8000
0x400AC000
0x400B0000
0x400B4000
0x400B8000
0x400BC000
0x400C0000
0x400C4000
0x400C8000
0x400D0000
0x400E0000
0x400E2600
0x60000000
11
12
Reserved
External SRAM
CS0
MATRIX
CS1
CS2
CS3
CS4
CS5
CS6
PMC
USART0
USART1
USART2
USART3
Reserved
UOTGHS
+1
6
7
UART
CHIPID
EEFC0
EEFC1
8
20
PIOA
2
CS7
NFC
PIOB
EMAC
CAN0
3
PIOC
4
Reserved
PIOD
PIOE
CAN1
Reserved
Reserved
TRNG
ADC
PIOF
RSTC
SUPC
RTT
DMAC
DACC
Reserved
WDT
System controller
Reserved
RTC
GPBR
reserved
37
11057BS–ATARM–13-Jul-12
9. Memories
9.1
Embedded Memories
9.1.1
Internal SRAM
• The 100-pin SAM3A/X8 product embeds a total of 96 Kbytes high-speed SRAM (64 Kbytes
SRAM0 and 32 Kbytes SRAM1).
• The 100-pin SAM3A/X4 product embeds a total of 64 Kbytes high-speed SRAM (32 Kbytes
SRAM0, 32 Kbytes SRAM1).
• The 100-pin SAM3A/4 product embeds a total of 36 Kbytes high-speed SRAM (16 Kbytes
SRAM0 and 16 Kbytes SRAM1).
The SRAM0 is accessible over System Cortex-M3 bus at address 0x2000 0000 and SRAM1 at
address 0x2008 0000. The user can see the SRAM as contiguous thanks to mirror effect, giving
0x2007 0000 - 0x2008 7FFF for SAM3X/A8, 0x2007 8000 - 0x2008 7FFF for SAM3X/A4 and
0x2007 C000 - 0x2008 3FFF for SAM3X/A2.
The SRAM0 and SRAM1 are in the bit band region. The bit band alias region is mapped from
0x2200 0000 to 0x23FF FFFF.
The NAND Flash Controller embeds 4224 bytes of internal SRAM. If the NAND Flash controller
is not used, these 4224 Kbytes of SRAM can be used as general purpose. It can be seen at
address 0x2010 0000.
9.1.2
Internal ROM
The SAM3X/A series product embeds an Internal ROM, which contains the SAM-BA and FFPI
program.
At any time, the ROM is mapped at address 0x0018 0000.
9.1.3
Embedded Flash
9.1.3.1
Flash Overview
• The Flash of the ATSAM3A/X8 is organized in two banks of 1024 pages (dual plane) of
256 bytes.
• The Flash of the ATSAM3A/X4 is organized in two banks of 512 pages (dual plane) of
256 bytes.
The Flash contains a 128-byte write buffer, accessible through a 32-bit interface.
9.1.3.2
9.1.3.3
Flash Power Supply
The Flash is supplied by VDDCORE.
Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas-
ters of the system. It enables reading the Flash and writing the write buffer. It also contains a
User Interface, mapped within the Memory Controller on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32-
bit internal bus. Its 128-bit wide memory interface increases performance.
38
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
The user can choose between high performance or lower current consumption by selecting
either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking
sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system
about the Flash organization, thus making the software generic.
9.1.3.4
Lock Regions
Several lock bits used to protect write and erase operations on lock regions. A lock region is
composed of several consecutive pages, and each lock region has its associated lock bit.
Table 9-1.
Number of Lock Bits
Product
Number of Lock Bits
Lock Region Size
16 kbytes (64 pages)
16 kbytes (64 pages)
ATSAM3X/A8
ATSAM3X/A4
32
16
If a locked-region’s erase or program command occurs, the command is aborted and the EEFC
triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The “Set Lock Bit”
command enables the protection. The “Clear Lock Bit” command unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.1.3.5
Security Bit Feature
The SAM3X/A series features a security bit, based on a specific General Purpose NVM bit
(GPNVM bit 0). When the security is enabled, any access to the Flash, either through the ICE
interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confi-
dentiality of the code programmed in the Flash.
This security bit can only be enabled through the “Set General Purpose NVM Bit 0” command of
the EEFC0 User Interface. Disabling the security bit can only be achieved by asserting the
ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated,
all accesses to the Flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
9.1.3.6
Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are
factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal-
ibration bits.
9.1.3.7
9.1.3.8
Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the unique identifier.
Fast Flash Programming Interface
The Fast Flash Programming Interface allows device programming through multiplexed fully-
handshaked parallel port. It allows gang programming with market-standard industrial
programmers.
39
11057BS–ATARM–13-Jul-12
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect
commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered
when TST, PA0, PA1 are set to high, PA2 and PA3 are set to low and NRST is toggled from 0
to 1.
The table below shows the signal assignment of the PIO lines in FFPI mode
Table 9-2.
FFPI Signal
PGMNCMD
FFPI PIO Assignment
PIO Used
PA0
PGMRDY
PGMNOE
PGMNVALID
PGMM[0]
PGMM[1]
PGMM[2]
PGMM[3]
PGMD[0]
PGMD[1]
PGMD[2]
PGMD[3]
PGMD[4]
PGMD[5]
PGMD[6]
PGMD[7]
PGMD[8]
PGMD[9]
PGMD[10]
PGMD[11]
PGMD[12]
PGMD[13]
PGMD[14]
PGMD[15]
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
9.1.3.9
SAM-BA® Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the
on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
40
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set
to 0.
9.1.3.10
GPNVM Bits
The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through
the “Clear GPNVM Bit” and “Set GPNVM Bit” commands of the EEFC0 User Interface.
Table 9-3.
General Purpose Non-volatile Memory Bits
GPNVMBit[#]
Function
0
1
2
Security bit
Boot mode selection
Flash selection (Flash 0 or Flash 1)
9.1.4
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed via GPNVM.
A general-purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or from the
Flash.
The GPNVM bit can be cleared or set respectively through the "Clear General-purpose NVM Bit"
and "Set General-purpose NVM Bit" commands of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM.
Asserting ERASE clears GPNVM Bit 1 and thus selects the boot from the ROM by default.
GPNVM2 enables to select if Flash 0 or Flash 1 is used for the boot.
Setting GPNVM bit 2 selects the boot from Flash 1, clearing it selects the boot from Flash 0.
41
11057BS–ATARM–13-Jul-12
9.2
External Memories
The 144-pin SAM3X features one External Memory Bus to offer interface to a wide range of
external memories and to any parallel peripheral.
9.2.1
External Memory Bus
• Integrates Four External Memory Controllers:
– Static Memory Controller
– NAND Flash Controller
– SLC NAND Flash ECC Controller
• Up to 24-bit Address Bus (up to 16 MBytes linear per chip select)
• Up to 8 chip selects, Configurable Assignment
9.2.2
Static Memory Controller
• 8- or 16-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
9.2.3
NAND Flash Controller
• Handles automatic Read/write transfer through 4224 bytes SRAM buffer
• DMA support
• Supports SLC NAND Flash technology
• Programmable timing on a per chip select basis
• Programmable Flash Data width 8-bit or 16-bit
9.2.4
NAND Flash Error Corrected Code Controller
• Integrated in the NAND Flash Controller
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte
pages
42
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
10. System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the sys-
tem such as power, resets, clocks, time, interrupts, watchdog, etc...
The System Controller User Interface also embeds the registers allowing to configure the Matrix.
43
11057BS–ATARM–13-Jul-12
Figure 10-1. System Controller Block Diagram
VDDBU
VDDIN
vr_standby
VDDOUT
Software Controlled
Voltage Regulator
FWUP
SHDN
WKUP0 - WKUP15
NRSTB
Supply
Controller
VDDIO
PIOx
PIOA/B/C/D/E/F
Input / Output Buffers
Zero-Power
Power-on Reset
VDDANA
ADVREF
ADx
General Purpose
Backup Registers
ADC & DAC
DACx
rtc_alarm
SLCK
RTC
RTT
bodbup_in
bodbup_on
VDDUTMI
Supply
Monitor
rtt_alarm
SLCK
USBx
USB
osc32k_xtal_en
XTALSEL
VDDCORE
vddcore_nreset
XIN32
Xtal 32 kHz
Slow Clock
SLCK
Oscillator
XOUT32
bodcore_on
bodcore_in
Brownout
Detector
Embedded
32 kHz RC
Oscillator
supc_interrupt
osc32k_rc_en
SRAM
Backup Power Supply
Peripherals
proc_nreset
vddcore_nreset
Reset
Controller
Matrix
Cortex-M3
periph_nreset
ice_nreset
NRST
Peripheral
Bridge
FSTT0 - FSTT15(1)
Flash
SLCK
Embedded
12 / 8 / 4 MHz
RC
Oscillator
Main Clock
MAINCK
Master Clock
Power
Management
Controller
MCK
XIN
3- 20 MHz
XTAL Oscillator
XOUT
MAINCK
PLLACK
UPLLCK
Watchdog
Timer
SLCK
PLLA
UPLL
MAINCK
Core Power Supply
FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins,
but are not physical pins.
44
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
10.1 System Controller and Peripherals Mapping
Please refer to Figure 8-1 on page 37.
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM3X/A embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDBU
• Brownout Detector on VDDCORE
• Supply Monitor on VDDUTMI
10.2.1
10.2.2
Power-on-Reset on VDDBU
The Power-on-Reset monitors VDDBU. It is always activated and monitors voltage at start up
but also during power down. If VDDBU goes below the threshold voltage, the entire chip is reset.
For more information, refer to the “Electrical Characteristics” section of the product datasheet.
Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft-
ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it
during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor-
mation, refer to the “Supply Controller” and “Electrical Characteristics” sections of the product
datasheet.
10.2.3
Supply Monitor on VDDUTMI
The Supply Monitor monitors VDDUTMI. It is not active by default. It can be activated by soft-
ware and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is
controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the
supply monitor power consumption by a factor of up to 2048. For more information, refer to the
“SUPC” and “Electrical Characteristics” sections of the product datasheet.
10.3 Reset Controller
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset, a wake-up reset, a software reset, a user reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is
capable to shape a reset signal for the external devices, simplifying to a minimum connection of
a push-button on the NRST pin to implement a manual reset.
10.4 Supply Controller
The Supply Controller controls the power supplies of each section of the processor and periph-
erals (via Voltage regulator control).
The Supply Controller has its own reset circuitry and is clocked by the 32 kHz Slow clock
generator.
The reset circuitry is based on a zero-power power-on reset cell. The zero-power power-on reset
allows the Supply Controller to start properly.
45
11057BS–ATARM–13-Jul-12
The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC
oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal
oscillator and select it as the Slow Clock source.
The Supply Controller starts up the device by enabling the Voltage Regulator, then it generates
the proper reset signals to the core power supply.
It also enables to set the system in different low power modes and to wake it up from a wide
range of events.
10.5 Clock Generator
The Clock Generator is made up of:
• One Low Power 32,768 Hz Slow Clock Oscillator with bypass mode
• One Low Power RC Oscillator
• One 3 to 20 MHz Crystal or Ceramic-based Oscillator, which can be bypassed
• One factory-programmed Fast RC Oscillator; 3 output frequencies can be selected: 4, 8 or 12
MHz. By default, 4 MHz is selected. 8 MHz and 12 MHz output are factory-calibrated.
• One 480 MHz UPLL providing a clock for the USB OTG High Speed Controller. Input
frequency is 12 MHz (only).
• One 96 to 192 MHz programmable PLL (PLLA), capable to provide the clock MCK to the
processor and to the peripherals. The input frequency of the PLL A is between 8 and 16 MHz.
46
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 10-2. Clock Generator Block Diagram
Clock Generator
XTALSEL
On Chip
32k RC OSC
Slow Clock
SLCK
XIN32
Slow Clock
Oscillator
XOUT32
XIN
3-20 MHz
Main
Oscillator
Main Clock
MAINCK
XOUT
On Chip
12/8/4 MHz
RC OSC
MAINSEL
HSCK
UPLL
UPLL Clock
UPLLCK
Divider
/6 /8
PLL and
Divider A
PLLA Clock
PLLACK
Status
Power
Control
Management
Controller
10.6 Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock HCLK
• the Free running processor clock FCLK
• the Cortex SysTick external clock
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• the USB OTG HS Clock UOTGCK
• independent peripheral clocks, typically at the frequency of MCK
• three programmable clock outputs: PCK0, PCK1 and PCK2
The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running
at 4 MHz.
47
11057BS–ATARM–13-Jul-12
Figure 10-3. Power Management Controller Block Diagram
Processor
Clock
Controller
HCK
int
Sleep Mode
Divider
/8
SystTick
FCLK
Master Clock Controller
SLCK
Prescaler
/1,/2,/4,...,/64
MAINCK
PLLACK
UPLL
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
MCK
ON/OFF
SLCK
MAINCK
PLLACK
UPLL
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
ON/OFF
HSCK
UOTGCK
The SysTick calibration value is fixed at 10500, which allows the generation of a time base of
1 ms with SystTick clock to 10.5 MHz (max HCLK/8).
10.7 Watchdog Timer
• 16-bit key-protected once-only Programmable Counter
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
10.8 SysTick Timer
• 24-bit down counter
• Self-reload capability
• Flexible system timer
10.9 Real Time Timer
• Real Time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system
48
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
10.10 Real Time Clock
• Low power consumption
• Full asynchronous design
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
10.11 General-Purpose Backup Registers
• Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
• Thirty maskable interrupts
• Sixteen priority levels
• Dynamic reprioritization of interrupts
• Priority grouping
– selection of preempting interrupt levels and non preempting interrupt levels.
• Support for tail-chaining and late arrival of interrupts.
– back-to-back interrupt processing without the overhead of state saving and
restoration between interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no
instruction overhead.
10.13 Chip Identification
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
• .JTAG ID: 0x05B2B03F
Table 10-1. ATSAM3A/X Chip IDs Register
Chip Name
CHIPID_CIDR
0x286E0A60
0x285E0A60
0x285B0960
0x284E0A60
0x284B0960
0x283E0A60
0x283B0960
CHIPID_EXID
ATSAM3X8H (Rev A)
ATSAM3X8E (Rev A)
ATSAM3X4E (Rev A)
ATSAM3X8C (Rev A)
ATSAM3X4C (Rev A)
ATSAM3A8C (Rev A)
ATSAM3A4C (Rev A)
0x0
0x0
0x0
0x0
0x0
0x0
0x0
49
11057BS–ATARM–13-Jul-12
10.14 UART
• Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
10.15 PIO Controllers
• Up to 6 PIO Controllers, PIOA, PIOB, PIOC, PIOD, PIOE and PIOF controlling a maximum of
167 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
Table 10-2. PIO Lines per PIO according to Version
Version
PIOA
PIOB
PIOC
PIOD
PIOE
PIOF
Total
100 pin SAM3X/A
144 pin SAM3X
30
32
1
-
31
10
-
-
-
-
63
103
• Fully programmable through Set/Clear Registers
• Multiplexing of four peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
– Input change, rising edge, falling edge, low level and level interrupt
– Debouncing and Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull-up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
• Synchronous output, provides Set and Clear of several I/O lines in a single write
50
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM3X/A series. A peripheral identifier is
required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Note that some Peripherals are always clocked. Please refer to the table below.
Table 11-1. Peripheral Identifiers
Instance ID
Instance Name
SUPC
RSTC
RTC
NVIC Interrupt
PMC Clock Control
Instance Description
Supply Controller
0
X
X
X
X
X
X
X
X
X
X
1
Reset Controller
2
Real Time Clock
3
RTT
Real Time Timer
4
WDG
Watchdog Timer
5
PMC
Power Management Controller
Enhanced Flash Controller 0
Enhanced Flash Controller 1
Universal Asynchronous Receiver Transceiver
Static Memory Controller
Reserved
6
EEFC0
EEFC1
UART
SMC
7
8
9
X
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PIOA
PIOB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Parallel I/O Controller A,
Parallel I/O Controller B
Parallel I/O Controller C
Parallel I/O Controller D
Parallel I/O Controller E
Parallel I/O Controller F
USART 0
PIOC
PIOD
PIOE
PIOF
USART0
USART1
USART2
USART3
HSMCI
TWI0
USART 1
USART 2
USART 3
Multimedia Card Interface
Two-Wire Interface 0
Two-Wire Interface 1
Serial Peripheral Interface
Serial Peripheral Interface
Synchronous Serial Controller
Timer Counter 0
TWI1
SPI0
SPI1
SSC
TC0
TC1
Timer Counter 1
TC2
Timer Counter 2
51
11057BS–ATARM–13-Jul-12
Table 11-1. Peripheral Identifiers (Continued)
Instance ID
Instance Name
TC3
NVIC Interrupt
PMC Clock Control
Instance Description
Timer Counter 3
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TC4
Timer Counter 4
TC5
Timer Counter 5
TC6
Timer Counter 6
TC7
Timer Counter 7
TC8
Timer Counter 8
PWM
Pulse Width Modulation Controller
ADC Controller
ADC
DACC
DMAC
UOTGHS
TRNG
EMAC
CAN0
CAN1
DAC Controller
DMA Controller
USB OTG High Speed
True Random Number Generator
Ethernet MAC
CAN Controller 0
CAN Controller 1
11.2 Peripheral Signal Multiplexing on I/O Lines
The SAM3X/A series product features 3 PIO (SAM3A and 100-pin SAM3X) or 4 PIO (144-pin
SAM3X) controllers, PIOA, PIOB, PIOC, PIOD, PIOE and PIOF, which multiplexes the I/O lines
of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The column “Comments” has
been inserted in this table for the user’s own comments; it may be used to track how pins are
defined in an application.
Note that some peripheral function, which are output only, might be duplicated within both
tables.
52
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
11.2.1
PIO Controller A Multiplexing
Table 11-2. Multiplexing on PIO Controller A (PIOA)
I/O Line
PA0
Peripheral A
CANTX0
CANRX0
TIOA1
Peripheral B
PWML3
PCK0
Extra Function
Comments
PA1
WKUP0
AD0
PA2
NANDRDY
PWMFI1
NWAIT
PWMFI0
NCS0
PA3
TIOB1
AD1/WKUP1
AD2
PA4
TCLK1
PA5
TIOA2
WKUP2
AD3
PA6
TIOB2
PA7
TCLK2
NCS1
WKUP3
WKUP4
PA8
URXD
PWMH0
PWMH3
DATRG
ADTRG
PWML1
PWMH2
TK
PA9
UTXD
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
RXD0
WKUP5
WKUP6
WKUP7
TXD0
RXD1
TXD1
RTS1
CTS1
TF
WKUP8
AD7
SCK1
TD
TWD0
SCK0
TWCK0
MCCK
A20
WKUP9
PWMH1
PWML2
PWML0
TCLK3
TCLK4
PCK1
MCCDA
MCDA0
MCDA1
MCDA2
MCDA3
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
AD4
AD5
AD6
A18
A19
A20
WKUP10
WKUP11
PCK2
NRD
PCK1
PCK2
53
11057BS–ATARM–13-Jul-12
11.2.2
PIO Controller B Multiplexing
Table 11-3. Multiplexing on PIO Controller B (PIOB)
I/O Line
PB0
Peripheral A
ETXCK/EREFCK (1)
ETXEN (1)
ETX0 (1)
ETX1 (1)
ECRSDV/ERXDV (1)
ERX0 (1)
ERX1 (1)
ERXER (1)
EMDC (1)
EMDIO (1)
UOTGVBOF
UOTGID
TWD1
Peripheral B
TIOA3 (2)
TIOB3 (2)
TIOA4 (2)
TIOB4 (2)
TIOA5 (2)
TIOB5 (2)
PWML4 (2)
PWML5 (2)
PWML6 (2)
PWML7 (2)
A18
Extra Function
Comments
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
See the Notes
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
A19
PWMH0
PWMH1
PWMH2
PWMH3
PWML0
AD8
AD9
TWCK1
CANTX1
CANRX1
TCLK5
DAC0/WKUP12
DAC1
RF
PWML1
AD10
RD
PWML2
AD11
RK
PWML3
AD12
TXD2
SPI0_NPCS1
SPI0_NPCS2
PCK0
AD13
RXD2
AD14/WKUP13
RTS2
CTS2
SPI0_NPCS3
NCS2
WKUP14
WKUP15
SCK2
RTS0
TIOA0
CTS0
TCLK0
NCS3
TIOB0
TCK/SWCLK
TDI
TCK after reset
TDI after reset
TDO after reset
TMS after reset
TDO/TRACESWO
TMS/SWDIO
Notes: 1. SAM3X only
2. SAM3A only
54
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
11.2.3
PIO Controller C Multiplexing
Table 11-4. Multiplexing on PIO Controller C (PIOC)
I/O Line
PC0
Peripheral A
Peripheral B
Extra Function
Comments
ERASE
PC1
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
PC2
D0
D1
PWML0
PWMH0
PWML1
PWMH1
PWML2
PWMH2
PWML3
PWMH3
ECRS
PC3
PC4
D2
PC5
D3
PC6
D4
PC7
D5
PC8
D6
PC9
D7
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
D8
D9
ERX2
D10
D11
D12
D13
D14
D15
NWR0/NWE
NANDOE
NANDWE
A0/NBS0
A1
ERX3
ECOL
ERXCK
ETX2
ETX3
ETXER
PWMH6
PWMH5
PWMH4
PWML4
PWML5
PWML6
PWML7
TIOA6
A2
A3
A4
A5
TIOB6
A6
TCLK6
TIOA7
A7
A8
TIOB7
A9
TCLK7
55
11057BS–ATARM–13-Jul-12
11.2.4
PIO Controller D Multiplexing
Table 11-5. Multiplexing on PIO Controller D (PIOD)
I/O Line
PD0
Peripheral A
Peripheral B
MCDA4
MCDA5
MCDA6
MCDA7
TXD3
Extra Function
Comments
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
144 pins
A10
A11
PD1
PD2
A12
PD3
A13
PD4
A14
PD5
A15
RXD3
PD6
A16
PWMFI2
TIOA8
PD7
A17
PD8
A21/NANDALE
A22/NANDCLE
NWR1/NBS1
TIOB8
PD9
TCLK8
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
56
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
11.2.5
PIO Controller E Multiplexing
Table 11-6. Multiplexing on PIO Controller E (PIOE)
I/O Line
PE0
Peripheral A
A19
Peripheral B
Extra Function
Comments
PE1
A20
PE2
A21/NANDALE
A22/NANDCLE
A23
PE3
PE4
PE5
NCS4
PE6
NCS5
PE7
PE8
PE9
TIOA3
TIOB3
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
TIOA4
TIOB4
TIOA5
TIOB5
PWMH0
PWMH1
PWML2
PWML0
PWML4
PWMH4
PWML5
PWMH5
PWML6
PWMH6
PWML7
PWMH7
NCS7
SCK3
NCS6
MCCDB
MCDB0
MCDB1
MCDB2
MCDB3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
57
11057BS–ATARM–13-Jul-12
11.2.6
PIO Controller F Multiplexing
Table 11-7. Multiplexing on PIO Controller F (PIOF)
I/O Line
PF0
Peripheral A
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
PWMH3
Peripheral B
Extra Function
Comments
PF1
PF2
PF3
PF4
CTS3
PF5
RTS3
58
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
12. Embedded Peripherals Overview
12.1 Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– Four Character FIFO in Reception
• Connection to DMA Channel Capabilities Optimizes Data Transfers
– One channel for the Receiver, One Channel for the Transmitter
12.2 Two Wire Interface (TWI)
• Master, Multi-Master and Slave Mode Operation
• Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
• One, two or three bytes for slave address
• Sequential read/write operations
• Bit Rate: up to 400 kbit/s
• General Call Supported in Slave Mode
• SMBUS Quick Command Supported in Master Mode
• Connection to Peripheral DMA Controller (PDC) for TWI0 and TWI1 and DMA Controller
(DMAC) for TWI0 Channel Capabilities Optimizes Data Transfers in Master Mode Only
12.3 Universal Asynchronous Receiver Transceiver (UART)
• Two-pin UART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
59
11057BS–ATARM–13-Jul-12
– Support for two PDC channels with connection to receiver and transmitter
– Connection to Peripheral DMA Controller or DMA Controller (TWI0) Channel
Capabilities Optimizes Data Transfers
12.4 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode, or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– Optional Manchester Encoding
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• SPI Mode
– Master or Slave
– Serial Clock programmable Phase and Polarity
– SPI Serial Clock (SCK) Frequency up to MCK/6
• IrDA modulation and demodulation
– Communication at up to 115.2 Kbps
• LIN Mode (USART0 only)
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or Slave
– Processing of frames with up to 256 data bytes
– Response Data length can be configurable or defined automatically by the Identifier
– Self synchronization in Slave node configuration
– Automatic processing and verification of the “Synch Break” and the “Synch Field”
– The “Synch Break” is detected even if it is partially superimposed with a data byte
– Automatic Identifier parity calculation/sending and verification
– Parity sending and verification can be disabled
– Automatic Checksum calculation/sending and verification
– Checksum sending and verification can be disabled
– Support both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the Master allocates slots to the scheduled frames automatically
60
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
– Generation of the Wakeup signal
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
• Interfaced with Peripheral DMA (PDC) Channels to Reduce Processor Overhead (All
USARTs) and with the DMA Controller (DMAC) (USART0 and 1)
12.5 Serial Synchronous Controller (SSC)
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader,...)
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
• Interfaced with the DMA Controller (DMAC) to Reduce Processor Overhead
12.6 Timer Counter (TC)
• Three 32-bit Timer Counter Channels
• Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and can contain:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Two global registers that act on all three TC Channels
• Quadrature decoder
– Advanced line filtering
– Position / revolution / speed
• 2-bit Gray Up/Down Counter for Stepper Motor
61
11057BS–ATARM–13-Jul-12
12.7 Pulse Width Modulation Controller (PWM)
• One Eight-channel (SAM3A and 144-pin SAM3X) or One Four-channel (100-pin SAM3X) 16-
bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
• Independent channel programming
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Bufferization
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
channel
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Bufferization
• Synchronous Channel mode
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
of periods
• Interfaced with Peripheral DMA (PDC) or with the DMA Controller (DMAC) Channels to
Reduce Processor Overhead
• Two independent event lines which can send up to 4 triggers on ADC within a period
• Three programmable external (PWMFIx pins) and three internal (from ADC, PMC controller
and Timer 0) Fault Inputs providing an asynchronous protection of outputs without MCU
intervention
• Stepper motor control (2 Channels)
12.8 High Speed Multimedia Card Interface (HSMCI)
• Compatibility with MultiMedia Card Specification Version 4.3
• Compatibility with SD Memory Card Specification Version 2.0
• Compatibility with SDIO Specification Version V2.0
• Compatibility with CE-ATA Specification 1.1
• Cards clock rate up to Master Clock divided by 2
• Boot Operation Mode support
• High Speed mode support
• Embedded power management to slow down clock rate when not used
• Supports 2 Multiplexed Slot(s)
62
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
– Each Slot for either a High Speed MultiMediaCard Bus (Up to 30 Cards) or an SD
Memory Card
• Support for Stream, Block and Multi-block Data Read and Write
• Supports Connection to DMA Controller (DMAC)
– Minimizes Processor Intervention for Large Buffer Transfers
• Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental
Access
• Support for CE-ATA Completion Signal Disable Command
• Protection Against Unexpected Modification On-the-Fly of the Configuration Registers
12.9 USB On-The-Go High Speed Port (UOTGHS)
• USB2.0 Compliant, Low/Full/High-Speed (LS/FS/HS) and On-The-Go, 1.5Mb/s, 12Mb/s,
480Mb/s
• 10 Pipes/Endpoints
• 4K bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
• Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
• Flexible Pipe/Endpoint Configuration and Management with 6 Dedicated DMA Channels
• On-Chip UTMI transceiver including Pull-ups/Pull-downs
• On-Chip OTG pad including VBUS analog comparator
12.10 Analog-to-Digital Converter (ADC)
• 12-bit Resolution
• 1 MHz Conversion Rate
• 2.4 V to 3.6 V Wide Range Power Supply Operation
• Selectable Single Ended or Differential Input Voltage
• Programmable Gain and Offset per channel For Maximum Full Scale Input Range 0 - VDD
• Integrated Multiplexer Offering Up to 16 Independent Analog Inputs
• Individual Enable and Disable of Each Channel
• Hardware or Software Trigger
– External Trigger Pin
– Timer Counter Outputs (Corresponding TIOA Trigger)
– Internal Trigger Counter
– PWM Event Line
• Drive of PWM Fault Input
• PDC Support
• Possibility of ADC Timings Configuration
• Two Sleep Modes and Conversion Sequencer
– Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all
Enabled Channels
– Possibility of Customized Channel Sequence
• Standby Mode for Fast Wakeup Time Response
– Power Down Capability
63
11057BS–ATARM–13-Jul-12
• Automatic Window Comparison of Converted Values
• Write Protect Registers
12.11 Digital-to-Analog Converter (DAC)
• 2 channels, 12-bit DAC
• Up to 1 mega-sample conversion rate in single channel mode
• Flexible conversion range
• Multiple trigger sources for each channel
• Built-in offset and gain calibration
• Possibility to drive output to ground
• Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H
stage)
• Two PDCA channels
• Power reduction mode
12.12 CAN Controller (CAN)
• Fully Compliant with CAN 2.0 Part A and 2.0 Part B
• Bit Rates up to 1Mbit/s
• 8 Object Oriented Mailboxes with the Following Properties:
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
– Object Configurable in Receive (with Overwrite or Not) or Transmit Modes
– Independent 29-bit Identifier and Mask Defined for Each Mailbox
– 32-bit Access to Data Registers for Each Mailbox Data Object
– Uses a CAN_SIZE_COUNTER-bit Timestamp on Receive and Transmit Messages
– Hardware Concatenation of ID Masked Bitfields To Speed Up Family ID Processing
• 16-bit Internal Timer for Timestamping and Network Synchronization
• Programmable Reception Buffer Length up to 8 Mailbox Objects
• Priority Management between Transmission Mailboxes
• Autobaud and Listening Mode
• Low Power Mode and Programmable Wake-up on Bus Activity or by the Application
• Data, Remote, Error and Overload Frame Handling
12.13 Ethernet MAC (EMAC)
• DMA Master on Receive and Transmit Channels
• Compatible with IEEE Standard 802.3
• 10 and 100 Mbit/s operation
• Full- and half-duplex operation
• Statistics Counter Registers
• MII (144-pin SAM3X)/RMII (all SAM3X) interface to the physical layer
• Interrupt generation to signal receive and transmit completion
64
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
• 128-byte transmit FIFO and 128-byte receive FIFO
• Automatic pad and CRC generation on transmitted frames
• Automatic discard of frames received with errors
• Address checking logic supports up to four specific 48-bit addresses
• Support Promiscuous Mode where all valid received frames are copied to memory
• Hash matching of unicast and multicast destination addresses
• Physical layer management through MDIO interface
• Half-duplex flow control by forcing collisions on incoming frames
• Full-duplex flow control with recognition of incoming pause frames
• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged
• Frames
• Multiple buffers per receive and transmit frame
• Jumbo frames up to 10,240 bytes supported
12.14 True Random Number Generator (TRNG)
• Passed NIST Special Publication 800-22 Tests Suite
• Passed Diehard Random Tests Suite
• Provides a 32-bit Random Number Every 84 Clock Cycles
12.15 External Bus Interface (EBI)
• Only present on 144-pin version of SAM3X
• Managing SMC, Nand Flash accesses offering:
– Up to 8 Configurable chip select
– Programmable timing on a per chip select basis
– 16-Mbyte Address Space per Chip Select
– 8- or 16-bit Data Bus
– Word, Halfword, Byte Transfers
– Byte Write or Byte Select Lines
– Programmable Setup, Pulse and Hold Time for Read Signals per Chip Select
– Programmable Setup, Pulse and Hold Time for Write Signals per Chip Select
– Programmable Data Float Time per Chip Select
– External Wait Request
– Automatic Switch to Slow Clock Mode
– Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to
32 Bytes
– NAND Flash Controller supporting NAND Flash with Multiplexed Data/Address
buses
– Supports SLC NAND Flash technology
– Supports Hardware Error Correcting Code (ECC), 1-bit error correction, 2-bit error
detection
– Detection and Correction by Software
65
11057BS–ATARM–13-Jul-12
13. Package Drawings
The SAM3X/A series devices are available in QFP (LQFP or PQFP) and LFBGA packages.
Figure 13-1. 100-lead LQFP Package Drawing
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
66
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 13-2. 100-ball LFBGA Package Drawing
67
11057BS–ATARM–13-Jul-12
Figure 13-3. 144-lead LQFP Package Drawing
68
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
Figure 13-4. 144-ball LFBGA Package Drawing
All dimensions are in mm
69
11057BS–ATARM–13-Jul-12
13.1 Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking may be in one of the following formats:
YYWW
V
ARM
XXXXXXXXX
where
• “YY”: manufactory year
• “WW”: manufactory week
• “V”: revision
“XXXXXXXXX”: lot number
70
SAM3X/A
11057BS–ATARM–13-Jul-12
SAM3X/A
14. Ordering Information
Table 14-1. SAM3X/A Ordering Information
Flash
Temperature
Ordering Code
MRL
(Kbytes)
Package
Package Type
Operating Range
Industrial
-40°C to 85°C
ATSAM3A4CA-AU
A
256
LQFP100
Green
Industrial
-40°C to 85°C
ATSAM3A8CA-AU
ATSAM3A4CA-CU
ATSAM3A8CA-CU
ATSAM3X4CA-AU
ATSAM3X8CA-AU
ATSAM3X4CA-CU
ATSAM3X8CA-CU
ATSAM3X4EA-AU
ATSAM3X8EA-AU
ATSAM3X4EA-CU
ATSAM3X8EA-CU
A
A
A
A
A
A
A
A
A
A
A
512
256
512
256
512
256
512
256
512
256
512
LQFP100
LFBGA100
LFBGA100
LQFP100
LQFP100
LFBGA100
LFBGA100
LQFP144
LQFP144
LFBGA144
LFBGA144
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
Industrial
-40°C to 85°C
71
11057BS–ATARM–13-Jul-12
Revision History
In the tables that follow, the most recent version of the document appears first.
“rfo” indicates changes requested during the review and approval loop.
Change
Request
Ref.
Doc. Rev
11057BS
Comments
SDRAM Controller info removed: Section “Features”; Table 1-1, “Configuration Summary”; Table 3-1,
“Signal Description List”; Section 9.2.1 “External Memory Bus”; Section 10. “System Controller”;
Table 11.1, “Peripheral Identifiers”; Section 12.15 “External Bus Interface (EBI)”, and Figure 8-1
”SAM3X/A Product Mapping”.
8316
I/O info modified in Section “Features”.
Section 1. “SAM3X/A Description” updated.
Figure 2-3 ”SAM3X4/8E (144 pins) Block Diagram” updated.
Table 11-5, “Multiplexing on PIO Controller D (PIOD)” updated.
“Write protected Registers” added to Section “Features”.
8213
Change
Request
Ref.
Doc. Rev
11057AS
Comments
First issue
72
SAM3X/A
11057BS–ATARM–13-Jul-12
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