ATTINY11-6PU_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 90 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 4 MIPS Throughput at 4 MHz

• Nonvolatile Program Memory

– 2K Bytes of Flash Program Memory

– Endurance: 1,000 Write/Erase Cycles

– Programming Lock for Flash Program Data Security

• Peripheral Features

8-bit

– Interrupt and Wake-up on Low-level Input

– One 8-bit Timer/Counter with Separate Prescaler

– On-chip Analog Comparator

Microcontroller

with 2K Bytes of

Flash

– Programmable Watchdog Timer with On-chip Oscillator

– Built-in High-current LED Driver with Programmable Modulation

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

– Power-on Reset Circuit with Programmable Start-up Time

– Internal Calibrated RC Oscillator

ATtiny28L

ATtiny28V

• Power Consumption at 1 MHz, 2V, 25°C

– Active: 3.0 mA

– Idle Mode: 1.2 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver

– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF

• Operating Voltages

Summary

– V_CC: 1.8V - 5.5V for the ATtiny28V

– V_CC: 2.7V - 5.5V for the ATtiny28L

• Speed Grades

– 0 - 1.2 MHz for the ATtiny28V

– 0 - 4 MHz For the ATtiny28L

Pin Configurations

PDIP

TQFP/QFN/MLF

RESET

PD0

1

2

3

4

5

6

7

8

9

28 PA0

27 PA1

PD1

26 PA3

PD2

25 PA2 (IR)

24 PB7

PD3

PD4

1

2

3

4

5

6

7

8

24 PB7

23 PB6

22 NC

21 GND

20 NC

19 NC

18 VCC

17 PB5

PD3

PD4

23 PB6

NC

VCC

GND

NC

VCC

GND

XTAL1

22 GND

21 NC

20 VCC

XTAL1

XTAL2

XTAL2 10

PD5 11

19 PB5

18 PB4 (INT1)

17 PB3 (INT0)

16 PB2 (T0)

15 PB1 (AIN1)

PD6 12

PD7 13

(AIN0) PB0 14

Rev. 1062FS–AVR–07/06

Note: This is a summary document. A complete document

1

is available on our Web site at www.atmel.com.

Description

The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-

tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves

throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize

power consumption versus processing speed. The AVR core combines a rich instruction

set with 32 general-purpose working registers. All the 32 registers are directly con-

nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

Block Diagram

Figure 1. The ATtiny28 Block Diagram

VCC

XTAL1

XTAL2

INTERNAL

8-BIT DATA BUS

CALIBRATED

OSCILLATOR

INTERNAL

OSCILLATOR

GND

RESET

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

MCU CONTROL

REGISTER

PROGRAM

FLASH

HARDWARE

STACK

TIMER/

COUNTER

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

INSTRUCTION

DECODER

Z

CONTROL

LINES

ALU

STATUS

REGISTER

HARDWARE

MODULATOR

PROGRAMMING

LOGIC

DATA REGISTER

PORTB

DATA REGISTER

PORTD

DATA DIR

REG. PORTD

DATA REGISTER

PORTA

PORTA CONTROL

REGISTER

PORTB

PORTA

PORTD

The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O

lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an

8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with

internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops

the CPU while allowing the timer/counter and interrupt system to continue functioning.

The Power-down mode saves the register contents but freezes the oscillator, disabling

all other chip functions until the next interrupt or hardware reset. The wake-up or inter-

2

ATtiny28L/V

1062FS–AVR–07/06

ATtiny28L/V

rupt on low-level input feature enables the ATtiny28 to be highly responsive to external

events, still featuring the lowest power consumption while in the power-down modes.

The device is manufactured using Atmel’s high-density, nonvolatile memory technology.

By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel

ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective

solution to many embedded control applications. The ATtiny28 AVR is supported with a

full suite of program and system development tools including: macro assemblers, pro-

gram debugger/simulators, in-circuit emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

Ground pin.

GND

Port A (PA3..PA0)

Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED

driver. At V_CC= 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are

bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B

pins that are externally pulled low will source current if the pull-ups are activated.

Port B also serves the functions of various special features of the ATtiny28 as listed on

page 27. If any of the special features are enabled, the pull-up(s) on the corresponding

pin(s) is automatically disabled. The port pins are tri-stated when a reset condition

becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for

each bit). The port pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

XTAL1

XTAL2

RESET

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

3

1062FS–AVR–07/06

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F

$3E

...

SREG

Reserved

PORTA

PACR

I

T

H

S

V

N

Z

C

page 6

$20

$1F

$1E

$1D

$1C

$1B

$1A

$19

$18

$17

$16

$15

$14

$13

$12

$11

$10

$0F

$0E

$0D

$0C

$0B

$0A

$09

$08

$07

$06

$05

$04

$03

$02

$01

$00

-

PORTA3

DDA3

PORTA2

PA2HC

-

PORTA1

DDA1

PORTA0

DDA0

page 32

PINA

PINA3

PINA1

PINA0

Reserved

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 32

Reserved

PORTD

DDRD

PORTD7

DDD7

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

page 33

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Reserved

ACSR

ACD

PLUPB

INT1

-

ACO

SE

LLIE

-

ACI

SM

ACIE

WDRF

ISC11

-

ACIS1

EXTRF

ISC01

-

ACIS0

PORF

ISC00

-

page 44

page 19

page 22

page 23

page 35

page 36

page 43

page 37

page 9

MCUCS

ICR

-

INT0

INTF0

-

TOIE0

TOV0

OOM01

ISC10

-

IFR

INTF1

FOV0

TCCR0

-

OOM00

CS02

CS01

CS00

TCNT0

Timer/Counter0 (8-bit)

ONTIM1

WDTOE

MODCR

WDTCR

OSCCAL

ONTIM4

-

ONTIM3

ONTIM2

-

ONTIM0

WDE

MCONF2

WDP2

MCONF1

WDP1

MCONF0

WDP0

-

Oscillator Calibration Register

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

4

ATtiny28L/V

1062FS–AVR–07/06

ATtiny28L/V

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

SUB

SUBI

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rd ← Rd - Rr

Rd ← Rd - K

Z,C,N,V,H

Z,N,V

1

Add with Carry Two Registers

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Rd ← Rd v K

Z,N,V

ORI

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (FFh - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

CLR

SER

Rd

Decrement

Rd ← Rd - 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

RCALL

RET

k

Relative Jump

PC ← PC + k + 1

None

I

2

Relative Subroutine Call

Subroutine Return

PC ← PC + k + 1

3

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z,N,V,C,H

Z N,V,C,H

None

1/2

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

5

1062FS–AVR–07/06

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

LD

Rd, Z

Z, Rr

Load Register Indirect

Store Register Indirect

Move between Registers

Load Immediate

In Port

Rd ← (Z)

(Z) ← Rr

Rd ← Rr

Rd ← K

Rd ← P

P ← Rr

None

2

1

3

ST

MOV

LDI

IN

Rd, Rr

Rd, K

Rd, P

P, Rr

OUT

LPM

Out Port

Load Program Memory

R0 ← (Z)

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)

Z,C,N,V

Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

6

ATtiny28L/V

1062FS–AVR–07/06

ATtiny28L/V

Ordering Information

Speed (MHz)

Power Supply (Volts)

Ordering Code

Package⁽¹⁾

Operation Range

ATtiny28L-4AC

ATtiny28L-4PC

ATtiny28L-4MC

32A

28P3

32M1-A

Commercial

(0°C to 70°C)

ATtiny28L-4AI

ATtiny28L-4AU⁽²⁾

32A

4

2.7 - 5.5

ATtiny28L-4PI

28P3

32M1-A

Industrial

ATtiny28L-4PU⁽²⁾

ATtiny28L-4MI

ATtiny28L-4MU⁽²⁾

(-40°C to 85°C)

ATtiny28V-1AC

ATtiny28V-1PC

ATtiny28V-1MC

32A

28P3

32M1-A

Commercial

(0°C to 70°C)

ATtiny28V-1AI

ATtiny28V-1AU⁽²⁾

32A

1.2

1.8 - 5.5

28P3

ATtiny28V-1PI

Industrial

ATtiny28V-1PU⁽²⁾

ATtiny28V-1MI

ATtiny28V-1MU⁽²⁾

(-40°C to 85°C)

28P3

32M1-A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3

28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

32M1-A

32-pad, 5x5x1.0 body, Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)

7

1062FS–AVR–07/06

Packaging Information

32A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

C

–

3. Lead coplanarity is 0.10 mm maximum.

L

–

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

B

R

8

ATtiny28L/V

1062FS–AVR–07/06

ATtiny28L/V

28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

9

1062FS–AVR–07/06

32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

0.08

C

(Unit of Measure = mm)

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

10

ATtiny28L/V

1062FS–AVR–07/06

ATtiny28L/V

Errata

All revisions

No known errata.

11

1062FS–AVR–07/06

Datasheet Revision

History

Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Rev – 01/06G

1. Updated chapter layout.

2. Updated “Ordering Information” on page 7.

Rev – 01/06G

1. Updated description for “Port A” on page 25.

2. Added note 6 in “DC Characteristics” on page 54.

3. Updated “Ordering Information” on page 7.

4. Added “Errata” on page 11.

Rev – 03/05F

1. Updated “Electrical Characteristics” on page 54.

2. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package

QFN/MLF”.

3. Updated “Ordering Information” on page 7.

12

ATtiny28L/V

1062FS–AVR–07/06

Atmel Corporation

Atmel Operations

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ers.

1062FS–AVR–07/06


型号：	ATTINY11-6PU
厂家：	ATMEL
描述：	8-bit Microcontroller with 1K Byte Flash 8 -bit微控制器1K字节的FLASH 微控制器和处理器外围集成电路光电二极管异步传输模式 ATM 时钟
文件：	总13页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY11-6PU [ATMEL]

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