ATTINY13-24SU [ATMEL]
RISC Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDSO8, 0.209 INCH, PLASTIC, SO-8;
| 型号： | ATTINY13-24SU |
| 厂家： | 
ATMEL |
| 描述： | RISC Microcontroller, 8-Bit, FLASH, 24MHz, CMOS, PDSO8, 0.209 INCH, PLASTIC, SO-8 时钟 ATM 异步传输模式 微控制器 光电二极管 外围集成电路 闪存 |
| 文件： | 总15页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 1K Byte of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 64 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 64 Bytes Internal SRAM
8-bit
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
• Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
ATtiny13
• I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
• Operating Voltage:
Preliminary
Summary
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
• Speed Grade
– ATtiny13V: 0 - 6 MHz @ 1.8 - 5.5V, 0 - 12 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 12 MHz @ 2.7 - 5.5V, 0 - 24 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 240µA
– Power-down Mode:
< 0.1µA at 1.8V
Pin Configurations
Figure 1. Pinout ATtiny13
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
(PCINT4/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/ADC1/T0/PCINT2)
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
Rev. 2535BS–AVR–01/04
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
Overview
The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
8-BIT DATABUS
STACK
POINTER
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
OSCILLATOR
SRAM
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
GND
MCU CONTROL
REGISTER
PROGRAM
COUNTER
MCU STATUS
REGISTER
PROGRAM
FLASH
TIMER/
COUNTER0
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
DATA
EEPROM
CONTROL
LINES
ALU
STATUS
REGISTER
ADC /
ANALOG COMPARATOR
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
RESET
CLKI
PB0-PB5
2
ATtiny13
2535BS–AVR–01/04
ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System Programmable
Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general pur-
pose working registers, one 8-bit Timer/Counter with compare modes, Internal and
External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with
internal Oscillator, and three software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and
Interrupt system to continue functioning. The Power-down mode saves the register con-
tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC
Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize
switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The On-chip ISP Flash allows the Program memory to be re-programmed In-System
through an SPI serial interface, by a conventional non-volatile memory programmer or
by an On-chip boot code running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-
cuit Emulators, and Evaluation kits.
Pin Descriptions
VCC
Digital supply voltage.
Ground.
GND
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13 as listed on
page 49.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
12 on page 30. Shorter pulses are not guaranteed to generate a reset.
3
2535BS–AVR–01/04
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
Reserved
SPL
I
T
–
H
–
S
–
V
–
N
–
Z
–
C
–
page 6
–
SP[7:0]
–
page 8
Reserved
GIMSK
–
–
–
–
–
INT0
PCIE
–
–
–
–
–
page 53
page 53
page 70
page 71
page 97
page 70
page 49
page 33
page 66
page 70
page 22
GIFR
INTF0
PCIF
–
–
–
–
–
–
TIMSK0
TIFR0
–
–
–
–
–
–
OCIE0B
OCF0B
RFLB
OCIE0A
OCF0A
PGWRT
TOIE0
TOV0
PGERS
–
–
–
SELFPRGEN
SPMCSR
OCR0A
MCUCR
MCUSR
TCCR0B
TCNT0
CTPB
Timer/Counter – Output Compare Register A
–
–
PUD
–
SE
–
SM1
SM0
–
ISC01
EXTRF
CS01
ISC00
PORF
CS00
–
–
WDRF
WGM02
BORF
CS02
FOC0A
FOC0B
–
Timer/Counter (8-bit)
OSCCAL
Reserved
TCCR0A
DWDR
Oscillator Calibration Register
–
COM0A1
COM0A0
COM0B1
COM0B0
DWDR[7:0]
–
–
WGM01
WGM00
page 69
page 94
Reserved
Reserved
Reserved
Reserved
OCR0B
GTCCR
Reserved
CLKPR
–
–
–
–
Timer/Counter – Output Compare Register B
page 70
page 73
TSM
–
–
–
–
–
–
–
–
PSR10
–
CLKPCE
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 24
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
–
–
–
–
WDTIF
WDTIE
WDP3
WDCE
WDE
WDP2
WDP1
EEWE
WDP0
EERE
page 37
–
–
–
–
–
–
EEPROM Address Register
EEPROM Data Register
page 14
page 14
page 15
EEDR
EECR
EEPM1
EEPM0
EERIE
EEMWE
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 51
page 51
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 51
PCMSK
DIDR0
PCINT5
ADC0D
PCINT4
ADC2D
PCINT3
ADC3D
PCINT2
ADC1D
PCINT1
EIN1D
PCINT0
AIN0D
page 54
page 76, page 91
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ACSR
–
–
–
–
–
–
–
–
–
–
–
ACD
–
ACBG
REFS0
ADSC
ACO
ACI
–
ACIE
–
–
–
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 74
page 88
page 89
page 90
page 90
page 91
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
ADEN
ADIF
ADIE
ADPS2
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
Reserved
Reserved
Reserved
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
–
–
–
4
ATtiny13
2535BS–AVR–01/04
ATtiny13
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
5
2535BS–AVR–01/04
Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N V= 0) then PC ← PC + k + 1
if (N V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
BRID
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
CBI
LSL
LSR
ROL
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
6
ATtiny13
2535BS–AVR–01/04
ATtiny13
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
7
2535BS–AVR–01/04
Ordering Information
Power Supply
Speed (MHz)
Ordering Code
Package(1)
Operation Range
ATtiny13-12PI
ATtiny13-12PJ(2)
8P3
8P3
ATtiny13-12SI
8S2
Industrial
(-40°C to 85°C)
12(3)
1.8 - 5.5
ATtiny13-12SJ(2)
ATtiny13-12SSI
ATtiny13-12SSJ(2)
8S2
S8S1
S8S1
ATtiny13-24PI
8P3
ATtiny13-24PJ(2)
8P3
ATtiny13-24SI
8S2
Industrial
(-40°C to 85°C)
24(3)
2.7 - 5.5
ATtiny13-24SJ(2)
ATtiny13-24SSI
ATtiny13-24SSJ(2)
8S2
S8S1
S8S1
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative.
3. For Speed vs. VCC, see “Maximum Speed vs. VCC” on page 116.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
S8S1
8
ATtiny13
2535BS–AVR–01/04
ATtiny13
Packaging Information
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
9
2535BS–AVR–01/04
8S2
C
1
E
E1
L
N
Top View
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0˚
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8˚
NOM
NOTE
SYMBOL
A1
A
A1
b
5
5
C
D
E1
E
D
2, 3
Side View
L
e
1.27 BSC
4
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
TITLE
REV.
DRAWING NO.
2325 Orchard Parkway
San Jose, CA 95131
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
8S2
C
R
10
ATtiny13
2535BS–AVR–01/04
ATtiny13
S8S1
1
E1
E
N
Top View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
5.79
3.81
1.35
0.1
MAX
6.20
3.99
1.75
0.25
4.98
0.25
0.51
1.27
NOM
NOTE
SYMBOL
A1
E
D
E1
A
Side View
A1
D
C
b
C
4.80
0.17
0.31
0.4
L
L
End View
e
1.27 BSC
0o
8o
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03
TITLE
DRAWING NO.
REV.
S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small
Outline (JEDEC SOIC)
2325 Orchard Parkway
San Jose, CA 95131
S8S1
A
R
11
2535BS–AVR–01/04
Errata
The revision letter in this section refers to the revision of the ATtiny13 device.
There are no known errata for this revision.
ATtiny13 Rev. C
ATtiny13 Rev. B
• Wrong values read after Erase Only operation
• High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail
• Device may lock for further programming
• debugWIRE communication not blocked by lock-bits
• Watchdog Timer Interrupt disabled
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase
Only operation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write
operation with 0xFF as data in order to erase a location. In any case, the Write Only
operation can be used as intended. Thus no special considerations are needed as
long as the erased location is not read before it is programmed.
2. High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may
fail
Writing to any of these locations and bits may in some occasions fail.
Problem Fix/Workaround
After a writing has been initiated, always observe the RDY/BSY signal. If the writing
should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in
revision C.
3. Device may lock for further programming
Special combinations of fuse bits will lock the device for further programming effec-
tively turning it into an OTP device. The following combinations of settings/fuse bits
will cause this effect:
–
–
–
128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time
(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled
RSTDISBL = 0.
Problem fix/ Workaround
Avoid the above fuse combinations. Selecting longer start-up time will eliminate the
problem.
4. debugWIRE communication not blocked by lock-bits
When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program
memory and EEPROM data memory can be read even if the lock-bits are set to
block further reading of the device.
12
ATtiny13
2535BS–AVR–01/04
ATtiny13
Problem fix/ Workaround
Do not ship products with on-chip debug of the tiny13 enabled.
5. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the
watchdog will be disabled, and the interrupt flag will automatically be cleared. This is
only applicable in interrupt only mode. If the Watchdog is configured to reset the
device in the watchdog time-out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a
new watchdog timeout occurs. This is done by selecting a long enough time-out
period.
ATtiny13 Rev. A
Revision A has not been sampled.
13
2535BS–AVR–01/04
Datasheet Change
Log for ATtiny13
Please note that the referring page numbers in this section are referring to this docu-
ment. The referring revision in this section are referring to the document revision.
Changes from Rev.
2535A-06/03 to Rev.
2535B-01/04
1.
2.
Updated Figure 2 on page 2.
Updated Table 12 on page 30, Table 17 on page 39, Table 37 on page 89
and Table 57 on page 116.
3.
4.
5.
6.
Updated “Calibrated Internal RC Oscillator” on page 22.
Updated the whole “Watchdog Timer” on page 35.
Updated Figure 53 on page 103 and Figure 56 on page 108.
Updated registers “MCU Control Register – MCUCR” on page 49,
“Timer/Counter Control Register B – TCCR0B” on page 69 and “Digital
Input Disable Register 0 – DIDR0” on page 76.
7.
Updated Absolute Maximum Ratings and DC Characteristics in “Electrical
Characteristics” on page 115.
8.
9.
Added “Maximum Speed vs. VCC” on page 116
Updated “ADC Characteristics – Preliminary Data” on page 118.
10. Updated “ATtiny13 Typical Characteristics – Preliminary Data” on page
119.
11. Updated “Ordering Information” on page 8.
12. Updated “Packaging Information” on page 9.
13. Updated “Errata” on page 12.
14. Changed instances of EEAR to EEARL.
14
ATtiny13
2535BS–AVR–01/04
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