ATTINY13A-SH [ATMEL]
8-bit Microcontroller with 1K Bytes In-System Programmable Flash; 8 -bit微控制器1K字节的系统内可编程闪存
| 型号： | ATTINY13A-SH |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 1K Bytes In-System Programmable Flash |
| 文件： | 总20页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
• High Endurance Non-volatile Memory segments
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
8-bit
– 64 Bytes Internal SRAM
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 Years at 85°C/100 Years at 25°C (see page 6)
– Programming Lock for Self-Programming Flash & EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Software Disable Function
– Internal Calibrated Oscillator
ATtiny13A
Summary
• I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
• Operating Voltage:
– 1.8 - 5.5V
• Speed Grade:
– 0 - 4 MHz @ 1.8 - 5.5V
– 0 - 10 MHz @ 2.7 - 5.5V
– 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 190 µA at 1.8 V and 1 MHz
– Idle Mode:
• 24 µA at 1.8 V and 1 MHz
Rev. 8126BS–AVR–12/08
1. Pin Configurations
Figure 1-1. Pinout of ATtiny13A
8-PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
1
2
3
4
8
7
6
5
VCC
(PCINT3/CLKI/ADC3) PB3
(PCINT4/ADC2) PB4
GND
PB2 (SCK/ADC1/T0/PCINT2)
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
20-QFN/MLF
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
1
15
VCC
2
3
4
5
14
13
12
11
PB2 (SCK/ADC1/T0/PCINT2)
DNC
DNC
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
(PCINT4/ADC2) PB4
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
10-QFN/MLF
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/CLKI/ADC3) PB3
DNC
1
2
3
4
5
10
9
VCC
PB2 (SCK/ADC1/T0/PCINT2)
DNC
8
(PCINT4/ADC2) PB4
GND
7
PB1 (MISO/AIN1/OC0B/INT0/PCINT1)
PB0 (MOSI/AIN0/OC0A/PCINT0)
6
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
2
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
1.1
Pin Description
1.1.1
VCC
Supply voltage.
1.1.2
1.1.3
GND
Ground.
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny13A as listed on page
55.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 18-4 on page 120. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
8126BS–AVR–12/08
2. Overview
The ATtiny13A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny13A achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
8-BIT DATABUS
STACK
POINTER
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
OSCILLATOR
SRAM
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
GND
MCU CONTROL
REGISTER
PROGRAM
COUNTER
MCU STATUS
REGISTER
PROGRAM
FLASH
TIMER/
COUNTER0
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INTERRUPT
UNIT
X
Y
Z
PROGRAMMING
LOGIC
INSTRUCTION
DECODER
DATA
EEPROM
CONTROL
LINES
ALU
STATUS
REGISTER
ADC /
ANALOG COMPARATOR
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
RESET
CLKI
PB0-PB5
4
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny13A provides the following features: 1K byte of In-System Programmable Flash, 64
bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-
isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-
ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny13A AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
5
8126BS–AVR–12/08
3. About
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25⋅C.
6
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
Reserved
SPL
I
T
–
H
–
S
–
V
–
N
–
Z
–
C
–
page 9
–
SP[7:0]
page 11
Reserved
GIMSK
–
–
–
–
–
–
–
INT0
INTF0
–
–
PCIE
PCIF
–
–
–
–
–
–
–
–
–
–
–
–
–
page 47
page 48
page 75
page 76
page 98
page 75
page 33
page 42
page 73
page 74
page 27
page 33
page 70
page 97
GIFR
–
–
–
–
–
TIMSK0
TIFR0
OCIE0B
OCF0B
RFLB
OCIE0A
OCF0A
PGWRT
TOIE0
TOV0
PGERS
–
–
–
–
SELFPR-
SPMCSR
OCR0A
MCUCR
MCUSR
TCCR0B
TCNT0
–
–
CTPB
Timer/Counter – Output Compare Register A
–
–
PUD
–
SE
–
SM1
SM0
–
ISC01
EXTRF
CS01
ISC00
PORF
CS00
–
–
WDRF
WGM02
BORF
CS02
FOC0A
FOC0B
–
Timer/Counter (8-bit)
OSCCAL
BODCR
TCCR0A
DWDR
Oscillator Calibration Register
–
–
–
–
–
–
–
–
BODS
BODSE
WGM00
COM0A1
COM0A0
COM0B1
COM0B0
WGM01
DWDR[7:0]
Reserved
Reserved
Reserved
Reserved
OCR0B
GTCCR
Reserved
CLKPR
–
–
–
–
Timer/Counter – Output Compare Register B
page 75
page 78
TSM
–
–
–
–
–
–
PSR10
–
CLKPCE
–
–
–
–
–
–
–
CLKPS3
–
CLKPS2
–
CLKPS1
PRTIM0
CLKPS0
PRADC
page 28
page 34
PRR
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEARL
–
–
–
WDTIF
WDTIE
WDP3
WDCE
WDE
WDP2
WDP1
EEPE
WDP0
EERE
page 42
–
–
–
–
–
–
EEPROM Address Register
EEPROM Data Register
page 20
page 20
page 21
EEDR
EECR
EEPM1
EEPM0
EERIE
EEMPE
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 57
page 57
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 58
PCMSK
DIDR0
PCINT5
ADC0D
PCINT4
ADC2D
PCINT3
ADC3D
PCINT2
ADC1D
PCINT1
AIN1D
PCINT0
AIN0D
page 48
page 81, page 95
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ACSR
–
–
–
–
–
–
–
–
–
–
–
ACD
–
ACBG
REFS0
ADSC
ACO
ACI
–
ACIE
–
–
–
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 80
page 92
page 93
page 94
page 94
page 95
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
ADEN
ADIF
ADIE
ADPS2
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
Reserved
Reserved
Reserved
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
–
–
–
7
8126BS–AVR–12/08
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are
cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation
the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work
with registers 0x00 to 0x1F only.
8
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
Indirect Jump to (Z)
PC ← PC + k + 1
PC ← Z
None
None
None
None
None
I
2
2
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
BRID
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
I/O(P,b) ← 0
None
None
2
2
1
1
1
LSL
LSR
ROL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
9
8126BS–AVR–12/08
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
s
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd ← (X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
SLEEP
WDR
No Operation
Sleep
None
None
None
None
1
1
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
6. Ordering Information
Speed (MHz) (1)
Power Supply (V) (1)
Ordering Code
Package (2) (3)
Operation Range
ATtiny13A-PU
ATtiny13A-SU
ATtiny13A-SH
ATtiny13A-SSU
ATtiny13A-SSH
ATtiny13A-MU
ATtiny13A-MMU
8P3
8S2
8S2
8S1
8S1
Industrial
(-40⋅C to 85⋅C)
20
1.8 - 5.5
20M1
10M1
Notes: 1. For device speed vs. VCC, see “Speed Grades” on page 118.
2. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
3. All packages are Pb-free, Halide-free, fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC)
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
8S1
20M1
10M1
11
8126BS–AVR–12/08
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
7.2
8S2
C
1
E
E1
L
N
θ
TOP VVIIEEWW
ENDD VVIIEEWW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
4
4
C
D
E1
E
D
2
L
SIDDE VIEW
θ
e
1.27 BSC
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/15/08
GPC
DRAWING NO.
TITLE
REV.
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
Package Drawing Contact:
packagedrawings@atmel.com
STN
8S2
F
13
8126BS–AVR–12/08
7.3
8S1
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
C
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
14
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
7.4
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
3
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
A
R
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
15
8126BS–AVR–12/08
7.5
10M1
D
y
Pin 1 ID
E
SIDE VIEW
TOP VIEW
A1
A
D1
K
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
MIN
MAX
NOM
NOTE
SYMBOL
A
0.80
0.90
1.00
A1
b
0.00
0.18
2.90
1.40
2.90
2.20
0.02
0.25
3.00
–
0.05
0.30
3.10
1.75
3.10
2.70
b
E1
D
D1
E
e
3.00
–
E1
e
0.50
–
L
0.30
–
0.50
0.08
–
L
BOTTOM VIEW
y
–
K
0.20
–
Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5.
2. The terminal #1 ID is a Lasser-marked Feature.
7/7/06
DRAWING NO. REV.
10M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
10M1, 10-pad, 3 x 3 x 1.0 mm Body, Lead Pitch 0.50 mm,
A
R
1.64 x 2.60 mm Exposed Pad, Micro Lead Frame Package
16
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
8. Errata
The revision letters in this section refer to the revision of the ATtiny13A device.
8.1
8.2
8.3
ATtiny13A Rev. G – H
No known errata.
ATtiny13A Rev. E – F
These device revisions were not sampled.
ATtiny13A Rev. A – D
These device revisions were referred to as ATtiny13/ATtiny13V.
17
8126BS–AVR–12/08
9. Datasheet Revision History
Please note that page numbers in this section refer to the current version of this document and
may not apply to previous versions.
9.1
Rev. 8126B – 11/08
1. Updated order codes on page 11 to reflect changes in material composition.
2. Updated sections:
– “DIDR0 – Digital Input Disable Register 0” on page 81
– “DIDR0 – Digital Input Disable Register 0” on page 95
3. Updated “Register Summary” on page 7.
9.2
Rev. 8126A – 05/08
1. Initial revision, created from document 2535I – 04/08.
2. Updated characteristic plots of section “Typical Characteristics” , starting on page 124.
3. Updated “Ordering Information” on page 11.
4. Updated section:
– “Speed Grades” on page 118
5. Update tables:
– “DC Characteristics, TA = -40⋅C to 85⋅C” on page 117
– “Calibration Accuracy of Internal RC Oscillator” on page 119
– “Reset, Brown-out, and Internal Voltage Characteristics” on page 120
– “ADC Characteristics, Single Ended Channels. TA = -40⋅C - 85⋅C” on page 121
– “Serial Programming Characteristics, TA = -40⋅C to 85⋅C” on page 122
6. Added description of new function, “Power Reduction Register”:
– Added functional description on page 31
– Added bit description on page 34
– Added section “Supply Current of I/O Modules” on page 124
– Updated Register Summary on page 7
7. Added description of new function, “Software BOD Disable”:
– Added functional description on page 31
– Updated section on page 32
– Added register description on page 33
– Updated Register Summary on page 7
8. Added description of enhanced function, “Enhanced Power-On Reset”:
– Updated Table 18-4 on page 120, and Table 18-5 on page 120
18
ATtiny13A
8126BS–AVR–12/08
ATtiny13A
19
8126BS–AVR–12/08
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Sales Contact
www.atmel.com
avr@atmel.com
www.atmel.com/contacts
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www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
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as components in applications intended to support or sustain life.
© 2008 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, AVR® and others are registered trademarks or trade-
marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
8126BS–AVR–12/08
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