ATTINY13_14_技术文档

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Througput at 20 MHz

• High Endurance Non-volatile Memory segments

– 1K Bytes of In-System Self-programmable Flash program memory

– 64 Bytes EEPROM

8-bit

– 64 Bytes Internal SRAM

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

– Write/Erase cyles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C (see page 6)

– Programming Lock for Self-Programming Flash & EEPROM Data Security

• Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

ATtiny13

ATtiny13V

• I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

– 20-pad MLF: Six Programmable I/O Lines

• Operating Voltage:

– 1.8 - 5.5V for ATtiny13V

– 2.7 - 5.5V for ATtiny13

• Speed Grade

– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

• 1 MHz, 1.8V: 240 µA

– Power-down Mode:

• < 0.1 µA at 1.8V

Rev. 2535J–AVR–08/10

1. Pin Configurations

Figure 1-1. Pinout ATtiny13/ATtiny13V

8-PDIP/SOIC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

1

2

3

4

8

7

6

5

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

20-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

1

15

VCC

2

3

4

5

14

13

12

11

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

(PCINT4/ADC2) PB4

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

10-QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

1

2

3

4

5

10

9

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

8

(PCINT4/ADC2) PB4

GND

7

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

6

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

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ATtiny13

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB5:PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13 as listed on page 54.

1.1.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page

115. Shorter pulses are not guaranteed to generate a reset.

The reset pin can also be used as a (weak) I/O pin.

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2. Overview

The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC

architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves

throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con-

sumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

8-BIT DATABUS

STACK

POINTER

CALIBRATED

INTERNAL

OSCILLATOR

WATCHDOG

OSCILLATOR

SRAM

WATCHDOG

TIMER

TIMING AND

CONTROL

VCC

GND

MCU CONTROL

REGISTER

PROGRAM

COUNTER

MCU STATUS

REGISTER

PROGRAM

FLASH

TIMER/

COUNTER0

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

X

Y

Z

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

DATA

EEPROM

CONTROL

LINES

ALU

STATUS

REGISTER

ADC /

ANALOG COMPARATOR

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT B DRIVERS

RESET

CLKI

PB0-PB5

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ATtiny13

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64

bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-

isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-

channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-

ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The

Power-down mode saves the register contents, disabling all chip functions until the next Inter-

rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules

except ADC, to minimize switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny13 AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.

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3. General Information

3.1

Resources

A comprehensive set of drivers, application notes, data sheets and descriptions on development

tools are available for download at http://www.atmel.com/avr.

3.2

Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

3.3

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATtiny13

4. CPU Core

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.1

Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

32 x 8

General

Purpose

Registrers

Instruction

Register

Interrupt

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program memory. This concept enables instructions to be executed

in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every Program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

4.2

4.3

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arithme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

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ATtiny13

4.3.1

SREG – Status Register

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

R/W

0

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

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4.4

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2 on page 10, each register is also assigned a Data memory address,

mapping them directly into the first 32 locations of the user Data Space. Although not being

physically implemented as SRAM locations, this memory organization provides great flexibility in

access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in

the file.

4.4.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.

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ATtiny13

Figure 4-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

0

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

4.5

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM is automaticall defined to the last

address in SRAM during power on reset. The Stack Pointer must be set to point above 0x60.

The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH

instruction, and it is decremented by two when the return address is pushed onto the Stack with

subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from

the Stack with the POP instruction, and it is incremented by two when data is popped from the

Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

4.5.1

SPL - Stack Pointer Low.

Bit

15

SP7

7

14

SP6

6

13

SP5

5

12

SP4

4

11

SP3

3

10

SP2

2

9

SP1

1

8

SP0

0

SPL

Read/Write

Initial Value

R/W

1

R/W

0

R/W

0

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

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4.6

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast access Register File concept. This is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions

per cost, functions per clocks, and functions per power-unit.

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock

cycle an ALU operation using two register operands is executed, and the result is stored back to

the destination register.

Figure 4-5. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

4.7

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

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ATtiny13

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence..

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.7.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the Program Vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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5. Memories

This section describes the different memories in the ATtiny13. The AVR architecture has two

main memory spaces, the Data memory and the Program memory space. In addition, the

ATtiny13 features an EEPROM Memory for data storage. All three memory spaces are linear

and regular.

5.1

In-System Reprogrammable Flash Program Memory

The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for program

storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 512 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13 Pro-

gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations.

“Memory Programming” on page 102 contains a detailed description on Flash data serial down-

loading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the

LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

Figure 5-1. Program Memory Map

Program Memory

0x0000

0x01FF

5.2

SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny13 SRAM Memory is organized.

The lower 160 Data memory locations address both the Register File, the I/O memory and the

internal data SRAM. The first 32 locations address the Register File, the next 64 locations the

standard I/O memory, and the last 64 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

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The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data

SRAM in the ATtiny13 are all accessible through all these addressing modes. The Register File

is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060

32 Registers

64 I/O Registers

Internal SRAM

(64 x 8)

0x009F

5.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

5.3

EEPROM Data Memory

The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate data

space, in which single bytes can be read and written. The EEPROM has an endurance of at

least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described

in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and

the EEPROM Control Register. For a detailed description of Serial data downloading to the

EEPROM, see page 105.

5.3.1

16

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

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The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-

tered power supplies, V_CCis likely to rise or fall slowly on Power-up/down. This causes the

device for some period of time to run at a voltage lower than specified as minimum for the clock

frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the

user must write the address into the EEARL Register and data into EEDR Register. If the

EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the

erase/write operation. Both the erase and write cycle are done in one operation and the total

programming time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase

and write operations are completed. While the device is busy with programming, it is not possi-

ble to do any other EEPROM operations.

5.3.3

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possible to do the erase operations when the system allows doing time-critical

operations (typically after Power-up).

5.3.4

5.3.5

Erase

Write

To erase a byte, the address must be written to EEARL. If the EEPMn bits are 0b01, writing the

EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-

ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation

completes. While the device is busy programming, it is not possible to do any other EEPROM

operations.

To write a location, the user must write the address into EEARL and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit

remains set until the write operation completes. If the location to be written has not been erased

before write, the data that is stored must be considered as lost. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-

quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 27.

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The following code examples show one assembly and one C function for erase, write, or atomic

write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling

interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r17) in address register

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0>>EEPM0)

/* Set up address and data registers */

EEARL = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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ATtiny13

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r17) in address register

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEARL = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

5.3.6

Preventing EEPROM Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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5.4

I/O Memory

The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 156.

All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed

by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general

purpose working registers and the I/O space. I/O Registers within the address range 0x00 -

0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value

of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction

set section for more details. When using the I/O specific commands IN and OUT, the I/O

addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD

and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5

Register Description

5.5.1

EEARL – EEPROM Address Register

Bit

7

–

6

–

5

EEAR5

R/W

X

4

EEAR4

R/W

X

3

EEAR3

R/W

X

2

EEAR2

R/W

X

1

EEAR1

R/W

X

0

EEAR0

R/W

X

EEARL

Read/Write

Initial Value

R

0

R

0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 5:0 – EEAR[5:0]: EEPROM Address

The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64 bytes

EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. The initial

value of EEARL is undefined. A proper value must be written before the EEPROM may be

accessed.

5.5.2

EEDR – EEPROM Data Register

Bit

7

6

EEDR6

R/W

X

5

EEDR5

R/W

X

4

EEDR4

R/W

X

3

EEDR3

R/W

X

2

EEDR2

R/W

X

1

EEDR1

R/W

X

0

EEDR0

R/W

X

EEDR7

R/W

X

EEDR

Read/Write

Initial Value

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEARL.

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ATtiny13

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ATtiny13

5.5.3

EECR – EEPROM Control Register

Bit

7

–

6

–

5

EEPM1

R/W

X

4

EEPM0

R/W

X

3

EERIE

R/W

0

2

EEMPE

R/W

0

1

EEPE

R/W

X

0

EERE

R/W

0

EECR

Read/Write

Initial Value

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibility with

future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny13 and will always read as zero.

• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be

triggered when writing EEPE. It is possible to program data in one atomic operation (erase the

old value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 5-1 on page 21.

While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be

reset to 0b00 unless the EEPROM is busy programming.

Table 5-1.

EEPROM Mode Bits

Programming

EEPM1

EEPM0

Time

3.4 ms

1.8 ms

–

Operation

0

1

0

1

0

1

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-

rupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.

When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.

The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no

EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by

hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction

is executed.

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• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-

rect address is set up in the EEARL Register, the EERE bit must be written to one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed. The user should poll the EEPE bit before starting the read opera-

tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change

the EEARL Register.

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ATtiny13

6. System Clock and Clock Options

6.1

Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 30. The clock systems are detailed below.

Figure 6-1. Clock Distribution

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_ADC

clk_FLASH

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Clock

Multiplexer

Watchdog

Oscillator

Calibrated RC

Oscillator

External Clock

6.1.1

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2

6.1.3

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

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6.1.4

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 6-1.

Device Clocking Options Select

Device Clocking Option

CKSEL1:0⁽¹⁾

External Clock (see page 24)

00

01, 10

11

Calibrated Internal 4.8/9.6 MHz Oscillator (see page 25)

Internal 128 kHz Oscillator (see page 26)

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the

start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-

2.

Table 6-2.

Number of Watchdog Oscillator Cycles

Typ Time-out

4 ms

Number of Cycles

512

64 ms

8K (8,192)

6.2.1

External Clock

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-

2. To run the device on an external clock, the CKSEL fuses must be programmed to “00”.

Figure 6-2. External Clock Drive Configuration

EXTERNAL

CLKI

GND

CLOCK

SIGNAL

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ATtiny13

When this clock source is selected, start-up times are determined by the SUT fuses as shown in

Table 6-3.

Start-up Times for the External Clock Selection

Start-up Time from

Power-down and Power-save

Additional Delay

from Reset

Recommended

Usage

SUT1..0

00

6 CK

14CK

BOD enabled

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

10

Slowly rising power

11

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

26 for details.

6.2.2

Calibrated Internal 4.8/9.6 MHz Oscillator

The calibrated internal oscillator provides a 4.8 or 9.6 MHz clock source. The frequency is nomi-

nal at 3V and 25°C. If the frequency exceeds the specification of the device (depends on V_CC),

the CKDIV8 fuse must be programmed so that the internal clock is divided by 8 during start-up.

See “System Clock Prescaler” on page 26. for more details.

The internal oscillator is selected as the system clock by programming the CKSEL fuses as

shown in Table 6-4. If selected, it will operate with no external components.

Table 6-4.

Internal Calibrated RC Oscillator Operating Modes

CKSEL1..0

10⁽¹⁾

Nominal Frequency

9.6 MHz

4.8 MHz

01

Note:

1. The device is shipped with this option selected.

During reset, hardware loads the calibration data into the OSCCAL register and thereby auto-

matically calibrates the oscillator. There are separate calibration bytes for 4.8 and 9.6 MHz

operation but only one is automatically loaded during reset (see section “Calibration Bytes” on

page 104). This is because the only difference between 4.8 MHz and 9.6 MHz mode is an inter-

nal clock divider.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 27, it is possible to get a higher calibration accuracy than by using the factory calibration.

See “Calibrated Internal RC Oscillator Accuracy” on page 118.

When this oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section “Calibration Bytes” on page 104.

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When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

Start-up Time

from Power-down

Additional Delay from

Reset (V_CC= 5.0V)

SUT1..0

00

Recommended Usage

BOD enabled

6 CK

14CK

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

10⁽¹⁾

Slowly rising power

11

Note:

1. The device is shipped with this option selected.

6.2.3

Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency depends on supply voltage, temperature and batch variations. This clock may be select

as the system clock by programming the CKSEL fuses to “11”.

When this clock source is selected, start-up times are determined by the SUT fuses as shown in

Table 6-6.

Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from

Power-down and Power-save

Additional Delay

from Reset

Recommended

Usage

SUT1:0

00

6 CK

14CK

BOD enabled

01

14CK + 4 ms

14CK + 64 ms

Reserved

Fast rising power

10

Slowly rising power

11

6.2.4

Default Clock Source

The device is shipped with CKSEL = “10”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is therefore the Internal RC Oscillator running at 9.6 MHz with longest start-

up time and an initial system clock prescaling of 8. This default setting ensures that all users can

make their desired clock source setting using an In-System or High-voltage Programmer.

6.3

System Clock Prescaler

The ATtiny13 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on

page 28. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH

are divided by a factor as shown in Table 6-8 on page 28.

6.3.1

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

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ATtiny13

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the

previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4

Register Description

6.4.1

OSCCAL – Oscillator Calibration Register

Bit

7

–

6

5

4

3

2

1

0

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

R

0

Device Specific Calibration Value

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in ATtiny13 and it will always read zero.

• Bits 6:0 – CAL[6:0]: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process vari-

ations from the Oscillator frequency. This is done automatically during Chip Reset. When

OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis-

ter will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the

highest available frequency.

The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is

written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the

EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or

4.8 MHz. Tuning to other values is not guaranteed, as indicated in Table 6-7 below.

To ensure stable operation of the MCU the calibration value should be changed in small steps. A

variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble

behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to

ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-7.

Internal RC Oscillator Frequency Range

Typical Lowest Frequency

Typical Highest Frequency

OSCCAL Value

0x00

with Respect to Nominal Frequency

50%

75%

100%

150%

200%

0x3F

0x7F

100%

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2535J–AVR–08/10

6.4.2

CLKPR – Clock Prescale Register

Bit

7

CLKPCE

R/W

0

6

–

5

–

4

–

3

2

1

0

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

Read/Write

Initial Value

R

0

R

0

R

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-8 on page 28.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.hee setting. The Application software must ensure that a sufficient division factor

is chosen if the selected clock source has a higher frequency than the maximum frequency of

the device at the present operating conditions. The device is shipped with the CKDIV8 fuse

programmed.

Table 6-8.

Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

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ATtiny13

Table 6-8.

Clock Prescaler Select (Continued)

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

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7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an

ideal choise for low power applications. In addition, sleep modes enable the application to shut

down unused modules in the MCU, thereby saving power. The AVR provides various sleep

modes allowing the user to tailor the power consumption to the application’s requirements.

7.1

Sleep Modes

Figure 6-1 on page 23 presents the different clock systems in the ATtiny13, and their distribu-

tion. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different

sleep modes and their wake up sources.

Table 7-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

X

ADC Noise

Reduction

X

X⁽¹⁾

Power-down

Note:

1. For INT0, only level interrupt.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which

sleep mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruc-

tion. See Table 7-2 on page 33 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 45

for details.

7.1.1

Idle Mode

When the SM[1:0] bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically halts clk_CPUand clk_FLASH, while

allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

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ATtiny13

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

7.1.2

ADC Noise Reduction Mode

When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode halts clk_I/O, clk_CPU, and clk_FLASH

while allowing the other clocks to run.

,

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change

interrupt can wake up the MCU from ADC Noise Reduction mode.

7.1.3

Power-down Mode

When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-

dog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out

Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This

sleep mode halts all generated clocks, allowing operation of asynchronous modules only.

7.2

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

7.2.1

7.2.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 81 for

details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. Refer to “Analog Comparator” on page 78 for details on how to con-

figure the Analog Comparator.

7.2.3

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the

Brown-out Detector is enabled by the BODLEVEL fuses, it will be enabled in all sleep modes,

and hence, always consume power. In the deeper sleep modes, this will contribute significantly

to the total current consumption. Refer to “Brown-out Detection” on page 36 for details on how to

configure the Brown-out Detector.

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2535J–AVR–08/10

7.2.4

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 37 for details on the start-up time.

7.2.5

7.2.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Interrupts” on page 44 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 52 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to

“DIDR0 – Digital Input Disable Register 0” on page 80 for details.

7.3

Register Description

7.3.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

Bit

7

–

6

5

SE

R/W

0

4

3

2

—

R

0

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

Read/Write

Initial Value

R

0

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

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ATtiny13

• Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1:0

These bits select between the three available sleep modes as shown in Table 7-2 on page 33.

Table 7-2.

Sleep Mode Select

SM1

SM0

Sleep Mode

Idle

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Reserved

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny13 and will always read as zero.

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8. System Control and Reset

8.0.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. The circuit diagram in Figure 8-1 on page 34 shows the reset logic. “System and

Reset Characteristics” on page 119 defines the electrical parameters of the reset circuitry.

Figure 8-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

Reset Circuit

BODLEVEL [1..0]

Pull-up Resistor

SPIKE

FILTER

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[1:0]

SUT[1:0]

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL fuses. The differ-

ent selections for the delay period are presented in “Clock Sources” on page 24.

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ATtiny13

8.1

Reset Sources

The ATtiny13 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the Brown-out Detector is enabled.

8.1.1

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in “System and Reset Characteristics” on page 119. The POR is activated whenever

V

_CCis below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

Figure 8-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 8-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

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8.1.2

External Reset

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer

than the minimum pulse width (See “System and Reset Characteristics” on page 119.) will gen-

erate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a

reset. When the applied signal reaches the Reset Threshold Voltage – V_RST– on its positive

edge, the delay counter starts the MCU after the Time-out period – t_TOUT– has expired.

Figure 8-4. External Reset During Operation

CC

8.1.3

Brown-out Detection

ATtiny13 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel during

operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected

by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free Brown-out

Detection. The hysteresis on the detection level should be interpreted as V_BOT+= V_BOT+ V_HYST/2

and V_BOT-= V_BOT- V_HYST/2.

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

8-5 on page 36), the Brown-out Reset is immediately activated. When V_CCincreases above the

trigger level (V_BOT+in Figure 8-5 on page 36), the delay counter starts the MCU after the Time-

out period t_TOUThas expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for lon-

ger than t_BODgiven in “System and Reset Characteristics” on page 119.

Figure 8-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

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ATtiny13

8.1.4

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

“Interrupts” on page 44 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

CC

CK

8.2

Internal Voltage Reference

ATtiny13 features an internal bandgap reference. This reference is used for Brown-out Detec-

tion, and it can be used as an input to the Analog Comparator or the ADC.

8.2.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 119. To save power, the

reference is not always turned on. The reference is on during the following situations:

• When the BOD is enabled (by programming the BODLEVEL [1..0] fuse).

• When the bandgap reference is connected to the Analog Comparator (by setting the ACBG

bit in ACSR).

• When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.3

Watchdog Timer

ATtiny13 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a

separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the

counter reaches a given time-out value. In normal operation mode, it is required that the system

uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out

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2535J–AVR–08/10

value is reached. If the system doesn't restart the counter, an interrupt or system reset will be

issued.

Figure 8-7. Watchdog Timer

128kHz

OSCILLATOR

WDP0

WDP1

WATCHDOG

WDP2

RESET

WDP3

WDE

MCU RESET

WDTIF

INTERRUPT

WDTIE

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used

to wake the device from sleep-modes, and also as a general system timer. One example is to

limit the maximum time allowed for certain operations, giving an interrupt when the operation

has run longer than expected. In System Reset mode, the WDT gives a reset when the timer

expires. This is typically used to prevent system hang-up in case of runaway code. The third

mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-

rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown

by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

mode bit (WDTIE) are locked to 1 and 0 respectively. To further ensure program security, altera-

tions to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and

changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)

and WDE. A logic one must be written to WDE regardless of the previous value of the

WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

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ATtiny13

The following code example shows one assembly and one C function for turning off the Watch-

dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts

globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example⁽¹⁾

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in

andi r16, (0xff - (1<<WDRF))

out MCUSR, r16

r16, MCUSR

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in

r16, WDTCR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCR, r16

; Turn off WDT

ldi

out

r16, (0<<WDE)

WDTCR, r16

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out

*/

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condi-

tion, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up

to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situa-

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2535J–AVR–08/10

tion, the application software should always clear the Watchdog System Reset Flag (WDRF)

and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out

value of the Watchdog Timer.

Assembly Code Example⁽¹⁾

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in

r16, WDTCR

ori

out

r16, (1<<WDCE) | (1<<WDE)

WDTCR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi

out

r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

WDTCR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example⁽¹⁾

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed sequence */

WDTCR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

Note:

1. The example code assumes that the part specific header file is included.

The Watchdog Timer should be reset before any change of the WDP bits, since a change in the

WDP bits can result in a time-out when switching to a shorter time-out period.

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ATtiny13

8.4

Register Description

8.4.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit

7

–

6

–

5

–

4

–

3

2

1

0

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

See Bit Description

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

8.4.2

WDTCR – Watchdog Timer Control Register

Bit

7

6

5

WDP3

R/W

0

4

WDCE

R/W

0

3

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

WDTIF

WDTIE

WDE

R/W

X

WDTCR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 - WDTIF: Watchdog Timer Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDTIF is cleared by writing a logic one to the flag. When the I-bit

in SREG and WDTIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDTIE: Watchdog Timer Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDTIF. Executing the corresponding interrupt vector will clear

WDTIE and WDTIF automatically by hardware (the Watchdog goes to System Reset Mode).

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This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Inter-

rupt and System Reset Mode, WDTIE must be set after each interrupt. This should however not

be done within the interrupt service routine itself, as this might compromise the safety-function of

the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a

System Reset will be applied.

Table 8-1.

Watchdog Timer Configuration

WDTON⁽¹⁾

WDE

WDTIE

Mode

Action on Time-out

None

1

0

1

0

1

0

Stopped

Interrupt Mode

System Reset Mode

Interrupt

Reset

Interrupt and System Reset

Mode

Interrupt, then go to System

Reset Mode

1

0

1

x

1

x

System Reset Mode

Reset

Note:

1. WDTON fuse set to “0“ means programmed and “1“ means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 8-2 on page 42..

Table 8-2.

Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

4K (4096) cycles

8K (8192) cycles

16K (16384) cycles

32K (32768) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

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ATtiny13

Table 8-2.

Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

Cycles

1

0

1

0

1

0

1

0

1

0

1

Reserved

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2535J–AVR–08/10

9. Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny13. For a

general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on

page 12.

9.1

Interrupt Vectors

The interrupt vectors of ATtiny13 are described in Table 9-1 below.

Table 9-1.

Vector No.

Reset and Interrupt Vectors

Program Address

Source

Interrupt Definition

External Pin, Power-on Reset,

Brown-out Reset, Watchdog Reset

1

0x0000

RESET

2

3

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

INT0

External Interrupt Request 0

Pin Change Interrupt Request 0

Timer/Counter Overflow

EEPROM Ready

PCINT0

4

TIM0_OVF

EE_RDY

ANA_COMP

TIM0_COMPA

TIM0_COMPB

WDT

5

6

Analog Comparator

7

Timer/Counter Compare Match A

Timer/Counter Compare Match B

Watchdog Time-out

8

9

10

ADC

ADC Conversion Complete

If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular

program code can be placed at these locations.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATtiny13 is:

Address Labels Code

Comments

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

;

rjmp

RESET

; Reset Handler

EXT_INT0

PCINT0

; IRQ0 Handler

; PCINT0 Handler

TIM0_OVF

EE_RDY

; Timer0 Overflow Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; Timer0 CompareA Handler

; Timer0 CompareB Handler

; Watchdog Interrupt Handler

; ADC Conversion Handler

ANA_COMP

TIM0_COMPA

TIM0_COMPB

WATCHDOG

ADC

0x000A RESET: ldi

r16, low(RAMEND); Main program start

SPL,r16 ; Set Stack Pointer to top of RAM

sei ; Enable interrupts

<instr> xxx

... ... ...

0x000B

0x000C

0x000D

...

out

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ATtiny13

9.2

External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that,

if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out-

puts. This feature provides a way of generating a software interrupt. Pin change interrupts PCI

will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins con-

tribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected

asynchronously. This implies that these interrupts can be used for waking the part also from

sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is

enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held

low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an

I/O clock, described in “Clock Systems and their Distribution” on page 23.

9.2.1

Low Level Interrupt

A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as described in

“System Clock and Clock Options” on page 23.

If the low level on the interrupt pin is removed before the device has woken up then program

execution will not be diverted to the interrupt service routine but continue from the instruction fol-

lowing the SLEEP command.

9.2.2

Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 9-1 below.

Figure 9-1. Timing of pin change interrupts

pin_lat

pcint_in_(0)

PCINT(0)

0

x

D

Q

pcint_syn

pcint_setflag

PCIF

pin_sync

PCINT(0) in PCMSK(x)

LE

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

45

2535J–AVR–08/10

9.3

Register Description

9.3.1

MCUCR – MCU Control Register

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit

7

–

6

5

SE

R/W

0

4

3

2

–

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 9-2 on page 46. The value on the INT0 pin is sampled before

detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock

period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If

low level interrupt is selected, the low level must be held until the completion of the currently

executing instruction to generate an interrupt.

Table 9-2.

Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

9.3.2

GIMSK – General Interrupt Mask Register

Bit

7

–

6

5

PCIE

R/W

0

4

–

3

–

2

–

1

–

0

–

INT0

R/W

0

GIMSK

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE: Pin Change Interrupt Enable

When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt

Vector. PCINT5..0 pins are enabled individually by the PCMSK Register.

46

ATtiny13

2535J–AVR–08/10

ATtiny13

9.3.3

GIFR – General Interrupt Flag Register

Bit

7

–

6

INTF0

R/W

0

5

PCIF

R/W

0

4

–

3

–

2

–

1

–

0

–

R

0

GIFR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT5:0 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

9.3.4

PCMSK – Pin Change Mask Register

Bit

7

6

–

5

PCINT5

R/W

0

4

PCINT4

R/W

0

3

PCINT3

R/W

0

2

PCINT2

R/W

0

1

PCINT1

R/W

0

PCINT0

R/W

0

–

R

0

PCMSK

Read/Write

Initial Value

R

0

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0

Each PCINT5:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT5:0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the cor-

responding I/O pin. If PCINT5:0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

47

2535J–AVR–08/10

10. I/O Ports

10.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 10-1. Refer to “Electrical Char-

acteristics” on page 115 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

C_pin

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description” on page 56.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

49. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 53. Refer to the individual module sections for a full description of the alter-

nate functions.

48

ATtiny13

2535J–AVR–08/10

ATtiny13

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 on page 49

shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

SLEEP:

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

SLEEP, and PUD are common to all ports.

,

10.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description” on page 56, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

49

2535J–AVR–08/10

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

10.2.2

10.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b10) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

No

Comment

0

1

0

1

0

1

X

0

Input

Tri-state (Hi-Z)

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

1

Input

X

Output

No

Output Low (Sink)

Output High (Source)

No

10.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 10-2 on page 49, the PINxn Register bit and the preced-

ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 on

page 51 shows a timing diagram of the synchronization when reading an externally applied pin

value. The maximum and minimum propagation delays are denoted t_pd,maxand t_pd,min

respectively.

50

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

XXX

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-4 on page 51. The out instruction sets the “SYNC LATCH” signal at the

positive edge of the clock. In this case, the delay tpd through the synchronizer is one system

clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

51

2535J–AVR–08/10

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values

are read back again, but as previously discussed, a nop instruction is included to be able to read

back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as

low and redefining bits 0 and 1 as strong high drivers.

10.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 10-2 on page 49, the digital input signal can be clamped to ground at the

input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep

Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power

consumption if some input signals are left floating, or have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 53.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

52

ATtiny13

2535J–AVR–08/10

ATtiny13

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

10.2.6

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5

shows how port pin control signals from the simplified Figure 10-2 on page 49 can be overridden

by alternate functions.

Figure 10-5. Alternate Port Functions

PUOExn

PUOVxn

1

PUD

0

DDOExn

DDOVxn

1

Q

D

0

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RESET

WRx

1

0

RRx

SYNCHRONIZER

RPx

SET

D

L

Q

D

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O:

I/O CLOCK

SLEEP:

SLEEP CONTROL

DIxn:

DIGITAL INPUT PIN n ON PORTx

AIOxn:

ANALOG INPUT/OUTPUT PIN n ON PORTx

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O, SLEEP,

and PUD are common to all ports. All other signals are unique for each pin.

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2535J–AVR–08/10

The overriding signals may not be present in all port pins, but Figure 10-5 serves as a generic

description applicable to all port pins in the AVR microcontroller family.

Table 10-2 on page 54 summarizes the function of the overriding signals. The pin and port

indexes from Figure 10-5 on page 53 are not shown in the succeeding tables. The overriding

signals are generated internally in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is enabled

when {DDxn, PORTxn, PUD} = 0b010.

Pull-up

Override Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV

is set/cleared, regardless of the setting of the DDxn,

PORTxn, and PUD Register bits.

Pull-up

Override Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by

the DDOV signal. If this signal is cleared, the Output driver

is enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared,

and the Output Driver is enabled, the port Value is

controlled by the PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of

the setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU state (Normal mode, sleep

mode).

Digital Input Enable

Override Enable

DIEOE

DIEOV

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

Digital Input Enable

Override Value

This is the Digital Input to alternate functions. In the figure,

the signal is connected to the output of the schmitt-trigger

but before the synchronizer. Unless the Digital Input is used

as a clock source, the module with the alternate function

will use its own synchronizer.

DI

Digital Input

This is the Analog Input/Output to/from alternate functions.

The signal is connected directly to the pad, and can be

used bi-directionally.

AIO

Analog Input/Output

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

10.3.1

54

Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 10-3 on page 55.

ATtiny13

2535J–AVR–08/10

ATtiny13

Table 10-3. Port B Pins Alternate Functions

Port Pin

Alternate Function

RESET: Reset Pin

dW:

debugWIRE I/O

PB5

ADC0: ADC Input Channel 0

PCINT5: Pin Change Interrupt, Source 5

ADC2: ADC Input Channel 2

PB4

PB3

PCINT4: Pin Change Interrupt 0, Source 4

CLKI:

External Clock Input

ADC3: ADC Input Channel 3

PCINT3: Pin Change Interrupt 0, Source 3

SCK:

Serial Clock Input

ADC1: ADC Input Channel 1

PB2

PB1

PB0

T0:

Timer/Counter0 Clock Source.

PCINT2: Pin Change Interrupt 0, Source 2

MISO: SPI Master Data Input / Slave Data Output

AIN1:

OC0B: Timer/Counter0 Compare Match B Output

INT0: External Interrupt 0 Input

Analog Comparator, Negative Input

PCINT1:Pin Change Interrupt 0, Source 1

MOSI:: SPI Master Data Output / Slave Data Input

AIN0:

Analog Comparator, Positive Input

OC0A: Timer/Counter0 Compare Match A output

PCINT0: Pin Change Interrupt 0, Source 0

Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 53.

Table 10-4. Overriding Signals for Alternate Functions in PB5:PB3

Signal

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

PB5/RESET/ADC0/PCINT5

PB4/ADC2/PCINT4

PB3/ADC3/CLKI/PCINT3

RSTDISBL⁽¹⁾• DWEN⁽¹⁾

0

1

RSTDISBL⁽¹⁾• DWEN⁽¹⁾

debugWire Transmit

0

RSTDISBL⁽¹⁾+ (PCINT5 •

PCIE + ADC0D)

DIEOE

PCINT4 • PCIE + ADC2D

PCINT3 • PCIE + ADC3D

DIEOV

DI

ADC0D

ADC2D

ADC3D

PCINT5 Input

PCINT4 Input

ADC2 Input

PCINT3 Input

ADC3 Input

AIO

RESET Input, ADC0 Input

Note:

1. 1 when the fuse is “0” (Programmed).

55

2535J–AVR–08/10

Table 10-5. Overriding Signals for Alternate Functions in PB2:PB0

Signal

Name

PB2/SCK/ADC1/

T0/PCINT2

PB1/MISO/AIN1/

OC0B/INT0/PCINT1

PB0/MOSI/AIN0/

AREF/OC0A/PCINT0

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

DIEOE

DIEOV

0

OC0B Enable

OC0A Enable

0

OC0B

OC0A

0

PCINT2 • PCIE + ADC1D

ADC1D

PCINT1 • PCIE + AIN1D

AIN1D

PCINT0 • PCIE + AIN0D

AIN0D

T0/INT0/

PCINT2 Input

DI

PCINT1 Input

PCINT0 Input

Analog Comparator

Negative Input

Analog Comparator Positive

Input

AIO

ADC1 Input

10.4 Register Description

10.4.1

MCUCR – MCU Control Register

Bit

7

–

6

5

SE

R/W

0

4

3

2

–

1

ISC01

R/W

0

ISC00

R/W

0

PUD

R/W

0

SM1

R/W

0

SM0

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

• Bits 7, 2– Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 49 for more details about this feature.

10.4.2

10.4.3

PORTB – Port B Data Register

Bit

7

6

–

5

PORTB5

R/W

0

4

PORTB4

R/W

0

3

PORTB3

R/W

0

2

PORTB2

R/W

0

1

PORTB1

R/W

0

PORTB0

R/W

0

–

R

0

PORTB

Read/Write

Initial Value

R

0

DDRB – Port B Data Direction Register

Bit

7

–

6

–

5

DDB5

R/W

0

4

DDB4

R/W

0

3

DDB3

R/W

0

2

DDB2

R/W

0

1

DDB1

R/W

0

DDB0

R/W

0

DDRB

Read/Write

Initial Value

R

0

R

0

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10.4.4

PINB – Port B Input Pins Address

Bit

7

–

6

–

5

4

3

2

1

0

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

PINB

Read/Write

Initial Value

R

0

R

0

N/A

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11. 8-bit Timer/Counter0 with PWM

11.1 Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

11.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units, and with PWM support. It allows accurate program execution timing (event man-

agement) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 11-1 on page 58. For

the actual placement of I/O pins, refer to “Pinout ATtiny13/ATtiny13V” on page 2. CPU accessi-

ble I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

Register and bit locations are listed in the “Register Description” on page 69.

Figure 11-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

Generation

=

OCRnB

TCCRnA

TCCRnB

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11.2.1

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See “Output Compare Unit” on page 60. for details. The Compare Match event will also

set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare

interrupt request.

11.2.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 11-1 on page 59 are also used extensively throughout the document.

Table 11-1. Definitions

BOTTOM

MAX

The counter reaches the BOTTOM when it becomes 0x00.

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is depen-

dent on the mode of operation.

11.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-

caler, see “Timer/Counter Prescaler” on page 76.

11.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-2 shows a block diagram of the counter and its surroundings.

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Figure 11-2. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

Edge

Detector

Tn

clk_Tn

clear

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

clk_Tn

top

bottom

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

Control Register B (TCCR0B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare output OC0A. For more

details about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 63.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

11.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation (See “Modes of Operation” on page 63.).

Figure 11-3 on page 61 shows a block diagram of the Output Compare unit.

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Figure 11-3. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

Waveform Generator

OCnx

FOCn

WGMn1:0

COMnX1:0

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare

Registers to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly.

11.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the

OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare

Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

11.5.2

11.5.3

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNT0 when using the Output Compare

Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

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generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when

changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

11.6 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses

the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.

Also, the COM0x1:0 bits control the OC0x pin output source. Figure 11-4 on page 62 shows a

simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O

bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control

Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring

to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system

reset occur, the OC0x Register is reset to “0”.

Figure 11-4. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCn

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

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The design of the Output Compare pin logic allows initialization of the OC0x state before the out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 69.

11.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is to be performed on the next Compare Match. For compare output actions in

the non-PWM modes refer to Table 11-2 on page 69. For fast PWM mode, refer to Table 11-3 on

page 70, and for phase correct PWM refer to Table 11-4 on page 70.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

11.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output

mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare

Match (See “Compare Match Output Unit” on page 62.).

For detailed timing information refer to Figure 11-8 on page 68, Figure 11-9 on page 68, Figure

11-10 on page 68 and Figure 11-11 on page 69 in “Timer/Counter Timing Diagrams” on page

67.

11.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

11.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the Compare Match output frequency. It

also simplifies the operation of counting external events.

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The timing diagram for the CTC mode is shown in Figure 11-5 on page 64. The counter value

(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun-

ter (TCNT0) is cleared.

Figure 11-5. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each Compare Match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC0

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= --------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

11.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the

operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

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for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 11-6 on page 65. The TCNT0 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes repre-

sent Compare Matches between OCR0x and TCNT0.

Figure 11-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows

the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available

for the OC0B pin (See Table 11-3 on page 70). The actual OC0x value will only be visible on the

port pin if the data direction for the port pin is set as output. The PWM waveform is generated by

setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and

clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes

from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ------------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

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in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

11.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 11-7 on page 66. The TCNT0 value is in the timing diagram shown as a histogram for

illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM out-

puts. The small horizontal line marks on the TCNT0 slopes represent Compare Matches

between OCR0x and TCNT0.

Figure 11-7. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCn

(COMnx1:0 = 3)

OCn

1

2

3

Period

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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (See Table 11-4 on page 70). The actual OC0x value will only be

visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is

generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x

and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-

pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ------------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 11-7 on page 66 OCn has a transition from high to low

even though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 11-7 on page 66. When the OCR0A value

is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of

an up-counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

11.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 11-8 on page 68 contains timing data for basic Timer/Counter operation.

The figure shows the count sequence close to the MAX value in all modes other than phase cor-

rect PWM mode.

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Figure 11-8. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 11-9 shows the same timing data, but with the prescaler enabled.

Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 11-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

Figure 11-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 11-11 on page 69 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode

and fast PWM mode where OCR0A is TOP.

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Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

11.9 Register Description

11.9.1

TCCR0A – Timer/Counter Control Register A

Bit

7

COM0A1

R/W

6

COM0A0

R/W

5

COM0B1

R/W

4

COM0B0

R/W

3

–

2

1

0

–

R

0

WGM01

R/W

0

WGM00

R/W

0

TCCR0A

Read/Write

Initial Value

R

0

• Bits 7:6 – COM01A:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting.

Table 11-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or

CTC mode (non-PWM).

Table 11-2. Compare Output Mode, non-PWM Mode

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0A disconnected.

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 11-3 on page 70 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to

fast PWM mode.

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Table 11-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM01

COM00

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match, set OC0A at TOP

Set OC0A on Compare Match, clear OC0A at TOP

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 64

for more details.

Table 11-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 11-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

0

1

0

1

Clear OC0A on Compare Match when up-counting. Set OC0A on

Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 66 for more details.

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0

bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin

must be set in order to enable the output driver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the

WGM02:0 bit setting.

Table 11-5 on page 71 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to

a normal or CTC mode (non-PWM).

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Table 11-5. Compare Output Mode, non-PWM Mode

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Toggle OC0B on Compare Match

Clear OC0B on Compare Match

Set OC0B on Compare Match

Table 11-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 11-6. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM01

COM00

Description

0

1

0

1

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match, set OC0B at TOP

Set OC0B on Compare Match, clear OC0B at TOP

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 64

for more details.

Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 11-7. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0A0

Description

0

1

Normal port operation, OC0B disconnected.

Reserved

Clear OC0B on Compare Match when up-counting. Set OC0B on

Compare Match when down-counting.

1

0

1

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

Note:

1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on

page 66 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

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• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 11-8 on page 72. Modes of operation supported by the

Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode,

and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 63).

Table 11-8. Waveform Generation Mode Bit Description

Timer/Counter

Mode of

Operation

Update of

OCRx at

TOV Flag

Mode

WGM2

WGM1

WGM0

TOP

Set on⁽¹⁾⁽²⁾

0

Normal

0xFF

Immediate

TOP

MAX

PWM

(Phase Correct)

1

0

1

0xFF

BOTTOM

2

3

4

0

1

0

1

0

CTC

OCRA

0xFF

–

Immediate

MAX

–

Fast PWM

Reserved

TOP

–

PWM

(Phase Correct)

5

1

0

1

OCRA

TOP

BOTTOM

6

7

1

0

1

Reserved

Fast PWM

–

OCRA

TOP

Notes: 1. MAX

= 0xFF

2. BOTTOM = 0x00

11.9.2

TCCR0B – Timer/Counter Control Register B

Bit

7

FOC0A

W

6

FOC0B

W

5

–

4

3

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

–

R

0

WGM02

R/W

0

TCCR0B

Read/Write

Initial Value

R

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

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ATtiny13

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “TCCR0A – Timer/Counter Control Register A” on page 69.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 11-9. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

11.9.3

TCNT0 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

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11.9.4

11.9.5

11.9.6

OCR0A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

OCR0A[7:0]

OCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

OCR0B – Output Compare Register B

Bit

7

6

5

4

3

2

1

0

OCR0B[7:0]

OCR0B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0B pin.

TIMSK0 – Timer/Counter Interrupt Mask Register

Bit

7

6

5

4

–

3

OCIE0B

R/W

0

2

OCIE0A

R/W

0

1

TOIE0

R/W

0

–

TIMSK0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bits 7:4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

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ATtiny13

11.9.7

TIFR0 – Timer/Counter 0 Interrupt Flag Register

Bit

7

–

6

–

5

–

4

–

3

OCF0B

R/W

0

2

OCF0A

R/W

0

1

TOV0

R/W

0

–

R

0

TIFR0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7:4, 0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 2 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 11-8, “Waveform

Generation Mode Bit Description” on page 72.

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12. Timer/Counter Prescaler

12.1 Overview

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024.

12.2 Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state

of the prescaler will have implications for situations where a prescaled clock is used. One exam-

ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 >

CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count

occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,

256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution.

12.3 External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk_T0). The

T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 12-1 on page 76 shows

a functional equivalent block diagram of the T0 synchronization and edge detector logic. The

registers are clocked at the positive edge of the internal system clock (clk_I/O). The latch is trans-

parent in the high period of the internal system clock.

The edge detector generates one clk_T₀pulse for each positive (CSn2:0 = 7) or negative (CSn2:0

= 6) edge it detects.

Figure 12-1. T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

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ATtiny13

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

Figure 12-2. Prescaler for Timer/Counter0

clk_I/O

Clear

PSR10

T0

Synchronization

clk_T0

Note:

1. The synchronization logic on the input pins (T0) is shown in Figure 12-1 on page 76.

12.4 Register Description.

12.4.1

GTCCR – General Timer/Counter Control Register

Bit

7

6

–

5

–

4

–

3

–

2

–

1

–

0

PSR10

R/W

0

TSM

R/W

0

GTCCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

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13. Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate inter-

rupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator

output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown

in Figure 13-1 on page 78.

Figure 13-1. Analog Comparator Block Diagram

BANDGAP

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

See Figure 1-1 on page 2, Table 10-5 on page 56, and Table 13-2 on page 80 for Analog Compar-

ator pin placement.

13.1 Analog Comparator Multiplexed Input

It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1:0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

13-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 13-1. Analog Comparator Multiplexed Input

ACME

ADEN

MUX1..0

Analog Comparator Negative Input

0

1

x

1

0

xx

00

01

10

11

AIN1

ADC0

ADC1

ADC2

ADC3

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ATtiny13

13.2 Register Description

13.2.1

ADCSRB – ADC Control and Status Register

Bit

7

–

6

ACME

R/W

0

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

ADCSRB

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 78.

13.2.2

ACSR– Analog Comparator Control and Status Register

Bit

7

6

5

4

3

ACIE

R/W

0

2

–

1

ACIS1

R/W

0

ACIS0

R/W

0

ACD

ACBG

ACO

ACI

R/W

0

ACSR

Read/Write

Initial Value

R/W

0

R/W

0

R

0

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. When the bandgap reference is used as input to the Analog Comparator, it will take certain

time for the voltage to stabilize. If not stabilized, the first value may give a wrong value.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny13 and will always read as zero.

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• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 13-2 on page 80.

Table 13-2. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

13.2.3

DIDR0 – Digital Input Disable Register 0

Bit

7

6

5

ADC0D

R/W

0

4

ADC2D

R/W

0

3

ADC3D

R/W

0

2

ADC1D

R/W

0

1

AIN1D

R/W

0

AIN0D

R/W

0

–

R

0

–

R

0

DIDR0

Read/Write

Initial Value

• Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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14. Analog to Digital Converter

14.1 Features

• 10-bit Resolution

• 0.5 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 13 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• Four Multiplexed Single Ended Input Channels

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 1.1V ADC Reference Voltage

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Canceler

14.2 Overview

The ATtiny13 features a 10-bit successive approximation ADC. A block diagram of the ADC is

shown in Figure 14-1.

Figure 14-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

INTERRUPT

FLAGS

ADTS[2:0]

8-BIT DATA BUS

15

0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

REGISTER (ADCSRA)

ADC DATA REGISTER

(ADCH/ADCL)

TRIGGER

SELECT

MUX DECODER

PRESCALER

START

CONVERSION LOGIC

V

CC

INTERNAL 1.1V

REFERENCE

SAMPLE & HOLD

COMPARATOR

10-BIT DAC

-

+

ADC3

ADC2

ADC1

ADC0

INPUT

MUX

ADC MULTIPLEXER

OUTPUT

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The ADC is connected to a 4-channel Analog Multiplexer which allows four single-ended voltage

inputs constructed from the pins of Port B. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. Internal reference voltages of nominally 1.1V or V_CC

are provided On-chip.

14.3 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

V

_CCor an internal 1.1V reference voltage.

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input

pins, can be selected as single ended inputs to the ADC.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

14.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to

trigger a new conversion at the next interrupt event.

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Figure 14-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADIF

ADATE

SOURCE 1

.

CONVERSION

LOGIC

.

EDGE

DETECTOR

SOURCE n

ADSC

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

14.5 Prescaling and Conversion Timing

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

Figure 14-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

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The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,

as shown in Figure 14-4 below.

Figure 14-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

LSB of Result

ADCH

ADCL

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

Sample & Hold

When the bandgap reference voltage is used as input to the ADC, it will take a certain time for

the voltage to stabilize. If not stabilized, the first value read after the first conversion may be

wrong.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

Figure 14-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

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When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in

Figure 14-6 below. This assures a fixed delay from the trigger event to the start of conversion. In

this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the

trigger source signal. Three additional CPU clock cycles are used for synchronization logic.

Figure 14-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high.

Figure 14-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

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For a summary of conversion times, see Table 14-1.

Table 14-1. ADC Conversion Time

Sample & Hold (Cycles

Condition

from Start of Conversion)

Conversion Time (Cycles)

First conversion

13.5

1.5

2

25

13

Normal conversions

Auto Triggered conversions

13.5

14.6 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and reference

selection only takes place at a safe point during the conversion. The channel and reference

selection is continuously updated until a conversion is started. Once the conversion starts, the

channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or reference selection values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

• When ADATE or ADEN is cleared.

• During conversion, minimum one ADC clock cycle after the trigger event.

• After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

14.6.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

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14.6.2

ADC Voltage Reference

The reference voltage for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either V_CC, or internal 1.1V reference. The first ADC conversion result after switching reference

voltage source may be inaccurate, and the user is advised to discard this result.

14.7 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must

be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the

CPU has been halted.

• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will

wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another

interrupt wakes up the CPU before the ADC conversion is complete, the interrupt will be

executed, and an ADC Conversion Complete interrupt request will be generated when the

ADC conversion completes. The CPU will remain in active mode until a new sleep command

is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

14.8 Analog Input Circuitry

The analog input circuitry for single ended channels is shown in Figure 14-8 An analog source

applied to ADCn is subjected to pin capacitance and input leakage of that pin, regardless if the

channel is chosen as input for the ADC, or not. When the channel is selected, the source drives

the S/H capacitor through the series resistance (combined resistance in input path).

Figure 14-8. Analog Input Circuitry

I_IH

n

1..100 kohm

C_S/H= 14 pF

I_IL

Note:

The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and

any stray or parasitic capacitance inside the device. The value given is worst case.

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The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present to avoid

distortion from unpredictable signal convolution. The user is advised to remove high frequency

components with a low-pass filter before applying the signals as inputs to the ADC.

14.9 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. When conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run over the analog ground plane.

• Keep analog tracks well away from high-speed switching digital tracks.

• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.

• Place bypass capacitors as close to V_CCand GND pins as possible.

Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as

described in Section 14.7 on page 87. This is especially the case when system clock frequency

is above 1 MHz. A good system design with properly placed, external bypass capacitors does

reduce the need for using ADC Noise Reduction Mode

14.10 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior:

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• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB.

Figure 14-9. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 14-10. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

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• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

Figure 14-11. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 14-12. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

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• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.

14.11 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 14-2 on page 91 and Table 14-3 on page 92). 0x000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

14.12 Register Description

14.12.1 ADMUX – ADC Multiplexer Selection Register

Bit

7

–

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

–

3

–

2

–

1

MUX1

R/W

0

MUX0

R/W

0

ADMUX

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved bit in the ATtiny13 and will always read as zero.

• Bit 6 – REFS0: Reference Selection Bit

This bit selects the voltage reference for the ADC, as shown in Table 14-2. If this bit is changed

during a conversion, the change will not go in effect until this conversion is complete (ADIF in

ADCSRA is set).

Table 14-2. Voltage Reference Selections for ADC

REFS0

Voltage Reference Selection

_CCused as analog reference.

Internal Voltage Reference.

0

1

V

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on

page 93.

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• Bits 4:2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 1:0 – MUX1:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC.

See Table 14-3 on page 92 for details. If these bits are changed during a conversion, the change

will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

Table 14-3. Input Channel Selections

MUX1..0

Single Ended Input

00

01

10

11

ADC0 (PB5)

ADC1 (PB2)

ADC2 (PB4)

ADC3 (PB3)

14.12.2 ADCSRA – ADC Control and Status Register A

Bit

7

ADEN

R/W

0

6

ADSC

R/W

0

5

ADATE

R/W

0

4

ADIF

R/W

0

3

ADIE

R/W

0

2

ADPS2

R/W

0

1

ADPS1

R/W

0

ADPS0

R/W

0

ADCSRA

Read/Write

Initial Value

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the data registers are updated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

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• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

Table 14-4. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

14.12.3 ADCL and ADCH – The ADC Data Register

14.12.3.1 ADLAR = 0

Bit

15

14

13

12

–

11

10

9

8

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

14.12.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

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The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 91.

14.12.4 ADCSRB – ADC Control and Status Register B

Bit

7

6

5

–

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

–

ACME

ADCSRB

Read/Write

Initial Value

R

0

R/W

0

R

0

R

0

R

0

• Bits 7, 5:3 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 14-5. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter Compare Match A

Timer/Counter Overflow

Timer/Counter Compare Match B

Pin Change Interrupt Request

14.12.5 DIDR0 – Digital Input Disable Register 0

Bit

7

–

6

–

5

ADC0D

R/W

0

4

3

ADC3D

R/W

0

2

ADC1D

R/W

0

1

AIN1D

R/W

0

AIN0D

R/W

0

ADC2D

DIDR0

Read/Write

Initial Value

R

0

R

0

R/W

0

• Bits 5:2 – ADC3D:ADC0D: ADC3:0 Digital Input Disable

When a bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled.

The corresponding PIN register bit will always read as zero when this bit is set. When an analog

signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit

should be written logic one to reduce power consumption in the digital input buffer.

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15. debugWIRE On-chip Debug System

15.1 Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

15.2 Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

15.3 Physical Interface

When the debugWIRE Enable (DWEN) fuse is programmed and lock bits are unprogrammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 15-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL fuses.

Figure 15-1. The debugWIRE Setup

1.8 - 5.5V

VCC

dW

dW(RESET)

GND

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When designing a system where debugWIRE will be used, the following must be observed:

• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the

pull-up resistor is optional.

• Connecting the RESET pin directly to V_CCwill not work.

• Capacitors inserted on the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

15.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio^®will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to

end customers.

15.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,

when the program in the CPU is running. When the CPU is stopped, care must be taken while

accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE docu-

mentation for detailed description of the limitations.

The debugWIRE interface is asynchronous, which means that the debugger needs to synchro-

nize to the system clock. If the system clock is changed by software (e.g. by writing CLKPS bits)

communication via debugWIRE may fail. Also, clock frequencies below 100 kHz may cause

communication problems.

A programmed DWEN fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN fuse should

be disabled when debugWire is not used.

15.6 Register Description

The following section describes the registers used with the debugWire.

15.6.1

DWDR –debugWire Data Register

Bit

7

6

5

4

3

2

1

0

DWDR[7:0]

DWDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The DWDR Register provides a communication channel from the running program in the MCU

to the debugger. This register is only accessible by the debugWIRE and can therefore not be

used as a general purpose register in the normal operations.

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16. Self-Programming the Flash

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory. The SPM

instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse

(to “0”).

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page buf-

fer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the

same page.

16.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

Note:

The CPU is halted during the Page Erase operation.

16.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

16.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

Note:

The CPU is halted during the Page Write operation.

16.4 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

Z9

Z1

1

8

Z8

Z0

0

ZH (R31)

ZL (R30)

Since the Flash is organized in pages (see Table 17-5 on page 104), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 16-1. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the software addresses the

same page in both the Page Erase and Page Write operation.

Figure 16-1. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The variables used in Figure 16-1 are listed in Table 17-5 on page 104.

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The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

16.5 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

fuses and lock bits from software will also be prevented during the EEPROM write operation. It is

recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that

the bit is cleared before writing to the SPMCSR Register.

16.6 Reading Fuse and Lock Bits from Firmware

It is possible to read fuse and lock bits from software.

16.6.1

Reading Lock Bits from Firmware

Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have

been set in SPMCSR will return lock bit values in the destination register. The RFLB and SELF-

PRGEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction

is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.

When RFLB and SELFPRGEN are cleared, LPM functions normally.

To read the lock bits, follow the below procedure.

1. Load the Z-pointer with 0x0001.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issuing an LPM instruction within three clock cycles will return lock bits in the destina-

tion register.

If successful, the contents of the destination register are as follows.

Bit

Rd

7

–

6

–

5

–

4

–

3

–

2

–

1

0

LB2

LB1

See section “Program And Data Memory Lock Bits” on page 102 for more information on lock

bits.

16.6.2

Reading Fuse Bits from Firmware

The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,

only the addresses are different.

To read the Fuse Low Byte (FLB), follow the below procedure:

1. Load the Z-pointer with 0x0000.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issuing an LPM instruction within three clock cycles will FLB in the destination register.

If successful, the contents of the destination register are as follows.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and

repeat the procedure above.

If successful, the contents of the destination register are as follows.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

See sections “Program And Data Memory Lock Bits” on page 102 and “Fuse Bytes” on page 103

for more information on fuse and lock bits.

16.7 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V_CCreset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

16.8 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 16-1 on page 100 shows the

typical programming time for Flash accesses from the CPU.

Table 16-1. SPM Programming Time⁽¹⁾

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write lock bits by SPM)

3.7 ms

4.5 ms

Note:

1. The min and max programming times is per individual operation.

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16.9 Register Description

16.9.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

Bit

7

–

6

–

5

–

4

CTPB

R/W

0

3

RFLB

R/W

0

2

PGWRT

R/W

0

1

PGERS

R/W

0

SELFPRGEN

SPMCSR

Read/Write

Initial Value

R

0

R

0

R

0

R/W

0

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and always read as zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR

Register, will read either the lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the

destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 99 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write operation.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special

meaning, see description above. If only SELFPRGEN is written, the following SPM instruction

will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB

of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM

instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and

Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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17. Memory Programming

This section describes how ATtiny13 memories can be programmed.

17.1 Program And Data Memory Lock Bits

ATtiny13 provides two lock bits which can be left unprogrammed (“1”) or can be programmed

(“0”) to obtain the additional security listed in Table 17-2 on page 102. The lock bits can be

erased to “1” with the Chip Erase command, only.

Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro-

grammed, even if the lock bits are set. Thus, when lock bit security is required, debugWIRE

should always be disabled by clearing the DWEN fuse.

Table 17-1. Lock Bit Byte

Lock Bit Byte

Bit No

Description

Default Value ⁽¹⁾

1 (unprogrammed)

7

6

5

4

3

2

1

0

–

LB2

LB1

Lock bit

Note:

1. “1” means unprogrammed, “0” means programmed

Table 17-2. Lock Bit Protection Modes

Memory Lock Bits ^{(1) (2)}

LB Mode

LB2

LB1

Protection Type

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

High-voltage and Serial Programming mode. Fuse bits are

locked in both Serial and High-voltage Programming mode.

debugWire is disabled.

2

3

1

0

Further programming and verification of the Flash and

EEPROM is disabled in High-voltage and Serial Programming

mode. Fuse bits are locked in both Serial and High-voltage

Programming mode. debugWire is disabled.

Notes: 1. Program fuse bits before lock bits. See section “Fuse Bytes” on page 103.

2. “1” means unprogrammed, “0” means programmed

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17.2 Fuse Bytes

The ATtiny13 has two fuse bytes. Table 17-3 on page 103 and Table 17-4 on page 103 describe

briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that

the fuses are read as logical zero, “0”, if they are programmed.

Table 17-3. Fuse High Byte

Fuse Bit

Bit No

Description

Default Value

–

7

6

5

4

3

2

1

0

–

1 (unprogrammed)

–

SELFPRGEN⁽¹⁾

DWEN⁽²⁾

Self Programming Enable

debugWire Enable

Brown-out Detector trigger level

External Reset disable

BODLEVEL1⁽³⁾

BODLEVEL0⁽³⁾

RSTDISBL⁽⁴⁾

Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 97.

2. DWEN must be unprogrammed when lock Bit security is required. See “Program And Data

Memory Lock Bits” on page 102.

3. See Table 18-5 on page 119 for BODLEVEL fuse decoding.

4. See “Alternate Functions of Port B” on page 54 for description of RSTDISBL and DWEN fuses.

When programming the RSTDISBL fuse, High-voltage Serial programming has to be used to

change fuses to perform further programming.

Table 17-4. Fuse Low Byte

Fuse Bit

Bit No

Description

Default Value

Enable Serial Programming and Data

Downloading

0 (programmed)

(SPI prog. enabled)

SPIEN⁽¹⁾

7

Preserve EEPROM memory through

Chip Erase

1 (unprogrammed)

(memory not preserved)

EESAVE

6

WDTON⁽²⁾

CKDIV8⁽³⁾

SUT1⁽⁴⁾

5

4

3

2

1

0

Watchdog Timer always on

Divide clock by 8

1 (unprogrammed)

0 (programmed)

1 (unprogrammed)

0 (programmed)

1 (unprogrammed)

0 (programmed)

Select start-up time

Select Clock source

SUT0⁽⁴⁾

CKSEL1⁽⁵⁾

CKSEL0⁽⁵⁾

Notes: 1. The SPIEN fuse is not accessible in SPI Programming mode.

2. Programming this fues will disable the Watchdog Timer Interrupt. See “Watchdog Timer” on

page 37 for details.

3. See “System Clock Prescaler” on page 26 for details.

4. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 18-3 on page 118 for details.

5. The default setting of CKSEL1..0 results in internal RC Oscillator @ 9.6 MHz. See Table 18-3

on page 118 for details.

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Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Program the fuse bits before

programming the lock bits. The status of the fuse bits is not affected by Chip Erase.

Fuse bits can also be read by the device firmware. See section “Reading Fuse and Lock Bits

from Firmware” on page 99.

17.2.1

Latching of Fuses

The fuse values are latched when the device enters programming mode and changes of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

17.3 Calibration Bytes

The signature area of the ATtiny13 contains two bytes of calibration data for the internal oscilla-

tor. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 9.6

MHz operation. During reset, this byte is automatically written into the OSCCAL register to

ensure correct frequency of the oscillator.

There is a separate calibration byte for the internal oscillator in 4.8 MHz mode of operation but

this data is not loaded automatically. The hardware always loads the 9.6 MHz calibraiton data

during reset. To use separate calibration data for the oscillator in 4.8 MHz mode the OSCCAL

register must be updated by firmware. The calibration data for 4.8 MHz operation is located in

the high byte at address 0x01 of the signature area.

17.4 Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and high-voltage programming mode, even when the device is

locked. The three bytes reside in a separate address space.

For the ATtiny13 the signature bytes are:

• 0x000: 0x1E (indicates manufactured by Atmel).

• 0x001: 0x90 (indicates 1 KB Flash memory).

• 0x002: 0x07 (indicates ATtiny13 device when 0x001 is 0x90).

17.5 Page Size

Table 17-5. No. of Words in a Page and No. of Pages in the Flash

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

512 words (1K byte)

16 words

PC[3:0]

32

PC[8:4]

8

Table 17-6. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM Size

Page Size

PCWORD

No. of Pages

PCPAGE

EEAMSB

64 bytes

4 bytes

EEA[1:0]

16

EEA[5:2]

5

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17.6 Serial Programming

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). See Figure 17-1.

Figure 17-1. Serial Programming and Verify

+1.8 - 5.5V

PB5

VCC

PB2

RESET

SCK

PB1

PB0

MISO

MOSI

GND

Note:

If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.

After RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase operations can be executed.

Table 17-7. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB0

PB1

PB2

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

Note:

In Table 17-7 above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins

dedicated for the internal SPI interface.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

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17.6.1

Serial Programming Algorithm

When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK.

When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See Figure

18-5 on page 121 and Figure 18-4 on page 121 for timing details.

To program and verify the ATtiny13 in the Serial Programming mode, the following sequence is

recommended (see four byte instruction formats in Table 17-9 on page 107):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse after SCK has been set to “0”. The pulse

duration must be at least t_RST(miniumum pulse widht of RESET pin, see Table 18-4 on

page 119) plus two CPU clock cycles.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 4 LSB of the address and data together with the Load Program

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 5 MSB

of the address. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH}

before issuing the next page. (See Table 17-8 on page 107.) Accessing the serial pro-

gramming interface before the Flash write operation completes can result in incorrect

programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling (RDY/BSY) is not used,

the user must wait at least t_{WD_EEPROM}before issuing the next byte. (See Table 17-8 on

page 107.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-

grammed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the

Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by

loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address.

When using EEPROM page access only byte locations loaded with the Load EEPROM

Memory Page instruction is altered. The remaining locations remain unchanged. If poll-

ing (RDY/BSY) is not used, the used must wait at least t_{WD_EEPROM}before issuing the

next page (See Table 17-6 on page 104). In a chip erased device, no 0xFF in the data

file(s) need to be programmed.

6. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

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.

Table 17-8. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

t_{WD_FUSE}

4.0 ms

9.0 ms

4.5 ms

17.6.2

Serial Programming Instruction set

The instruction set is described in Table 17-9.

Table 17-9. Serial Programming Instruction Set

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

xxxx xxxx

bbbb bbbb

Byte4

Operation

Enable Serial Programming after

RESET goes low.

Programming Enable

Chip Erase

1010 1100

0010 H000

0101 0011

100x xxxx

0000 000a

xxxx xxxx

Chip Erase EEPROM and Flash.

Read H (high or low) data o from

Program memory at word address a:b.

Read Program Memory

oooo oooo

Write H (high or low) data i to Program

memory page at word address b. Data

low byte must be loaded before Data

high byte is applied within the same

address.

0100 H000

000x xxxx

xxxx bbbb

iiii iiii

Load Program Memory Page

Write Program memory Page at

address a:b.

0100 1100

1010 0000

1100 0000

0000 000a

000x xxxx

bbbb xxxx

xxbb bbbb

xxxx xxxx

oooo oooo

iiii iiii

Write Program Memory Page

Read EEPROM Memory

Write EEPROM Memory

Read data o from EEPROM memory at

address b.

Write data i to EEPROM memory at

address b.

Load data i to EEPROM memory page

buffer. After data is loaded, program

EEPROM page.

Load EEPROM Memory

Page (page access)

1100 0001

1100 0010

0101 1000

0000 0000

00xx xxxx

0000 0000

0000 00bb

xxbbbb00

xxxx xxxx

iiii iiii

Write EEPROM Memory

Page (page access)

xxxx xxxx

xxoo oooo

Write EEPROM page at address b.

Read lock bits. “0” = programmed, “1”

= unprogrammed. See Table 17-1 on

page 102 for details.

Read Lock Bits

Write Lock Bits

Write lock bits. Set bits = “0” to

program lock bits. See Table 17-1 on

page 102 for details.

1010 1100

111x xxxx

xxxx xxxx

11ii iiii

107

2535J–AVR–08/10

Table 17-9. Serial Programming Instruction Set (Continued)

Instruction Format

Instruction

Byte 1

Byte 2

Byte 3

Byte4

Operation

Read fuse low/high byte. Bit “0” =

programmed, “1” = unprogrammed.

See “Fuse Bytes” on page 103 for

details.

Read Fuse Byte

0101 H000

0000 H000

xxxx xxxx

oooo oooo

Set fuse low/high byte. Set bit to “0” to

program, “1” to unprogram. See “Fuse

Bytes” on page 103 for details.

1010 1100

1010 H000

xxxx xxxx

iiii iiii

Write Fuse Byte

0011 0000

0011 1000

000x xxxx

xxxx xxbb

oooo oooo

Read Signature Byte

Read Calibration Byte

Read Signature Byte o at address b.

Read Calibration Byte. See

“Calibration Bytes” on page 104

0000 000b

If o = “1”, a programming operation is

still busy. Wait until this bit returns to

“0” before applying another command.

1111 0000

0000 0000

xxxx xxxx

xxxx xxxo

Poll RDY/BSY

Note:

a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care

17.7 High-Voltage Serial Programming

This section describes how to program and verify Flash Program memory, EEPROM Data mem-

ory, lock bits and fuse bits in the ATtiny13.

Figure 17-2. High-voltage Serial Programming

+11.5 - 12.5V

+1.8 - 5.5V

PB5

PB3

VCC

PB2

(RESET)

SCI

SDO

SII

PB1

PB0

GND

SDI

108

ATtiny13

2535J–AVR–08/10

ATtiny13

Table 17-10. Pin Name Mapping

Signal Name in High-voltage

Serial Programming Mode

Pin Name

PB0

I/O

Function

SDI

SII

I

Serial Data Input

Serial Instruction Input

Serial Data Output

PB1

I

SDO

SCI

PB2

O

I

PB3

Serial Clock Input (min. 220ns period)

The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is

220 ns.

Table 17-11. Pin Values Used to Enter Programming Mode

SDI

SII

Symbol

Value

Prog_enable[0]

Prog_enable[1]

Prog_enable[2]

0

SDO

17.7.1

High-Voltage Serial Programming Algorithm

To program and verify the ATtiny13 in the High-voltage Serial Programming mode, the following

sequence is recommended (See instruction formats in Table 17-13 on page 110):

The following algorithm puts the device in High-voltage Serial Programming mode:

1. Set Prog_enable pins listed in Table 17-11 to “000”, RESET pin to “0” and Vcc to 0V.

2. Apply 4.5 - 5.5V between VCC and GND. Ensure that Vcc reaches at least 1.8V within

the next 20µs.

3. Wait 20 - 60µs, and apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has

been applied to ensure the Prog_enable Signature has been latched.

5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO

pin.

6. Wait at least 300µs before giving any serial instructions on SDI/SII.

7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of the Vcc is unable to fulfill the requirements listed above, the following alterna-

tive algorithm can be used.

1. Set Prog_enable pins listed in Table 17-11 to “000”, RESET pin to “0” and Vcc to 0V.

2. Apply 4.5 - 5.5V between VCC and GND.

3. Monitor Vcc, and as soon as Vcc reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10µs after theHigh-voltage has been

applied to ensure the Prog_enable Signature has been latched.

5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO

pin.

109

2535J–AVR–08/10

6. Wait until Vcc actually reaches 4.5 - 5.5V before giving any serialinstructions on

SDI/SII.

7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

Table 17-12. High-voltage Reset Characteristics

Minimum High-voltage Period for

Supply Voltage

RESET Pin High-voltage Threshold

Latching Prog_enable

V_CC

V_HVRST

12V

t_HVRST

100 ns

4.5V

5.5V

12

17.7.2

High-Voltage Serial Programming Instruction set

The instruction set is described in Table 17-13.

Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

SDI

SII

0_1000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr.3 until SDO goes

high for the Chip Erase cycle to

finish.

Chip Erase

SDO

SDI

SII

0_0001_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Write

Flash”

Command

Enter Flash Programming code.

SDO

Repeat after Instr. 1 - 5 until the

entire page buffer is filled or until all

data within the page is filled. See

Note 1.

SDI 0_ bbbb_bbbb _00

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_dddd_dddd_00

0_0011_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1101_00

x_xxxx_xxxx_xx

SII

0_0000_1100_00

x_xxxx_xxxx_xx

SDO

Load Flash

Page Buffer

SDI

SII

0_0000_0000_00

0_0111_1100_00

x_xxxx_xxxx_xx

Instr 5.

SDO

Wait after Instr 3 until SDO goes

high. Repeat Instr. 2 - 3 for each

loaded Flash Page until the entire

Flash or all data is programmed.

Repeat Instr. 1 for a new 256 byte

page. See Note 1.

SDI

SII

0_0000_000a_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Load Flash High

Address and

Program Page

SDO

SDI

SII

0_0000_0010_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Read

Flash”

Command

Enter Flash Read mode.

SDO

SDI

SII

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_000a_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqqx_xx

Repeat Instr. 1, 3 - 6 for each new

address. Repeat Instr. 2 for a new

256 byte page.

SDO

Read Flash Low

and High Bytes

SDI

SII

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

p_pppp_pppx_xx

Instr 5 - 6.

SDO

SDI

SII

0_0001_0001_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Write

EEPROM”

Command

Enter EEPROM Programming

mode.

SDO

110

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2535J–AVR–08/10

ATtiny13

Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued)

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

Repeat Instr. 1 - 4 until the entire

page buffer is filled or until all data

within the page is filled. See Note

2.

SDI

SII

0_00bb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1101_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Load EEPROM

Page Buffer

SDO

Wait after Instr. 2 until SDO goes

high. Repeat Instr. 1 - 2 for each

loaded EEPROM page until the

entire EEPROM or all data is

programmed.

SDI

SII

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Program

EEPROM Page

SDO

SDI

SII

0_00bb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1101_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

Repeat Instr. 1 - 5 for each new

address. Wait after Instr. 5 until

SDO goes high. See Note 3.

SDO

Write EEPROM

Byte

SDI

SII

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Instr. 5

SDO

SDI

SII

0_0000_0011_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Read

EEPROM”

Command

Enter EEPROM Read mode.

SDO

SDI

SII

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_aaaa_aaaa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqq0_00

Repeat Instr. 1, 3 - 4 for each new

address. Repeat Instr. 2 for a new

256 byte page.

Read EEPROM

Byte

SDO

SDI

SII

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_A987_6543_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO goes

high. Write A - 3 = “0” to program

the Fuse bit.

Write Fuse Low

Bits

SDO

SDI

SII

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_000F_EDCB_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO goes

high. Write F - B = “0” to program

the Fuse bit.

Write Fuse High

Bits

SDO

SDI

0_0010_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0021_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO goes

high. Write 2 - 1 = “0” to program

the Lock Bit.

Write Lock Bits SII

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

A_9876_543x_xx

Read Fuse Low

Bits

Reading A - 3 = “0” means the

Fuse bit is programmed.

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1010_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1110_00

x_xxFE_DCBx_xx

Read Fuse High

Bits

Reading F - B = “0” means the fuse

bit is programmed.

SDO

SDI

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

x_xxxx_x21x_xx

Reading 2, 1 = “0” means the lock

bit is programmed.

Read Lock Bits SII

SDO

111

2535J–AVR–08/10

Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued)

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

SDI

SII

0_0000_1000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_00bb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqqx_xx

Read Signature

Bytes

Repeats Instr 2 4 for each

signature byte address.

SDO

SDI

SII

0_0000_1000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_000b_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

p_pppp_pppx_xx

Read

Calibration Byte

SDO

SDI

SII

0_0000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “No

Operation”

Command

SDO

Note:

a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits,

x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 fuse, 4 = CKSEL1 fuse, 5 = SUT0 fuse, 6 = SUT1 fuse, 7 = CKDIV8,

fuse, 8 = WDTON fuse, 9 = EESAVE fuse, A = SPIEN fuse, B = RSTDISBL fuse, C = BODLEVEL0 fuse, D= BODLEVEL1 fuse,

E = MONEN fuse, F = SELFPRGEN fuse

The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-

wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of

EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.

17.8 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the

EESAVE fuse is programmed) and Flash after a Chip Erase.

• Address High byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

17.8.1

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus lock bits. The lock bits are

not reset until the Program memory has been completely erased. The fuse bits are not changed.

A Chip Erase must be performed before the Flash and/or EEPROM are re-programmed.

1. Load command “Chip Erase” (see Table 17-13 on page 110).

2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.

3. Load Command “No Operation”.

Note:

1. The EEPROM memory is preserved during Chip Erase if the EESAVE fuse is programmed.

112

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ATtiny13

17.8.2

Programming the Flash

The Flash is organized in pages, see Table 17-9 on page 107. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

1. Load Command “Write Flash” (see Table 17-13 on page 110).

2. Load Flash Page Buffer.

3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for

the “Page Programming” cycle to finish.

4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been

programmed.

5. End Page Programming by Loading Command “No Operation”.

When writing or reading serial data to the ATtiny13, data is clocked on the rising edge of the

serial clock, see Figure 17-4 on page 114, Figure 18-6 on page 122 and Table 18-9 on page 122

for details.

Figure 17-3. Addressing the Flash which is Organized in Pages

PCMSB

PAGEMSB

PCWORD

PROGRAM

COUNTER

PCPAGE

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

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2535J–AVR–08/10

Figure 17-4. High-voltage Serial Programming Waveforms

SDI

PB0

MSB

LSB

SII

PB1

MSB

SDO

PB2

MSB

LSB

SCI

0

1

2

3

4

5

6

7

8

9

10

PB3

17.8.3

Programming the EEPROM

The EEPROM is organized in pages, see Table 18-8 on page 121. When programming the

EEPROM, the data is latched into a page buffer. This allows one page of data to be pro-

grammed simultaneously. The programming algorithm for the EEPROM Data memory is as

follows (refer to Table 17-13 on page 110):

1. Load Command “Write EEPROM”.

2. Load EEPROM Page Buffer.

3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Pro-

gramming” cycle to finish.

4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been

programmed.

5. End Page Programming by Loading Command “No Operation”.

17.8.4

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to Table 17-13 on page 110):

1. Load Command "Read Flash".

2. Read Flash Low and High Bytes. The contents at the selected address are available at

serial output SDO.

17.8.5

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to Table 17-13 on page

110):

1. Load Command “Read EEPROM”.

2. Read EEPROM Byte. The contents at the selected address are available at serial out-

put SDO.

17.8.6

Programming and Reading the Fuse and Lock Bits

The algorithms for programming and reading the fuse low/high bits and lock bits are shown in

Table 17-13 on page 110.

114

ATtiny13

2535J–AVR–08/10

ATtiny13

17.8.7

17.8.8

Reading the Signature Bytes and Calibration Byte

The algorithms for reading the Signature bytes and Calibration byte are shown in Table 17-13 on

page 110.

Power-off sequence

Set SCI to “0”. Set RESET to “1”. Turn V_CCpower off.

18. Electrical Characteristics

18.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

18.2 DC Characteristics

Table 18-1.

DC Characteristics, T_A= -40°C to +85°C

Symbol

Parameter

Condition

Min.

-0.5

Typ.⁽¹⁾

Max.

0.2V_CC

0.3V_CC

Units

(2)

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

V

Input Low Voltage,

Any Pin as I/O

V_IL

Input Low Voltage,

(2)

V_CC= 1.8V - 5.5

V_CC= 1.8V - 2.4V

-0.5

0.2V_CC

V

RESET Pin as Reset ⁽³⁾

(4)

0.7V_CC

0.6V_CC

V_CC+ 0.5

V

Input High Voltage,

Any Pin as I/O

V_CC= 2.4V - 5.5V

V_IH

Input High Voltage,

(4)

V_CC= 1.8V - 5.5V

0.9V_CC

V_CC+ 0.5

V

RESET Pin as Reset ⁽³⁾

I_OL= 20 mA, V_CC= 5V

I_OL= 10 mA, V_CC= 3V

I_OL= 10 mA, V_CC= 5V

0.7

0.5

0.7

0.5

V

Output Low Voltage,

Pins PB0 and PB1 ⁽⁵⁾

V_OL

Output Low Voltage,

Pins PB2, PB3 and PB4 ⁽⁵⁾

I

_OL= 5 mA, V_CC= 3V

I_OH= -20 mA, V_CC= 5V

_OH= -10 mA, V_CC= 3V

4.2

2.5

4.2

2.5

Output High Voltage,

Pins PB0 and PB1 ⁽⁶⁾

I

V_OH

I_OH= -10 mA, V_CC= 5V

I_OH= -5 mA, V_CC= 3V

Output High Voltage,

Pins PB2, PB3 and PB4 ⁽⁶⁾

Input Leakage

Current I/O Pin

I_LIL

V_CC= 5.5V, pin low

-1

1

µA

115

2535J–AVR–08/10

Table 18-1.

Symbol

DC Characteristics, T_A= -40°C to +85°C (Continued)

Parameter Condition

Min.

Typ.⁽¹⁾

Max.

Units

Input Leakage

Current I/O Pin

I_LIH

V_CC= 5.5V, pin high

-1

1

µA

Pull-Up Resistor, I/O Pin

V_CC= 5.5V, input low

20

30

50

80

0.35

1.8

6

kΩ

R_PU

Pull-Up Resistor, Reset Pin V_CC= 5.5V, input low

f = 1MHz, V_CC= 2V

0.3

1.6

5

mA

µA

Supply Current,

f = 4MHz, V_CC= 3V

Active Mode

f = 8MHz, V_CC= 5V

f = 1MHz, V_CC= 2V

0.08

0.41

1.6

5

0.2

1

I_CC

Supply Current,

f = 4MHz, V_CC= 3V

Idle Mode

f = 8MHz, V_CC= 5V

3

WDT enabled, V_CC= 3V

Supply Current,

Power-Down Mode

10

2

WDT disabled, V_CC= 3V

0.5

µA

Notes: 1. Typical values at +25°C.

2. “Max” means the highest value where the pin is guaranteed to be read as low.

3. Not tested in production.

4. “Min” means the lowest value where the pin is guaranteed to be read as high.

5. Although each I/O port can under non-transient, steady state conditions sink more than the test conditions, the sum of all I_OL

(for all ports) should not exceed 60 mA. If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are

not guaranteed to sink current greater than the listed test condition.

6. Although each I/O port can under non-transient, steady state conditions source more than the test conditions, the sum of all

I_OH(for all ports) should not exceed 60 mA. If I_OHexceeds the test condition, V_OHmay exceed the related specification. Pins

are not guaranteed to source current greater than the listed test condition.

116

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ATtiny13

18.3 Speed Grades

The maximum operating frequency of the device depends on V_CC.As shown in Figure 18-1 and

Figure 18-2, the maximum frequency vs. V_CCrelationship is linear between 1.8V < V_CC< 2.7V

and between 2.7V < V_CC< 4.5V.

Figure 18-1. Maximum Frequency vs. V_CCfor ATtiny13V

10 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 18-2. Maximum Frequency vs. V_CCfor ATtiny13

20 MHz

10 MHz

Safe Operating Area

2.7V

4.5V

5.5V

117

2535J–AVR–08/10

18.4 Clock Characteristics

18.4.1

Calibrated Internal RC Oscillator Accuracy

It is possible to manually calibrate the internal oscillator to be more accurate than default factory

calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and

temperature characteristics can be found in Figure 19-50 on page 148, Figure 19-51 on page

148, Figure 19-52 on page 149, Figure 19-53 on page 149, Figure 19-54 on page 150, and Fig-

ure 19-55 on page 150.

Table 18-2. Calibration Accuracy of Internal RC Oscillator

Calibration

Method

Accuracy at given Voltage

& Temperature⁽¹⁾

Target Frequency

V_CC

Temperature

Factory

Calibration

4.8 / 9.6 MHz

3V

25°C

±10%

±2%

Fixed voltage within:

1.8V – 5.5V⁽²⁾

Fixed temperature

within:

-40°C to +85°C

Fixed frequency within:

4 – 5 MHz / 8 – 10 MHz

User

Calibration

2.7V – 5.5V⁽³⁾

Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).

2. Voltage range for ATtiny13V.

3. Voltage range for ATtiny13.

18.4.2

External Clock Drive

Figure 18-3. External Clock Drive Waveform

V_IH1

V_IL1

Table 18-3. External Clock Drive

V_CC= 1.8 - 5.5V

V_CC= 2.7 - 5.5V

V_CC= 4.5 - 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Min.

Max.

Min.

0

Max.

Min.

0

Max.

Units

MHz

ns

Clock Frequency

0

4

10

20

Clock Period

250

100

40

50

20

t_CHCX

t_CLCX

High Time

ns

Low Time

40

ns

t_CLCH

Rise Time

2.0

2

1.6

2

0.5

2

µs

t_CHCL

Fall Time

µs

Δt_CLCL

Change in period from one clock cycle to the next

%

118

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ATtiny13

18.5 System and Reset Characteristics

Table 18-4. Reset, Brown-out and Internal Voltage Reference Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

Power-on Reset Threshold Voltage (rising) T_A= -40 to +85°C

1.2

V

V_POT

Power-on Reset Threshold Voltage

T_A= -40 to +85°C

1.1

V

(falling)⁽¹⁾

V_RST

t_RST

V_HYST

t_BOD

V_BG

t_BG

RESET Pin Threshold Voltage

V_CC= 1.8V - 5.5V

0.2 V_CC

0.9 V_CC

2.5

V

µs

mV

µs

V

Minimum pulse width on RESET Pin

Brown-out Detector Hysteresis

Min Pulse Width on Brown-out Reset

Bandgap reference voltage

50

2

1.0

1.1

40

15

1.2

70

Bandgap reference start-up time

Bandgap reference current consumption

µs

I_BG

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

18.5.1

Brown-Out Detection

Table 18-5. V_BOTvs. BODLEVEL Fuse Coding

BODLEVEL [1:0] Fuses

Min⁽¹⁾

Typ⁽¹⁾

BOD Disabled

Max⁽¹⁾

Units

11

10

01

00

1.8

2.7

4.3

V

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed.

18.6 Analog Comparator Characteristics

Table 18-6. Analog Comparator Characteristics, T_A= -40°C to +85°C

Symbol

V_AIO

Parameter

Condition

Min

Typ

Max

40

Units

mV

Input Offset Voltage

Input Leakage Current

V_CC= 5V, V_IN= V_CC/ 2

V_CC= 2.7V

< 10

I_LAC

-50

50

nA

750

500

100

75

Analog Propagation Delay

(from saturation to slight overdrive)

V

_CC= 4.0V

V_CC= 2.7V

_CC= 4.0V

V_CC= 1.8V - 5.5

t_APD

ns

Analog Propagation Delay

(large step change)

V

t_DPD

Note:

Digital Propagation Delay

1

2

CLK

All parameters are based on simulation results and they are not tested in production

119

2535J–AVR–08/10

18.7 ADC Characteristics

Table 18-7. ADC Characteristics, Single Ended Channels. T_A= -40°C to +85°C

Symbol

Parameter

Condition

Min

Typ

Max

Units

Resolution

10

Bits

V

_REF= 4V, V_CC= 4V,

2

3

LSB

ADC clock = 200 kHz

V_REF= 4V, V_CC= 4V

ADC clock = 1 MHz

Absolute accuracy

(Including INL, DNL, and

Quantization, Gain and Offset

Errors)

V

_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

1.5

2.5

LSB

Noise Reduction Mode

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Noise Reduction Mode

Integral Non-Linearity (INL)

(Accuracy after Offset and

Gain Calibration)

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

1

LSB

Differential Non-linearity

(DNL)

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

0.5

2.5

1.5

LSB

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

Gain Error

V_REF= 4V, V_CC= 4V

ADC clock = 200 kHz

Offset Error

Conversion Time

Free Running Conversion

13

50

260

1000

V_REF

µs

kHz

V

Clock Frequency

V_IN

Input Voltage

GND

Input Bandwidth

38.5

1.1

kHz

V

V_INT

R_AIN

Internal Voltage Reference

Analog Input Resistance

1.0

1.2

100

MΩ

120

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ATtiny13

18.8 Serial Programming Characteristics

Figure 18-4. Serial Programming Timing

MOSI

t_SLSH

t_OVSH

t_SHOX

SCK

t_SHSL

MISO

Figure 18-5. Serial Programming Waveform

SERIAL DATA INPUT

MSB

LSB

(MOSI)

SERIAL DATA OUTPUT

MSB

(MISO)

SERIAL CLOCK INPUT

(SCK)

SAMPLE

Table 18-8. Serial Programming Characteristics, T_A= -40°C to +85°C, V_CC= 1.8 - 5.5V

(Unless Otherwise Noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (ATtiny13V, V_CC= 1.8 - 5.5V)

Oscillator Period (ATtiny13V, V_CC= 1.8 - 5.5V)

Oscillator Frequency (ATtiny13, V_CC= 2.7 - 5.5V)

Oscillator Period (ATtiny13, V_CC= 2.7 - 5.5V)

Oscillator Frequency (ATtiny13, V_CC= 4.5V - 5.5V)

Oscillator Period (ATtiny13, V_CC= 4.5V - 5.5V)

SCK Pulse Width High

1

1000

0

1/t_CLCL

t_CLCL

1/t_CLCL

t_CLCL

9.6

20

MHz

ns

104

0

MHz

ns

50

(1)

t_SHSL

2 t_CLCL

ns

(1)

t_SLSH

SCK Pulse Width Low

2 t_CLCL

ns

t_OVSH

t_SHOX

Note:

MOSI Setup to SCK High

t_CLCL

ns

MOSI Hold after SCK High

2 t_CLCL

ns

1. 2 t_CLCLfor f_ck< 12 MHz, 3 t_CLCLfor f_ck>= 12 MHz

121

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18.9 High-voltage Serial Programming Characteristics

Figure 18-6. High-voltage Serial Programming Timing

SDI (PB0), SII (PB1)

t_IVSH

t_SLSH

t_SHIX

SCI (PB3)

t_SHSL

SDO (PB2)

t_SHOV

Table 18-9. High-voltage Serial Programming Characteristics

T_A= 25°C, V_CC= 5.0V ± 10% (Unless otherwise noted)

Symbol

t_SHSL

Parameter

Min

110

50

Typ

Max

Units

ns

SCI (PB3) Pulse Width High

t_SLSH

SCI (PB3) Pulse Width Low

ns

t_IVSH

SDI (PB0), SII (PB1) Valid to SCI (PB3) High

SDI (PB0), SII (PB1) Hold after SCI (PB3) High

SCI (PB3) High to SDO (PB2) Valid

Wait after Instr. 3 for Write Fuse Bits

ns

t_SHIX

50

ns

t_SHOV

16

ns

t_{WLWH_PFB}

2.5

ms

122

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ATtiny13

19. Typical Characteristics

The data contained in this section is largely based on simulations and characterization of similar

devices in the same process and design methods. Thus, the data should be treated as indica-

tions of how the part will behave.

The following charts show typical behavior. These figures are not tested during manufacturing.

During characterisation devices are operated at frequencies higher than test limits but they are

not guaranteed to function properly at frequencies higher than the ordering code indicates.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. Current consumption is a function of several factors such as oper-

ating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed

and ambient temperature. The dominating factors are operating voltage and frequency.

A sine wave generator with rail-to-rail output is used as clock source but current consumption in

Power-Down mode is independent of clock selection. The difference between current consump-

tion in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Watchdog

Timer disabled represents the differential current drawn by the Watchdog Timer.

The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:

I_CP≈ V_CC× C_L× f_SW

where V_CC= operating voltage, C_L= load capacitance and f_SW= average switching frequency of

I/O pin.

19.1 Active Supply Current

Figure 19-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MH

z

1.2

1

5.5 V

5.0 V

0.8

0.6

0.4

0.2

0

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

123

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Figure 19-2. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20MH

z

14

12

10

8

5.5 V

5.0 V

4.5 V

6

4.0 V

3.3 V

2.7 V

4

2

1.8 V

0

2

4

6

8

10

Frequency (MHz)

12

14

16

18

20

Figure 19-3. Active Supply Current vs. V_CC(Internal RC Oscillator, 9.6 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 9.6 MH

z

8

7

6

5

4

3

2

1

0

85 °C

-40 °C

25 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

124

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ATtiny13

Figure 19-4. Active Supply Current vs. V_CC(Internal RC Oscillator, 4.8 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 4.8 MH

z

4.5

4

25 °C

-40 °C

85 °C

3.5

3

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-5. Active Supply Current vs. V_CC(Internal WDT Oscillator, 128 kHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL WD OSCILLATOR, 128 KHz

0.14

-40 °C

25 °C

85 °C

0.12

0.1

0.08

0.06

0.04

0.02

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

125

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Figure 19-6. Active Supply Current vs. V_CC(32 kHz External Clock)

ACTIVE SUPPLY CURRENT vs. V_CC

32 kHz EXTERNAL CLOCK

0.04

25 °C

85 °C

0.035

0.03

0.025

0.02

0.015

0.01

0.005

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

19.2 Idle Supply Current

Figure 19-7. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

(0.1 - 1.0 MHz)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

126

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ATtiny13

Figure 19-8. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20MHz

5

4.5

4

5.5 V

3.5

3

5.0 V

4.5 V

2.5

2

1.5

4.0 V

1

3.3 V

2.7 V

0.5

0

1.8 V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 19-9. Idle Supply Current vs. V_CC(Internal RC Oscillator, 9.6 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 9.6 MH

z

2.5

2

85 °C

25 °C

-40 °C

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

127

2535J–AVR–08/10

Figure 19-10. Idle Supply Current vs. V_CC(Internal RC Oscillator, 4.8 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 4.8 MH

z

1.2

1

85 °C

25 °C

-40 °C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-11. Idle Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL WD OSCILLATOR, 128 KH

z

0.035

0.03

0.025

0.02

0.015

0.01

0.005

0

-40 °C

25 °C

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

128

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ATtiny13

Figure 19-12. Idle Supply Current vs. V_CC(32 kHz External Clock)

IDLE SUPPLY CURRENT vs. V_CC

32kHz EXTERNAL CLOCK

10

9

8

7

6

5

4

3

2

1

0

85 °C

25 °C

-40 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

19.3 Power-Down Supply Current

Figure 19-13. Power-Down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

1.8

1.6

1.4

1.2

1

85 ˚C

0.8

0.6

0.4

0.2

0

-40 ˚C

25 ˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

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Figure 19-14. Power-Down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

10

-40 ˚C

85 ˚C

25 ˚C

9

8

7

6

5

4

3

2

1

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

19.4 Pin Pull-up

Figure 19-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 5V

160

140

25 ˚C

85 ˚C

120

-40 ˚C

100

80

60

40

20

0

1

2

3

4

5

6

V_OP(V)

130

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ATtiny13

Figure 19-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V

CC = 2.7

80

25 ˚C

85 ºC

70

60

50

40

30

20

10

0

-40 ˚C

0

0.5

1

1.5

V_OP(V)

2

2.5

3

Figure 19-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 5V

120

25 ˚C

-40 ˚C

100

85 ˚C

80

60

40

20

0

1

2

3

4

5

V_RESET(V)

131

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Figure 19-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 2.7V

60

25 ˚C

-40 ˚C

50

85 ˚C

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_RESET(V)

19.5 Pin Driver Strength

Figure 19-19. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

LOW POWER PORTS, V_CC= 5V

70

-40 ˚C

60

25 ˚C

50

85 ˚C

40

30

20

10

0

1

2

3

4

5

6

V_OH(V)

132

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ATtiny13

Figure 19-20. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

LOW POWER PORTS, V_CC= 2.7V

25

20

15

10

5

-40 °C

25 °C

85 °C

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 19-21. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

LOW POWER PORTS, V_CC= 1.8V

7

-40 ˚C

25 ˚C

6

85 ˚C

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

133

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Figure 19-22. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

LOW POWER PORTS, V_CC= 5V

50

45

-40 ˚C

40

25 ˚C

35

85 ˚C

30

25

20

15

10

5

0

0.5

1

1.5

2

2.5

V_OL(V)

Figure 19-23. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Low Power Ports, V_CC= 2.7V

20

18

-40 ˚C

16

25 ˚C

14

85 ˚C

12

10

8

6

4

2

0

0.5

1

1.5

2

2.5

V_OL(V)

134

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ATtiny13

Figure 19-24. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

LOW POWER PORTS, 1.8V

7

6

5

4

3

2

1

0

-40 ˚C

25 ˚C

85 ˚C

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

Figure 19-25. I/O Pin Source Current vs. Output Voltage (V_CC= 5V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

90

80

70

60

50

40

30

20

10

0

-40 ˚C

25 ˚C

85 ˚C

2

3

4

5

6

V_OH(V)

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Figure 19-26. I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

35

30

-40 ˚C

25 ˚C

25

85 ˚C

20

15

10

5

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 19-27. I/O Pin Source Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

10

-40 ˚C

9

25 ˚C

8

85 ˚C

7

6

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

136

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ATtiny13

Figure 19-28. I/O Pin Sink Current vs. Output Voltage (V_CC= 5V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

100

90

-40 ˚C

80

70

60

50

40

30

20

10

0

25 ˚C

85 ˚C

0

0.5

1

1.5

2

2.5

V_OL(V)

Figure 19-29. I/O Pin Sink Current vs. Output Voltage (V_CC= 2.7V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

40

35

30

25

20

15

10

5

-40 ˚C

25 ˚C

85 ˚C

0

0.5

1

1.5

2

2.5

V_OL(V)

137

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Figure 19-30. I/O Pin Sink Current vs. Output Voltage (V_CC= 1.8V)

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

14

12

10

8

-40 ˚C

25 ˚C

85 ˚C

6

4

2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V

_OL(V)

Figure 19-31. Reset Pin as I/O - Source Current vs. Output Voltage (V_CC= 5V)

RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

1.6

1.4

-40 ˚C

1.2

25 ˚C

1

85 ˚C

0.8

0.6

0.4

0.2

0

2

3

4

5

V_OH(V)

138

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ATtiny13

Figure 19-32. Reset Pin as I/O - Source Current vs. Output Voltage (V_CC= 2.7V)

RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

2.5

2

-40 ˚C

25 ˚C

85 ˚C

1.5

1

0.5

0

0.5

1

1.5

2

2.5

3

V_OH(V)

Figure 19-33. Reset Pin as I/O - Source Current vs. Output Voltage (V_CC= 1.8V)

RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

2.5

-40 °C

2

25 °C

1.5

85 °C

1

0.5

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OH(V)

139

2535J–AVR–08/10

Figure 19-34. Reset Pin as I/O - Sink Current vs. Output Voltage (V_CC= 5V)

RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 5V

14

-40 ˚C

12

25 ˚C

10

85 ˚C

8

6

4

2

0

0.5

1

1.5

2

2.5

V_OL(V)

Figure 19-35. Reset Pin as I/O - Sink Current vs. Output Voltage (V_CC= 2.7V)

RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 2.7V

4.5

-40 ˚C

4

3.5

25 ˚C

3

85 ˚C

2.5

2

1.5

1

0.5

0

0.5

1

1.5

2

2.5

V_OL(V)

140

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-36. Reset Pin as I/O - Sink Current vs. Output Voltage (V_CC= 1.8V)

RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE

V_CC= 1.8V

1.6

1.4

-40 ˚C

25 ˚C

85 ˚C

1.2

1

0.8

0.6

0.4

0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

V_OL(V)

19.6 Pin Thresholds and Hysteresis

Figure 19-37. I/O Pin Input Threshold Voltage vs. V_CC(VIH, I/O Pin Read as '1')

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3

85 ˚C

25 ˚C

-40 ˚C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

141

2535J–AVR–08/10

Figure 19-38. I/O Pin Input Threshold Voltage vs. V_CC(VIL, I/O Pin Read as '0')

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

3

85 ˚C

25 ˚C

-40 ˚C

2.5

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-39. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V_CC

0.45

0.4

-40 ºC

25 ºC

0.35

0.3

0.25

0.2

85 ºC

0.15

0.1

0.05

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

142

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-40. Reset Pin as I/O - Input Threshold Voltage vs. V_CC(VIH, Reset Pin Read as '1')

RESET PIN AS I/O - THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3

2.5

2

-40 ˚C

1.5

25 ˚C

1

85 ˚C

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-41. Reset Pin as I/O - Input Threshold Voltage vs. V_CC(VIL, Reset Pin Read as '0')

RESET PIN AS I/O - THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

2.5

2

1.5

85 ˚C

1

25 ˚C

0.5

-40 ˚C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

143

2535J–AVR–08/10

Figure 19-42. Reset Pin as I/O - Pin Hysteresis vs. V_CC

RESET PIN AS IO - PIN HYSTERESIS vs. V_CC

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

-40 ºC

25 ºC

85 ºC

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-43. Reset Input Threshold Voltage vs. V_CC(VIH, Reset Pin Read as '1')

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

2.5

2

1.5

-40 ˚C

1

85 ˚C

25 ˚C

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

144

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-44. Reset Input Threshold Voltage vs. V_CC(VIL, Reset Pin Read as '0')

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

2.5

2

1.5

1

85 ˚C

25 ˚C

-40 ˚C

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-45. Reset Input Pin Hysteresis vs. V_CC

RESET INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

0.5

0.4

0.3

0.2

0.1

0

-40 ºC

85 ºC

25 ºC

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

145

2535J–AVR–08/10

19.7 BOD Thresholds and Analog Comparator Offset

Figure 19-46. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3

V

4.5

4.4

4.3

4.2

Rising V_CC

Falling V_CC

-60

-40

-20

0

20

Temperature (C)

40

60

80

100

Figure 19-47. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7

V

2.9

2.8

2.7

2.6

Rising V_CC

Falling V_CC

-60

-40

-20

0

20

Temperature (C)

40

60

80

100

146

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-48. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8

V

1.9

1.85

1.8

Rising V_CC

Falling V_CC

1.75

-60

-40

-20

0

20

Temperature (C)

40

60

80

100

Figure 19-49. Bandgap Voltage vs. V_CC

BANDGAP VOLTAGE vs. V_CC

1.06

1.04

1.02

1

85ºC

25ºC

0.98

0.96

0.94

0.92

-40ºC

1.5

2.5

3.5

4.5

5.5

V_CC(V)

147

2535J–AVR–08/10

19.8 Internal Oscillator Speed

Figure 19-50. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

10.3

10.1

9.9

9.7

9.5

9.3

9.1

8.9

8.7

8.5

5.5 V

4.5 V

2.7 V

1.8 V

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

Figure 19-51. Calibrated 9.6 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. V_CC

11

10.5

10

85 ˚C

25 ˚C

9.5

9

-40 ˚C

8.5

8

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

148

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-52. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

18

16

14

12

10

8

25 ˚C

6

4

2

0

8

16

24

32

40

48

56

64

72

80

88

96

104 112 120

OSCCAL VALUE

Figure 19-53. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

5.1

5

4.9

4.8

4.7

4.6

4.5

1.8 V

5.5 V

4.0 V

2.7 V

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

149

2535J–AVR–08/10

Figure 19-54. Calibrated 4.8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. V_CC

5.2

85 ˚C

5

4.8

4.6

4.4

25 ˚C

-40 ˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-55. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

10

9

8

7

6

5

4

3

2

1

25 ˚C

0

8

16

24

32

40

48

56

64

72

80

88

96

104 112 120 127

OSCCAL VALUE

150

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-56. 128 kHz Watchdog Oscillator Frequency vs. V_CC

128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

120

-40 ˚C

25 ˚C

115

110

105

100

85 ˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-57. 128 kHz Watchdog Oscillator Frequency vs. Temperature

128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

118

116

114

112

110

108

106

104

102

100

1.8 V

2.7 V

4.0 V

5.5 V

-60

-40

-20

0

20

40

60

80

100

Temperature (C)

151

2535J–AVR–08/10

19.9 Current Consumption of Peripheral Units

Figure 19-58. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. V_CC

35

30

25

20

15

10

5

-40 ˚C

25 ˚C

85 ˚C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-59. ADC Current vs. V_CC

ADC CURRENT vs. V_CC

350

300

250

200

150

100

50

-40 ˚C

25 ˚C

85 ˚C

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

152

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-60. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. V_CC

140

120

100

80

-40 ˚C

25 ˚C

85 ˚C

60

40

20

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

Figure 19-61. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. Vcc

4

3.5

3

2.5

2

1.5

1

-40 °C

25 °C

0.5

0

85 °C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

153

2535J–AVR–08/10

19.10 Current Consumption in Reset and Reset Pulse width

Figure 19-62. Reset Supply Current vs. V_CC(0.1 - 1.0 MHz, Excluding Current through the

Reset Pull-up)

RESET SUPPLY CURRENT vs. V_CC

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

0.14

0.12

0.1

5.5 V

5.0 V

4.5 V

4.0 V

0.08

0.06

0.04

0.02

0

3.3 V

2.7 V

1.8 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (MHz)

Figure 19-63. Reset Supply Current vs. V_CC(1 - 24 MHz, Excluding Current through the Reset

Pull-up)

RESET SUPPLY CURRENT vs. V_CC

1 - 24 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

3.5

5.5V

5.0V

4.5V

3

2.5

2

1.5

1

4.0V

3.3V

0.5

0

2.7V

1.8V

0

2

4

6

8

10

12

14

16

18

20

22

24

Frequency (MHz)

154

ATtiny13

2535J–AVR–08/10

ATtiny13

Figure 19-64. Reset Pulse Width vs. V_CC

RESET PULSE WIDTH vs. V

CC

2500

2000

1500

1000

500

85 ºC

25 ºC

-40 ºC

0

1.8

2.1

2.5

2.7

3

3.3

3.5

4

4.5

5

5.5

6

V_CC(V)

155

2535J–AVR–08/10

20. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F

0x3E

0x3D

0x3C

0x3B

0x3A

0x39

0x38

0x37

0x36

0x35

0x34

0x33

0x32

0x31

0x30

0x2F

0x2E

0x2D

0x2C

0x2B

0x2A

0x29

0x28

0x27

0x26

0x25

0x24

0x23

0x22

0x21

0x20

0x1F

0x1E

0x1D

0x1C

0x1B

0x1A

0x19

0x18

0x17

0x16

0x15

0x14

0x13

0x12

0x11

0x10

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

SREG

Reserved

SPL

I

T

–

H

–

S

–

V

–

N

–

Z

–

C

–

page 9

–

SP[7:0]

–

page 11

Reserved

GIMSK

–

INT0

PCIE

–

page 46

page 47

page 74

page 75

page 97

page 74

page 32

page 41

page 72

page 73

page 27

GIFR

INTF0

PCIF

–

TIMSK0

TIFR0

–

OCIE0B

OCF0B

RFLB

OCIE0A

OCF0A

PGWRT

TOIE0

TOV0

PGERS

–

SELFPR-

SPMCSR

OCR0A

MCUCR

MCUSR

TCCR0B

TCNT0

CTPB

Timer/Counter – Output Compare Register A

–

PUD

–

SE

–

SM1

SM0

–

ISC01

EXTRF

CS01

ISC00

PORF

CS00

–

WDRF

WGM02

BORF

CS02

FOC0A

FOC0B

–

Timer/Counter (8-bit)

OSCCAL

Reserved

TCCR0A

DWDR

Oscillator Calibration Register

–

COM0A1

COM0A0

COM0B1

COM0B0

DWDR[7:0]

–

WGM01

WGM00

page 69

page 96

Reserved

OCR0B

GTCCR

Reserved

CLKPR

–

Timer/Counter – Output Compare Register B

page 74

page 77

TSM

–

PSR10

–

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

page 28

Reserved

WDTCR

Reserved

EEARL

–

WDTIF

WDTIE

WDP3

WDCE

WDE

WDP2

WDP1

EEPE

WDP0

EERE

page 41

–

EEPROM Address Register

EEPROM Data Register

page 20

page 21

EEDR

EECR

EEPM1

EEPM0

EERIE

EEMPE

Reserved

PORTB

DDRB

–

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 56

PINB

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 57

PCMSK

DIDR0

PCINT5

ADC0D

PCINT4

ADC2D

PCINT3

ADC3D

PCINT2

ADC1D

PCINT1

AIN1D

PCINT0

AIN0D

page 47

page 80, page 94

Reserved

ACSR

–

ACD

–

ACBG

REFS0

ADSC

ACO

ACI

–

ACIE

–

ACIS1

MUX1

ADPS1

ACIS0

MUX0

ADPS0

page 79

page 91

page 92

page 93

page 94

ADMUX

ADCSRA

ADCH

ADLAR

ADATE

ADEN

ADIF

ADIE

ADPS2

ADC Data Register High Byte

ADC Data Register Low Byte

ADCL

ADCSRB

Reserved

–

ACME

–

ADTS2

ADTS1

ADTS0

–

156

ATtiny13

2535J–AVR–08/10

ATtiny13

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are

cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation

the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work

with registers 0x00 to 0x1F only.

157

2535J–AVR–08/10

21. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

Indirect Jump to (Z)

PC ← PC + k + 1

PC ← Z

None

I

2

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BRID

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

CBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

I/O(P,b) ← 0

None

2

1

LSL

LSR

ROL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

158

ATtiny13

2535J–AVR–08/10

ATtiny13

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

s

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd ← (X)

Rd, X

Load Indirect

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

SLEEP

WDR

No Operation

Sleep

None

1

(see specific descr. for Sleep function)

(see specific descr. for WDR/Timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

159

2535J–AVR–08/10

22. Ordering Information

Speed (MHz) ⁽³⁾

Power Supply (V)

Ordering Code ⁽⁴⁾

Package ⁽²⁾

Operation Range

ATtiny13V-10PU

ATtiny13V-10SU

ATtiny13V-10SUR

ATtiny13V-10SSU

ATtiny13V-10SSUR

ATtiny13V-10MU

ATtiny13V-10MUR

ATtiny13V-10MMU

ATtiny13V-10MMUR

8P3

8S2

S8S1

20M1

10M1

Industrial

10

1.8 - 5.5

(-40°C to +85°C)⁽¹⁾

ATtiny13-20PU

ATtiny13-20SU

8P3

8S2

ATtiny13-20SUR

ATtiny13-20SSU

ATtiny13-20SSUR

ATtiny13-20MU

ATtiny13-20MUR

ATtiny13-20MMU

ATtiny13-20MMUR

8S2

S8S1

20M1

10M1

Industrial

20

2.7 - 5.5

(-40°C to +85°C)⁽¹⁾

Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. For Speed vs. V_CC, see “Speed Grades” on page 117.

4. Code indicators:

– U: matte tin

– R: tape & reel

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2

8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC)

S8S1

20M1

10M1

8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

160

ATtiny13

2535J–AVR–08/10

ATtiny13

23. Packaging Information

23.1 8P3

E

1

E1

N

Top View

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

D

e

MIN

MAX

NOM

NOTE

SYMBOL

D1

A2 A

A

0.210

0.195

0.022

0.070

0.045

0.014

0.400

2

A2

b

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

0.130

0.018

0.060

0.039

0.010

0.365

5

6

b2

b3

c

D

3

4

3

b2

L

D1

E

b3

4 PLCS

0.310

0.250

0.325

0.280

b

E1

e

0.100 BSC

0.300 BSC

0.130

Side View

eA

L

4

2

0.115

0.150

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

8P3

B

R

161

2535J–AVR–08/10

23.2 8S2

C

1

E

E1

L

N

θ

TOP VVIIEEWW

ENDD VVIIEEWW

e

b

COMMON DIMENSIONS

(Unit of Measure = mm)

A

MIN

1.70

0.05

0.35

0.15

5.13

5.18

7.70

0.51

0°

MAX

2.16

0.25

0.48

0.35

5.35

5.40

8.26

0.85

8°

NOM

NOTE

SYMBOL

A1

A

A1

b

4

C

D

E1

E

D

2

L

SIDDE VIEW

θ

e

1.27 BSC

3

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. Determines the true geometric position.

4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/15/08

GPC

DRAWING NO.

TITLE

REV.

8S2, 8-lead, 0.208” Body, Plastic Small

Outline Package (EIAJ)

Package Drawing Contact:

packagedrawings@atmel.com

STN

8S2

F

162

ATtiny13

2535J–AVR–08/10

ATtiny13

23.3 S8S1

1

3

2

H

N

Top View

e

B

A

D

COMMON DIMENSIONS

(Unit of Measure = mm)

Side View

MIN

–

MAX

1.75

0.51

0.25

5.00

4.00

NOM

NOTE

SYMBOL

A

B

C

D

E

e

–

A2

L

–

C

–

1.27 BSC

E

H

L

–

6.20

1.27

End View

Note:

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

10/10/01

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

8S1

A

R

Small Outline (JEDEC SOIC)

163

2535J–AVR–08/10

23.4 20M1

D

1

2

Pin 1 ID

SIDE VIEW

E

3

TOP VIEW

A2

A1

D2

A

0.08

C

1

2

3

Pin #1

Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

E2

MIN

0.70

–

MAX

0.80

0.05

b

NOM

0.75

NOTE

SYMBOL

A

A1

A2

b

0.01

L

0.20 REF

0.23

0.18

2.45

0.35

0.30

2.75

0.55

e

D

4.00 BSC

2.60

D2

E

BOTTOM VIEW

4.00 BSC

2.60

E2

e

0.50 BSC

0.40

Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

Note:

L

10/27/04

DRAWING NO. REV.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,

20M1

A

R

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

164

ATtiny13

2535J–AVR–08/10

ATtiny13

23.5 10M1

D

y

Pin 1 ID

E

SIDE VIEW

TOP VIEW

A1

A

D1

K

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

MIN

MAX

NOM

NOTE

SYMBOL

A

0.80

0.90

1.00

A1

b

0.00

0.18

2.90

1.40

2.90

2.20

0.02

0.25

3.00

–

0.05

0.30

3.10

1.75

3.10

2.70

b

E1

D

D1

E

e

3.00

–

E1

e

0.50

–

L

0.30

–

0.50

0.08

–

L

BOTTOM VIEW

y

–

K

0.20

–

Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5.

2. The terminal #1 ID is a Lasser-marked Feature.

7/7/06

TITLE

DRAWING NO. REV.

10M1

2325 Orchard Parkway

San Jose, CA 95131

10M1, 10-pad, 3 x 3 x 1.0 mm Body, Lead Pitch 0.50 mm,

A

R

1.64 x 2.60 mm Exposed Pad, Micro Lead Frame Package

165

2535J–AVR–08/10

24. Errata

The revision letter in this section refers to the revision of the ATtiny13 device.

24.1 ATtiny13 Rev. D

• EEPROM can not be written below 1.9 Volt

1. EEPROM can not be written below 1.9 Volt

Writing the EEPROM at V_CCbelow 1.9 volts might fail.

Problem Fix/Workaround

Do not write the EEPROM when V_CCis below 1.9 volts.

24.2 ATtiny13 Rev. C

Revision C has not been sampled.

24.3 ATtiny13 Rev. B

• Wrong values read after Erase Only operation

• High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail

• Device may lock for further programming

• debugWIRE communication not blocked by lock-bits

• Watchdog Timer Interrupt disabled

• EEPROM can not be written below 1.9 Volt

24.3.1

Wrong values read after Erase Only operation

At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only oper-

ation may read as programmed (0x00).

Problem Fix/Workaround

If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write opera-

tion with 0xFF as data in order to erase a location. In any case, the Write Only operation can

be used as intended. Thus no special considerations are needed as long as the erased loca-

tion is not read before it is programmed.

24.3.2

24.3.3

High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail

Writing to any of these locations and bits may in some occasions fail.

Problem Fix/Workaround

After a writing has been initiated, always observe the RDY/BSY signal. If the writing should

fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision D.

Device may lock for further programming

Special combinations of fuse bits will lock the device for further programming effectively

turning it into an OTP device. The following combinations of settings/fuse bits will cause this

effect:

– 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.

– 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.

166

ATtiny13

2535J–AVR–08/10

ATtiny13

– 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time

(SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0.

Problem fix/ Workaround

Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem.

24.3.4

24.3.5

debugWIRE communication not blocked by lock-bits

When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory

and EEPROM data memory can be read even if the lock-bits are set to block further reading

of the device.

Problem fix/ Workaround

Do not ship products with on-chip debug of the tiny13 enabled.

Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog

will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in

interrupt only mode. If the Watchdog is configured to reset the device in the watchdog time-

out following an interrupt, the device works correctly.

Problem fix / Workaround

Make sure there is enough time to always service the first timeout event before a new

watchdog timeout occurs. This is done by selecting a long enough time-out period.

24.3.6

EEPROM can not be written below 1.9 Volt

Writing the EEPROM at V_CCbelow 1.9 volts might fail.

Problem Fix/Workaround

Do not write the EEPROM when V_CCis below 1.9 volts.

24.4 ATtiny13 Rev. A

Revision A has not been sampled.

167

2535J–AVR–08/10

25. Datasheet Revision History

Please note that the referring page numbers in this section refer to the complete document.

25.1 Rev. 2535J-08/10

Added tape and reel part numbers in “Ordering Information” on page 160. Removed text “Not

recommended for new design” from cover page. Updated last page.

25.2 Rev. 2535I-05/08

1. Updated document template, layout and paragraph formats.

2. Updated “Features” on page 1.

3. Created Sections:

– “Calibrated Internal RC Oscillator Accuracy” on page 118

– “Analog Comparator Characteristics” on page 119

4. Updated Sections:

– “System Clock and Clock Options” on page 23

– “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25

– “External Interrupts” on page 45

– “Analog Noise Canceling Techniques” on page 88

– “Limitations of debugWIRE” on page 96

– “Reading Fuse and Lock Bits from Firmware” on page 99

– “Fuse Bytes” on page 103

– “Calibration Bytes” on page 104

– “High-Voltage Serial Programming” on page 108

– “Ordering Information” on page 160

5. Updated Figure:

– “Analog Input Circuitry” on page 87

– “High-voltage Serial Programming Timing” on page 122

6. Moved Figures:

– “Serial Programming Timing” on page 121

– “Serial Programming Waveform” on page 121

– “High-voltage Serial Programming Timing” on page 122

7. Updated Tables:

– “DC Characteristics, TA = -40°C to +85°C” on page 115

– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V

(Unless Otherwise Noted)” on page 121

8. Moved Tables:

– “Serial Programming Instruction Set” on page 107

– “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V

(Unless Otherwise Noted)” on page 121

– “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5.0V ± 10%

(Unless otherwise noted)” on page 122

9. Updated Register Description for Sections:

168

ATtiny13

2535J–AVR–08/10

ATtiny13

– “TCCR0A – Timer/Counter Control Register A” on page 69

– “DIDR0 – Digital Input Disable Register 0” on page 94

10. Updated description in Step 1. on page 106.

11. Changed device status to “Not Recommended for New Designs”.

25.3 Rev. 2535H-10/07

1.

Updated “Features” on page 1.

2.

3.

4.

5.

6.

7.

8.

9.

Updated “Pin Configurations” on page 2.

Added “Data Retention” on page 6.

Updated “Assembly Code Example(1)” on page 39.

Updated Table 21 in “Alternate Functions of Port B” on page 54.

Updated Bit 5 description in “GIMSK – General Interrupt Mask Register” on page 46.

Updated “ADC Voltage Reference” on page 87.

Updated “Calibration Bytes” on page 104.

Updated “Read Calibration Byte” on page 108.

10. Updated Table 51 in “Serial Programming Characteristics” on page 121.

11. Updated Algorithm in “High-Voltage Serial Programming Algorithm” on page 109.

12. Updated “Read Calibration Byte” on page 112.

13. Updated values in “External Clock Drive” on page 118.

14. Updated “Ordering Information” on page 160.

15. Updated “Packaging Information” on page 161.

25.4 Rev. 2535G-01/07

1.

Removed Preliminary.

2.

3.

4.

5.

6.

7.

8.

9.

Updated Table 7-1 on page 30, Table 8-1 on page 42,Table 18-8 on page 121.

Removed Note from Table 7-1 on page 30.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 79.

Updated “Prescaling and Conversion Timing” on page 83.

Updated Figure 18-4 on page 121.

Updated “DC Characteristics” on page 115.

Updated “Ordering Information” on page 160.

Updated “Packaging Information” on page 161.

25.5 Rev. 2535F-04/06

1.

Revision not published.

25.6 Rev. 2535E-10/04

1.

2.

3.

2.

4.

5.

6.

7.

Bits EEMWE/EEWE changed to EEMPE/EEPE in document.

Updated “Pinout ATtiny13/ATtiny13V” on page 2.

Updated “Write Fuse Low Bits” in Table 17-13 on page 110, Table 18-3 on page 118.

Added “Pin Change Interrupt Timing” on page 45.

Updated “GIMSK – General Interrupt Mask Register” on page 46.

Updated “PCMSK – Pin Change Mask Register” on page 47.

Updated item 4 in “Serial Programming Algorithm” on page 106.

Updated “High-Voltage Serial Programming Algorithm” on page 109.

169

2535J–AVR–08/10

8.

9.

Updated “DC Characteristics” on page 115.

Updated “Typical Characteristics” on page 122.

10. Updated “Ordering Information” on page 160.

11. Updated “Packaging Information” on page 161.

12. Updated “Errata” on page 166.

25.7 Rev. 2535D-04/04

1.

Maximum Speed Grades changed: 12MHz to 10MHz, 24MHz to 20MHz

Updated “Serial Programming Instruction Set” on page 107.

Updated “Speed Grades” on page 117

2.

3.

4.

Updated “Ordering Information” on page 160

25.8 Rev. 2535C-02/04

1.

2.

3.

4.

5.

6.

7.

8.

9.

C-code examples updated to use legal IAR syntax.

Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE.

Updated “Stack Pointer” on page 11.

Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.

Updated “OSCCAL – Oscillator Calibration Register” on page 27.

Updated typo in introduction on “Watchdog Timer” on page 37.

Updated “ADC Conversion Time” on page 86.

Updated “Serial Programming” on page 105.

Updated “Electrical Characteristics” on page 115.

10. Updated “Ordering Information” on page 160.

11. Removed rev. C from “Errata” on page 166.

25.9 Rev. 2535B-01/04

1.

Updated Figure 2-1 on page 4.

2.

3.

4.

5.

6.

Updated Table 7-1, Table 8-1, Table 14-2 and Table 18-3.

Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25.

Updated the whole “Watchdog Timer” on page 37.

Updated Figure 17-1 on page 105 and Figure 17-2 on page 108.

Updated registers “MCUCR – MCU Control Register”, “TCCR0B – Timer/Counter Con-

trol Register B” and “DIDR0 – Digital Input Disable Register 0”.

Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteris-

tics” on page 115.

7.

8.

9.

Added “Speed Grades” on page 117

Updated “” on page 120.

10. Updated “Typical Characteristics” on page 123.

11. Updated “Ordering Information” on page 160.

12. Updated “Packaging Information” on page 161.

13. Updated “Errata” on page 166.

14. Changed instances of EEAR to EEARL.

25.10 Rev. 2535A-06/03

1.

Initial Revision.

170

ATtiny13

2535J–AVR–08/10

ATtiny13

Table of Contents

Features..................................................................................................... 1

Pin Configurations ................................................................................... 2

1

2

3

1.1

Pin Descriptions .................................................................................................3

Overview ................................................................................................... 4

2.1

Block Diagram ...................................................................................................4

General Information ................................................................................. 6

3.1

3.2

3.3

3.4

Resources .........................................................................................................6

Code Examples .................................................................................................6

Data Retention ...................................................................................................6

Disclaimer ..........................................................................................................6

4

CPU Core .................................................................................................. 7

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Architectural Overview .......................................................................................7

ALU – Arithmetic Logic Unit ...............................................................................8

Status Register ..................................................................................................8

General Purpose Register File ........................................................................10

Stack Pointer ...................................................................................................11

Instruction Execution Timing ...........................................................................12

Reset and Interrupt Handling ...........................................................................12

5

Memories ................................................................................................ 15

5.1

5.2

5.3

5.4

5.5

In-System Reprogrammable Flash Program Memory .....................................15

SRAM Data Memory ........................................................................................15

EEPROM Data Memory ..................................................................................16

I/O Memory ......................................................................................................20

Register Description ........................................................................................20

6

7

System Clock and Clock Options ......................................................... 23

6.1

6.2

6.3

6.4

Clock Systems and their Distribution ...............................................................23

Clock Sources .................................................................................................24

System Clock Prescaler ..................................................................................26

Register Description ........................................................................................27

Power Management and Sleep Modes ................................................. 30

7.1

7.2

Sleep Modes ....................................................................................................30

Minimizing Power Consumption ......................................................................31

i

2535J–AVR–08/10

7.3

Register Description ........................................................................................32

8

9

System Control and Reset .................................................................... 34

8.1

8.2

8.3

8.4

Reset Sources .................................................................................................35

Internal Voltage Reference ..............................................................................37

Watchdog Timer ..............................................................................................37

Register Description ........................................................................................41

Interrupts ................................................................................................ 44

9.1

9.2

9.3

Interrupt Vectors ..............................................................................................44

External Interrupts ...........................................................................................45

Register Description ........................................................................................46

10 I/O Ports .................................................................................................. 48

10.1

10.2

10.3

10.4

Overview ..........................................................................................................48

Ports as General Digital I/O .............................................................................49

Alternate Port Functions ..................................................................................53

Register Description ........................................................................................56

11 8-bit Timer/Counter0 with PWM ............................................................ 58

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

Features ..........................................................................................................58

Overview ..........................................................................................................58

Timer/Counter Clock Sources .........................................................................59

Counter Unit ....................................................................................................59

Output Compare Unit .......................................................................................60

Compare Match Output Unit ............................................................................62

Modes of Operation .........................................................................................63

Timer/Counter Timing Diagrams .....................................................................67

Register Description ........................................................................................69

12 Timer/Counter Prescaler ....................................................................... 76

12.1

12.2

12.3

12.4

Overview ..........................................................................................................76

Prescaler Reset ...............................................................................................76

External Clock Source .....................................................................................76

Register Description. .......................................................................................77

13 Analog Comparator ............................................................................... 78

13.1

13.2

Analog Comparator Multiplexed Input .............................................................78

Register Description ........................................................................................79

14 Analog to Digital Converter .................................................................. 81

ii

ATtiny13

2535J–AVR–08/10

ATtiny13

14.1

14.2

14.3

14.4

14.5

14.6

14.7

14.8

14.9

Features ..........................................................................................................81

Overview ..........................................................................................................81

Operation .........................................................................................................82

Starting a Conversion ......................................................................................82

Prescaling and Conversion Timing ..................................................................83

Changing Channel or Reference Selection .....................................................86

ADC Noise Canceler .......................................................................................87

Analog Input Circuitry ......................................................................................87

Analog Noise Canceling Techniques ...............................................................88

14.10 ADC Accuracy Definitions ...............................................................................88

14.11 ADC Conversion Result ...................................................................................91

14.12 Register Description ........................................................................................91

15 debugWIRE On-chip Debug System .................................................... 95

15.1

15.2

15.3

15.4

15.5

15.6

Features ..........................................................................................................95

Overview ..........................................................................................................95

Physical Interface ............................................................................................95

Software Break Points .....................................................................................96

Limitations of debugWIRE ...............................................................................96

Register Description ........................................................................................96

16 Self-Programming the Flash ................................................................. 97

16.1

16.2

16.3

16.4

16.5

16.6

16.7

16.8

16.9

Performing Page Erase by SPM ......................................................................97

Filling the Temporary Buffer (Page Loading) ...................................................97

Performing a Page Write .................................................................................98

Addressing the Flash During Self-Programming .............................................98

EEPROM Write Prevents Writing to SPMCSR ................................................99

Reading Fuse and Lock Bits from Firmware ...................................................99

Preventing Flash Corruption ..........................................................................100

Programming Time for Flash when Using SPM ............................................100

Register Description ......................................................................................101

17 Memory Programming ......................................................................... 102

17.1

17.2

17.3

17.4

17.5

Program And Data Memory Lock Bits ...........................................................102

Fuse Bytes .....................................................................................................103

Calibration Bytes ...........................................................................................104

Signature Bytes .............................................................................................104

Page Size ......................................................................................................104

iii

2535J–AVR–08/10

17.6

17.7

17.8

Serial Programming .......................................................................................105

High-Voltage Serial Programming .................................................................108

Considerations for Efficient Programming .....................................................112

18 Electrical Characteristics .................................................................... 115

18.1

18.2

18.3

18.4

18.5

18.6

18.7

18.8

18.9

Absolute Maximum Ratings* .........................................................................115

DC Characteristics .........................................................................................115

Speed Grades ...............................................................................................117

Clock Characteristics .....................................................................................118

System and Reset Characteristics ................................................................119

Analog Comparator Characteristics ...............................................................119

ADC Characteristics ......................................................................................120

Serial Programming Characteristics ..............................................................121

High-voltage Serial Programming Characteristics .........................................122

19 Typical Characteristics ........................................................................ 123

19.1

19.2

19.3

19.4

19.5

19.6

19.7

19.8

19.9

Active Supply Current ....................................................................................123

Idle Supply Current ........................................................................................126

Power-Down Supply Current .........................................................................129

Pin Pull-up .....................................................................................................130

Pin Driver Strength ........................................................................................132

Pin Thresholds and Hysteresis ......................................................................141

BOD Thresholds and Analog Comparator Offset ..........................................146

Internal Oscillator Speed ...............................................................................148

Current Consumption of Peripheral Units ......................................................152

19.10 Current Consumption in Reset and Reset Pulse width .................................154

20 Register Summary ............................................................................... 156

21 Instruction Set Summary .................................................................... 158

22 Ordering Information ........................................................................... 160

23 Packaging Information ........................................................................ 161

23.1

23.2

23.3

23.4

23.5

8P3 ................................................................................................................161

8S2 ................................................................................................................162

S8S1 ..............................................................................................................163

20M1 ..............................................................................................................164

10M1 ..............................................................................................................165

24 Errata ..................................................................................................... 166

iv

ATtiny13

2535J–AVR–08/10

ATtiny13

24.1

24.2

24.3

24.4

ATtiny13 Rev. D ............................................................................................166

ATtiny13 Rev. C ............................................................................................166

ATtiny13 Rev. B .............................................................................................166

ATtiny13 Rev. A .............................................................................................167

25 Datasheet Revision History ................................................................ 168

25.1

25.2

25.3

25.4

25.5

25.6

25.7

25.8

25.9

Rev. 2535J-08/10 ..........................................................................................168

Rev. 2535I-05/08 ...........................................................................................168

Rev. 2535H-10/07 .........................................................................................169

Rev. 2535G-01/07 .........................................................................................169

Rev. 2535F-04/06 ..........................................................................................169

Rev. 2535E-10/04 ..........................................................................................169

Rev. 2535D-04/04 .........................................................................................170

Rev. 2535C-02/04 .........................................................................................170

Rev. 2535B-01/04 ..........................................................................................170

25.10 Rev. 2535A-06/03 ..........................................................................................170

Table of Contents....................................................................................... i

v

2535J–AVR–08/10

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Tel: 1(408) 441-0311

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2535J–AVR–08/10


型号：	ATTINY13_14
厂家：	ATMEL
描述：	High Endurance Non-volatile Memory segments
文件：	总176页 (文件大小：3102K)
中文：	中文翻译
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